WO2022083231A1 - 半导体结构及其制作方法 - Google Patents

半导体结构及其制作方法 Download PDF

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Publication number
WO2022083231A1
WO2022083231A1 PCT/CN2021/110881 CN2021110881W WO2022083231A1 WO 2022083231 A1 WO2022083231 A1 WO 2022083231A1 CN 2021110881 W CN2021110881 W CN 2021110881W WO 2022083231 A1 WO2022083231 A1 WO 2022083231A1
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film layer
semiconductor structure
groove
sidewall
layer
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French (fr)
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李涛
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01332—Making the insulator
    • H10D64/0135—Making the insulator by deposition of a layer, e.g. metal, metal compound or polysilicon, followed by transformation thereof into the insulator
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/667—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/42—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a gas or vapour
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials

Definitions

  • the present application relates to the field of semiconductors, and in particular, to a semiconductor structure and a fabrication method thereof.
  • the low-pressure chemical vapor deposition process LPCVD can achieve a lower step coverage, but cannot control the step coverage accurately and stably.
  • Embodiments of the present invention provide a semiconductor structure and a manufacturing method thereof, which are beneficial to obtain a multi-layer structure with high step coverage.
  • an embodiment of the present invention provides a semiconductor structure, comprising: a substrate, wherein the substrate has a groove; a first film layer, the first film layer covers the bottom surface and sidewalls of the groove; a second film layer A film layer, the second film layer covers the surface of the first film layer, and the step coverage of the second film layer is different from that of the first film layer.
  • Another aspect of the present invention further provides a method for fabricating a semiconductor structure, comprising: providing a substrate, wherein the substrate has a groove; forming a first film layer, the first film layer covering the bottom surface and sidewalls of the groove; A second film layer is formed, the second film layer covers the surface of the first film layer, and the step coverage of the second film layer is different from that of the first film layer.
  • the combination of two film layers with different step coverage ratios can make the overall step coverage ratio of the combined film layer approach the step coverage ratio of the second film layer, thereby obtaining a composite film with a step coverage ratio at an intermediate value. layer to meet the corresponding electrical requirements.
  • the second film layer with a larger step coverage can maintain or make up for the surface defects of the first film layer, and accordingly, it is beneficial to avoid the film layer with a lower step coverage rate from amplifying the defects of another film layer with a higher step coverage rate , so as to ensure that the overall film layer has good surface properties.
  • 1 to 5 are schematic structural diagrams corresponding to each step of a method for fabricating a semiconductor structure according to an embodiment of the present invention.
  • 1 to 5 are schematic structural diagrams corresponding to each step of a method for fabricating a semiconductor structure according to an embodiment of the present invention.
  • a substrate 10 is provided and a first film layer 111 is formed.
  • the substrate 10 has a groove 101 therein, and the material of the substrate 10 includes semiconductor materials such as silicon or germanium.
  • the material of the substrate 10 is silicon as an example for illustration.
  • the first film layer 111 is formed by the reaction between the functional group 111 a and the substrate 10 .
  • the functional group 111a includes a hydroxyl radical, and the hydroxyl radical reacts with silicon to generate silicon dioxide and derivative water that form the first film layer 111; in other embodiments, the material of the first film layer may also be Silicon Nitride.
  • the first film layer is formed by immobilizing predetermined material molecules with functional groups. Specifically, after the functional groups covering the sidewalls and the bottom surface of the groove are formed, gaseous preset material molecules are blown to the groove surface, and the gaseous preset material molecules are fixed on the surface of the groove sidewalls through the functional groups to form a first film layer.
  • the functional groups to fix the preset material molecules to form the first film layer: first, the preset material molecules are the constituent materials of the first film layer, and the preset material molecules do not interact with the functional groups. Reaction, that is, no derivatives are generated, only chemical bonds or intermolecular forces are combined; secondly, the pre-set material molecules react with functional groups to generate the constituent materials of the first film layer.
  • the first film layer can also be formed by the reaction of the first precursor and the second precursor, and the functional group is used to fix the first precursor. Specifically, after the functional groups covering the sidewalls and the bottom surface of the groove are formed, the first precursor and the second precursor are sequentially blown to the groove surface, the functional groups fix part of the first precursor, the second precursor and the fixed first precursor The bulk reacts to generate preset material molecules to form the first film layer.
  • the first film layer 111 with lower step coverage is formed first, and then the second film layer (not shown) with higher step coverage is formed, which is beneficial to avoid the first film layer 111 Amplify the surface defects of the second film layer, and help fill the surface defects of the first film layer 111 by the second film layer formed subsequently, thereby reducing the difficulty of repairing the surface defects, so that the first film layer 111 and the second film layer are composed of
  • the overall film layer has good surface properties.
  • a film layer with a higher step coverage ratio can also be formed first, so as to use the film layer to fill and repair damage or defects on the bottom surface and sidewalls of the groove.
  • a low pressure chemical vapor deposition process is used to form the functional group 111a, and the functional group 111a is a hydroxyl radical.
  • the process steps of forming the functional group 111a include: blowing a mixed gas containing hydrogen and oxygen to the surface of the substrate 10 at a specific pressure; and increasing the temperature of the reaction chamber to make the hydrogen and oxygen react to produce hydroxyl radicals.
  • the generated hydroxyl radicals can undergo oxidation reaction with the substrate 10 to generate the constituent material of the first film layer 111 , that is, silicon dioxide.
  • the contact of the blown mixed gas with the surface of the substrate 10 will cause its own air pressure to attenuate, and the mixed gas will be diffused from the top of the groove 101 to the bottom of the groove 101 in the process of diffusing.
  • the sidewall surfaces of the substrate 10 are in continuous contact. Therefore, the air pressure at the top of the groove 101 is higher than the air pressure at the bottom of the groove 101 after the mixed gas is blown. Specifically, in the direction from the top of the groove 101 toward the bottom of the groove 101 , the gas pressure of the mixed gas decreases.
  • the quantity of hydroxyl radicals generated at the top of the groove 101 is greater than that generated at the bottom of the groove 101
  • the density of the hydroxyl radicals covering the top sidewalls of the grooves 101 is greater than that of the hydroxyl radicals covering the bottom sidewalls of the grooves 101 Density. Specifically, in the direction extending from the top sidewall of the groove 101 to the bottom sidewall of the groove 101 , the density of hydroxyl radicals covering the surface of the sidewall of the groove 101 decreases.
  • the thickness of the first film layer 111 covering the top sidewall is greater than the thickness of the first film layer 111 covering the bottom sidewall. In the direction in which the sidewalls extend, the thickness of the first film layer 111 decreases.
  • the pressure decay rate of the mixed gas is faster when it contacts the surface of the substrate 10. Therefore, after the mixed gas is blown, the pressure of the mixed gas at the bottom of the groove 101 is the same as that at the bottom of the groove 101.
  • the difference between the gas pressures of the mixed gas at the top of the groove 101 is relatively large; further, after the first film layer 111 is formed, the thickness of the first film layer 111 covering the bottom sidewall of the groove 101 and the bottom surface of the groove 101 is different from the thickness of the first film layer 111 covering the groove 101.
  • the difference in thickness of the first film layer 111 on the top sidewall of the groove 101 is large, that is, the step coverage ratio of the first film layer 111 formed by the low pressure chemical vapor deposition process is low.
  • the step coverage of the first film layer 111 is related to the aspect ratio of the groove 101 .
  • the larger the aspect ratio the longer the decay time of the mixed gas pressure when the mixed gas is blown at the same rate, and the bottom of the groove 101 will be longer.
  • the greater the difference in air pressure with the top so that after the first film layer 111 is formed, the thickness difference of the first film layer 111 covering the top sidewall and the bottom sidewall of the groove 101 is greater, and the step coverage is lower. .
  • the size of the thickness difference and the size of the step coverage will affect the thickness of the second film layer to be formed subsequently. Specifically, under the condition that the step coverage of the overall film layer to be achieved remains unchanged, the larger the thickness difference, or the smaller the step coverage, the greater the thickness value of the second film layer to be formed subsequently. Under the changed conditions, the process time required to form the second film layer is longer.
  • the aspect ratio of the groove 101 is 1 ⁇ 100.
  • the gas pressure at the top of the groove 101 is 5 Torr to 10 Torr, such as 6 Torr, 7 Torr or 8 Torr, and the bottom of the groove 101 is at a pressure of 5 Torr to 10 Torr.
  • the air pressure is 0Torr ⁇ 5Torr, such as 2Torr, 3Torr or 4Torr.
  • the process temperature of the low pressure chemical vapor deposition process is 500°C to 1000°C, for example, 600°C, 700°C or 800°C. At this process temperature, the deposition process has a faster deposition rate, which can effectively shorten the process time of the first film layer 111 .
  • a second film layer 112 covering the surface of the first film layer 111 is formed.
  • an atomic layer deposition process is used to form a second film layer 112 with a higher step coverage , so that the step coverage of the overall film layer formed by the first film layer 111 and the second film layer 112 is greater than that of the first film layer 111 , that is, the overall film layer has a relatively high step coverage.
  • the atomic layer deposition process is self-limiting, that is, the first precursor covered by the second precursor will not be combined with other second precursors, so the monolayer film formed by the reaction of the first precursor and the second precursor Has a uniform thickness.
  • the second film layer 112 with higher step coverage can be formed, and the step coverage of the second film layer 112 is greater than that of the first film layer 111 .
  • the material of the second film layer 112 is the same as the material of the first film layer 111, so that it is beneficial to change the step coverage of the whole film layer composed of the same material without changing the material properties. , so that the structure of the overall film layer meets the preset electrical requirements; in other embodiments, the material properties of the first film layer are different from those of the second film layer, and the method of changing the material properties includes changing the material itself, injecting Doping ions and adjusting the grain size, etc.
  • the second film layer 112 is a single-layer structure; in other embodiments, the second film layer is a multi-layer structure, and the materials of at least two film layers in the multi-layer structure are different.
  • a film layer composed of other materials is introduced to adjust the electrical properties of the overall film layer, so as to avoid the influence of its own electrical properties due to the thicker minimum thickness of the overall film layer.
  • the electrical properties of different regions of the overall film layer are differentiated to meet specific electrical properties.
  • the thickness of the overall film layer with the preset step coverage may be thick due to the limitation of the process characteristics of the deposition process.
  • the electrical properties of the overall film are still differentiated, but the electrical properties of different regions are weakened.
  • the electrical properties of the overall film can be adjusted by introducing a film composed of other materials, so that the electrical properties of different regions of the overall film can be adjusted. There are differences, and the electrical properties of the overall film layer meet the preset requirements.
  • any film layer included in the second film layer 112 has a higher step coverage. Therefore, in the second film layer 112
  • the introduction of sub-layers composed of other materials is conducive to ensuring that the sub-layers have the same effect on different regions of the overall film layer, that is, at the same time, the electrical properties of different regions of the overall film layer are enhanced without affecting the electrical properties of different regions.
  • the electrical properties of different regions of the overall film layer meet the preset requirements.
  • the deposition rate of the deposition process itself is relatively fast, it is impossible for the deposition time to be affected by the performance of the reaction device, the gas supply rate, etc. Infinitely shortened, so the finally formed first film layer 111 has a minimum thickness difference.
  • the thickness of the final formed overall film layer satisfying the preset step coverage ratio requirement may be relatively thick due to the large difference in the minimum thickness of the first film layer 111 .
  • the process steps of forming the second film layer 112 include: blowing the first precursor 112a into the reaction chamber, so that the first precursor 112a evenly covers the surface of the first film layer 111; gas to purge the first precursor 112a and derivatives not attached to the surface of the first film layer 111; pass the second precursor (not shown) to make the second precursor react with the first precursor 112a , to generate the constituent material of the second film layer 112; pass in an inert gas to purge the unreacted mixed gas and derivatives; perform a cyclic reaction to thicken the second film layer 112, so as to make the step coverage of the overall film layer meet preset needs.
  • the first precursor 112a may be silicon tetrachloride
  • the second precursor may be a mixed gas of hydrogen and oxygen.
  • Oxygen and silicon tetrachloride can form silicon dioxide and derivative chlorine gas at high temperature, and silicon dioxide is the constituent material of the second film layer 112; the derivative chlorine gas can react with hydrogen to generate hydrogen chloride, which is beneficial to avoid the reaction waste gas containing serious pollutants.
  • Toxic gas chlorine to improve reaction safety.
  • the first film layer 111 and the second film layer 112 serve as the gate dielectric layer 11, that is, the first film layer 111 and the second film layer 112 together constitute a certain functional layer with a specific function. ; In other embodiments, the first film layer and the second film layer may jointly constitute other functional layers with a specific function, or the first film layer and the second film layer respectively have a specific function.
  • the gate electrode 12 is formed.
  • a gate 12 is formed and filled in the groove 101.
  • the gate 12 includes a blocking layer 121 and a metal layer 122, and the blocking layer 121 is located between the metal layer 122 and the gate. between the dielectric layers 11 , to prevent metal ions in the metal layer 122 from migrating into the gate dielectric layer 11 or the substrate 10 , and to ensure that the gate dielectric layer 11 and the substrate 10 have predetermined properties.
  • the material of the blocking layer 121 includes titanium nitride, and the material of the metal layer 122 includes tungsten.
  • a planarization process is further performed to remove the material higher than the top surface of the substrate 10 to form the gate dielectric layer 11 and the gate 12 completely within the substrate.
  • the gate dielectric layer 11 covering the bottom sidewall and the bottom surface of the groove 101 is thinner, so that the operating voltage of the gate 12 is reduced; the gate dielectric layer 11 covering the top sidewall of the groove 101 is relatively thin. Thick, in this way, is beneficial to reduce the leakage current of the source and the drain, specifically the gate-induced drain leakage current GIDL, thereby improving the reliability of the semiconductor structure.
  • the combination of two film layers with different step coverages can make the overall step coverage of the combined film layer approach the step coverage of the second film layer, so that the step coverage is at an intermediate value.
  • the combined film layer to meet the corresponding electrical requirements.
  • the embodiments of the present invention further provide a semiconductor structure, which can be fabricated by the above-mentioned fabrication method of the semiconductor structure.
  • the semiconductor structure includes: a substrate 10 having a groove 101 in the substrate 10 ; a first film layer 111 covering the bottom surface and sidewalls of the groove 101 ; a second film layer 112 , the second film layer 112 Covering the surface of the first film layer 111 , the step coverage of the second film layer 112 is different from that of the first film layer 111 .
  • the step coverage of the second film layer 112 is greater than that of the first film layer 111 , the second film layer 112 is a single-layer structure, and the material of the first film layer 111 and the second film layer are The materials of 1112 are the same; in other embodiments, the second film layer is a multi-layer structure, and the materials of at least two film layers in the multi-layer structure are different.
  • the sidewall of the groove 101 includes a bottom sidewall and a top sidewall.
  • the thickness of the first film layer 111 covering the bottom sidewall is smaller than that covering the top sidewall.
  • the thickness of the first film layer 111 of the wall Specifically, in a direction extending from the top sidewall to the bottom sidewall, the thickness of the first film layer 111 decreases.
  • the first film layer 111 and the second film layer 112 constitute a gate dielectric layer 11 ; the semiconductor structure further includes: a gate electrode 12 , and the gate electrode 12 is filled in the groove 101 .
  • the combination of two film layers with different step coverages can make the overall step coverage of the combined film layer approach the step coverage of the second film layer, so that the step coverage is at an intermediate value.
  • the combined film layer to meet the corresponding electrical requirements.

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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本发明实施例提供一种半导体结构及其制作方法，半导体结构包括：基底，所述基底内具有凹槽；第一膜层，所述第一膜层覆盖所述凹槽底面和侧壁；第二膜层，所述第二膜层覆盖所述第一膜层表面，所述第二膜层的阶梯覆盖率不同于所述第一膜层的阶梯覆盖率。本发明实施例有利于获取具有预设阶梯覆盖率的多层结构。

Description

半导体结构及其制作方法
交叉引用
本申请基于申请号为202011149559.2、申请日为2020年10月23日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请涉及半导体领域，特别涉及一种半导体结构及其制作方法。
背景技术
现有的膜层制备工艺都是致力于精确的膜厚控制、较高的阶梯覆盖率以及较好的膜厚均匀度，但是对于一些特殊膜层，需要在不改变膜层自身特性的情况下，降低阶梯覆盖率以达到电性上的要求。
目前，低压化学气相沉积工艺LPCVD可以实现较低的阶梯覆盖率，但是无法精准和稳定地控制阶梯覆盖率。
发明内容
本发明实施例提供一种半导体结构及其制作方法，有利于获取具有高阶梯覆盖率的多层结构。
为解决上述问题，本发明实施例提供一种半导体结构，包括：基底，所述基底内具有凹槽；第一膜层，所述第一膜层覆盖所述凹槽底 面和侧壁；第二膜层，所述第二膜层覆盖所述第一膜层表面，所述第二膜层的阶梯覆盖率不同于所述第一膜层的阶梯覆盖率。
本发明另一方面还提供一种半导体结构的制作方法，包括：提供基底，所述基底内具有凹槽；形成第一膜层，所述第一膜层覆盖所述凹槽底面和侧壁；形成第二膜层，所述第二膜层覆盖所述第一膜层表面，所述第二膜层的阶梯覆盖率不同于所述第一膜层的阶梯覆盖率。
与现有技术相比，本发明实施例提供的技术方案具有以下优点：
上述技术方案中，采用两种不同阶梯覆盖率的膜层进行组合，可使得组合膜层的整体阶梯覆盖率向第二膜层的阶梯覆盖率靠近，进而获取阶梯覆盖率处于中间值的组合膜层，以满足对应的电性要求。
具有较大阶梯覆盖率的第二膜层可保持或弥补第一膜层的表面缺陷，相应地，有利于避免阶梯覆盖率较低的膜层放大阶梯覆盖率较高的另一膜层的缺陷，从而保证整体膜层具有良好的表面性能。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，除非有特别申明，附图中的图不构成比例限制。
图1至图5为本发明实施例提供的半导体结构的制作方法各步骤对应的结构示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合附图对本发明的各实施例进行详细的阐述。然而，本领域的普通技 术人员可以理解，在本发明各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。
图1至图5为本发明实施例提供的半导体结构的制作方法各步骤对应的结构示意图。
参考图1和图2，提供基底10和形成第一膜层111。
基底10内具有凹槽101，基底10的材料包括硅或锗等半导体材料，本实施例以基底10的材料为硅作为示例性说明。
在一可选实施例中，第一膜层111由官能团111a与基底10反应生成。具体地，官能团111a包括氢氧自由基，氢氧自由基与硅反应生成组成第一膜层111的材料二氧化硅和衍生物水；在其他实施例中，第一膜层的材料还可以是氮化硅。
在一可选实施例中，第一膜层由官能团固定预设材料分子形成。具体地，在形成覆盖凹槽侧壁和底面的官能团之后，向凹槽表面吹送气态的预设材料分子，气态的预设材料分子通过官能团固定于凹槽侧壁表面，形成第一膜层。
在一可选实施例中，官能团固定预设材料分子以形成第一膜层的方式有两种：第一，预设材料分子为第一膜层的组成材料，预设材料分子不与官能团发生反应，即不产生衍生物，仅通过化学键或分子间作用力进行结合；第二，预设材料分子与官能团发生反应以生成第一膜层的组成材料。
在一可选实施例中，第一膜层还可以由第一前驱体和第二前驱体反应生成，官能团用于固定第一前驱体。具体地，在形成覆盖凹槽侧壁和底面的官能团之后，向凹槽表面依次吹送第一前驱体和第二前驱体，官能团固定部分第一前驱体，第二前驱体与固定的第一前驱体反应生成预设材料分子，以构成第一膜层。
在一可选实施例中，先形成阶梯覆盖率较低的第一膜层111，再形成阶梯覆盖率较高的第二膜层(未图示)，如此，有利于避免第一膜层111放大第二膜层的表面缺陷，以及有利于通过后续形成的第二膜层填补第一膜层111的表面缺陷，从而降低表面缺陷的修复难度，使得第一膜层111和第二膜层构成的整体膜层具有良好的表面特性。
在一可选实施例中，还可以先形成阶梯覆盖率较高的膜层，以利用该膜层去填补并修复凹槽底面和侧壁的损伤或缺陷。
在一可选实施例中，采用低压化学气相沉积工艺形成官能团111a，官能团111a为氢氧自由基。具体地，形成官能团111a的工艺步骤包括：以特定压力向基底10表面吹送包含有氢气和氧气的混合气体；升高反应腔室的温度以使得氢气和氧气反应生产氢氧自由基。生成的氢氧自由基可与基底10发生氧化反应，以生成第一膜层111的组成材料，即二氧化硅。
在进行低压化学气相沉积工艺的过程中，吹送的混合气体与基底10表面发生接触会使得自身的气压发生衰减，而混合气体在自凹槽101顶部向凹槽101底部扩散的过程中，会与基底10侧壁表面持续接触。因此，在进行混合气体的吹送之后，凹槽101顶部的气压大于 凹槽101底部的气压。具体地，在凹槽101顶部朝向凹槽101底部的方向上，混合气体的气压递减。
在一可选实施例中，在氢气和氧气的反应过程中，由于压力越大平均自由程越短，因此凹槽101顶部生成的氢氧自由基的数量大于凹槽101底部生成的氢氧自由基的数量；进一步地，在漂浮的氢氧自由基附着在凹槽101侧壁之后，覆盖凹槽101顶部侧壁的氢氧自由基的密度大于覆盖凹槽101底部侧壁的氢氧自由基的密度。具体地，在凹槽101顶部侧壁向凹槽101底部侧壁延伸的方向上，覆盖于凹槽101侧壁表面的氢氧自由基的密度递减。
由于覆盖顶部侧壁的氢氧自由基的密度大于覆盖底部侧壁的氢氧自由基的密度，因此顶部侧壁的氧化速率大于底部侧壁的氧化速率，顶部侧壁反应生成二氧化硅的速率更快。如此，在反应生成第一膜层111之后，覆盖顶部侧壁的第一膜层111的厚度大于覆盖底部侧壁的第一膜层111的厚度，具体地，在凹槽101顶部侧壁向底部侧壁延伸的方向上，第一膜层111的厚度递减。
需要说明的是，由于在低压化学气相沉积工艺中，混合气体在接触基底10表面时气压衰减速率较快，因此在进行混合气体的吹送之后，位于凹槽101底部的混合气体的气压与位于凹槽101顶部的混合气体的气压的差值较大；进一步地，在形成第一膜层111之后，覆盖凹槽101底部侧壁和覆盖凹槽101底面的第一膜层111的厚度与覆盖凹槽101顶部侧壁的第一膜层111的厚度的差值较大，即采用低压化学气相沉积工艺形成的第一膜层111的阶梯覆盖率较低。
第一膜层111的阶梯覆盖率与凹槽101的深宽比有关，深宽比越大，在以相同的速率进行混合气体的吹送时，混合气体气压的衰减时间越长，凹槽101底部和顶部之间的气压差越大，如此，在形成第一膜层111之后，覆盖凹槽101顶部侧壁和底部侧壁的第一膜层111的厚度差越大，以及阶梯覆盖率越低。
需要说明的是，厚度差的大小以及阶梯覆盖率的大小会影响后续需要形成的第二膜层的厚度。具体地，在需要达到的整体膜层的阶梯覆盖率不变的条件下，厚度差越大，或者阶梯覆盖率越小，后续需要形成的第二膜层的厚度值越大，在沉积速率不变的条件下，形成第二膜层所需的工艺时间越长。
在一可选实施例中，凹槽101的深宽比为1～100。
在一可选实施例中，由于低压化学气相沉积工艺中的气压衰减特性，在进行混合气体的吹送之后，凹槽101顶部的气压为5Torr～10Torr，例如6Torr、7Torr或8Torr，凹槽101底部的气压为0Torr～5Torr，例如2Torr、3Torr或4Torr。
在一可选实施例中，低压化学气相沉积工艺的工艺温度为500℃～1000℃，例如600℃、700℃或800℃。在该工艺温度下，沉积工艺具有较快的沉积速率，可有效缩短第一膜层111的工艺时长。
参考图3和图4，形成覆盖第一膜层111表面的第二膜层112。
在一可选实施例中，在采用低压化学气相沉积工艺形成阶梯覆盖率较低、具有厚度差异的第一膜层111之后，采用原子层沉积工艺形成阶梯覆盖率较高的第二膜层112，以使第一膜层111和第二膜层112 构成的整体膜层的阶梯覆盖率大于第一膜层111的阶梯覆盖率，即使得整体膜层具有相对较高的阶梯覆盖率。
由于原子层沉积工艺具有自限性，即被第二前驱体覆盖的第一前驱体不会再与其他第二前驱体结合，因此第一前驱体和第二前驱体反应生成的单层膜层具有均匀厚度。通过逐层形成上述单层膜层，可以形成具有较高阶梯覆盖率的第二膜层112，第二膜层112的阶梯覆盖率大于第一膜层111的阶梯覆盖率。
在一可选实施例中，第二膜层112的材料与第一膜层111的材料相同，如此，有利于在不改变材料性质的条件下改变由同一材料构成的整体膜层的阶梯覆盖率，从而使得整体膜层的结构满足预设的电性要求；在其他实施例中，第一膜层的材料性质与第二膜层的材料性质不同，改变材料性质的方式包括改变材料本身、注入掺杂离子以及调整晶粒尺寸等方式。
在一可选实施例中，第二膜层112为单层结构；在其他实施例中，第二膜层为多层结构，多层结构中至少两层膜层的材料不同，如此，可通过引入由其他材料组成的膜层调整整体膜层的电学性能，避免因整体膜层的最小厚度较厚而导致自身的电学性能受到影响。
具体来说，本实施例中，通过调整第一膜层和第二膜层构成的整体膜层的阶梯覆盖率，使得整体膜层的不同区域的电学性能存在差异化，以满足特定的电性需求；但在形成整体膜层的过程中，可能因为沉积工艺的工艺特性限制，导致最终具有预设阶梯覆盖率的整体膜层的厚度偏厚，在这一情况下，虽然整体膜层不同区域的电学性能依旧 存在差异化，但是不同区域的电学性能都被减弱，此时，可通过引入由其他材料组成的膜层来调节整体膜层的电学特性，以使得整体膜层不同区域的电学性能存在差异化，且整体膜层的电学性能满足预设需求。
在一可选实施例中，由于第二膜层112采用原子层沉积工艺形成，第二膜层112包含的任一膜层都具有较高的阶梯覆盖率，因此，在第二膜层112中引入由其他材料组成的子膜层，有利于保证子膜层对整体膜层不同区域的影响相同，即同时增强整体膜层不同区域的电学性能，而不影响不同区域的电学性能差异化，最终使得整体膜层不同区域的电学性能满足预设要求。
关于沉积工艺的工艺特性限制，至少包括以下方面：在进行低压化学气相沉积工艺的过程中，由于沉积工艺自身的沉积速率较快，而沉积时间受反应装置性能、送气速率等方面的影响不可能无限缩短，因此最终形成的第一膜层111具有一最小厚度差。在调整整体膜层的阶梯覆盖率时，可能因为第一膜层111的最小厚度差较大，从而导致最终形成的满足预设阶梯覆盖率要求的整体膜层的厚度偏厚。
在一可选实施例中，形成第二膜层112的工艺步骤包括：向反应腔室内吹送第一前驱体112a，以使第一前驱体112a均匀覆盖在第一膜层111表面；通入惰性气体，以吹扫未附着在第一膜层111表面的第一前驱体112a和衍生物；通入第二前驱体(未图示)，以使第二前驱体与第一前驱体112a发生反应，以生成第二膜层112的组成材料；通入惰性气体，以吹扫未反应的混合气体和衍生物；进行循环反应， 增厚第二膜层112，以使整体膜层的阶梯覆盖率满足预设需要。
以第二膜层112的材料为二氧化硅为例，第一前驱物112a可以四氯化硅，第二前驱物可以是氢气和氧气的混合气体。氧气和四氯化硅可以在高温下形成二氧化硅和衍生物氯气，二氧化硅为第二膜层112的组成材料；衍生物氯气可与氢气反应生成氯化氢，有利于避免反应废气中包含剧毒气体氯气，提高反应安全性。
在一可选实施例中，第一膜层111和第二膜层112作为栅介质层11，也就是说，第一膜层111和第二膜层112共同构成具有特定作用的某一功能层；在其他实施例中，第一膜层和第二膜层可共同构成具有特定作用的其他功能层，或者，第一膜层和第二膜层分别具有某一特定作用。
参考图5，形成栅极12。
在一可选实施例中，在形成栅介质层11之后，形成位于填充于凹槽101内的栅极12，栅极12包括阻拦层121和金属层122，阻拦层121位于金属层122和栅介质层11之间，以避免金属层122中的金属离子向栅介质层11或基底10内迁移，保证栅介质层11和基底10具有预设性能。
其中，阻拦层121的材料包括氮化钛，金属层122的材料包括钨。
在一可选实施例中，在形成栅极12之后，还进行平坦化工艺，以去除高于基底10顶面的材料，形成完全位于基底内的栅介质层11和栅极12。
在一可选实施例中，覆盖凹槽101底部侧壁和底面的栅介质层 11较薄，如此，有利于降低栅极12的工作电压；覆盖凹槽101顶部侧壁的栅介质层11较厚，如此，有利于降低源极和漏极的漏电流，具体为栅诱导漏极泄漏电流GIDL，从而提高半导体结构的可靠性。
在一可选实施例中，采用两种不同阶梯覆盖率的膜层进行组合，可使得组合膜层的整体阶梯覆盖率向第二膜层的阶梯覆盖率靠近，进而获取阶梯覆盖率处于中间值的组合膜层，以满足对应的电性要求。
相应地，本发明实施例还提供一种半导体结构，可采用上述半导体结构的制作方法制成。
参考图5，半导体结构包括：基底10，基底10内具有凹槽101；第一膜层111，第一膜层111覆盖凹槽101底面和侧壁；第二膜层112，第二膜层112覆盖第一膜层111表面，第二膜层112的阶梯覆盖率不同于第一膜层111的阶梯覆盖率。
在一可选实施例中，第二膜层112的阶梯覆盖率大于第一膜层111的阶梯覆盖率，第二膜层112为单层结构，第一膜层111的材料与第二膜层1112的材料相同；在其他实施例中，第二膜层为多层结构，多层结构中至少两层膜层的材料不同。
在一可选实施例中，凹槽101侧壁包括底部侧壁和顶部侧壁，在垂直于凹槽101侧壁的方向上，覆盖底部侧壁的第一膜层111的厚度小于覆盖顶部侧壁的第一膜层111的厚度。具体地，在顶部侧壁向底部侧壁延伸的方向上，第一膜层111的厚度递减。
在一可选实施例中，第一膜层111和第二膜层112构成栅介质层11；半导体结构还包括：栅极12，栅极12填充于凹槽101内。
在一可选实施例中，采用两种不同阶梯覆盖率的膜层进行组合，可使得组合膜层的整体阶梯覆盖率向第二膜层的阶梯覆盖率靠近，进而获取阶梯覆盖率处于中间值的组合膜层，以满足对应的电性要求。
本领域的普通技术人员可以理解，上述各实施方式是实现本发明的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本发明的精神和范围。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各自更动与修改，因此本发明的保护范围应当以权利要求限定的范围为准。

Claims (13)

  1. 一种半导体结构，包括：
    基底，所述基底内具有凹槽；
    第一膜层，所述第一膜层覆盖所述凹槽底面和侧壁；
    第二膜层，所述第二膜层覆盖所述第一膜层表面，所述第二膜层的阶梯覆盖率不同于所述第一膜层的阶梯覆盖率。
  2. 根据权利要求1所述的半导体结构，其中，所述第二膜层的阶梯覆盖率大于所述第一膜层的阶梯覆盖率。
  3. 根据权利要求2所述的半导体结构，其中，所述第二膜层为多层结构，所述多层结构中至少两层膜层的材料不同。
  4. 根据权利要求1或2所述的半导体结构，其中，所述凹槽侧壁包括底部侧壁和顶部侧壁，在垂直于所述凹槽侧壁的方向上，覆盖所述底部侧壁的第一膜层的厚度小于覆盖所述顶部侧壁的第一膜层的厚度。
  5. 根据权利要求4所述的半导体结构，其中，在所述顶部侧壁向所述底部侧壁延伸的方向上，所述第一膜层的厚度递减。
  6. 根据权利要求1所述的半导体结构，其中，所述第一膜层的材料与所述第二膜层的材料相同。
  7. 根据权利要求1所述的半导体结构，其中，所述第一膜层与所述第二膜层构成栅介质层；还包括：栅极，所述栅极填充于所述凹槽内。
  8. 一种半导体结构的制作方法，包括：
    提供基底，所述基底内具有凹槽；
    形成第一膜层，所述第一膜层覆盖所述凹槽底面和侧壁；
    形成第二膜层，所述第二膜层覆盖所述第一膜层表面，所述第二膜层的阶梯覆盖率不同于所述第一膜层的阶梯覆盖率。
  9. 根据权利要求8所述的半导体结构的制作方法，其中，采用低压化学气相沉积工艺形成所述第一膜层，采用原子层沉积工艺形成所述第二膜层，所述第二膜层的阶梯覆盖率大于所述第一膜层的阶梯覆 盖率。
  10. 根据权利要求9所述的半导体结构的制作方法，其中，所述低压化学气相沉积工艺包括：在所述凹槽内形成官能团，所述官能团用于与所述基底反应生成预设材料分子，所述凹槽底部的官能团的密度小于所述凹槽顶部的官能团的密度。
  11. 根据权利要求9所述的半导体结构的制作方法，其中，所述凹槽侧壁包括底部侧壁以及顶部侧壁；所述低压化学气相沉积工艺包括：形成覆盖所述凹槽侧壁的官能团，所述官能团用于固定第一前驱体，覆盖所述底部侧壁的官能团具有第一密度，覆盖所述顶部侧壁的官能团具有第二密度，所述第二密度大于所述第一密度；向所述凹槽侧壁依次吹送所述第一前驱体和第二前驱体，所述第二前驱体用于与固定的所述第一前驱体反应生成预设材料分子。
  12. 根据权利要求11所述的半导体结构的制作方法，其中，形成具有所述第二密度的官能团的环境压力为5Torr～10Torr，形成具有所述第一密度的官能团的环境压力为0Torr～5Torr。
  13. 根据权利要求8所述的半导体结构的制作方法，其中，所述第一膜层和所述第二膜层构成栅介质层；在形成所述第二膜层之后，还包括：形成填充于所述凹槽内的栅极。
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