WO2022077959A1 - 存储器及其制作方法 - Google Patents

存储器及其制作方法 Download PDF

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Publication number
WO2022077959A1
WO2022077959A1 PCT/CN2021/103801 CN2021103801W WO2022077959A1 WO 2022077959 A1 WO2022077959 A1 WO 2022077959A1 CN 2021103801 W CN2021103801 W CN 2021103801W WO 2022077959 A1 WO2022077959 A1 WO 2022077959A1
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WIPO (PCT)
Prior art keywords
layer
contact window
conductive film
isolation layer
memory
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PCT/CN2021/103801
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English (en)
French (fr)
Inventor
金星
程明
李冉
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长鑫存储技术有限公司
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Priority to US17/480,379 priority Critical patent/US20220122978A1/en
Publication of WO2022077959A1 publication Critical patent/WO2022077959A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto

Definitions

  • Embodiments of the present application relate to the field of semiconductors, and in particular, to a memory and a method for fabricating the same.
  • the size change of a certain component will have a greater impact on the overall performance of the semiconductor structure, for example, the size change of the bit line structure.
  • bit line structure increasing the feature size of the bit line structure will compress the space of the capacitor contact hole and reduce the cross-sectional area of the capacitor contact window, and the small cross-sectional area of the capacitor contact window is likely to cause poor contact, which in turn leads to storage capacitors. Failure; reducing the feature size of the bit line structure, it is easy to cause the bit line structure to collapse due to an excessively large aspect ratio.
  • Embodiments of the present application provide a memory and a manufacturing method thereof, which are beneficial to improve the signal transmission performance of the memory.
  • an embodiment of the present application provides a memory, including: a substrate, an active region located in the substrate, and a bit line structure located on the substrate, the active region extending along a first direction; a capacitor; a contact window, the capacitive contact window is located between adjacent bit line structures, at least one center line of the bottom surface of the capacitive contact window extends along a second direction, between the second direction and the first direction
  • the included angle is less than or equal to 45 degrees.
  • an embodiment of the present application further provides a method for fabricating a memory, including: providing a substrate, an active region located in the substrate, and a bit line structure located on the substrate, the active region being along a first direction extending; forming a sacrificial layer filled between adjacent bit line structures, and forming a mask layer covering the top surface of the sacrificial layer, the mask layer is used to form an isolation layer; forming the isolation layer and the Capacitive contact windows between adjacent isolation layers, at least one centerline of the bottom surface of the capacitive contact windows extends along a second direction, and the included angle between the second direction and the first direction is less than or equal to 45 Spend.
  • the dislocation between the capacitive contact window and the active area is reduced, so that the When the area of the bottom surface of the window is the same, the contact area between the bottom surface of the capacitive contact window and the active region is larger, thereby making the signal transmission performance of the capacitive contact window better.
  • FIG. 1 to FIG. 23 are schematic structural diagrams corresponding to each step of a method for fabricating a memory provided by an embodiment of the present application.
  • FIG. 1 to FIG. 23 are schematic structural diagrams corresponding to each step of a method for fabricating a memory provided by an embodiment of the present application.
  • FIG. 1 is a top view corresponding to a step of a method for fabricating a memory provided by an embodiment of the present application
  • FIG. 2 is a schematic cross-sectional structure diagram of the structure shown in FIG. 1 along the first cross-sectional direction AA1.
  • a substrate 10 an active region 101 located within the substrate 10, a bit line structure 11 located on the substrate 10, and an isolation film 114 are provided.
  • the active region 101 extends along the first direction s1.
  • the bit line structure 11 includes a first conductive layer 111, a second conductive layer 112 and a top dielectric layer 113 stacked in sequence, the first conductive layer 111 and the second conductive layer 112 are located in the substrate 10, the first conductive layer 111 and the active region 101 contacts; the bit line structure 11 further includes an underlying dielectric layer 110 , and the underlying dielectric layer 110 is used to define the positions of the first conductive layer 111 and the second conductive layer 112 .
  • the isolation film 114 covers the top surface and sidewalls of the bit line structure 11 , specifically, covers the top surface and sidewalls of the top dielectric layer 113 , covers the sidewalls of the bottom dielectric layer 110 , and also covers the surface of the substrate 10 .
  • the substrate 10 further has a buried word line 102, the bit line structure 11 extends along the first coordinate direction X, the buried word line 102 extends along the second coordinate direction Y, and the first coordinate direction X is perpendicular to The second coordinate direction Y.
  • the included angle between the first coordinate direction and the second coordinate direction is less than 90 degrees.
  • a sacrificial layer 12 is formed to fill between adjacent bit line structures 11 , and a bonding layer 131 is formed to cover the top surface of the sacrificial layer 12 .
  • the material of the sacrificial layer 12 and the material of the isolation film 114 have a larger etching selectivity ratio, so as to avoid the etching of the material of the isolation film 114 by the etchant used to remove the sacrificial layer 12 , thereby ensuring that the bit line structure 11 has good signal transmission performance.
  • the material of the sacrificial layer 12 may be spin-on dielectrics (SOD), such as silicon dioxide, and the material of the isolation film 114 may be silicon nitride.
  • the bonding layer 131 is used to fix the sacrificial layer 12 and the mask layer formed subsequently to prevent the mask layer from shifting during the process, thereby improving the mask accuracy of the mask layer and improving the capacitive contact formed by the mask layer.
  • the positional accuracy of the window ensures good electrical conductivity between the capacitive contact window and the active region 101, thereby enabling the memory to have good signal transmission performance.
  • the material of the bonding layer 131 may be tetraethyl orthosilicate (TEOS).
  • the mask layer 13 covering the top surface of the bonding layer 131 is formed.
  • the mask layer 13 may be a single-layer structure, or may be a multi-layer structure stacked in sequence.
  • the mask layer 13 includes a first sub-mask layer 132 , a second sub-mask layer 133 , a third sub-mask layer 134 , a fourth sub-mask layer 135 and a fifth sub-mask layer that are stacked in sequence Layer 136.
  • the material of the first sub-mask layer 132 may include carbon-containing compounds
  • the material of the second sub-mask layer 133 may include silicon oxynitride
  • the third sub-mask layer 134 may be a spin-on carbon layer (Spin-on Carbon , SOC)
  • the fourth sub-mask layer 135 may be a silicon oxide hard mask interlayer structure (Si-O-based Hard Mask, SHB)
  • the fifth sub-mask layer 136 is a photoresist layer.
  • the fifth sub-mask layer 136 is exposed to light to form patterned openings 136a.
  • FIG. 5 is a top view of the structure shown in FIG. 4 after an exposure process is performed;
  • FIG. 6 is a schematic cross-sectional structure diagram of the structure shown in FIG. 5 along the second cross-sectional direction BB2.
  • the exposed fifth sub-mask layer 136 is composed of a plurality of mutually parallel and discrete mask strips, and different mask strips extend in the same direction; the exposed fifth sub-mask layer 136 is used to define the capacitance contacts formed subsequently
  • the position of the window specifically defines the extending direction of at least one center line of the bottom surface of the capacitor contact window, that is, the extending direction of at least one center line of the bottom surface of the capacitor contact window is the same as the extending direction of the mask strip.
  • the mask strip extends along the second direction s2, and the included angle between the second direction s2 and the first direction s1 is less than or equal to 45 degrees, such as 30 degrees, 20 degrees or 10 degrees.
  • the included angle between the extension direction of at least one center line of the bottom surface of the capacitive contact window and the extending direction of the active region can be controlled to be less than or equal to a preset value, thereby reducing the dislocation between the bottom surface of the capacitive contact window and the active region, so that the capacitive contact window can be
  • the area of the bottom surface is the same, the contact area between the bottom surface of the capacitive contact window and the active region is larger, thereby making the signal transmission performance of the capacitive contact window better.
  • the sacrificial layer 12 is etched using a Self-aligned Double Patterning (SADP) process to form a mask for filling the first isolation layer. isolation slot.
  • SADP Self-aligned Double Patterning
  • the third sub-mask layer 134 and the fourth sub-mask layer 135 are etched, and a sixth sub-mask layer 137 is formed.
  • the third sub-mask layer 134 and the fourth sub-mask layer 135 are etched through the patterned opening 136 a (refer to FIG. 6 ), and the second sub-mask layer 134 is exposed by etching through the third sub-mask layer 134
  • the remaining fifth sub-mask layer 136 (refer to FIG. 6) is removed; a sixth sub-mask layer 137 is formed by a deposition process, and the sixth sub-mask layer 137 covers the fourth sub-mask layer 135
  • the sixth sub-mask layer 137 has a reserved groove 137a therein.
  • a seventh sub-mask layer 138 and isolation trenches 14a are formed for filling the first isolation layer.
  • the sixth sub-mask layer 137 , the second sub-mask layer 133 , the first sub-mask layer 133 , the The mask layer 132, the bonding layer 131, the sacrificial layer 12 and the underlying dielectric layer 110 are etched to form an isolation trench 14a exposing the surface of the substrate 10; after the isolation trench 14a is formed, a first planarization process may be used to remove the second sub-mask The film layer 133 , the third sub-mask layer 134 , the fourth sub-mask layer 135 , the sixth sub-mask layer 137 and the seventh sub-mask layer 138 , thereby improving the fabrication efficiency of the memory.
  • the underlying dielectric layer may not be etched, that is, the surface of the underlying dielectric layer is exposed by the isolation trench, and the part of the underlying dielectric layer exposed by the isolation trench is used as a part of the isolation layer formed subsequently, which is beneficial to reduce the number of process steps , shorten the process cycle.
  • the fixing strength is high, and the removal of the first sub-mask layer 132 directly by the planarization process may result in the indirect connection with the first sub-mask layer 132 .
  • the sacrificial layer 12 collapses due to lack of support, or the sacrificial layer 12 has internal defects.
  • the first sub-mask layer 132 is removed and the isolation trench 14 a is filled to form the first isolation layer 14 .
  • the first sub-mask layer 132 is removed by an etching process, so as to avoid the removal of the first mask layer 132 from damaging the intermediate structure or leaving process defects, and ensuring that the final memory has higher yield.
  • a second planarization process is performed to reduce the height of the first isolation layer 14 .
  • the height of the subsequently formed capacitive contact window can be limited by reducing the height of the first isolation layer 14 to avoid structural defects such as collapse and fracture of the first isolation layer 14 and the capacitive contact window due to an excessively high aspect ratio, It is ensured that the final formed memory has good structural stability.
  • the bonding layer 131 is removed while reducing the height of the first isolation layer 14 .
  • the remaining sacrificial layer 12 (refer to FIG. 12 ) is removed, and part of the underlying dielectric layer 110 exposed on the first isolation layer 14 is removed to form capacitor contact holes 15 a that expose at least part of the surface of the active region 101 .
  • the remaining sacrificial layers 12 between adjacent first isolation layers 14 may be removed by a wet etching process, and the exposed portions of the first isolation layers 14 may be removed by a maskless dry etching process Bottom dielectric layer 110 .
  • the first isolation layer 14 will also be etched, that is, the height of the first isolation layer 14 will be further reduced. Therefore, If the final formed capacitor contact hole 15a needs to have a preset depth, it is necessary to reserve the first isolation layer 14 with a height greater than the preset depth in the second planarization process, and the difference between the actual reserved height and the preset depth The value is equal to the thickness of the underlying dielectric layer 110 in the direction perpendicular to the substrate 10 .
  • a conductive film and a shielding layer 153 are formed in the capacitor contact hole 15a (refer to FIG. 14), and the shielding layer 153 is on the conductive film.
  • the conductive film includes a first conductive film 151 and a second conductive film 152 , the first conductive film 151 is in contact with the active region 101 , and the second conductive film 152 is located on the first conductive film 151 .
  • Both the first conductive film 151 and the second conductive film 152 can be formed by first filling the capacitor contact hole 15a and then performing a dry etching process.
  • a deposition process may be used to form the second preliminary conductive film 152a filling the capacitor contact hole 14a, and a dry etching process may be used to etch and remove part of the second preliminary conductive film 152a , the remaining second initial conductive film 152 a serves as the second conductive film 152 .
  • the contact resistance between the capacitive contact window formed by the first conductive film 151 and the second conductive film 152 and the active region 101 can be reduced by controlling the materials of the first conductive film 151 and the second conductive film 152 , so that the final formed memory has good signal transmission performance.
  • the material of the active region 101 may include monocrystalline silicon
  • the material of the first conductive film 151 may include polycrystalline silicon
  • the material of the second conductive film 152 may include tungsten.
  • At least one center line of the bottom surface of the first conductive film 151 extends along the second direction due to the limitation of the mask strip.
  • the bottom surface of the first conductive film 151 is a parallelogram, and the short side of the parallelogram is close to the bit line structure.
  • the long side of the parallelogram extends along the second direction s2, that is, parallel to the The center line of the long side extends along the second direction; in other embodiments, the bottom surface of the first conductive film is a parallelogram, the long side of the parallelogram is close to the bit line structure, and due to the limitation of the mask strip, the center line parallel to the short side extends in the second direction.
  • the etching selectivity ratio between the material of the shielding layer 153 and the material of the first isolation layer 14 is greater than 50. In this way, it is beneficial to ensure that in the process of etching the first isolation layer 14 by the wet etching process, the etchant can smooth the sidewall of the shielding layer 153 without causing over-etching, so as to ensure the smoothed shielding layer 153 Has precise masking effects.
  • “smoothing” usually includes two degrees: first, preliminary smoothing, that is, grinding right angles into rounded corners; second, deep smoothing, that is, further grinding straight line transitions into arc transitions.
  • the preliminary smoothing of the rhombus can refer to grinding the four straight corners of the rhombus into rounded corners, and the rounded corners are still connected and transitioned by straight lines;
  • the deep smoothing of the rhombus can refer to grinding the rhombus into an oval shape .
  • “Smoothing” in the embodiments of the present application refers to depth smoothing.
  • a portion of the first isolation layer 14 is removed by a wet etching process, so as to smooth the sidewall of the shielding layer 153 .
  • the shielding layer 153 includes a plurality of discrete shielding grids, the shielding grids are located in the capacitor contact holes, and smoothing the sidewalls of the shielding layer 153 actually refers to smoothing the sidewalls of each shielding grid.
  • the masking grid is a parallelogram before smoothing, and the long side of the parallelogram extends along the second direction s2; after smoothing, the masking grid is an ellipse, and the long axis of the ellipse extends along the second direction s2.
  • each masking grid is a parallelogram before smoothing, and the short side of the parallelogram extends along the second direction; after smoothing, the masking grid is elliptical, and the long axis of the ellipse extends along the second direction.
  • the second conductive film 152 and the first isolation layer 14 are etched with a partial thickness, and the top surface of the etched first isolation layer 14 is higher than the first conductive layer 14 .
  • the top surface of the film 151 and the top surface of the etched second conductive film 152 are the same as the top surface of the masking grid; after the second conductive film 152 is etched, the masking layer 153 is removed.
  • the second conductive film is etched using the smoothed shielding layer as a mask, and the bottom surface of the etched second conductive film is the same as the top surface of the shielding lattice; or, the smoothed shielding layer is Mask, etch the second conductive film and the first conductive film of partial thickness, the bottom surface of the etched second conductive film is the same as the top surface of the shielding grid, and the top surface of the etched first conductive film is the same as the shielding grid Alternatively, the second conductive film and the first conductive film are etched using the smoothed shielding layer as a mask, and the bottom surface of the etched first conductive film is the same as the top surface of the shielding grid.
  • FIG. 21 is a schematic three-dimensional structure diagram of the structure shown in FIG. 20
  • FIG. 22 is a top view of the structure shown in FIG. 20 . 20 to 22, the second isolation layer 16 is formed.
  • a second isolation layer 16 filled between adjacent conductive films is formed, and the top surface of the second isolation layer 16 is flush with the top surface of the capacitor contact window.
  • the two isolation layers 16 and the first isolation layer 14 constitute an isolation layer.
  • the position of the second isolation layer 16 is related to the etching area of the previous etching process, and the second isolation layer 16 fills the grooves etched by the previous etching process.
  • the first conductive film 151 and the second conductive film 152 are distributed in a quadrangular shape, and in the direction perpendicular to the surface of the substrate, the central axis of the first conductive film 151 and the central axis of the second conductive film 152 coincide.
  • the central axis of the first conductive film 151 has an orthographic projection point 17 perpendicular to the direction of the substrate surface.
  • the distance d1 is smaller than the second distance d2 between adjacent second conductive films 152 , that is, the parasitic capacitance between adjacent second conductive films 152 is smaller than the parasitic capacitance between adjacent first conductive films 151 .
  • smoothing the conductive film is beneficial to reduce the parasitic capacitance between adjacent capacitive contact windows and improve the signal transmission performance of the capacitive contact windows.
  • the conductive film is etched through, so that the bottom surface pattern of the conductive film is the same as the top surface pattern of the conductive film, both of which are elliptical in the exemplary embodiment, which is beneficial to reduce the parasitic capacitance between adjacent conductive films.
  • the dislocation between the capacitive contact window and the active area is reduced, so that the When the area of the bottom surface of the window is the same, the contact area between the bottom surface of the capacitive contact window and the active region is larger, thereby making the signal transmission performance of the capacitive contact window better.
  • an embodiment of the present application further provides a memory, which can be manufactured by using the above-mentioned manufacturing method of the memory.
  • the memory includes: a substrate 10, an active region 101 located in the substrate 10, and a bit line structure 11 located on the substrate 10, the active region 101 extending along the first direction s1; a capacitive contact window, a capacitive contact The windows are located between adjacent bit line structures 11 , and at least one centerline of the bottom surface of the capacitive contact window extends along the second direction s2 , and the included angle between the second direction s2 and the first direction s1 is less than or equal to 45 degrees.
  • the bottom surface of the capacitive contact window is a parallelogram, the short side of the quadrilateral is close to the bit line structure 11, and the long side of the parallelogram extends along the second direction s2; in other embodiments, the bottom surface of the capacitive contact window is a parallelogram, a parallelogram The long side of the parallelogram is close to the bit line structure 11, and the short side of the parallelogram extends along the second direction s2.
  • the top surface of the capacitive contact window is an ellipse
  • the bottom surface is a parallelogram
  • the long axis of the ellipse extends along the second direction s2;
  • the long axis of the shape extends in the second direction.
  • the capacitive contact window includes a first pillar in contact with the active region 101 and a second pillar on the first pillar.
  • the top surface of the second pillar is elliptical and parallel to the surface of the substrate 10 .
  • the cross-sectional area of the second cylinder is smaller than the cross-sectional area of the first cylinder.
  • first column body and the second column body are divided by the size of the cross-sectional area; in other embodiments, the first column body and the second column body are divided by the material type.
  • the memory further includes: an isolation layer, the isolation layer is located between the bit line structures 11 and used to isolate adjacent capacitor contact windows, and the isolation layer covers the top surface of the first pillar exposed by the second pillar.
  • the isolation layer includes a first isolation layer 14 and a second isolation layer 16 located on the first isolation layer 14, and the second isolation layer 16 covers the top surface of the first pillar exposed by the second pillar.
  • the capacitive contact windows are arranged in a quadrangular shape.
  • the dislocation between the capacitive contact window and the active area is reduced, so that the When the area of the bottom surface of the window is the same, the contact area between the bottom surface of the capacitive contact window and the active region is larger, thereby making the signal transmission performance of the capacitive contact window better.

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Abstract

本申请实施例提供一种存储器及其制作方法，存储器包括：基底、位于所述基底内的有源区以及位于所述基底上的位线结构，所述有源区沿第一方向延伸；电容接触窗，所述电容接触窗位于相邻所述位线结构之间，所述电容接触窗的底面的至少一中心线沿第二方向延伸，所述第二方向与所述第一方向之间的夹角小于等于45度。本申请有利于提高存储器的信号传输性能。

Description

存储器及其制作方法
交叉引用
本申请基于申请号为202011103503.3、申请日为2020年10月15日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请实施例涉及半导体领域，特别涉及一种存储器及其制作方法。
背景技术
随着半导体集成电路器件特征尺寸的不断缩小，某一元件的尺寸变化会对半导体结构的整体性能造成较大的影响，例如位线结构的尺寸变化。
具体来说，增大位线结构的特征尺寸，则会压缩电容接触孔的空间以及减小电容接触窗的横截面积，而电容接触窗横截面积较小容易造成接触不良，进而导致存储电容失效；减小位线结构的特征尺寸减小，则容易导致位线结构因高宽比过大而发生坍塌。
如何在不改变特定元件特征尺寸的情况下优化半导体结构的性能，是当前研究的重点。
发明内容
本申请实施例提供一种存储器及其制作方法，有利于提高存储器的信号传输性能。
为解决上述问题，本申请实施例提供一种存储器，包括：基底、位于所述基底内的有源区以及位于所述基底上的位线结构，所述有源区沿第一方向延伸；电容接触窗，所述电容接触窗位于相邻所述位线结构之间，所述电容接触窗的底面的至少一中心线沿第二方向延伸，所述第二方向与所述第一方向之间的夹角小于等于45度。
相应地，本申请实施例还提供一种存储器的制作方法，包括：提供基底、位于所述基底内的有源区以及位于所述基底上的位线结构，所述有源区沿第一方向延伸；形成填充于相邻所述位线结构之间的牺牲层，以及形成覆盖所述牺牲层顶面的掩膜层，所述掩膜层用于形成隔离层；形成所述隔离层以及位于相邻所述隔离层之间的电容接触窗，所述电容接触窗的底面的至少一中心线沿第二方向延伸，所述第二方向与所述第一方向之间的夹角小于等于45度。
与现有技术相比，本申请实施例提供的技术方案具有以下优点：
上述技术方案中，通过控制电容接触窗底面至少一中心线的延伸方向与有源区的延伸方向的夹角小于等于预设值，减小电容接触窗与有源区的错位，使得在电容接触窗底面面积相同的情况下，电容接触窗底面与有源区的接触面积较大，进而使得电容接触窗的信号传输性能较好。
另外，将电容接触窗底面设置为长轴沿第二方向延伸的椭圆形，有利于增大相邻电容接触窗之间的间距，减小相邻电容接触窗之间的寄生电容，提高电容接触窗的信号传输速率。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，附图中具有相同参考数字标号的元件表示为类似的元件，除非有特别申明，附图中的图不构成比例限制。
图1至图23为本申请实施例提供的存储器的制作方法各步骤对应的结构示意图。
具体实施方式
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合附图对本申请的各实施例进行详细的阐述。然而，本领域的普通技 术人员可以理解，在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。
图1至图23为本申请实施例提供的存储器的制作方法各步骤对应的结构示意图。
图1为本申请实施例提供的存储器的制作方法一步骤对应的俯视图；图2为图1所示结构沿第一截面方向AA1的剖面结构示意图。
参考图1和图2，提供基底10、位于基底10内的有源区101、位于基底10上的位线结构11以及隔离膜114。
有源区101沿第一方向s1延伸。
位线结构11包括依次层叠的第一导电层111、第二导电层112以及顶层介质层113，第一导电层111与第二导电层112位于基底10内，第一导电层111与有源区101接触；位线结构11还包括底层介质层110，底层介质层110用于限定第一导电层111和第二导电层112的位置。
隔离膜114覆盖位线结构11顶面和侧壁，具体为覆盖顶层介质层113顶面和侧壁和覆盖底层介质层110侧壁，以及还覆盖基底10表面。
一些实施例中，基底10内还具有埋入式字线102，位线结构11沿第一坐标方向X延伸，埋入式字线102沿第二坐标方向Y延伸，第一坐标方向X垂直于第二坐标方向Y。在其他实施例中，在同一平面内，第一坐标方向与第二坐标方向之间的夹角小于90度。
参考图3，形成填充于相邻位线结构11之间的牺牲层12，以及形成覆盖牺牲层12顶面的结合层131。
在同一刻蚀工艺下，牺牲层12的材料与隔离膜114的材料之间具有较大的刻蚀选择比，以避免用于去除牺牲层12的刻蚀剂对隔离 膜114的材料造成刻蚀，进而保证位线结构11具有良好的信号传输性能。具体地，牺牲层12的材料可以是旋涂式电介质(Spin-on Dielectrics，SOD)，例如二氧化硅，隔离膜114的材料可以是氮化硅。
结合层131用于固定牺牲层12和后续形成的掩膜层，以避免掩膜层在工艺过程中发生偏移，从而提高掩膜层的掩膜精度，以及提高利用掩膜层形成的电容接触窗的位置精度，保证电容接触窗与有源区101之间具有较好的导电性能，进而使得存储器具有良好的信号传输性能。
其中，结合层131的材料可以是正硅酸乙酯(TEOS)。
参考图4，形成覆盖结合层131顶面的掩膜层13。
掩膜层13可以为单层结构，也可以为依次堆叠的多层结构。
一些实施例中，掩膜层13包括依次堆叠的第一子掩膜层132、第二子掩膜层133、第三子掩膜层134、第四子掩膜层135以及第五子掩膜层136。其中，第一子掩膜层132的材料可包括含碳化合物，第二子掩膜层133的材料可包括氮氧化硅，第三子掩膜层134可以是旋涂碳层(Spin-on Carbon，SOC)，第四子掩膜层135可以是硅氧基硬掩膜中间层结构(Si-O-based Hard Mask，SHB)，第五子掩膜层136为光刻胶层。
参考图5和图6，对第五子掩膜层136进行曝光，形成图案化开口136a。
图5为图4所示结构在进行曝光工艺后的俯视图；图6为图5所示结构沿第二截面方向BB2的剖面结构示意图。
曝光后的第五子掩膜层136由多条相互平行且分立的掩膜条组成，不同掩膜条的延伸方向相同；曝光后的第五子掩膜层136用于限定后续形成的电容接触窗的位置，具体为限定电容接触窗底面至少一中心线的延伸方向，即使得电容接触窗底面至少一中心线的延伸方向与掩膜条的延伸方向相同。一些实施例中，掩膜条沿第二方向s2延 伸，第二方向s2与第一方向s1之间的夹角小于等于45度，例如30度、20度或10度。如此，可控制电容接触窗底面至少一中心线的延伸方向与有源区的延伸方向的夹角小于等于预设值，从而减小电容接触窗底面与有源区的错位，使得在电容接触窗底面面积相同的情况下，电容接触窗底面与有源区的接触面积较大，进而使得电容接触窗的信号传输性能较好。
一些实施例中，在形成第五子掩膜层136之后，采用自对准双重成像工艺(Self-aligned Double Patterning，SADP)对牺牲层12进行刻蚀，以形成用于填充第一隔离层的隔离槽。自对准双重成像工艺的具体工艺步骤如下：
参考图7，刻蚀第三子掩膜层134和第四子掩膜层135，并形成第六子掩膜层137。
具体地，通过图案化开口136a(参考图6)对第三子掩膜层134和第四子掩膜层135进行刻蚀，且在刻穿第三子掩膜层134而暴露出第二子掩膜层133之后，去除剩余的第五子掩膜层136(参考图6)；采用沉积工艺，形成第六子掩膜层137，第六子掩膜层137覆盖第四子掩膜层135顶面和侧壁、覆盖第三子掩膜层134侧壁以及覆盖第二子掩膜层133顶面。
一些实施例中，第六子掩膜层137内具有预留槽137a。
参考图8和图9，形成第七子掩膜层138和隔离槽14a，隔离槽14a用于填充第一隔离层。
一些实施例中，利用第七子掩膜层138、第三子掩膜层134和第四子掩膜层135依次对第六子掩膜层137、第二子掩膜层133、第一子掩膜层132、结合层131、牺牲层12以及底层介质层110进行刻蚀，形成暴露基底10表面的隔离槽14a；在形成隔离槽14a之后，可采用第一平坦化工艺去除第二子掩膜层133、第三子掩膜层134、第四子掩膜层135、第六子掩膜层137以及第七子掩膜层138，从而提高存 储器的制作效率。
在其他实施例中，也可以不刻蚀底层介质层，即隔离槽暴露底层介质层表面，且将隔离槽暴露的部分底层介质层作为后续形成的隔离层的一部分，如此，有利于减少工艺步骤，缩短工艺周期。
由于第一子掩膜层132通过结合层131与牺牲层12固定，固定强度较高，直接采用平坦化工艺去除第一子掩膜层132可能会导致与第一子掩膜层132间接连接的牺牲层12因缺少支撑而发生坍塌，或者使得牺牲层12具有内部缺陷。
参考图10和图11，去除第一子掩膜层132以及填充隔离槽14a以形成第一隔离层14。
一些实施例中，在进行平坦化工艺之后，采用刻蚀工艺去除第一子掩膜层132，避免第一掩膜层132的去除破坏中间结构或者留下工艺缺陷，保证最终制成的存储器具有较高的良率。
参考图12，进行第二平坦化工艺，降低第一隔离层14的高度。
一些实施例中，可通过降低第一隔离层14的高度限定后续形成的电容接触窗的高度，避免第一隔离层14和电容接触窗因高宽比过大而发生坍塌、断裂等结构缺陷，保证最终形成的存储器具有良好的结构稳定性。
一些实施例中，在降低第一隔离层14高度的同时，去除结合层131。
参考图13和图14，去除剩余牺牲层12(参考图12)，以及去除位于第一隔离层14暴露的部分底层介质层110，形成暴露至少部分有源区101表面的电容接触孔15a。
一些实施例中，可采用湿法刻蚀工艺去除剩余的位于相邻第一隔离层14之间的牺牲层12，以及可采用无掩膜干法刻蚀工艺去除第一隔离层14暴露的部分底层介质层110。
需要说明的是，在采用无掩膜干法刻蚀工艺刻蚀底层介质层110 的过程中，第一隔离层14也会被刻蚀，即第一隔离层14的高度会进一步降低，因此，若需要使得最终形成的电容接触孔15a具有预设深度，则需要在第二平坦化工艺中预留高度大于预设深度的第一隔离层14，实际预留高度与预设深度之间的差值等于在垂直于基底10方向上的底层介质层110的厚度。
参考图15至图17，在电容接触孔15a(参考图14)内形成导电膜和遮蔽层153，遮蔽层153位于导电膜上。
一些实施例中，导电膜包括第一导电膜151和第二导电膜152，第一导电膜151与有源区101相接触，第二导电膜152位于第一导电膜151上。第一导电膜151和第二导电膜152都可以通过先填充满电容接触孔15a再进行干法刻蚀工艺形成。
举例来说，在形成第一导电膜151之后，可采用沉积工艺形成填充满电容接触孔14a的第二初始导电膜152a，并可采用干法刻蚀工艺刻蚀去除部分第二初始导电膜152a，剩余的第二初始导电膜152a作为第二导电膜152。
一些实施例中，可通过控制第一导电膜151和第二导电膜152的材料，降低由第一导电膜151和第二导电膜152构成的电容接触窗与有源区101之间的接触电阻，使得最终形成的存储器具有良好的信号传输性能。
具体地，有源区101的材料可包括单晶硅，第一导电膜151的材料可包括多晶硅，第二导电膜152的材料可包括钨。
一些实施例中，由于掩膜条的限定，第一导电膜151底面至少一中心线沿第二方向延伸。具体地，示例实施例中，第一导电膜151底面为平行四边形，且平行四边形的短边靠近位线结构，由于掩膜条的限定，平行四边形的长边沿第二方向s2延伸，即平行于长边的中心线沿第二方向延伸；在其他实施例中，第一导电膜底面为平行四边形，平行四边形的长边靠近位线结构，由于掩膜条的限定，平行于短边的 中心线沿第二方向延伸。
一些实施例中，在同一刻蚀工艺下，遮蔽层153的材料与第一隔离层14的材料的刻蚀选择比大于50。如此，有利于保证在采用湿法刻蚀工艺刻蚀第一隔离层14的过程中，刻蚀剂能够平滑遮蔽层153的侧壁，且不会造成过刻蚀，保证平滑后的遮蔽层153具有精确遮蔽效果。
需要说明的是，“平滑”通常包括两种程度：第一，初步平滑，即将直角磨成圆角；第二，深度平滑，即进一步将直线过渡磨成弧线过渡。具体来说，对菱形进行初步平滑，可指代将菱形的四个直线角磨成圆角，圆角之间依旧通过直线连接过渡；对菱形进行深度平滑，可指代将菱形磨成椭圆形。本申请实施例中的“平滑”指的是深度平滑。
参考图18，采用湿法刻蚀工艺去除部分第一隔离层14，以平滑遮蔽层153的侧壁。
一些实施例中，遮蔽层153包括多个分立的遮蔽格，遮蔽格位于电容接触孔内，平滑遮蔽层153的侧壁实际指的是平滑每一遮蔽格的侧壁。
一些实施例中，遮蔽格在平滑之前为平行四边形，平行四边形的长边沿第二方向s2延伸；在进行平滑之后，遮蔽格为椭圆形，椭圆形的长轴沿第二方向s2延伸。
在其他实施例中，每一遮蔽格在平滑之前为平行四边形，且平行四边形的短边沿第二方向延伸；在进行平滑之后，遮蔽格为椭圆形，椭圆形的长轴沿第二方向延伸。
参考图19，以平滑后的遮蔽层153(参考图18)为掩膜，刻蚀至少部分导电膜，剩余导电膜作为电容接触窗。
一些实施例中，以平滑后的遮蔽层153为掩膜，刻蚀部分厚度的第二导电膜152以及第一隔离层14，刻蚀后的第一隔离层14的顶面 高于第一导电膜151的顶面，刻蚀后的第二导电膜152的顶面与遮蔽格的顶面相同；在刻蚀第二导电膜152之后，去除遮蔽层153。
在其他实施例中，以平滑后的遮蔽层为掩膜，刻蚀第二导电膜，刻蚀后的第二导电膜的底面与遮蔽格的顶面相同；或者，以平滑后的遮蔽层为掩膜，刻蚀第二导电膜和部分厚度的第一导电膜，刻蚀后的第二导电膜的底面与遮蔽格的顶面相同，刻蚀后的第一导电膜的顶面与遮蔽格的顶面相同；或者，以平滑后的遮蔽层为掩膜，刻蚀第二导电膜和第一导电膜，刻蚀后的第一导电膜的底面与遮蔽格的顶面相同。
图21为图20所示结构的立体结构示意图，图22为图20所示结构的俯视图。参考图20至图22，形成第二隔离层16。
一些实施例中，在刻蚀第一隔离层14之后，形成填充于相邻导电膜之间的第二隔离层16，第二隔离层16的顶面与电容接触窗的顶面平齐，第二隔离层16与第一隔离层14构成隔离层。
第二隔离层16的位置与前一刻蚀工艺的刻蚀区域有关，第二隔离层16填充满前一刻蚀工艺刻蚀出的凹槽。
一些实施例中，参考图23，第一导电膜151和第二导电膜152呈四边形分布，在垂直于基底表面的方向上，第一导电膜151的中心轴与第二导电膜152的中心轴重合。
一些实施例中，第一导电膜151的中心轴具有垂直于基底表面方向的正投影点17，在相邻正投影点17的连线方向上，相邻第一导电膜151之间的第一间距d1小于相邻第二导电膜152之间的第二间距d2，即相邻第二导电膜152之间的寄生电容小于相邻第一导电膜151之间的寄生电容。换句话说，对导电膜进行平滑，有利于降低相邻电容接触窗之间的寄生电容，提高电容接触窗的信号传输性能。
一些实施例中，仅对部分厚度的导电膜进而刻蚀，以保证导电膜底面与有源区之间具有较大的接触面积，从而使得导电膜与有源区之 间具有较好的信号传输性能。在其他实施例中，刻穿导电膜，以使导电膜底面图案与导电膜顶面图案相同，示例实施例中都为椭圆形，如此，有利于减小相邻导电膜之间的寄生电容。
一些实施例中，通过控制电容接触窗底面至少一中心线的延伸方向与有源区的延伸方向的夹角小于等于预设值，减小电容接触窗与有源区的错位，使得在电容接触窗底面面积相同的情况下，电容接触窗底面与有源区的接触面积较大，进而使得电容接触窗的信号传输性能较好。
相应地，本申请实施例还提供一种存储器，可采用上述存储器的制作方法制成。
参考图21和图22，存储器包括：基底10、位于基底10内的有源区101以及位于基底10上的位线结构11，有源区101沿第一方向s1延伸；电容接触窗，电容接触窗位于相邻位线结构11之间，电容接触窗的底面的至少一中心线沿第二方向s2延伸，第二方向s2与第一方向s1之间的夹角小于等于45度。
一些实施例中，电容接触窗底面为平行四边形，四边形的短边靠近位线结构11，平行四边形的长边沿第二方向s2延伸；在其他实施例中，电容接触窗底面为平行四边形，平行四边形的长边靠近位线结构11，平行四边形的短边沿第二方向s2延伸。
一些实施例中，电容接触窗顶面为椭圆形，底面为平行四边形，椭圆形的长轴沿第二方向s2延伸；在其他实施例中，电容接触窗顶面和底面都为椭圆形，椭圆形的长轴沿第二方向延伸。
一些实施例中，电容接触窗包括与有源区101接触的第一柱体和位于第一柱体上的第二柱体，第二柱体的顶面为椭圆形，在平行于基底10表面的平面内，第二柱体的截面积小于第一柱体的截面积。
一些实施例中，第一柱体与第二柱体通过截面积的大小进行划分；在其他实施例中，第一柱体与第二柱体通过材料类型进行划分。
一些实施例中，存储器还包括：隔离层，隔离层位于位线结构11之间，且用于隔离相邻电容接触窗，隔离层覆盖第一柱体被第二柱体暴露出的顶面。具体地，隔离层包括第一隔离层14和位于第一隔离层14上的第二隔离层16，第二隔离层16覆盖第一柱体被第二柱体暴露出的顶面。
一些实施例中，电容接触窗呈四边形排列。
一些实施例中，通过控制电容接触窗底面至少一中心线的延伸方向与有源区的延伸方向的夹角小于等于预设值，减小电容接触窗与有源区的错位，使得在电容接触窗底面面积相同的情况下，电容接触窗底面与有源区的接触面积较大，进而使得电容接触窗的信号传输性能较好。
本领域的普通技术人员可以理解，上述各实施方式是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。任何本领域技术人员，在不脱离本申请的精神和范围内，均可作各自更动与修改，因此本申请的保护范围应当以权利要求限定的范围为准。

Claims (13)

  1. 一种存储器，包括：
    基底、位于所述基底内的有源区以及位于所述基底上的位线结构，所述有源区沿第一方向延伸；
    电容接触窗，所述电容接触窗位于相邻所述位线结构之间，所述电容接触窗的底面的至少一中心线沿第二方向延伸，所述第二方向与所述第一方向之间的夹角小于等于45度。
  2. 根据权利要求1所述的存储器，其中，所述电容接触窗底面为平行四边形，所述平行四边形的短边靠近所述位线结构，所述平行四边形的长边沿所述第二方向延伸。
  3. 根据权利要求1所述的存储器，其中，所述电容接触窗底面为平行四边形，所述平行四边形的长边靠近所述位线结构，所述平行四边形的短边沿所述第二方向延伸。
  4. 根据权利要求1所述的存储器，其中，所述电容接触窗底面为椭圆形，所述椭圆形的长轴沿所述第二方向延伸。
  5. 根据权利要求1所述的存储器，其中，所述电容接触窗顶面为椭圆形，所述椭圆形的长轴沿所述第二方向延伸。
  6. 根据权利要求5所述的存储器，其中，所述电容接触窗包括与所述有源区接触的第一柱体和位于所述第一柱体上的第二柱体，所述第二柱体的顶面为所述椭圆形，在平行于所述基底表面的平面内，所述第二柱体的截面积小于所述第一柱体的截面积。
  7. 根据权利要求6所述的存储器，其中，还包括：隔离层，所述隔离层位于相邻所述位线结构之间，且用于隔离相邻所述电容接触窗，所述隔离层覆盖所述第一柱体被所述第二柱体暴露出的顶面。
  8. 根据权利要求5所述的存储器，其中，所述电容接触窗呈四边形排列。
  9. 一种存储器的制作方法，包括：
    提供基底、位于所述基底内的有源区以及位于所述基底上的位线结构，所述有源区沿第一方向延伸；
    形成填充于相邻所述位线结构之间的牺牲层，以及形成覆盖所述牺牲层顶面的掩膜层，所述掩膜层用于形成隔离层；
    形成所述隔离层以及位于相邻所述隔离层之间的电容接触窗，所述电容接触窗的底面的至少一中心线沿第二方向延伸，所述第二方向与所述第一方向之间的夹角小于等于45度。
  10. 根据权利要求9所述的存储器的制作方法，其中，形成所述电容接触窗的工艺步骤包括：形成第一隔离层以及位于相邻所述第一隔离层之间的导电膜和遮蔽层，所述遮蔽层位于所述导电膜上；采用湿法刻蚀工艺去除部分所述第一隔离层，以平滑所述遮蔽层的侧壁；以平滑后的所述遮蔽层为掩膜，刻蚀至少部分所述导电膜，剩余所述导电膜作为所述电容接触窗。
  11. 根据权利要求10所述的存储器的制作方法，其中，在同一刻蚀工艺中，刻蚀至少部分所述导电膜以及至少部分所述第一隔离层；在刻蚀所述第一隔离层之后，还包括：形成填充于相邻所述导电膜之间的第二隔离层，所述第二隔离层的顶面与所述电容接触窗的顶面平齐，所述第二隔离层与所述第一隔离层构成所述隔离层。
  12. 根据权利要求10所述的存储器的制作方法，其中，所述刻蚀至少部分所述导电膜，包括：刻穿所述导电膜，以使所述导电膜底面图案与所述导电膜顶面图案相同。
  13. 根据权利要求10所述的存储器的制作方法，其中，平滑前的所述遮蔽层的顶面为平行四边形，平滑后的所述遮蔽层的顶面为椭圆形。
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