WO2022073303A1 - 阵列基板及其制作方法、显示装置 - Google Patents

阵列基板及其制作方法、显示装置 Download PDF

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WO2022073303A1
WO2022073303A1 PCT/CN2020/139979 CN2020139979W WO2022073303A1 WO 2022073303 A1 WO2022073303 A1 WO 2022073303A1 CN 2020139979 W CN2020139979 W CN 2020139979W WO 2022073303 A1 WO2022073303 A1 WO 2022073303A1
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layer
oxide
array substrate
disposed
oxide semiconductor
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French (fr)
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张军
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TCL China Star Optoelectronics Technology Co Ltd
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TCL China Star Optoelectronics Technology Co Ltd
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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present application generally relates to the field of display technology, and more particularly, to an array substrate, a manufacturing method thereof, and a display device.
  • IGZO Indium Gallium Zinc Oxide: Indium Gallium Zinc Oxide
  • the IGZO layer in the IGZO thin film transistor is sensitive to the environment, especially when the IGZO layer is exposed to air, its surface defects can easily absorb H 2 O and O 2 in the air, resulting in the increase of oxygen vacancies in the IGZO layer. , thereby increasing the carrier concentration, which will ultimately affect the electrical properties of the IGZO thin-film transistor device.
  • the IGZO layer is easily etched by the etchant, resulting in unstable processes such as disconnection.
  • the present application proposes an array substrate, a manufacturing method thereof, and a display device, which can effectively reduce the interference of acid, water, oxygen, etc. in the external environment on the IGZO layer, and effectively prevent the IGZO layer during wet etching.
  • the problem of process instability such as disconnection is caused by excessive etching of the layer.
  • an array substrate which includes:
  • a barrier layer disposed on the oxide semiconductor layer
  • a gate insulating layer disposed on the blocking layer and the oxide protective layer
  • the gate is disposed on the gate insulating layer.
  • a channel is formed on the oxide protection layer, and the orthographic projection of the blocking layer on the substrate at least covers the orthographic projection of the channel on the substrate.
  • the array substrate further includes:
  • a source electrode and a drain electrode are disposed on the interlayer dielectric layer, and the source electrode and the drain electrode are respectively electrically connected to the oxide protection layer through the interlayer dielectric layer.
  • the material of the oxide semiconductor layer is C-axis aligned crystalline indium gallium zinc oxide.
  • the material of the oxide protective layer is indium tin oxide.
  • the material of the barrier layer is indium gallium zinc tin oxide.
  • the oxide semiconductor layer has a film thickness of 100-1000 ⁇ .
  • the barrier layer has a film thickness of 10-200 ⁇ .
  • Another aspect of the present application provides a method for fabricating an array substrate, comprising the following steps:
  • a gate insulating layer is formed on the barrier layer and the oxide protective layer, and a gate is formed on the gate insulating layer.
  • the oxide semiconductor layer, the barrier layer, and the oxide protective layer are continuously formed and combined in different cavities in the same device.
  • forming an oxide semiconductor layer on the substrate includes:
  • An indium gallium zinc oxide layer is formed on the substrate, and a high temperature process is used to convert the indium gallium zinc oxide in the indium gallium zinc oxide layer into a C-axis aligned crystalline indium gallium zinc oxide to form a material
  • the oxide semiconductor layer is a C-axis aligned crystalline indium gallium zinc oxide.
  • forming an oxide protective layer on the barrier layer includes:
  • a channel is formed on the indium tin oxide layer to form the oxide protective layer.
  • a display device including a device body and an array substrate disposed on the device body, the array substrate comprising:
  • a barrier layer disposed on the oxide semiconductor layer
  • a gate insulating layer disposed on the blocking layer and the oxide protective layer
  • the gate is disposed on the gate insulating layer.
  • a channel is formed on the oxide protection layer, and the orthographic projection of the blocking layer on the substrate at least covers the orthographic projection of the channel on the substrate.
  • the array substrate further includes:
  • a source electrode and a drain electrode are disposed on the interlayer dielectric layer, and the source electrode and the drain electrode are respectively electrically connected to the oxide protection layer through the interlayer dielectric layer.
  • the material of the oxide semiconductor layer is C-axis aligned crystalline indium gallium zinc oxide.
  • the material of the oxide protective layer is indium tin oxide.
  • the material of the barrier layer is indium gallium zinc tin oxide.
  • the oxide semiconductor layer has a film thickness of 100-1000 ⁇ .
  • the barrier layer has a film thickness of 10-200 ⁇ .
  • the oxide semiconductor layer is formed into a film
  • a barrier layer and an oxide protective layer are formed on the surface of the film layer, which can effectively reduce the acid, water and oxygen in the external environment.
  • the interference of other factors maintain the original characteristics of the thin film transistor device, make the thin film transistor device stable, efficient and long life in the working process, which helps to improve the problem that the conventional process cannot stably guarantee its electrical performance.
  • the barrier layer can also effectively prevent the problem of process instability such as disconnection caused by excessive etching of the oxide semiconductor layer during wet etching, thereby stabilizing the electrical properties of different batches of array substrates and improving the electronic properties of the array substrates. Mobility and device stability.
  • FIG. 1 is a schematic cross-sectional view of an array substrate according to an embodiment of the present application
  • FIG. 2 is a schematic flowchart of a method for fabricating an array substrate according to an embodiment of the present application.
  • 3-10 are schematic cross-sectional views illustrating a process of fabricating an array substrate according to an embodiment of the present application.
  • an embodiment or “an embodiment” is intended to indicate that a particular configuration, structure, or feature described with respect to the embodiment is included in at least one embodiment.
  • phrases such as “in an embodiment” or “in an embodiment” that may be present in various places in this specification do not necessarily refer to the same embodiment, but may instead refer to a different embodiment.
  • the particular configurations, structures or features defined in this specification may be combined in any suitable manner even other than those presented.
  • Reference numerals and spatial references (such as “upper,” “lower,” etc.) are used herein for convenience only, and therefore do not limit the scope of protection or the scope of the embodiments.
  • FIG. 1 is a schematic cross-sectional view of an array substrate according to an embodiment of the present application
  • FIG. 2 is a schematic flowchart of a manufacturing method of an array substrate according to an embodiment of the present application
  • FIGS. 3-10 are manufacturing methods according to an embodiment of the present application. Schematic cross-sectional schematic diagram of the process of the array substrate.
  • the present application provides an array substrate, including: a substrate 101 ; an oxide semiconductor layer 102 , disposed on the substrate 101 ; a barrier layer 103 , disposed on the oxide semiconductor layer 102 ; and an oxide protective layer 104 , arranged on the barrier layer 103; the gate insulating layer 105, arranged on the barrier layer 103 and the oxide protective layer 104; the gate 106, arranged on the gate insulating layer 105; the interlayer dielectric layer 107, arranged on the gate 106, the oxide protective layer 104 and the substrate 101; and the source electrode 108 and the drain electrode 109, which are arranged on the interlayer dielectric layer 107, and the source electrode 108 and the drain electrode 109 pass through the interlayer dielectric layer 107 and the oxide protective layer respectively.
  • the substrate 101 is transparent, and is made of glass, for example. Although only a portion of the substrate 101 is shown in FIG. 1, it should be understood that the substrate 101 may have a width of, for example, several centimeters to several meters.
  • an oxide semiconductor layer 102 is provided on the substrate 101 .
  • the material of the oxide semiconductor layer 102 is C-Axis Aligned Crystal Indium Gallium Zinc Oxide (CAAC-IGZO: C-Axis Aligned Crystal Indium Gallium Zinc Oxide). That is, the CAAC-IGZO layer corresponds to an example of the oxide semiconductor layer 102 in the present application.
  • the oxide semiconductor layer 102 has a film thickness of 100-1000 ⁇ .
  • CAAC-IGZO Compared with amorphous IGZO in the prior art, CAAC-IGZO has smaller resistance, fewer internal crystal defects, extremely low off current, and can greatly reduce power consumption, so it can effectively improve electron mobility and device stability.
  • any processing technique suitable for the particular material to be deposited such as Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), electroplating, etc., can be used to form the substrate 101 .
  • various components eg, the oxide semiconductor layer 102 and those described below.
  • photolithographic and etching processes can be used to shape and size the various features on the substrate 101 such that the features are formed on the substrate, as is well known to those skilled in the art 101 above the selected area.
  • a barrier layer 103 is provided on the oxide semiconductor layer 102 .
  • the material of the barrier layer 103 is IGZTO (Indium Gallium Zinc Tin Oxide: Indium Gallium Zinc Tin Oxide). That is, the IGZTO layer corresponds to an example of the barrier layer 103 in the present application.
  • the film thickness of the barrier layer 103 is 10-200 ⁇ .
  • an oxide protective layer 104 is provided on the barrier layer 103 .
  • the material of the oxide protection layer 104 is ITO (Indium Tin Oxide), that is, the ITO layer is equivalent to an example of the oxide protection layer 104 in the present application.
  • the oxide protective layer 104 has a film thickness of 100-1000 ⁇ . Since ITO and IGZTO have a good bonding force, in the subsequent process, using ITO to contact the source-drain metal material can effectively reduce the contact resistance at the source and drain, thereby improving the overall mobility of electrons in the channel of the array substrate and stability.
  • a channel is provided on the oxide protective layer 104 , and the orthographic projection of the barrier layer 103 on the substrate 101 covers the orthographic projection of the channel on the substrate 101 . Therefore, in the process of etching the oxide protective layer 104, the barrier layer 103 can effectively prevent the problem of process instability such as disconnection caused by excessive etching of the oxide semiconductor layer 102 during wet etching.
  • barrier layer 103 covers the oxide semiconductor layer 102 in the drawings, as long as the orthographic projection of the barrier layer 103 on the substrate 101 covers the orthographic projection of the channel on the substrate 101 , the barrier layer 103 may only cover A part of the oxide semiconductor layer 102 .
  • a gate insulating layer 105 is provided on the barrier layer 103 and the oxide protective layer 104 , and the material of the gate insulating layer 105 is, for example, SiOx or Al 2 O 3 /SiNx or the like.
  • a gate electrode 106 is provided on the gate insulating layer 105, and the material of the gate electrode 106 is, for example, a metal composite film such as Mo or Al/Cu.
  • an interlayer dielectric layer 107 is provided on the gate electrode 106 , the oxide protective layer 104 and the substrate 101 , and the material of the interlayer dielectric layer 107 is, for example, SiOx or Al 2 O 3 /SiNx or the like.
  • a source electrode 108 and a drain electrode 109 are provided on the interlayer dielectric layer 107 , and the source electrode 108 and the drain electrode 109 are respectively electrically connected to the oxide protective layer 104 through the interlayer dielectric layer 107 .
  • the materials of the gate electrode 106 , the source electrode 108 , and the drain electrode 109 include but are not limited to metal materials such as Mo, Al, Cu, and MoTi.
  • the present application uses the above-mentioned array substrate to form a barrier layer 103 and an oxide protective layer 104 on the surface of the oxide semiconductor layer 102 after film formation, which can effectively reduce the interference of factors such as acid, water, and oxygen in the external environment. , to maintain the original characteristics of the IGZO thin film transistor device, so that the IGZO thin film transistor device is stable, efficient and long-lived in the working process, which helps to improve the problem that the conventional process cannot stably guarantee its electrical performance.
  • the barrier layer 103 can also effectively prevent the problem of process instability such as disconnection caused by excessive etching of the oxide semiconductor layer 102 during wet etching.
  • the present application also provides a method for fabricating an array substrate. Now described in detail below with reference to Figures 2-10, the method includes the following steps:
  • a substrate 101 is provided, and an oxide semiconductor layer 102 is formed on the substrate 101 .
  • the oxide semiconductor layer 102 can be formed by any suitable method.
  • an IGZO layer is first deposited on the substrate 101 by a PVD process, and the film-forming temperature of IGZO is 300-1000° C. to ensure the crystallinity of IGZO so as to improve its electrical properties, and then a high temperature process is used to make the IGZO layer This translates into an oxide semiconductor layer 102 of material C-axis aligned crystalline indium gallium zinc oxide.
  • an oxide protective layer 104 is formed on the barrier layer 103 .
  • the oxide protection layer 104 can be deposited by a PVD process. In this process, the film formation temperature of the oxide protection layer 104 is 25-100° C., so that the crystallinity of the ITO layer can be reduced to facilitate the subsequent etching process.
  • the oxide semiconductor layer 102 , the barrier layer 103 , and the oxide protective layer 104 are continuously formed and combined in different cavities in the same device.
  • the barrier layer 103 and the oxide protective layer 104 are formed on the oxide semiconductor layer 102 after the oxide semiconductor layer 102 is formed in a vacuum environment, it can be avoided that in the subsequent production process, the length of the parking time during the transportation process and the inconvenience in the environment
  • the physical properties of CAAC-IGZO are affected by the increase of certain factors. This is because both the oxide protective layer 104 and the barrier layer 103 can effectively reduce the influence of H 2 O and O 2 in the air on the physical properties of the oxide semiconductor layer 102 during transportation or parking.
  • a channel is formed on the oxide protection layer 104 , for example, by yellow photolithography, and then the oxide protection layer 104 is etched with aluminate to form the channel, because the barrier layer 103 The etching rate in aluminate is extremely low, so alumina can block the etching of the oxide semiconductor layer 102, thereby forming a better etching interface. Then, photoresist is applied to perform photolithography, and then the sides of the barrier layer 103 and the oxide semiconductor layer 102 are uniformly etched (not shown).
  • a gate insulating layer 105 is formed on the barrier layer 103 and the oxide protective layer 104, for example, by CVD deposition of SiOx or Al2O3 /SiNx or a composite film layer.
  • a metal composite film layer such as Mo or Al/Cu is deposited by PVD to form the gate electrode 106 .
  • a pattern is formed through a yellow light and etching process, wherein the gate insulating layer 105 and the gate 106 are etched into a desired pattern.
  • the interlayer dielectric layer 107 is formed by depositing, for example, a film layer such as SiOx or Al 2 O 3 /SiNx by CVD.
  • through holes for the source electrode 108 and the drain electrode 109 are formed in the interlayer dielectric layer 107 by, for example, yellow light and etching, so that the source electrode is formed by depositing a metal composite film such as Mo or Al/Cu by PVD, for example.
  • 108 and the drain 109 are respectively electrically connected to the oxide protective layer 104 through the interlayer dielectric layer 107 .
  • an array substrate as shown in FIG. 1 is formed.
  • the present application also provides a display device including the above-mentioned array substrate.
  • the present application provides an array substrate, a manufacturing method thereof, and a display device.
  • a barrier layer and an oxide protective layer are formed on the surface of the film layer, which can effectively reduce the exposure to the external environment.
  • the interference of factors such as acid, water, oxygen, etc. maintains the original characteristics of the thin-film transistor device, making the thin-film transistor device stable, efficient and long-lived in the working process, which helps to improve the problem that the conventional process cannot stably guarantee its electrical performance.
  • the barrier layer can also effectively prevent the problem of process instability such as disconnection caused by excessive etching of the oxide semiconductor layer during wet etching, thereby stabilizing the electrical properties of array substrates in different batches and improving the electronic properties of the array substrate. Mobility and device stability.

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Abstract

本申请提供了一种阵列基板及其制作方法、显示装置，所述阵列基板包括：基板；氧化物半导体层，设置于所述基板上；阻挡层，设置于所述氧化物半导体层上；氧化物保护层，设置于所述阻挡层上；栅极绝缘层，设置于所述阻挡层和所述氧化物保护层上；以及栅极，设置于所述栅极绝缘层上。由此，本申请能够稳定不同批次的阵列基板的电学性能，并提高阵列基板的电子迁移率和器件稳定性。

Description

阵列基板及其制作方法、显示装置 技术领域
本申请大体上涉及显示技术领域，并且更具体地涉及阵列基板及其制作方法、显示装置。
 背景技术
随着液晶显示器尺寸的不断增大，驱动频率也不断提高，传统的非晶硅薄膜晶体管由于其电子迁移率而很难满足需求。相比于传统的非晶硅薄膜晶体管，IGZO（Indium Gallium Zinc Oxide：铟镓锌氧化物）薄膜晶体管具备较好的物理性质，包括低工艺温度带来的高电子迁移率、优良的均匀性、以及表面平坦性等，这可以为显示技术领域的发展提供帮助。
然而，由于IGZO薄膜晶体管中的IGZO层对环境比较敏感，特别是在IGZO层暴露于空气中时，其表面缺陷容易吸收空气中的H 2O和O 2，而导致IGZO层中的氧空缺增加，从而增加载流子的浓度，最终会影响IGZO薄膜晶体管器件的电学性能。另外，在形成IGZO薄膜晶体管的其它膜层时，IGZO层容易受到刻蚀液的过度刻蚀，从而造成断线等工艺不稳定的问题。
技术问题
鉴于上述内容，本申请提出了一种阵列基板及其制作方法、显示装置，以有效地降低外界环境中的酸、水、氧气等对IGZO层的干扰，并有效地预防湿法蚀刻时对IGZO层过度刻蚀而造成断线等工艺不稳定的问题。
 技术解决方案
为实现上述目的及其它相关目的，本申请的一方面提供了一种阵列基板，其包括：
基板；
氧化物半导体层，设置于所述基板上；
阻挡层，设置于所述氧化物半导体层上；
氧化物保护层，设置于所述阻挡层上；
栅极绝缘层，设置于所述阻挡层和所述氧化物保护层上；以及
栅极，设置于所述栅极绝缘层上。
在一些实施例中，所述氧化物保护层上设有一沟道，所述阻挡层在所述基板上的正投影至少覆盖所述沟道在所述基板上的正投影。
在一些实施例中，所述阵列基板还包括：
层间介质层，设置于所述栅极、所述氧化物保护层和所述基板上；以及
源极和漏极，设置于所述层间介质层上，所述源极和漏极分别穿过所述层间介质层与所述氧化物保护层电连接。
在一些实施例中，所述氧化物半导体层的材料为C轴对齐的结晶铟镓锌氧化物。
在一些实施例中，所述氧化物保护层的材料为氧化铟锡。
在一些实施例中，所述阻挡层的材料为铟镓锌锡氧化物。
在一些实施例中，所述氧化物半导体层的膜厚为100-1000Å。
在一些实施例中，所述阻挡层的膜厚为10-200Å。
本申请的另一个方面提供了一种阵列基板的制作方法，包括以下步骤：
提供一基板，在所述基板上形成氧化物半导体层；
在所述氧化物半导体层上形成阻挡层；
在所述阻挡层上形成氧化物保护层；以及
在所述阻挡层和所述氧化物保护层上形成栅极绝缘层，在所述栅极绝缘层上形成栅极。
在一些实施例中，所述氧化物半导体层、所述阻挡层、以及所述氧化物保护层在同一装置中的不同腔体连续地成膜相结合。
在一些实施例中，在所述基板上形成氧化物半导体层包括：
在所述基板上形成铟镓锌氧化物层，并通过一高温制程使所述铟镓锌氧化物层中的铟镓锌氧化物转换为C轴对齐的结晶铟镓锌氧化物，以形成材料为C轴对齐的结晶铟镓锌氧化物的所述氧化物半导体层。
在一些实施例中，所述在所述阻挡层上形成氧化物保护层包括：
在所述阻挡层上形成氧化铟锡层；
在所述氧化铟锡层上形成一沟道，以形成所述氧化物保护层。
本申请的又一个方面提供了一种显示装置，其包括装置主体以及设置于所述装置主体的阵列基板，所述阵列基板包括：
基板；
氧化物半导体层，设置于所述基板上；
阻挡层，设置于所述氧化物半导体层上；
氧化物保护层，设置于所述阻挡层上；
栅极绝缘层，设置于所述阻挡层和所述氧化物保护层上；以及
栅极，设置于所述栅极绝缘层上。
在一些实施例中，所述氧化物保护层上设有一沟道，所述阻挡层在所述基板上的正投影至少覆盖所述沟道在所述基板上的正投影。
在一些实施例中，所述阵列基板还包括：
层间介质层，设置于所述栅极、所述氧化物保护层和所述基板上；以及
源极和漏极，设置于所述层间介质层上，所述源极和漏极分别穿过所述层间介质层与所述氧化物保护层电连接。
在一些实施例中，所述氧化物半导体层的材料为C轴对齐的结晶铟镓锌氧化物。
在一些实施例中，所述氧化物保护层的材料为氧化铟锡。
在一些实施例中，所述阻挡层的材料为铟镓锌锡氧化物。
在一些实施例中，所述氧化物半导体层的膜厚为100-1000Å。
在一些实施例中，所述阻挡层的膜厚为10-200Å。
 有益效果
本申请通过上述的阵列基板及其制作方法、显示装置，在氧化物半导体层成膜后在其膜层表面生成阻挡层和氧化物保护层，可以有效地降低外界环境中的酸、水、氧气等因素的干扰，保持薄膜晶体管器件原有的特性，使得薄膜晶体管器件在工作过程中稳定，高效以及长寿命，有助于改善常规制程无法稳定保障其电学性能的问题。而且阻挡层还可以有效地预防湿法蚀刻时对氧化物半导体层过度刻蚀而造成断线等工艺不稳定的问题，从而能够稳定不同批次的阵列基板的电学性能，并提高阵列基板的电子迁移率和器件稳定性。
 附图说明
本申请的其它目的、特征和优点将参照附图来从随后的详细描述中清楚地显现，应注意的是，附图并不一定是按比例绘制，为了说明清晰的目的，部分结构可能放大或是缩小，在附图中：
图1是根据本申请一实施例的阵列基板的截面示意图；
图2是根据本申请一实施例的阵列基板的制作方法的流程示意图；以及
图3-10是制作根据本申请一实施例的阵列基板的流程截面示意图。
附图中出现的参考标记涉及以下技术特征：
101 基板
102 氧化物半导体层
103 阻挡层
104 氧化物保护层
105 栅极绝缘层
106 栅极
107 层间介质层
108 源极
109 漏极
S201-S205 步骤。
 本发明的实施方式
在下面的描述中，所提到“实施例”或“一实施例”旨在指出关于实施例描述的特定构造、结构或特征被包括在至少一个实施例中。因此，可在本说明书的各处存在的诸如“实施例中”或“一实施例中”等短语不必表示同一个实施例，而是可改为表示不同实施例。此外，本说明书中限定的特定构型、结构或特征可按甚至不同于所呈现的那些方式而按任何适合的方式组合。参考标号和空间参照（诸如，“上”、“下”等）在此仅为了方便使用，且因此不限制保护范围或实施例的范围。
应理解的是，当元件、层、区域或组件被称为“在”另一元件、层、区域或组件“上”、“连接到”或“结合到”另一元件、层、区域或组件时，该元件、层、区域或组件可以直接在所述另一元件、层、区域或组件上、直接连接到或直接结合到所述另一元件、层、区域或组件，或者可以存在一个或更多个中间元件、层、区域或组件。然而，“直接连接/直接结合”指的是一个组件直接连接或结合另一组件而没有中间组件。同时，可以对描述组件之间的关系的诸如“在……之间”、“直接在……之间”或者“与……邻近”和“直接与……邻近”的其它表述进行类似地解释。此外，还将理解的是，当元件或层被称为“在”两个元件或层“之间”时，该元件或层可以是位于所述两个元件或层之间的唯一元件或层，或者也可以存在一个或多个中间元件或层。
以下，将参照附图来详细地描述本申请的实施例。其中，图1是根据本申请一实施例的阵列基板的截面示意图，图2是根据本申请一实施例的阵列基板的制作方法的流程示意图，以及图3-10是制作根据本申请一实施例的阵列基板的流程截面示意图。
如图1所示，本申请提供了一种阵列基板，包括：基板101；氧化物半导体层102，设置于基板101上；阻挡层103，设置于氧化物半导体层102上；氧化物保护层104，设置于阻挡层103上；栅极绝缘层105，设置于阻挡层103和氧化物保护层104上；栅极106，设置于栅极绝缘层105上；层间介质层107，设置于栅极106、氧化物保护层104和基板101上；以及源极108和漏极109，设置于层间介质层107上，源极108和漏极109分别穿过层间介质层107与氧化物保护层104电连接。
在一些实施例中，基板101是透明的，并且例如由玻璃制成。尽管图1中仅示出了基板101的一部分，但应当理解的是，基板101可以具有例如数厘米到数米的宽度。
接着参考图1，在基板101上设置氧化物半导体层102。在一些实施例中，氧化物半导体层102的材料为C轴对齐的结晶铟镓锌氧化物（CAAC-IGZO：C-Axis Aligned Crystal Indium Gallium Zinc Oxide）。即，CAAC-IGZO层相当于本申请中的氧化物半导体层102的一例。在一些实施例中，氧化物半导体层102的膜厚为100-1000Å。
与现有技术中的非晶IGZO相比，CAAC-IGZO的电阻较小、晶体内部缺陷少、具有极低的关闭电流、还可极大地降低功耗，因此可以有效地提高电子迁移率和器件稳定性。
应理解的是，能够使用任何适合于待沉积的特定材料的处理技术（诸如物理气相沉积（PVD：Physical Vapor Deposition）、化学气相沉积（CVD：Chemical Vapor Deposition）、电镀等）来形成基板101上的各种构件（例如，氧化物半导体层102和以下描述的那些）。尽管在附图中未具体示出，但应理解的是，如本领域人员所熟知的，能够使用光刻工艺和蚀刻工艺来使基板101上的各个构件成形和确定大小，使得构件形成在基板101的选定区域上方。
接着参考图1，在氧化物半导体层102上设置阻挡层103。在一些实施例中，阻挡层103的材料为IGZTO（Indium Gallium Zinc Tin Oxide：铟镓锌锡氧化物）。即，IGZTO层相当于本申请中的阻挡层103的一例。在一些实施例中，阻挡层103的膜厚为10-200Å。
然后，在阻挡层103上设置氧化物保护层104。在一些实施例中，氧化物保护层104的材料为ITO（Indium Tin Oxide：氧化铟锡），即，ITO层相当于本申请中的氧化物保护层104的一例。在一些实施例中，氧化物保护层104的膜厚为100-1000Å。由于ITO和IGZTO结合力较好，因而在后续制程作业的过程中，使用ITO和源漏极金属材料接触可以有效降低源漏极处的接触电阻，从而提高阵列基板的沟道中电子的整体迁移率和稳定性。
接着参考图1，在氧化物保护层104上设有一沟道，并且阻挡层103在基板101上的正投影覆盖该沟道在基板101上的正投影。由此，在例如对氧化物保护层104进行刻蚀的工艺中，阻挡层103可以有效地预防湿法蚀刻时对氧化物半导体层102过度刻蚀而造成断线等工艺不稳定的问题。
应理解的是，虽然附图中阻挡层103覆盖氧化物半导体层102，但只要阻挡层103在基板101上的正投影覆盖该沟道在基板101上的正投影，阻挡层103也可以只覆盖氧化物半导体层102的一部分。
接着参考图1，在阻挡层103和氧化物保护层104上设有栅极绝缘层105，栅极绝缘层105的材料例如为SiOx或者Al 2O 3/SiNx等。另外，在栅极绝缘层105上设有栅极106，栅极106的材料为例如Mo或者Al/Cu等金属复合膜。另外，在栅极106、氧化物保护层104和基板101上设有层间介质层107，层间介质层107的材料例如为SiOx或者Al 2O 3/SiNx等。另外，在层间介质层107上设有源极108和漏极109，源极108和漏极109分别穿过层间介质层107与氧化物保护层104电连接。
在本申请的实施例中，栅极106、源极108、以及漏极109的材料包括且不限于Mo、Al、Cu、MoTi等金属材料。
本申请通过上述的阵列基板，在氧化物半导体层102成膜后在其膜层表面生成阻挡层103和氧化物保护层104，可以有效地降低外界环境中的酸、水、氧气等因素的干扰，保持IGZO薄膜晶体管器件原有的特性，使得IGZO薄膜晶体管器件在工作过程中稳定，高效以及长寿命，有助于改善常规制程无法稳定保障其电学性能的问题。而且阻挡层103还可以有效地预防湿法蚀刻时对氧化物半导体层102过度刻蚀而造成断线等工艺不稳定的问题。
本申请还提供了一种阵列基板的制作方法。现在将参照图2-10来在下文中详细描述，该方法包括如下步骤：
S201：如图3所示，提供一基板101，在基板101上形成氧化物半导体层102。氧化物半导体层102能够通过任何适合的方法来形成。在一个实施例中，在基板101上先通过PVD工艺来沉积IGZO层，IGZO的成膜温度为300-1000℃，保证IGZO的结晶性从而能够提升其电学性能，然后通过一高温制程使IGZO层转换成材料为C轴对齐的结晶铟镓锌氧化物的氧化物半导体层102。
S202：在氧化物半导体层102上形成阻挡层103。
S203：如图4所示，在阻挡层103上形成氧化物保护层104。氧化物保护层104可以通过PVD工艺来沉积，在该工艺中，使氧化物保护层104的成膜温度25-100℃，从而能够降低ITO层的结晶性，以便于后续的刻蚀工艺。
在一些实施例中，氧化物半导体层102、阻挡层103、以及氧化物保护层104在同一装置中的不同腔体连续地成膜相结合。
通过在真空环境下形成氧化物半导体层102以后，在氧化物半导体层102上形成阻挡层103和氧化物保护层104，能够避免在后续生产过程中，在转运过程中停放时间长短以及环境中不确定因素变多而对CAAC-IGZO的物理性质产生影响。这是因为，在转运或是停放的期间，氧化物保护层104和阻挡层103都能有效地减少空气中的H 2O和O 2等对氧化物半导体层102的物理性质造成影响。
如图5所示，接下来，在氧化物保护层104上形成一沟道，例如先通过黄光光刻，然后采用铝酸对氧化物保护层104进行刻蚀来形成该沟道，因阻挡层103在铝酸中刻蚀速率极低，所以可以阻挡住铝酸对氧化物半导体层102的刻蚀，从而形成较好的刻蚀界面。随后，再涂装光刻胶进行光刻，之后对阻挡层103和氧化物半导体层102的侧边进行统一蚀刻（未示出）。
S204：如图6所示，在阻挡层103和氧化物保护层104上，例如通过CVD沉积SiOx或者Al 2O 3/SiNx等或者复合膜层来形成栅极绝缘层105。接下来，如图7所示，在栅极绝缘层105上，例如通过PVD沉积Mo或者Al/Cu等金属复合膜层来形成栅极106。
S205：如图8-10所示，通过黄光和刻蚀工艺形成图形，其中栅极绝缘层105和栅极106被刻蚀成所需的图形。接着，例如通过CVD沉积SiOx或者Al 2O 3/SiNx等膜层来形成层间介质层107。接着，层间介质层107例如通过黄光和刻蚀制作出用于源极108和漏极109的通孔，使得例如通过PVD沉积Mo或者Al/Cu等金属复合膜层而制作出的源极108和漏极109分别穿过层间介质层107与氧化物保护层104电连接。
由此，形成如图1所示的阵列基板。
此外，本申请还提供了一种显示装置，包括如以上所述的阵列基板。
综上所述，本申请提供了一种阵列基板及其制作方法、显示装置，在氧化物半导体层成膜后在其膜层表面生成阻挡层和氧化物保护层，可以有效地降低外界环境中的酸、水、氧气等因素的干扰，保持薄膜晶体管器件原有的特性，使得薄膜晶体管器件在工作过程中稳定，高效以及长寿命，有助于改善常规制程无法稳定保障其电学性能的问题。而且阻挡层还可以有效地预防湿法蚀刻时对氧化物半导体层过度刻蚀而造成断线等工艺不稳定的问题，从而能够稳定不同批次的阵列基板的电学性能，并提高阵列基板的电子迁移率和器件稳定性。
该书面描述使用示例来公开本申请，包括最佳模式，并且还使本领域技术人员能够实践本申请，包括制造和使用任何装置或系统以及执行任何包含的方法。本申请可申请专利的范围由权利要求书限定，并且可包括本领域技术人员想到的其它示例。如果这些其它示例具有不与权利要求书的字面语言不同的结构要素，或者如果它们包括与权利要求书的字面语言无实质差异的等同结构要素，则意在使这些其它示例处于权利要求书的范围内。

Claims (20)

  1. 一种阵列基板，包括：
    基板；
    氧化物半导体层，设置于所述基板上；
    阻挡层，设置于所述氧化物半导体层上；
    氧化物保护层，设置于所述阻挡层上；
    栅极绝缘层，设置于所述阻挡层和所述氧化物保护层上；以及
    栅极，设置于所述栅极绝缘层上。
  2. 根据权利要求1所述阵列基板，其中，所述氧化物保护层上设有一沟道，所述阻挡层在所述基板上的正投影至少覆盖所述沟道在所述基板上的正投影。
  3. 根据权利要求2所述阵列基板，其中，还包括：
    层间介质层，设置于所述栅极、所述氧化物保护层和所述基板上；以及
    源极和漏极，设置于所述层间介质层上，所述源极和漏极分别穿过所述层间介质层与所述氧化物保护层电连接。
  4. 根据权利要求1所述阵列基板，其中，所述氧化物半导体层的材料为C轴对齐的结晶铟镓锌氧化物。
  5. 根据权利要求1所述阵列基板，其中，所述氧化物保护层的材料为氧化铟锡。
  6. 根据权利要求1所述阵列基板，其中，所述阻挡层的材料为铟镓锌锡氧化物。
  7. 根据权利要求1所述阵列基板，其中，所述氧化物半导体层的膜厚为100-1000Å。
  8. 根据权利要求1所述阵列基板，其中，所述阻挡层的膜厚为10-200Å。
  9. 一种阵列基板的制作方法，包括以下步骤：
    提供一基板，在所述基板上形成氧化物半导体层；
    在所述氧化物半导体层上形成阻挡层；
    在所述阻挡层上形成氧化物保护层；以及
    在所述阻挡层和所述氧化物保护层上形成栅极绝缘层，在所述栅极绝缘层上形成栅极。
  10. 根据权利要求9所述用于制作阵列基板的方法，其中，所述氧化物半导体层、所述阻挡层、以及所述氧化物保护层在同一装置中的不同腔体连续地成膜相结合。
  11. 根据权利要求9所述用于制作阵列基板的方法，其中，在所述基板上形成氧化物半导体层包括：
    在所述基板上形成铟镓锌氧化物层，并通过一高温制程使所述铟镓锌氧化物层中的铟镓锌氧化物转换为C轴对齐的结晶铟镓锌氧化物，以形成材料为C轴对齐的结晶铟镓锌氧化物的所述氧化物半导体层。
  12. 根据权利要求9所述用于制作阵列基板的方法，其中，所述在所述阻挡层上形成氧化物保护层包括：
    在所述阻挡层上形成氧化铟锡层；
    在所述氧化铟锡层上形成一沟道，以形成所述氧化物保护层。
  13. 一种显示装置，包括装置主体以及设置于所述装置主体的阵列基板，所述阵列基板包括：
    基板；
    氧化物半导体层，设置于所述基板上；
    阻挡层，设置于所述氧化物半导体层上；
    氧化物保护层，设置于所述阻挡层上；
    栅极绝缘层，设置于所述阻挡层和所述氧化物保护层上；以及
    栅极，设置于所述栅极绝缘层上。
  14. 根据权利要求13所述阵列基板，其中，所述氧化物保护层上设有一沟道，所述阻挡层在所述基板上的正投影至少覆盖所述沟道在所述基板上的正投影。
  15. 根据权利要求14所述阵列基板，其中，还包括：
    层间介质层，设置于所述栅极、所述氧化物保护层和所述基板上；以及
    源极和漏极，设置于所述层间介质层上，所述源极和漏极分别穿过所述层间介质层与所述氧化物保护层电连接。
  16. 根据权利要求13所述阵列基板，其中，所述氧化物半导体层的材料为C轴对齐的结晶铟镓锌氧化物。
  17. 根据权利要求13所述阵列基板，其中，所述氧化物保护层的材料为氧化铟锡。
  18. 根据权利要求13所述阵列基板，其中，所述阻挡层的材料为铟镓锌锡氧化物。
  19. 根据权利要求13所述阵列基板，其中，所述氧化物半导体层的膜厚为100-1000Å。
  20. 根据权利要求13所述阵列基板，其中，所述阻挡层的膜厚为10-200Å。
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