WO2022068125A1 - 存储器电路结构及其操作的方法 - Google Patents

存储器电路结构及其操作的方法 Download PDF

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Publication number
WO2022068125A1
WO2022068125A1 PCT/CN2021/073533 CN2021073533W WO2022068125A1 WO 2022068125 A1 WO2022068125 A1 WO 2022068125A1 CN 2021073533 W CN2021073533 W CN 2021073533W WO 2022068125 A1 WO2022068125 A1 WO 2022068125A1
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Prior art keywords
circuit
programming
voltage
current
path
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PCT/CN2021/073533
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English (en)
French (fr)
Inventor
许晓欣
余杰
董大年
余兆安
吕杭炳
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中国科学院微电子研究所
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Priority to US18/247,213 priority Critical patent/US20230368838A1/en
Publication of WO2022068125A1 publication Critical patent/WO2022068125A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0023—Address circuits or decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0023—Address circuits or decoders
    • G11C13/0026—Bit-line or column circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0064—Verifying circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0097—Erasing, e.g. resetting, circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0064—Verifying circuits or methods
    • G11C2013/0066—Verify correct writing whilst writing is in progress, e.g. by detecting onset or cessation of current flow in cell and using the detector output to terminate writing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G11C2013/0073—Write using bi-directional cell biasing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G11C2013/0078—Write using current through the cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G11C2013/009—Write using potential difference applied between cell electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/79—Array wherein the access device being a transistor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/82—Array having, for accessing a cell, a word line, a bit line and a plate or source line receiving different potentials

Definitions

  • the present disclosure belongs to the field of storage technology, and relates to a memory circuit structure and an operation method thereof.
  • Resistive random access memory has many advantages as a new type of memory. In terms of process, it is fully compatible with the current mature CMOS process, with simple preparation and high integration; in programming operation, it has the advantages of low operating voltage, fast response speed, and low power consumption; at the same time, resistive memory relies on resistive state. Diversity, can be used for brain-like, neural network, neuron and other applications.
  • the programming parameters of the devices are discrete.
  • the existing programming scheme will cause some devices in the array to be over-programmed or under-programmed, which reduces the cycle capability of the devices in the memory array and increases the bit error rate of the memory array. . Improving the retention characteristics and durability of the device and reducing the bit error rate of the memory array are the problems that must be solved when the resistive memory is oriented to the application.
  • the present disclosure provides a memory circuit structure and an operation method thereof, so as to improve the endurance (Endurance) and retention (Retention) characteristics of a resistive memory, improve the uniformity of the resistance state, and reduce the bit error rate of the array .
  • the above-mentioned memory circuit structure includes: a memory array, including at least two memory cells; a decoder, which is respectively connected to a bit line and a word line of the memory array, for selecting specific memory cells in a specific row and a specific column to operate; a programming circuit, Used to generate voltage pulse or constant current pulse; polarity switching circuit, connected with programming circuit, used to realize switching between voltage programming and current programming of programming circuit under setting operation and reset operation; detection circuit, connected with storage array , which is used to detect the detection signal of the current or voltage corresponding to the specific storage unit in the storage array, and feed back the detection signal to the control unit, and the detection signal output by the detection circuit is used to enable the polarity switching circuit to switch; and the control unit, with According to the detection signal, the polarity switching circuit is controlled to perform the switching operation and the pulse output of the programming circuit is controlled.
  • the programming circuit under the setting operation, the programming circuit generates a voltage pulse, and the first path of the polarity switching circuit is turned on, so that the programming circuit realizes voltage programming along the first path; in the voltage programming stage, the detection circuit detects Whether the first current flowing through the specific memory cell exceeds the first preset value; if the first current exceeds the first preset value, the control unit controls the polarity switching circuit to switch from the first path to the second path, and makes the programming circuit output constant current pulse to realize current programming along the second path; in the current programming stage, the detection circuit detects whether the first voltage on the specific memory cell exceeds the second preset value; if the first voltage exceeds the second preset value, the control The unit controls the programming circuit to stop the output.
  • the programming circuit under the reset operation, the programming circuit generates a constant current pulse, and the second path of the polarity switching circuit is turned on, so that the programming circuit realizes current programming along the second path; in the current programming stage, the detection circuit Detecting whether the second voltage flowing through the specific memory cell is less than the third preset value; if the second voltage is less than the third preset value, the control unit controls the polarity switching circuit to switch from the second path to the first path, and makes the programming circuit outputting voltage pulses to realize voltage programming along the first path; in the voltage programming stage, the detection circuit detects whether the second current on the specific memory cell is less than the fourth preset value; if the second current is less than the fourth preset value, control The unit controls the programming circuit to stop the output.
  • the polarity switching circuit includes two groups of selection transistors connected in parallel, each group of selection transistors includes at least two selection transistors connected in series, and the two groups of selection transistors are respectively a first group of selection transistors and a second group of selection transistors , the first group of selection transistors are controlled on and off by the first selection signal output by the control unit, the second group of selection transistors are controlled on and off by the second selection signal output by the control unit, and the first selection signal controls the first group of selection transistors to turn on The second selection signal controls the second group of selection transistors to turn off, or the first selection signal controls the first group of selection transistors to turn off while the second selection signal controls the second group of selection transistors to turn on.
  • the polarity switching circuit is controlled by the control signals Sel_b and Sel of the strobe tube to control the operation mode of writing and erasing of the device.
  • the first selection signal (Sel_b) controls the first group of selection transistors to turn on
  • the second selection signal (Sel) controls the second group of selection transistors to turn off
  • the first path of the polarity switching circuit is turned on , so that the programming circuit implements voltage programming along the first path.
  • the first selection signal controls the first group of selection transistors to turn off
  • the second selection signal controls the second group of selection transistors to turn on
  • the second path of the polarity switching circuit is turned on, and the second path is different from the first path, so that the programming circuit Current programming is achieved along the second path.
  • the second path of the polarity switching circuit is turned on.
  • the above-mentioned detection circuit includes: a first transistor, a first comparator, a second transistor, a second comparator, and a logic gate.
  • the on-off of the first transistor is controlled by the first selection signal output by the control unit; one end of the first transistor is used as the input end of the detection circuit.
  • the negative input terminal of the first comparator is connected to the other terminal of the first transistor; the positive input terminal of the first comparator is used to input the detection signal of the voltage corresponding to the specific storage unit.
  • the on-off of the second transistor is controlled by the second selection signal output from the control unit; one end of the second transistor is connected to the memory array.
  • the positive input terminal of the second comparator is connected to the other terminal of the second transistor, and the negative input terminal of the second comparator is used for inputting the reference voltage.
  • the negative input terminal of the first comparator is connected to the positive input terminal of the second comparator.
  • the two input ends of the logic gate are respectively connected to the output end of the first comparator and the output end of the second comparator, and the output of the logic gate is a detection signal.
  • the above-mentioned memory circuit structure further includes: a current supply and management circuit.
  • the above-mentioned current supply and management circuit includes a current mirror circuit, and the current mirror circuit includes two output ends; wherein, one output end of the two output ends of the current mirror circuit is connected to the input end of the polarity switching circuit, and the current mirror circuit has two output ends. The other of the two output terminals is connected to the input terminal of the detection circuit.
  • the above-mentioned memory circuit structure further includes: a bias voltage circuit, and the above-mentioned bias voltage circuit is connected to the programming circuit.
  • the control unit outputs an enable signal to make the bias circuit generate an analog voltage signal; the analog voltage signal is output to the programming circuit.
  • the above-mentioned storage unit is a resistive memory.
  • Another aspect of the present disclosure provides a method of operating a memory circuit structure as described above, where the above operation is a set operation or a reset operation.
  • the above method includes: under a setting operation or a reset operation, the decoder selects a specific memory cell in a specific row and a specific column in the memory array to operate; the detection circuit detects the detection signal of the current or voltage corresponding to the specific memory cell in the memory array, and Feedback the detection signal to the control unit; the controller controls the polarity switching circuit to perform switching operations and control the pulse output of the programming circuit according to the detection signal; the programming circuit generates voltage pulses or constant current pulses under the action of the controller, and the polarity switching circuit Under the switching operation of the switching circuit, the voltage-first programming and the current-current programming under the setting operation are realized, or the current-first programming and the voltage-seconding programming under the reset operation are realized.
  • the control unit can control the polarity switching circuit to perform the switching operation and control the pulse output of the programming circuit according to the detection signal of the detection unit, so that the programming circuit is in the set or reset operation.
  • the switching between voltage programming and current programming can be realized, so that the voltage programming and constant current programming can work together in the setting or reset operation.
  • the removal process is optimized to optimize the endurance and retention characteristics of the resistive memory, improve the uniformity of the resistance state, and reduce the bit error rate of the array, so that in multiple read and write cycles/cycles, it can also Effectively maintain the performance of the resistive memory.
  • FIG. 1 is a structural block diagram of a memory circuit structure according to an embodiment of the present disclosure.
  • FIG. 2 is a schematic diagram of a circuit structure of a partial structure of a memory circuit structure according to an embodiment of the present disclosure.
  • FIG 3 is a schematic diagram of a first path of voltage programming of a memory circuit structure according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of a second path of current programming of a memory circuit structure according to an embodiment of the present disclosure.
  • FIG. 5 is a timing diagram illustrating operations on a specific memory cell according to an embodiment of the present disclosure.
  • FIG. 6 is a graph of error bit count versus cycle number for a memory circuit structure according to an embodiment of the present disclosure.
  • FIG. 7 is a comparison diagram of the resistance state distribution function curve of a memory circuit structure according to an embodiment of the present disclosure and a memory circuit of the prior art.
  • the structure of a resistive memory is usually a stacked structure, including: a resistive material layer and electrode layers located on and below the resistive material layer.
  • the resistance states of the resistive memory are different. For example, upon application of a set operating voltage, oxygen ions in the device move toward the oxygen storage layer of the upper electrode layer, thereby forming oxygen vacancy conductive filaments in the RRAM, which is in a low resistance state. When a reset operating voltage is applied, oxygen ions recombine with oxygen vacancies, the conductive filaments are broken, and the RRAM is in a high resistance state.
  • the present disclosure proposes a memory circuit structure and a method for operating the same, by which the formation of conductive filaments is stabilized in a coordinated manner based on voltage programming and current programming, or the fracture is caused by a coordinated manner based on current programming and voltage programming.
  • the interstitial region of the filament minimizes the presence of residual oxygen ions or removes residual oxygen ions in the interstitial region, thereby improving the retention specificity and cycle durability of the resistive switching device under set and reset operations.
  • the control unit can control the polarity switching circuit to perform the switching operation and control the pulse output of the programming circuit according to the detection signal of the detection unit, so that the programming circuit is in the setting or resetting operation, It can realize switching between voltage programming and current programming, so that in the setting or reset operation, the cooperative work of voltage programming and constant current programming can be realized, so as to optimize the endurance and retention characteristics of resistive memory, and improve the uniformity of resistance state, The bit error rate of the array is reduced, so that the performance of the resistive memory can be effectively maintained in multiple read and write cycles/cycles.
  • a memory circuit structure is provided.
  • FIG. 1 is a structural block diagram of a memory circuit structure according to an embodiment of the present disclosure.
  • the memory circuit structure of the embodiment of the present disclosure includes: a memory array 7, a decoder (Decoder) 8, a programming circuit (Write circuit) 3, a polarity switching circuit (Polarity switching circuit 4, a detection circuit (Detection circuit) circuit) 6 and a control unit (Arbiter) 1.
  • the memory array 7 includes at least two memory cells, and the above-mentioned memory cells are resistive memory.
  • the above-mentioned memory cells are resistive memory.
  • other types of storage units conforming to the technical concept of the present disclosure also fall within the protection scope of the present disclosure.
  • the decoder 8 is connected to the bit line BL and the word line WL of the memory array 7, respectively, and is used to select specific memory cells in a specific row and a specific column for operation.
  • the programming circuit 3 is used to generate voltage pulses or constant current pulses.
  • the polarity switching circuit 4 is connected to the programming circuit 3, and is used to realize the switching between the voltage programming and the current programming of the programming circuit 3 under a set operation and a reset operation.
  • the detection circuit 6 is connected to the memory array 7 , and is used for detecting the detection signal FB of the current or voltage corresponding to a specific memory cell in the memory array 7 , and feeding back the detection signal FB to the control unit 1 .
  • the detection signal FB output by the detection circuit 6 is used to enable the polarity switching circuit 4 to switch.
  • the control unit 1 is used to control the polarity switching circuit 4 to perform switching operations and control the pulse output of the programming circuit 3 according to the detection signal FB.
  • FIG. 2 is a schematic diagram of a circuit structure of a partial structure of a memory circuit structure according to an embodiment of the present disclosure.
  • the polarity switching circuit 4 includes two groups of selection transistors connected in parallel, and each group of selection transistors includes at least two selection transistors connected in series.
  • each group of selection transistors includes a series connection of selection transistors.
  • the 4 select transistors are exemplified, and the present disclosure is not limited thereto.
  • the gate transistors are divided into two groups by the first selection signal Sel_b and the second selection signal Sel_b.
  • the two sets of select transistors are depicted as a first set of select transistors and a second set of select transistors, the first set of select transistors being illustrated in FIG. 2 as the first, third, fifth and seventh arranged from top to bottom select transistor.
  • the second set of select transistors is illustrated in FIG. 2 as the second, fourth, sixth and eighth select transistors arranged from top to bottom.
  • the first selection signal Sel_b is a non-signal of the second selection signal Sel
  • the first group of selection transistors are controlled by the first selection signal Sel_b output from the control unit 1 to be on and off
  • the second group of selection transistors are controlled by
  • the second selection signal Sel output by the control unit 1 controls on-off, that is, the first selection signal controls the first group of selection transistors to be turned on while the second selection signal controls the second group of selection transistors to turn off, or the first selection signal controls the first group of selection transistors to turn off.
  • the second selection signal controls the second group selection transistors to be turned on.
  • the above-mentioned detection circuit 6 includes: a first transistor, a first comparator, a second transistor, a second comparator, and a logic gate.
  • the on-off of the first transistor is controlled by the first selection signal Sel_b output from the control unit 1 .
  • One end of the first transistor serves as the input end of the detection circuit 6 .
  • the negative input terminal of the first comparator is connected to the other terminal of the first transistor, and the positive input terminal of the first comparator is used for inputting a detection signal corresponding to a voltage of a specific memory cell, which is described as V ref1 here.
  • the on-off of the second transistor is controlled by the second selection signal Sel output from the control unit 1, and one end of the second transistor is connected to the memory array.
  • the positive input terminal of the second comparator is connected to the other terminal of the second transistor, and the negative input terminal of the second comparator is used for inputting a reference voltage, which is described as V ref2 here.
  • the negative input terminal of the first comparator is connected to the positive input terminal of the second comparator.
  • the two input ends of the logic gate are respectively connected to the output end of the first comparator and the output end of the second comparator, and the output of the logic gate is a detection signal.
  • the logic gate is an AND gate, two input terminals of the AND gate are respectively connected to the output terminal of the first comparator and the output terminal of the second comparator, and the output of the AND gate is the detection signal FB.
  • the above-mentioned memory circuit structure further includes: a current supply and management circuit 5 .
  • the above-mentioned current supply and management circuit 5 includes a current mirror circuit, and the current mirror circuit includes two output ends; wherein, one output end of the two output ends of the current mirror circuit is connected to the input end of the polarity switching circuit 4, and the current mirror circuit The other of the two outputs of the circuit is connected to the input of the detection circuit 6 .
  • the current mirror circuit includes two transistors, described as a third transistor and a fourth transistor, respectively.
  • the source of the third transistor is connected to the power supply voltage VCC (analog signal power supply voltage), and the drain of the third transistor is used as one output end of the two output ends of the current mirror circuit, and is connected to the input end of the polarity switching circuit 4;
  • the gate and drain of the three transistors are shorted.
  • the gate of the third transistor is connected to the gate of the fourth transistor, the source of the fourth transistor is connected to the power supply voltage VCC (analog signal power supply voltage), and the drain of the fourth transistor is used as one of the two output terminals of the current mirror circuit.
  • the other output terminal is connected to the input terminal of the detection circuit 6 .
  • the drain of the fourth transistor is also connected to one end of the resistor, and the other end of the resistor is grounded.
  • the above-mentioned memory circuit structure further includes: a bias circuit 2 , and the above-mentioned bias circuit 2 is connected to a programming circuit 3 .
  • the control unit 1 outputs an enable signal en to enable the bias circuit to generate an analog voltage signal data1 ; the above-mentioned analog voltage signal data1 is output to the programming circuit 3 .
  • the digital voltage signal data0 input by the control unit 1 and the detection signal FB fed back by the detection circuit 6 are also illustrated.
  • the control unit 1 outputs the first selection signal Sel_b, the second selection signal Sel_b, and the enable signal en according to the detection signal FB.
  • the digital input signal Data[4:0] of the bias circuit 2 is a 5-bit digital signal.
  • the bias circuit 2 generates an analog signal data1 and outputs the analog voltage signal data1 to the programming circuit 3 .
  • FIG. 3 is a schematic diagram of a first path of voltage programming of a memory circuit structure according to an embodiment of the present disclosure.
  • 4 is a schematic diagram of a second path of current programming of a memory circuit structure according to an embodiment of the present disclosure.
  • FIG. 5 is a timing diagram illustrating operations on a specific memory cell according to an embodiment of the present disclosure.
  • the data of Sel and data1 are configured first. en is equivalent to a gating circuit, which is responsible for applying the configured data to the device. Every time FB changes from a low level to a high level, the circuit for programming the device changes, and the programming mode changes accordingly.
  • the first path is shown by the dashed-dotted line in FIG. 3, and the path where the first group of selection transistors are turned on is used as an example for the first path.
  • the first programming data is written along the first path through the analog voltage signal data1. to a specific storage unit.
  • the detection circuit detects whether the first current flowing through the specific memory cell exceeds the first preset value; if the first current exceeds the first preset value, refer to the first rectangular waveform of FB shown in FIG. 5 .
  • FB is high level, which can correspond to logic "1" (when the first current is less than the first preset value, FB is low level and can correspond to logic "0", as shown by the horizontal line in Figure 5)
  • the second path is shown by the double-dot chain line in FIG.
  • the second programming data is written to a specific memory cell along the second path through the analog voltage signal data1.
  • the preset value can be set according to the actual needs of the device.
  • a certain current flows through the device to enhance the stability of the conductive path in the device.
  • the oxygen vacancy concentration in the conductive path is increased without increasing the size of the conductive path.
  • the retention of the RRAM is improved.
  • the second path is shown by the double-dot chain line in FIG. 4 , taking the path in which the second group of selection transistors are turned on as an example.
  • the first erased data is written to a specific memory along the second path through the analog voltage signal data1. unit.
  • the first path is shown by the dashed-dotted line in FIG. 3, and the path where the first group of selection transistors are turned on is used as an example for the first path.
  • the second erased data is written along the first path through the analog voltage signal data1. into a specific storage unit.
  • the preset value can be set according to the actual needs of the device. During the reset operation, a large current will cause instantaneous heat on the conductive channel inside the device to break the oxygen vacancy channel. Since the process of breaking the conductive path is very random, there are differences in each break. A small voltage pulse is introduced after programming in order to make the random oxygen vacancies more aggregated after the conduction channel is broken, minimizing unnecessary discrete oxygen vacancies, thus making the broken conduction channel more stable.
  • the first selection signal (Sel_b) controls the first group of selection transistors to turn on
  • the second selection signal (Sel) controls the second group of selection transistors to turn off
  • the The first path of the sexual switching circuit is turned on, so that the programming circuit realizes voltage programming along the first path.
  • the first selection signal controls the first group of selection transistors to turn off
  • the second selection signal controls the second group of selection transistors to turn on
  • the second path of the polarity switching circuit is turned on, and the second path is different from the first path, so that the programming circuit Current programming is achieved along the second path.
  • FIG. 6 is a graph of error bit count versus cycle number for a memory circuit structure according to an embodiment of the present disclosure.
  • FIG. 7 is a comparison diagram of the resistance state distribution function curve of a memory circuit structure according to an embodiment of the present disclosure and a memory circuit of the prior art.
  • the circle in Figure 6 represents the change data of the number of error bits and the number of times of cyclically erasing and writing the device under the traditional single-pulse operation scheme.
  • the triangle represents the change data of the number of error bits and the number of times of cyclically erasing and writing the device under the circuit operation scheme proposed by the present disclosure.
  • the dotted lines respectively represent the variation trend of the number of device error bits fitted with the cycles of erasing and writing under the two pulse operation schemes. It can be clearly seen from FIG. 6 that, under the same number of error bits, the circuit scheme proposed by the present disclosure can make the same device operate for more times.
  • FIG. 7 Shown in FIG. 7 is the resistance state distribution function comparison of the conventional scheme (unoptimized) and the disclosed scheme (optimized), respectively, the conventional scheme is a single voltage pulse operation.
  • Figure 7 shows the distribution probabilities of high- and low-resistance states obtained by cycling the device under the two schemes. It can be seen from FIG. 7 that the uniformity of the device resistance value distribution obtained by the operation of the solution (optimized) of the present disclosure is better than that of the traditional solution (not optimized).
  • a method of operation of a memory circuit structure is provided.
  • the above operations are set operations or reset operations.
  • the above method includes the following operations: S21-S24.
  • the decoder selects a specific memory cell in a specific row and a specific column in the memory array to operate.
  • the detection circuit detects a detection signal of a current or voltage corresponding to a specific memory cell in the memory array, and feeds back the detection signal to the control unit.
  • the controller controls the polarity switching circuit to perform the switching operation and control the pulse output of the programming circuit according to the detection signal.
  • the programming circuit In operation S24, the programming circuit generates a voltage pulse or a constant current pulse under the action of the controller, and realizes the first voltage programming and the second current programming under the setting operation under the switching operation of the polarity switching circuit, or realizes the first programming under the reset operation.
  • a circuit scheme in which the two programming modes are coordinated is used to optimize the programming and erasing processes of the entire storage array.
  • the control unit can be detected according to the detection unit. signal to control the polarity switching circuit to perform the switching operation and control the pulse output of the programming circuit, so that the programming circuit can switch between voltage programming and current programming in the setting or reset operation, so that in the setting or reset operation, the voltage Programming and constant current programming work together to optimize the endurance and retention characteristics of resistive memory, improve the uniformity of resistance states, and reduce the bit error rate of the array, so that in multiple read and write cycles/cycles , and can effectively maintain the performance of the resistive memory.
  • the present disclosure provides a memory circuit structure and an operation method thereof.
  • the control unit can control the polarity switching circuit to perform the switching operation and control according to the detection signal of the detection unit.
  • the pulse output of the programming circuit enables the programming circuit to switch between voltage programming and current programming during the setting or reset operation, so that the voltage programming and constant current programming can work together during the setting or reset operation.
  • the mode-coordinated circuit scheme optimizes the programming and erasing processes of the entire memory array, thereby optimizing the durability and retention characteristics of the resistive memory, improving the uniformity of the resistance state, and reducing the bit error rate of the array, so that it can be read in multiple times. During the write cycle/cycle, the performance of the resistive memory can also be effectively maintained.

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Abstract

一种存储器电路结构及其操作的方法，存储器电路结构包括: 存储阵列，包含至少两个存储单元; 译码器，与存储阵列的位线和字线分别连接; 编程电路，用于产生电压脉冲或恒流脉冲; 极性切换电路，与编程电路连接，用于在设置操作及复位操作下实现编程电路在电压编程与电流编程之间的切换; 检测电路，与存储阵列连接，用于检测存储阵列中特定存储单元对应的电流或电压的检测信号，并将检测信号反馈给控制单元，检测电路输出的检测信号用于使能极性切换电路进行切换; 以及控制单元，用于根据检测信号来控制极性切换电路进行切换操作以及控制编程电路的脉冲输出。上述结构优化了阻变存储器的耐久性和保持特性，提高阻态的均一性，降低阵列的误码率。

Description

存储器电路结构及其操作的方法 技术领域
本公开属于存储技术领域，涉及一种存储器电路结构及其操作的方法。
背景技术
电阻式随机存取存储器(RRAM)作为新型存储器有着众多的优势。在工艺上，它完全兼容现在成熟的CMOS工艺，制备简单，集成度高等；在编程操作上，拥有工作电压低，响应速度快，功耗低等优点；同时，阻变存储器凭借着阻态的多样性，可用于类脑，神经网络，神经元等应用。
在存储阵列中，器件的编程参数是离散的，现有的编程方案会使阵列中部分器件处于过编程或者编程不足的问题，使得存储阵列中器件的循环能力降低，造成存储阵列误码率增加。提高器件的保持特性和耐久性，减少存储阵列的误码率是阻变存储器面向应用时必须解决的问题。
发明内容
有鉴于此，本公开提供了一种存储器电路结构及其操作的方法，以提高阻变存储器的耐久性(Endurance)和保持(Retention)特性，提高阻态的均一性，降低阵列的误码率。
本公开的一个方面提供了一种存储器电路结构。上述存储器电路结构包括：存储阵列，包含至少两个存储单元；译码器，与存储阵列的位线和字线分别连接，用于选择特定行和特定列的特定存储单元进行操作；编程电路，用于产生电压脉冲或恒流脉冲；极性切换电路，与编程电路连接，用于在设置操作及复位操作下实现编程电路在电压编程与电流编程之间的切换；检测电路，与存储阵列连接，用于检测存储阵列中特定存储单元对应的电流或电压的检测信号，并将检测信号反馈给控制单元，检测电路输出的检测信号用于使能极性切换电路进行切换；以及控制单元，用于根据检测信号来控制极性切换电路进行切换操作以及控制编程电路的脉冲输出。
根据本公开的实施例，在设置操作下，编程电路产生电压脉冲，极性 切换电路的第一路径导通，以使编程电路沿着第一路径实现电压编程；在电压编程阶段，检测电路检测流过特定存储单元的第一电流是否超过第一预设值；如果第一电流超过第一预设值，控制单元控制极性切换电路由第一路径切换至第二路径，并使得编程电路输出恒流脉冲，以沿着第二路径实现电流编程；在电流编程阶段，检测电路检测特定存储单元上的第一电压是否超过第二预设值；如果第一电压超过第二预设值，控制单元控制编程电路停止输出。
根据本公开的实施例，在复位操作下，编程电路产生恒流脉冲，极性切换电路的第二路径导通，以使编程电路沿着第二路径实现电流编程；在电流编程阶段，检测电路检测流过特定存储单元的第二电压是否小于第三预设值；如果第二电压小于第三预设值，控制单元控制极性切换电路由第二路径切换至第一路径，并使得编程电路输出电压脉冲，以沿着第一路径实现电压编程；在电压编程阶段，检测电路检测特定存储单元上的第二电流是否小于第四预设值；如果第二电流小于第四预设值，控制单元控制编程电路停止输出。
根据本公开的实施例，极性切换电路包括两组并联的选择晶体管，每组选择晶体管内包括串联的至少两个选择晶体管，两组选择晶体管分别为第一组选择晶体管和第二组选择晶体管，第一组选择晶体管由控制单元输出的第一选择信号控制通断，第二组选择晶体管由控制单元输出的第二选择信号控制通断，第一选择信号控制第一组选择晶体管开启的同时第二选择信号控制第二组选择晶体管关闭，或者，第一选择信号控制第一组选择晶体管关闭的同时第二选择信号控制第二组选择晶体管开启。极性切换电路由选通管的控制信号Sel_b和Sel控制对器件的写入和擦除的操作方式。第一选择信号Sel_b和第二选择信号Sel中，Sel_b是Sel信号的非信号，即在电路中Sel＝1，Sel_b＝0；或者，Sel＝0，Sel_b＝1。
根据本公开的实施例，当第一选择信号(Sel_b)控制第一组选择晶体管开启，且第二选择信号(Sel)控制第二组选择晶体管关闭时，极性切换电路的第一路径导通，使得编程电路沿着第一路径实现电压编程。当第一选择信号控制第一组选择晶体管关闭，且第二选择信号控制第二组选择晶体管开启时，极性切换电路的第二路径导通，第二路径不同于第一路径， 使得编程电路沿着第二路径实现电流编程。在一实施例，当Sel_b＝1，Sel＝0时，极性切换电路的第一路径导通，使得编程电路沿着第一路径实现电压编程。当Sel_b＝0，Sel＝1时，极性切换电路的第二路径导通。
根据本公开的实施例，上述检测电路包括：第一晶体管、第一比较器、第二晶体管、第二比较器以及逻辑门。第一晶体管由控制单元输出的第一选择信号控制通断；第一晶体管的一端作为检测电路的输入端。第一比较器的负极输入端与第一晶体管的另一端连接；第一比较器的正极输入端用于输入特定存储单元对应的电压的检测信号。第二晶体管由控制单元输出的第二选择信号控制通断；第二晶体管的一端与存储阵列连接。第二比较器的正极输入端与第二晶体管的另一端连接，第二比较器的负极输入端用于输入参考电压。第一比较器的负极输入端和第二比较器的正极输入端连接。逻辑门的两个输入端分别连接第一比较器的输出端和第二比较器的输出端，逻辑门的输出为检测信号。
根据本公开的实施例，上述存储器电路结构还包括：电流供应和管理电路。上述电流供应和管理电路包括电流镜电路，该电流镜电路包含两个输出端；其中，电流镜电路的两个输出端中的一个输出端与极性切换电路的输入端连接，电流镜电路的两个输出端中的另一个输出端与检测电路的输入端连接。
根据本公开的实施例，上述存储器电路结构还包括：偏压电路，上述偏压电路与编程电路连接。其中，控制单元输出使能信号以使偏压电路产生模拟电压信号；上述模拟电压信号输出至编程电路中。
根据本公开的实施例，上述存储单元为阻变存储器。
本公开的另一个方面提供了一种如上所述的存储器电路结构的操作的方法，上述操作为设置操作或复位操作。上述方法包括：在设置操作或复位操作下，译码器选择存储阵列中特定行和特定列的特定存储单元进行操作；检测电路检测存储阵列中特定存储单元对应的电流或电压的检测信号，并将检测信号反馈给控制单元；控制器根据检测信号来控制极性切换电路进行切换操作以及控制编程电路的脉冲输出；编程电路在控制器的作用下产生电压脉冲或恒流脉冲，并在极性切换电路的切换操作下实现设置操作下的先电压编程、后电流编程，或者实现复位操作下的先电流编程、 后电压编程。
从上述技术方案可以看出，本公开提供的存储器电路结构及其操作的方法，至少具有以下有益效果：
对存储阵列进行设置(set)或复位(reset)操作时，控制单元可以根据检测单元的检测信号来控制极性切换电路进行切换操作以及控制编程电路的脉冲输出，使得编程电路在设置或复位操作中，可以实现电压编程和电流编程之间的切换，从而在设置或复位操作中，实现电压编程和恒流编程协同工作，利用两种编程模式协同的电路方案，对整个存储阵列的编程和擦除过程进行优化，从而优化阻变存储器的耐久性(Endurance)和保持(Retention)特性，提高阻态的均一性，降低阵列的误码率，从而在多次读写周期/循环中，还可以有效保持阻变存储器的性能。
附图说明
图1为根据本公开一实施例所示的存储器电路结构的结构框图。
图2为根据本公开一实施例所示的存储器电路结构的部分结构的电路结构示意图。
图3为根据本公开一实施例所示的存储器电路结构的电压编程的第一路径示意图。
图4为根据本公开一实施例所示的存储器电路结构的电流编程的第二路径示意图。
图5为根据本公开一实施例所示的对特定存储单元进行操作的时序图。
图6为根据本公开一实施例所示的存储器电路结构的错误位计数随着循环次数变化的曲线。
图7为根据本公开一实施例所示的存储器电路结构与现有技术的存储器电路的电阻态分布函数曲线对比图。
【符号说明】
1-控制单元；                     2-偏压电路；
3-编程电路；                     4-极性切换电路；
5-电流供应和管理电路；           6-检测电路；
7-存储阵列；                     8-译码器。
具体实施方式
阻变存储器(RRAM)的结构通常为叠层结构，包括：阻变材料层以及位于阻变材料层上、下方的电极层。在不同极性的脉冲电压激励下，阻变存储器呈现的电阻状态不同。例如，在施加设置(set)操作电压时，器件中氧离子向上方电极层的储氧层移动，从而在RRAM中形成氧空位导电细丝，该RRAM处于低阻态。当施加复位(Reset)操作电压时，氧离子与氧空位复合，导电细丝断裂，RRAM处于高阻态。
在实现本公开的过程中发现：当形成细丝不稳定，或者断裂细丝的间隙区域存在残余氧离子时，会导致阻变器件的保持特性和稳定性变差。有鉴于此，本公开提出了一种存储器电路结构及其操作的方法，通过基于电压编程和电流编程协同的方式，使得导电细丝形成稳定，或者基于电流编程和电压编程协同的方式，使得断裂细丝的间隙区域尽可能减少残余氧离子的存在或者去除间隙区域的残余氧离子，从而提升设置操作和复位操作下阻变器件的保持特定和循环耐久性。
本公开提供的存储器电路结构及其操作的方法中，控制单元可以根据检测单元的检测信号来控制极性切换电路进行切换操作以及控制编程电路的脉冲输出，使得编程电路在设置或复位操作中，可以实现电压编程和电流编程之间的切换，从而在设置或复位操作中，实现电压编程和恒流编程的协同工作，从而优化阻变存储器的耐久性和保持特性，提高阻态的均一性，降低阵列的误码率，从而在多次读写周期/循环中，还可以有效保持阻变存储器的性能。
为使本公开的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本公开进一步详细说明。
在本公开的第一个示例性实施例中，提供了一种存储器电路结构。
图1为根据本公开一实施例所示的存储器电路结构的结构框图。
参照图1所示，本公开实施例的存储器电路结构，包括：存储阵列7、译码器(Decoder)8、编程电路(Write circuit)3、极性切换电路(Polarity switching circuit4、检测电路(Detection circuit)6以及控制单元(Arbiter)1。
根据本公开的实施例，存储阵列7包含至少两个存储单元，上述存储单元为阻变存储器。当然，符合本公开的技术构思的其他类型的存储单元也在本公开的保护范围之内。
译码器8与存储阵列7的位线BL和字线WL分别连接，用于选择特定行和特定列的特定存储单元进行操作。编程电路3用于产生电压脉冲或恒流脉冲。极性切换电路4与编程电路3连接，用于在设置(set)操作及复位(reset)操作下实现编程电路3在电压编程与电流编程之间的切换。检测电路6与存储阵列7连接，用于检测存储阵列7中特定存储单元对应的电流或电压的检测信号FB，并将检测信号FB反馈给控制单元1。检测电路6输出的检测信号FB用于使能极性切换电路4进行切换。控制单元1用于根据检测信号FB来控制极性切换电路4进行切换操作以及控制编程电路3的脉冲输出。
图2为根据本公开一实施例所示的存储器电路结构的部分结构的电路结构示意图。
根据本公开的实施例，参照图2所示，极性切换电路4包括两组并联的选择晶体管，每组选择晶体管内包括串联的至少两个选择晶体管，图2中以每组选择晶体管包括串联的4个选择晶体管进行示例，本公开不局限于此。
为了方便描述，以第一选择信号Sel_b和第二选择信号Sel将选通管分为两组。两组选择晶体管分别描述为第一组选择晶体管和第二组选择晶体管，第一组选择晶体管在图2中示意为自上而下排列的第一个、第三个、第五个和第七个选择晶体管。第二组选择晶体管在图2中示意为自上而下排列的第二个、第四个、第六个和第八个选择晶体管。结合图1和图2所示，第一选择信号Sel_b是第二选择信号Sel的非信号，第一组选择晶体管由控制单元1输出的第一选择信号Sel_b控制通断，第二组选择晶体管由控制单元1输出的第二选择信号Sel控制通断，即，第一选择信号控制第一组选择晶体管开启的同时第二选择信号控制第二组选择晶体管关闭，或者，第一选择信号控制第一组选择晶体管关闭的同时第二选择信号控制第二组选择晶体管开启。
根据本公开的实施例，参照图2所示，上述检测电路6包括：第一晶 体管、第一比较器、第二晶体管、第二比较器以及逻辑门。第一晶体管由控制单元1输出的第一选择信号Sel_b控制通断。第一晶体管的一端作为检测电路6的输入端。第一比较器的负极输入端与第一晶体管的另一端连接，第一比较器的正极输入端用于输入特定存储单元对应的电压的检测信号，这里以V ref1进行描述。第二晶体管由控制单元1输出的第二选择信号Sel控制通断，第二晶体管的一端与存储阵列连接。第二比较器的正极输入端与第二晶体管的另一端连接，第二比较器的负极输入端用于输入参考电压，这里以V ref2进行描述。第一比较器的负极输入端和第二比较器的正极输入端连接。逻辑门的两个输入端分别连接第一比较器的输出端和第二比较器的输出端，逻辑门的输出为检测信号。本实施例中，逻辑门为与门(AND gate)，与门的两个输入端分别连接第一比较器的输出端和第二比较器的输出端，与门的输出为检测信号FB。
根据本公开的实施例，参照图2所示，上述存储器电路结构还包括：电流供应和管理电路5。上述电流供应和管理电路5包括电流镜电路，该电流镜电路包含两个输出端；其中，电流镜电路的两个输出端中的一个输出端与极性切换电路4的输入端连接，电流镜电路的两个输出端中的另一个输出端与检测电路6的输入端连接。
参照图2所示，电流镜电路包括两个晶体管，分别描述为第三晶体管和第四晶体管。第三晶体管的源极接电源电压VCC(模拟信号电源电压)，第三晶体管的漏极作为电流镜电路的两个输出端中的一个输出端，与极性切换电路4的输入端连接；第三晶体管的栅极与漏极短接。第三晶体管的栅极与第四晶体管的栅极连接，第四晶体管的源极与电源电压VCC(模拟信号电源电压)连接，第四晶体管的漏极作为电流镜电路的两个输出端中的另一个输出端，与检测电路6的输入端连接。第四晶体管的漏极还与电阻的一端连接，该电阻的另一端接地。
根据本公开的实施例，参照图1所示，上述存储器电路结构还包括：偏压电路(Bias circuit)2，上述偏压电路2与编程电路3连接。其中，控制单元1输出使能信号en以使偏压电路产生模拟电压信号data1；上述模拟电压信号data1输出至编程电路3中。参照图1所示，还示意了控制单元1输入的数字电压信号data0，以及由检测电路6反馈的检测信号FB。 控制单元1根据上述检测信号FB输出第一选择信号Sel_b、第二选择信号Sel以及使能信号en。在一实例中，偏压电路2的数字输入信号Data[4:0]为5位的数字信号。偏压电路2产生模拟信号data1并输出该模拟电压信号data1至编程电路3。
图3为根据本公开一实施例所示的存储器电路结构的电压编程的第一路径示意图。图4为根据本公开一实施例所示的存储器电路结构的电流编程的第二路径示意图。图5为根据本公开一实施例所示的对特定存储单元进行操作的时序图。
根据本公开的实施例，在进行SET和RESET操作前，都是先配置好Sel和data1的数据。en相当于门控电路，负责将配置好的数据能作用到器件上。FB每次由低电平转变成高电平时，对器件编程的电路就会发生变化，编程模式也随之变化。
根据本公开的实施例，参照图3-图5所示，在设置(set或者SET)操作下，Sel＝1且Sel_b＝0，编程电路产生电压脉冲，极性切换电路的第一路径导通，以使编程电路沿着第一路径实现电压编程。第一路径参照图3中单点划线所示，以第一组选择晶体管导通的路径为第一路径进行示例，该阶段中第一编程数据通过模拟电压信号data1沿着第一路径写入至特定存储单元。在电压编程阶段，检测电路检测流过特定存储单元的第一电流是否超过第一预设值；如果第一电流超过第一预设值，参照图5中示意的FB的第一个矩形波形所示，FB为高电平，可以对应逻辑“1”(第一电流小于第一预设值的情况下，FB为低电平，可以对应逻辑“0”，参照图5中水平线部分所示)，控制单元控制极性切换电路由第一路径切换至第二路径，Sel＝0且Sel_b＝1，使得编程电路输出恒流脉冲，以沿着第二路径实现电流编程。第二路径参照图4中双点划线所示，以第二组选择晶体管导通的路径进行示例，该阶段中第二编程数据通过模拟电压信号data1沿着第二路径写入至特定存储单元。在电流编程阶段，检测电路检测特定存储单元上的第一电压(V ref1)是否超过第二预设值(例如为参考电压V ref2)；如果第一电压超过第二预设值，此时FB＝逻辑“1”，参照图5中示意的FB的第二个矩形波形所示，控制单元控制编程电路停止输出。
预设值可以根据器件的实际需要进行设置，在编程过程中，通过引入 小的恒流脉冲，使得器件在编程成功后，流过一定的电流增强器件中导电通路的稳定性。在不增加导电通路的尺寸情况下，使得导电通路中氧空位浓度增加。从而，使得RRAM的保持性变好。
根据本公开的实施例，参照图3-图5所示，在复位(reset或RESET)操作下，Sel＝0且Sel_b＝1，编程电路产生恒流脉冲，极性切换电路的第二路径导通，以使编程电路沿着第二路径实现电流编程。第二路径参照图4中双点划线所示，以第二组选择晶体管导通的路径进行示例，该阶段中第一擦除数据通过模拟电压信号data1沿着第二路径写入至特定存储单元。在电流编程阶段，检测电路检测流过特定存储单元的第二电压是否小于第三预设值；如果第二电压小于第三预设值，参照图5中示意的FB的第三个矩形波形所示，FB＝逻辑“1”，控制单元控制极性切换电路由第二路径切换至第一路径，Sel＝1且Sel_b＝0，使得编程电路输出电压脉冲，以沿着第一路径实现电压编程。第一路径参照图3中单点划线所示，以第一组选择晶体管导通的路径为第一路径进行示例，该阶段中第二擦除数据通过模拟电压信号data1沿着第一路径写入至特定存储单元。在电压编程阶段，检测电路检测特定存储单元上的第二电流是否小于第四预设值；如果第二电流小于第四预设值，此时FB＝逻辑“1”，参照图5中示意的FB的第四个矩形波形所示，控制单元控制编程电路停止输出。
预设值可以根据器件的实际需要进行设置，在复位操作时，通过大电流使得器件内部导电通道上瞬间发热致使氧空位通道断裂，由于导电通路断裂的过程很随机，每次断裂都存在差异。在编程后引入小电压脉冲为了使在导电通道断裂后，随机的氧空位可以更聚集，尽量减少不必要的离散的氧空位，从而使得断裂的导电通道更稳定。
根据本公开的实施例，参照图3-图5所示，当第一选择信号(Sel_b)控制第一组选择晶体管开启，且第二选择信号(Sel)控制第二组选择晶体管关闭时，极性切换电路的第一路径导通，使得编程电路沿着第一路径实现电压编程。当第一选择信号控制第一组选择晶体管关闭，且第二选择信号控制第二组选择晶体管开启时，极性切换电路的第二路径导通，第二路径不同于第一路径，使得编程电路沿着第二路径实现电流编程。
图6为根据本公开一实施例所示的存储器电路结构的错误位计数随着 循环次数变化的曲线。图7为根据本公开一实施例所示的存储器电路结构与现有技术的存储器电路的电阻态分布函数曲线对比图。
图6中圆圈表示的是传统单脉冲操作方案下，错误位数与循环擦写器件次数变化数据。三角形表示的是本公开提出的电路操作方案下，错误位数与循环擦写器件次数变化数据。虚线分别表示的是两种脉冲操作方案下随着循环擦写次数拟合的器件错误位数的变化趋势。由图6可以明显看出，在相同错误位数下，本公开提出的电路方案可使同一器件循环操作更多次数。
图7中展示的分别是传统方案(未优化)与本公开方案(优化)的电阻态分布函数对比，传统方案是单电压脉冲操作。图7中展示了两种方案下循环操作器件得到的高阻态与低阻态的分布概率。由图7可以看出，采用本公开方案(优化)操作得到的器件阻值分布的均一性优于传统方案(未优化)。
在本公开的第二个示例性实施例中，提供了一种存储器电路结构的操作的方法。上述操作为设置操作或复位操作。
上述方法包括以下操作：S21～S24。
在操作S21，在设置操作或复位操作下，译码器选择存储阵列中特定行和特定列的特定存储单元进行操作。
在操作S22，检测电路检测存储阵列中特定存储单元对应的电流或电压的检测信号，并将检测信号反馈给控制单元。
在操作S23，控制器根据检测信号来控制极性切换电路进行切换操作以及控制编程电路的脉冲输出。
在操作S24，编程电路在控制器的作用下产生电压脉冲或恒流脉冲，并在极性切换电路的切换操作下实现设置操作下的先电压编程、后电流编程，或者实现复位操作下的先电流编程、后电压编程。
上述操作方法对存储阵列进行设置(set)或复位(reset)操作时，利用两种编程模式协同的电路方案，对整个存储阵列的编程和擦除过程进行优化，控制单元可以根据检测单元的检测信号来控制极性切换电路进行切换操作以及控制编程电路的脉冲输出，使得编程电路在设置或复位操作中，可以实现电压编程和电流编程之间的切换，从而在设置或复位操作中，实 现电压编程和恒流编程协同工作，从而优化阻变存储器的耐久性(Endurance)和保持(Retention)特性，提高阻态的均一性，降低阵列的误码率，从而在多次读写周期/循环中，还可以有效保持阻变存储器的性能。
综上所述，本公开提供了一种存储器电路结构及其操作的方法，对存储阵列进行设置或复位操作时，控制单元可以根据检测单元的检测信号来控制极性切换电路进行切换操作以及控制编程电路的脉冲输出，使得编程电路在设置或复位操作中，可以实现电压编程和电流编程之间的切换，从而在设置或复位操作中，实现电压编程和恒流编程协同工作，利用两种编程模式协同的电路方案，对整个存储阵列的编程和擦除过程进行优化，从而优化阻变存储器的耐久性和保持特性，提高阻态的均一性，降低阵列的误码率，从而在多次读写周期/循环中，还可以有效保持阻变存储器的性能。
还需要说明的是，虽然结合附图对本公开进行了说明，但是附图中公开的实施例旨在对本公开优选实施方式进行示例性说明，而不能理解为对本公开的一种限制。附图中的尺寸比例仅仅是示意性的，并不能理解为对本公开的限制。实施例中提到的方向用语，例如“上”、“下”、“前”、“后”、“左”、“右”等，仅是参考附图的方向，并非用来限制本公开的保护范围。贯穿附图，相同的元素由相同或相近的附图标记来表示。在可能导致对本公开的理解造成混淆时，将省略常规结构或构造。
并且图中各部件的形状和尺寸不反映真实大小和比例，而仅示意本公开实施例的内容。另外，在权利要求中，不应将位于括号之间的任何参考符号构造成对权利要求的限制。
说明书与权利要求中所使用的序数例如“第一”、“第二”、“第三”等的用词，以修饰相应的元件，其本身并不意味着该元件有任何的序数，也不代表某一元件与另一元件的顺序、或是制造方法上的顺序，该些序数的使用仅用来使具有某命名的一元件得以和另一具有相同命名的元件能做出清楚区分。再者，单词“包含”或“包括”不排除存在未列在权利要求中的元件或步骤。位于元件之前的单词“一”或“一个”不排除存在多个这样的元件。
除非存在技术障碍或矛盾，本公开的上述各种实施方式可以自由组合以形成另外的实施例，这些另外的实施例均在本公开的保护范围中。
以上所述的具体实施例，对本公开的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本公开的具体实施例而已，并不用于限制本公开，凡在本公开的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (10)

  1. 一种存储器电路结构，其特征在于，包括：
    存储阵列，包含至少两个存储单元；
    译码器，与所述存储阵列的位线和字线分别连接，用于选择特定行和特定列的特定存储单元进行操作；
    编程电路，用于产生电压脉冲或恒流脉冲；
    极性切换电路，与所述编程电路连接，用于在设置操作及复位操作下实现所述编程电路在电压编程与电流编程之间的切换；
    检测电路，与所述存储阵列连接，用于检测所述存储阵列中所述特定存储单元对应的电流或电压的检测信号，并将所述检测信号反馈给控制单元，所述检测电路输出的检测信号用于使能所述极性切换电路进行切换；以及
    控制单元，用于根据所述检测信号来控制所述极性切换电路进行切换操作以及控制所述编程电路的脉冲输出。
  2. 根据权利要求1所述的存储器电路结构，其特征在于，
    在设置操作下，所述编程电路产生电压脉冲，所述极性切换电路的第一路径导通，以使所述编程电路沿着第一路径实现电压编程；
    在电压编程阶段，所述检测电路检测流过特定存储单元的第一电流是否超过第一预设值；
    如果所述第一电流超过第一预设值，所述控制单元控制所述极性切换电路由第一路径切换至第二路径，并使得所述编程电路输出恒流脉冲，以沿着所述第二路径实现电流编程；
    在电流编程阶段，所述检测电路检测所述特定存储单元上的第一电压是否超过第二预设值；
    如果所述第一电压超过第二预设值，所述控制单元控制所述编程电路停止输出。
  3. 根据权利要求1所述的存储器电路结构，其特征在于，
    在复位操作下，所述编程电路产生恒流脉冲，所述极性切换电路的第二路径导通，以使所述编程电路沿着第二路径实现电流编程；
    在电流编程阶段，所述检测电路检测流过特定存储单元的第二电压是否小于第三预设值；
    如果所述第二电压小于第三预设值，所述控制单元控制所述极性切换电路由第二路径切换至第一路径，并使得所述编程电路输出电压脉冲，以沿着所述第一路径实现电压编程；
    在电压编程阶段，所述检测电路检测所述特定存储单元上的第二电流是否小于第四预设值；
    如果所述第二电流小于第四预设值，所述控制单元控制所述编程电路停止输出。
  4. 根据权利要求1所述的存储器电路结构，其特征在于，所述极性切换电路包括两组并联的选择晶体管，每组选择晶体管内包括串联的至少两个选择晶体管，所述两组选择晶体管分别为第一组选择晶体管和第二组选择晶体管，所述第一组选择晶体管由所述控制单元输出的第一选择信号控制通断，所述第二组选择晶体管由所述控制单元输出的第二选择信号控制通断，所述第一选择信号控制所述第一组选择晶体管开启的同时所述第二选择信号控制所述第二组选择晶体管关闭，或者，所述第一选择信号控制所述第一组选择晶体管关闭的同时所述第二选择信号控制所述第二组选择晶体管开启。
  5. 根据权利要求4所述的存储器电路结构，其特征在于，
    当所述第一选择信号(Sel_b)控制所述第一组选择晶体管开启，且所述第二选择信号(Sel)控制所述第二组选择晶体管关闭时，所述极性切换电路的第一路径导通，使得所述编程电路沿着所述第一路径实现电压编程；
    当所述第一选择信号控制所述第一组选择晶体管关闭，且所述第二选择信号控制所述第二组选择晶体管开启时，所述极性切换电路的第二路径导通，所述第二路径不同于所述第一路径，使得所述编程电路沿着所述第二路径实现电流编程。
  6. 根据权利要求1所述的存储器电路结构，其特征在于，所述检测电路包括：
    第一晶体管，由所述控制单元输出的第一选择信号控制通断；所述第一晶体管的一端作为所述检测电路的输入端；
    第一比较器，所述第一比较器的负极输入端与所述第一晶体管的另一端连接，所述第一比较器的正极输入端用于输入所述特定存储单元对应的电压的检测信号；
    第二晶体管，由所述控制单元输出的第二选择信号控制通断；所述第二晶体管的一端与所述存储阵列连接；
    第二比较器，所述第二比较器的正极输入端与所述第二晶体管的另一端连接，所述第二比较器的负极输入端用于输入参考电压；所述第一比较器的负极输入端和所述第二比较器的正极输入端连接；以及
    逻辑门，所述逻辑门的两个输入端分别连接所述第一比较器的输出端和所述第二比较器的输出端，所述逻辑门的输出为检测信号。
  7. 根据权利要求6所述的存储器电路结构，其特征在于，还包括：
    电流供应和管理电路，所述电流供应和管理电路包括电流镜电路，所述电流镜电路包含两个输出端；
    其中，所述电流镜电路的两个输出端中的一个输出端与所述极性切换电路的输入端连接，所述电流镜电路的两个输出端中的另一个输出端与所述检测电路的输入端连接。
  8. 根据权利要求1所述的存储器电路结构，其特征在于，还包括：
    偏压电路，所述偏压电路与所述编程电路连接；
    其中，所述控制单元输出使能信号以使偏压电路产生模拟电压信号；所述模拟电压信号输出至编程电路中。
  9. 根据权利要求1-8中任一项所述的存储器电路结构，其特征在于，所述存储单元为阻变存储器。
  10. 一种如权利要求1-9中任一项所述的存储器电路结构的操作的方法，所述操作为设置操作或复位操作，其特征在于，所述方法包括：
    在所述设置操作或复位操作下，所述译码器选择所述存储阵列中特定行和特定列的特定存储单元进行操作；
    所述检测电路检测所述存储阵列中所述特定存储单元对应的电流或电压的检测信号，并将所述检测信号反馈给控制单元；
    所述控制器根据所述检测信号来控制所述极性切换电路进行切换操作以及控制所述编程电路的脉冲输出；
    所述编程电路在控制器的作用下产生电压脉冲或恒流脉冲，并在所述极性切换电路的切换操作下实现设置操作下的先电压编程、后电流编程，或者实现复位操作下的先电流编程、后电压编程。
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