WO2022068126A1 - 存储单元和阻变存储器的操作方法、电子设备 - Google Patents

存储单元和阻变存储器的操作方法、电子设备 Download PDF

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WO2022068126A1
WO2022068126A1 PCT/CN2021/073534 CN2021073534W WO2022068126A1 WO 2022068126 A1 WO2022068126 A1 WO 2022068126A1 CN 2021073534 W CN2021073534 W CN 2021073534W WO 2022068126 A1 WO2022068126 A1 WO 2022068126A1
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resistive
voltage
value
resistive device
constant
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PCT/CN2021/073534
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English (en)
French (fr)
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许晓欣
余杰
董大年
余兆安
吕杭炳
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中国科学院微电子研究所
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Publication of WO2022068126A1 publication Critical patent/WO2022068126A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00

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  • the present disclosure belongs to the field of storage technology, and relates to an operation method of a storage unit and a resistive memory, and an electronic device.
  • Resistive variable memory has the advantages of simple structure, small size and high integration. Its preparation process is independent of the front-end process (FEOL) and is compatible with advanced logic processes such as HKMG and FinFET, so it is an embedded non-volatile memory for advanced nodes (below 28nm). Volatile memory solution.
  • the resistive memory will have a high resistance state and a low resistance state under the excitation of pulse voltages of different polarities, and can be used as a storage or logic device based on different resistance state differences.
  • a larger device parameter is selected for the programming operation, which will lead to the appearance of the device. High resistance state fluctuations and poor device uniformity problems also lead to reduced device durability and data retention characteristics.
  • the present disclosure provides an operation method and electronic device of a memory cell and a resistive memory, so as to improve at least one of uniformity and data retention characteristics of the resistive memory.
  • a first aspect of the present disclosure provides a method of operating a memory unit.
  • the storage unit includes: a resistive switching device.
  • the operation method of the above-mentioned storage unit includes: performing a writing operation on the resistive device.
  • the writing operation includes: applying a first voltage for writing on the resistive switching device; during the application of the writing voltage, determining whether the resistance value of the resistive switching device reaches a low resistance state threshold; When the value reaches the low resistance state threshold, a constant current is applied to the resistive switching device, and the voltage value generated by the constant current on the resistive switching device is smaller than the voltage value of the first voltage.
  • the above-mentioned writing operation further includes: during the period of applying the constant current, determining whether the duration of applying the constant current to the resistive device is greater than a first preset duration; if the duration of applying the constant current to the resistive device is greater than the first duration For a preset time period, the constant current applied to the resistive device stops loading.
  • the above-mentioned writing operation further includes: during the application of the constant current, determining whether the voltage value of the resistive device is greater than a preset voltage value; when the voltage value of the resistive device is greater than the preset voltage value , the constant current applied to the resistive device stops loading.
  • the above operation method further includes: performing an erasing operation on the resistive device.
  • the erasing operation includes: applying a second voltage for erasing on the resistive device; during the period of applying the erasing voltage, determining whether the resistance value of the resistive device reaches a reference resistance value; when the resistance value of the resistive device reaches In the case of the reference resistance value, a constant voltage is applied to the resistive switching device, and the voltage value of the constant voltage is smaller than the voltage value of the second voltage.
  • the above-mentioned erasing operation further includes: during the period of applying the constant voltage, determining whether the duration of applying the constant voltage to the resistive device is greater than a second preset duration; if the duration of applying the constant voltage to the resistive device is greater than the second duration For a preset time period, the constant voltage applied on the resistive device stops loading.
  • the above-mentioned erasing operation further includes: during the period of applying the constant voltage, determining whether the passing current of the resistive device is less than a preset current value; when the passing current of the resistive device is less than the preset current value , the constant voltage applied across the resistive device stops loading.
  • the above-mentioned memory cell further includes: a transistor connected in series with the resistive switching device.
  • the gate of the transistor is used to connect to the word line
  • the source of the transistor is used to connect to the source line
  • the drain of the transistor is connected to one electrode end of the resistive device
  • the other electrode end of the resistive device is used to connect with the source line. bit line connection.
  • a specific pulse is applied to the word line corresponding to the transistor connected to the resistive switching device, the source line corresponding to the transistor connected to the resistive switching device is kept low, and the bit line connected to the resistive switching device is kept high, so as to realize the pairing of the resistive switching device.
  • Write operation of resistive devices is a sequence in which the first voltage and the third current are successively loaded successively, and the current value of the third current is equal to the current value of the constant current.
  • Another specific pulse is a sequence in which the second voltage and the fourth voltage are successively applied successively, and the voltage value of the fourth voltage is equal to the voltage value of the constant voltage.
  • a second aspect of the present disclosure provides a method of operating a resistive memory.
  • the resistive memory includes a memory array, and the memory array includes at least two memory cells.
  • the operation method of the above-mentioned resistive memory includes: selecting a target memory cell based on a word line and a bit line; for the target memory cell, executing any of the above-mentioned operation methods of the memory cell.
  • a third aspect of the present disclosure provides an electronic device.
  • the above electronic device includes: one or more processors; and a storage medium for storing one or more programs. Wherein, when one or more programs are executed by one or more processors, the one or more processors can operate any one of the storage units described above, the electronic device is independent of the storage unit, or the electronic device is independent of the storage unit.
  • the device includes a storage unit. Or, when one or more programs are executed by one or more processors, causing one or more processors to execute the above-mentioned operation method of the resistive memory, the electronic device is independent of the resistive memory, or the electronic device The device includes a resistive memory.
  • the resistive switching device is programmed based on the written first voltage, and conductive filaments can be formed in the resistive switching material layer. After the resistive switching device reaches the low resistance state threshold, the resistive switching device is The programming is successful (or described as setting/setting is successful), but the local area of the formed conductive filament is relatively thin, and the formed conductive filament is not very stable. If oxygen ions and oxygen vacancies recombine, it will cause relaxation Then continue to apply a relatively small constant current to the resistive switching device, thereby promoting the stability of the formation of conductive filaments during the setting (Set) process of the resistive switching device, and improving the maintenance of the device in a low resistance state. capability, improve the uniformity and data retention characteristics of the resistive switching device, and also improve the durability of the device.
  • the duration or degree of applying the constant current is controlled based on the first preset duration or the preset voltage value, which can effectively ensure that the conductive filaments of the resistive device are formed more stably. Avoid moving the resistive device to the direction of high resistance value due to the constant current being applied for too long or the degree is too large.
  • the resistive device is erased based on the second voltage, so that oxygen ions and oxygen vacancies in the resistive device are recombined, resulting in the breakage of the conductive filament, and the resistance value of the resistive device reaches the reference value.
  • the resistive device is successfully erased (or described as successful reset), but there may be a phenomenon that the conductive filament is not completely broken, and there may be oxygen vacancies in the broken gap area;
  • a small constant voltage is applied to the resistive switching device, so that in the reset process of the resistive switching device, the oxygen vacancies in the gap of the resistive switching material layer can be removed, so that the high-resistance state retention characteristics of the device are improved, so that the The distribution of the resistance value in the high resistance state of the device is more concentrated, the uniformity and data retention characteristics of the resistive switching device are improved, the soft failure of the device is reduced, and the durability of the device is also improved.
  • the duration or degree of applying the constant voltage is controlled based on the second preset duration or the limitation of the preset current value, so as to ensure that the conductive filaments of the resistive device have a relatively complete degree of breakage and at the same time
  • the resistive switching device is effectively prevented from moving to a higher resistance value direction due to the constant voltage being applied for too long or the degree is too large, so as to avoid higher energy consumption in the next writing operation.
  • FIG. 1 is a pulse timing diagram corresponding to an operation method of a memory cell according to an embodiment of the present disclosure.
  • FIG. 2 is a schematic diagram of (a) an exemplary path of an operation method of a memory cell according to an embodiment of the present disclosure, (b) a state diagram of writing and erasing a corresponding resistive device; (c) an existing operation The state of the resistive device corresponding to the over-programming in the method is shown, and (d) is the state of the resistive device corresponding to the under-programming in the existing operation method.
  • FIG. 3 is a flowchart of a method for writing a memory cell according to an embodiment of the present disclosure.
  • FIG. 4 is a flowchart of a method for erasing a memory cell according to an embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of a memory cell according to an embodiment of the present disclosure.
  • FIG. 6 is a timing diagram of a word line, a bit line, a source line and an equivalent pulse on a resistive switching device corresponding to a 1T1R structure of a memory cell according to an embodiment of the present disclosure.
  • FIG. 7 is a distribution diagram of high and low resistance states after a programming operation is performed on the resistive memory compared with the existing solution and the operating method of the resistive memory according to the embodiment of the present disclosure.
  • FIG. 8 is a data retention characteristic diagram obtained by testing the resistive memory at 150°C for 5 hours after programming the resistive memory by comparing the existing solution with the operating method of the resistive memory shown in the embodiment of the present disclosure.
  • a resistive memory is generally an array structure having a plurality of memory cells, each memory cell may be a 1T-1R structure, that is, a structure including one transistor and one resistive switching device.
  • the resistive device includes: a resistive material layer, and electrode layers located on the upper and lower sides of the resistive material layer. Under the excitation of different pulse voltages, the resistive material layer exhibits different resistance characteristics and has different resistance states.
  • a write (also called programming) operation a set/set operating voltage is applied to the resistive memory, and oxygen ions in the RRAM move to the oxygen storage layer at the upper electrode, forming oxygen vacancies in the resistive material layer Conductive filament, corresponding to the RRAM in a low resistance state.
  • a reset (Reset) operating voltage is applied to the resistive memory, oxygen ions and oxygen vacancies recombine, causing the conductive filaments to break, and the corresponding RRAM is in a high resistance state.
  • the programming parameters of the resistive device fluctuate, in order to ensure the programming success rate of the resistive device, a larger device parameter is generally selected for programming. Therefore, for the devices in the memory array, over-programming often occurs, and the formed conductive filaments are thicker. In this case, in the subsequent erasing process, higher energy is required for filament breakage, and it is prone to incomplete filament breakage, which may lead to a phenomenon of soft failure, resulting in reduced device durability. The incomplete erasing phenomenon of the device also leads to: the high resistance state fluctuation of the device is relatively large, and the uniformity of the device is deteriorated.
  • adaptive programming can slow down the degradation speed of the device and prolong the life of the device, under this programming condition, after the Set operation of the device is completed, although the conductive filaments in the device are formed, the conductive filaments are not very stable, and oxygen ions are not very stable. Recombination with oxygen vacancies results in relaxation, which leads to changes in the resistance state of the device, often manifested as poor ability to maintain low resistance states and unstable device operation.
  • the voltage excitation stops when the device reaches the reference resistance value.
  • the residual oxygen vacancies will With reconnection of the filament, the resistance value becomes smaller and the hold-up capability of the device decreases.
  • the present disclosure proposes an operation method of a memory cell, an operation method of a resistive memory, and an electronic device capable of improving the uniformity, data retention characteristics, and durability of the resistive device.
  • the first exemplary embodiment of the present disclosure provides an operating method of a memory cell.
  • the storage unit includes: a resistive switching device.
  • FIG. 1 is a pulse timing diagram corresponding to an operation method of a memory cell according to an embodiment of the present disclosure.
  • 2 is a schematic diagram of (a) an exemplary path of an operation method of a memory cell according to an embodiment of the present disclosure, (b) a state diagram of writing and erasing a corresponding resistive device; (c) an existing operation The state of the resistive device corresponding to the over-programming in the method is shown, and (d) is the state of the resistive device corresponding to the under-programming in the existing operation method.
  • FIG. 3 is a flowchart of a method for writing a memory cell according to an embodiment of the present disclosure. In the pulse timing diagrams shown in FIGS.
  • the left-right direction is the time axis
  • the up-down direction is the voltage axis.
  • the horizontal dotted lines in FIG. 1 indicate the same horizontal line
  • the vertical dotted lines indicate different operation stages, including four stages: writing, reading, erasing, and reading.
  • the operation method of the memory cell according to the embodiment of the present disclosure includes: performing a writing operation on a resistive switching device.
  • the writing operation includes the following steps: S31-S33.
  • step S31 a first voltage for writing is applied to the resistive device.
  • step S32 during the period of applying the write voltage, it is determined whether the resistance value of the resistive switching device reaches the low resistance state threshold.
  • the above-mentioned determining whether the resistance value of the resistive device reaches the low resistance state threshold includes: during the period of applying the write voltage, according to whether the pass current I pass1 of the resistive device is greater than the first threshold A reference value I ref1 is used to determine whether the resistance value of the resistive device reaches the low resistance state threshold.
  • the above-mentioned low-resistance state threshold may be a range, and then the corresponding first reference value is also a range.
  • the first reference value calculated from any value within the low-resistance threshold range can be used for judgment to determine the timing of entering the constant current application.
  • the curve arrows are used to indicate the loading timing of three different constant currents corresponding to paths 3, 2, 1 during the writing period
  • Fig. 2 (a) shows the writing and reading corresponding to path 3.
  • the pulse timing trend corresponding to each stage of fetching, erasing and reading.
  • step S33 when the resistance value of the resistive switching device reaches the low resistance state threshold, a constant current is applied to the resistive switching device, and the voltage value generated by the constant current on the resistive switching device is smaller than the voltage value of the first voltage.
  • the voltage value generated by the constant current on the resistive device is 1/10 to 1/2 of the voltage value of the first voltage, including the endpoint value.
  • the voltage value generated by the constant current on the resistive device is 3/10, 1/3, 2/5 or 1/2 of the voltage value of the first voltage.
  • a constant current is applied to the resistive switching device.
  • the current value of the constant current is shown as I 3 , and the constant current is generated on the resistive switching device.
  • the voltage value of is less than the voltage value of the first voltage.
  • the resistance value of the resistive device itself may fluctuate or change.
  • the selection of the current value I of the above-mentioned constant current should satisfy: the above-mentioned constant current
  • the voltage value generated on the resistive device is always smaller than the voltage value V 1 of the first voltage.
  • an adaptive programming method is used to reduce the over-programming of the device.
  • the resistance value of the resistive switching device reaches a low resistance state threshold
  • the applied voltage is immediately removed to prevent the device from being over-programmed.
  • the conductive filaments in the device are not very stable, and there is a phenomenon of insufficient programming. Oxygen ions and oxygen vacancies recombine, resulting in a relaxation phenomenon, resulting in a change in the resistance state of the device, which is often manifested as poor ability to maintain a low resistance state and unstable device operation.
  • the voltage excitation is stopped. There are residual oxygen vacancies in the gap between the residual filament and the electrode in the device. During the process, the residual oxygen vacancies will reconnect with the filaments, resulting in a smaller resistance value and lower device retention.
  • the resistive switching device in the writing operation, is programmed based on the written first voltage, which can Conductive filaments are formed in the resistive material layer. After the resistive device reaches the low-resistance threshold, the resistive device is successfully set/positioned, but there will be local areas of the formed conductive filaments that are relatively thin, and the formed conductive filaments are relatively thin.
  • the silk is not very stable, and if oxygen ions and oxygen vacancies recombine, it will cause a relaxation phenomenon; therefore, the present disclosure continues to apply a relatively small constant current to the resistive switching device, thereby improving the setting (Set) of the resistive switching device.
  • the above-mentioned writing operation further includes the step of determining whether the constant current stops being loaded.
  • the above-mentioned step of determining whether the constant current stops being loaded may include steps S34a and S35a, or steps S34b and S35b.
  • step S34a during the period of applying the constant current, it is determined whether the duration for which the resistive device applies the constant current is greater than the first preset duration.
  • step S35a if the duration of applying the constant current to the resistive device is longer than the first preset duration, the constant current applied to the resistive device stops loading.
  • step S34b during the period of applying the constant current, it is determined whether the voltage value of the resistive device is greater than the preset voltage value.
  • step S35b when the voltage value of the resistive switching device is greater than the preset voltage value, the constant current applied to the resistive switching device stops loading.
  • the duration or degree of applying the constant current is controlled based on the first preset duration or the preset voltage value, which can effectively avoid resistive switching while ensuring that the conductive filaments of the resistive device are formed more stably.
  • the resistive switching device moves in the direction of high resistance value due to the application of constant current for too long or too much.
  • the above-mentioned first preset time period and preset voltage value can be set according to actual needs.
  • the above conditions are to avoid the constant current loading time/degree being too large, which will cause the low resistance state of the resistive device to stabilize and then increase. Timing to stop loading constant current.
  • FIG. 4 is a flowchart of a method for erasing a memory cell according to an embodiment of the present disclosure.
  • the above operation method further includes: performing an erasing operation on the resistive device.
  • the erasing operation includes the following steps: S41-S43.
  • step S41 a second voltage for erasing is applied to the resistive device.
  • step S42 during the period of applying the erasing voltage, it is determined whether the resistance value of the resistive device reaches the reference resistance value.
  • the above-mentioned determining whether the resistance value of the resistive device reaches the reference resistance value includes: during the period of applying the erasing voltage, according to whether the pass current I pass2 of the resistive device is greater than the second
  • the reference value I ref2 is used to determine whether the resistance value of the resistive device reaches the reference resistance value.
  • the above reference resistance value may be a range, and then the corresponding second reference value is also a range.
  • the second reference value calculated from any value within the reference resistance value range can be used for judgment, so as to determine the timing of entering the constant voltage application. For example, in FIG. 1 , the loading timings of three different constant voltages corresponding to the paths 3, 2, and 1 during erasing are indicated by the curved arrows.
  • step S43 when the resistance value of the resistive switching device reaches the reference resistance value, a constant voltage is applied to the resistive switching device, and the voltage value of the constant voltage is smaller than the voltage value of the second voltage.
  • the voltage value of the above-mentioned constant voltage is 1/10 to 1/2 of the voltage value of the second voltage, including the endpoint value.
  • the voltage value of the constant voltage is 1/5, 3/10, 1/3, or 2/5 of the voltage value of the second voltage.
  • the resistive device in the erasing operation, is erased based on the second voltage, so that the resistance changes Oxygen ions and oxygen vacancies in the device recombine, resulting in the breakage of the conductive filaments.
  • the resistive device is successfully reset, but the conductive filament may not be completely broken. , there may be oxygen vacancies in the fractured gap region; then continue to apply a relatively small constant voltage to the resistive device, so that during the reset process of the resistive device, the gap of the resistive material layer can be closed.
  • the removal of oxygen vacancies in the device improves the high-resistance state retention characteristics of the device, as shown in the right figure in (b) of Figure 2, so that the distribution of the high-resistance state resistance value of the device is more concentrated, and the uniformity of the resistive switching device is improved. and data retention characteristics, reduce the soft failure of the device, and also improve the durability of the device.
  • the above-mentioned erasing operation further includes the step of determining whether the constant voltage stops loading.
  • the above-mentioned step of determining whether the constant voltage is stopped from loading may include steps S44a and S45a, or steps S44b and S45b.
  • step S44a during the period of applying the constant voltage, it is determined whether the duration for which the resistive device applies the constant voltage is greater than the second preset duration.
  • step S45a if the duration of applying the constant voltage to the resistive device is longer than the second preset duration, the constant voltage applied to the resistive device stops being loaded.
  • step S44b during the period of applying the constant voltage, it is determined whether the passing current of the resistive device is smaller than the preset current value.
  • step S45b when the passing current of the resistive device is less than the preset current value, the constant voltage applied to the resistive device stops loading.
  • the duration or degree of applying the constant voltage is controlled based on the second preset duration or the limitation of the preset current value, which can effectively avoid resistance while ensuring that the conductive filaments of the resistive device are fractured more completely.
  • the resistive device moves to a higher resistance value direction due to the constant voltage being applied for too long or the degree is too large, so as to avoid higher energy consumption in the next writing operation.
  • the above-mentioned second preset duration and preset current value can be set according to actual needs.
  • the above conditions are to avoid that the constant voltage loading time/degree is too large, resulting in a further increase after the high resistance state of the resistive device is realized. time to stop applying constant voltage.
  • FIG. 5 is a schematic structural diagram of a memory cell according to an embodiment of the present disclosure.
  • the above-mentioned memory cell includes: a resistive switching device, and a transistor connected in series with the resistive switching device.
  • the gate of the transistor is used to connect to the word line WL
  • the source of the transistor is used to connect to the source line SL
  • the drain of the transistor is connected to one electrode end of the resistive device
  • the other electrode end of the resistive device is used for connected to the bit line BL.
  • the equivalent voltage drawn from one electrode terminal of the resistive device is V O .
  • FIG. 6 is a timing diagram of a word line, a bit line, a source line and an equivalent pulse on a resistive switching device corresponding to a 1T1R structure of a memory cell according to an embodiment of the present disclosure.
  • timing diagrams of the word line WL, the bit line BL, the source line SL and the equivalent voltage VO are respectively illustrated.
  • a specific pulse is applied to the word line WL corresponding to the transistor connected to the resistive switching device, the source line SL corresponding to the transistor connected to the resistive switching device is maintained at a low level, and the bit line BL connected to the resistive switching device is maintained at a high level.
  • the above-mentioned specific pulse is a sequence in which the first voltage and the third current are successively loaded successively, and the current value of the third current is equal to the current value of the constant current.
  • Another specific pulse is applied to the source line SL corresponding to the transistor connected to the resistive switching device, the word line WL corresponding to the transistor connected to the resistive switching device is maintained at a high level, and the bit line WL connected to the resistive switching device The line BL is kept low to realize the erasing operation of the resistive device.
  • Another specific pulse is a sequence in which the second voltage and the fourth voltage are successively applied successively, and the voltage value of the fourth voltage is equal to the voltage value of the constant voltage.
  • the above operation method also includes: a read operation performed after the write operation and a read operation performed after the erase operation.
  • the above-mentioned reading operation is the same as that in the prior art, and will not be described in detail here.
  • the second exemplary embodiment of the present disclosure provides an operating method of a resistive memory.
  • the resistive memory includes a memory array, and the memory array includes at least two memory cells.
  • the operating method of the resistive memory in this embodiment includes: selecting a target memory cell based on a word line and a bit line; for the target memory cell, executing any of the above-mentioned memory cell operating methods.
  • the memory array is an array structure, and the memory cell corresponding to a specific row and column can be selected based on the decoder, and the selected memory cell is the target memory cell.
  • the operation method described in the first embodiment is performed on the target memory cell, and the resistive memory after writing, reading, erasing and reading based on the above operation method has good resistance state uniformity and data retention characteristics, And has good durability.
  • FIG. 7 is a distribution diagram of high and low resistance states after a programming operation is performed on the resistive memory compared with the existing solution and the operating method of the resistive memory according to the embodiment of the present disclosure.
  • FIG. 8 is a data retention characteristic diagram obtained by testing the resistive memory at 150° C. for 5 hours after programming the resistive memory by comparing the existing solution and the operating method of the resistive memory according to the embodiment of the present disclosure.
  • the existing adaptive programming method and the operating method of the embodiment of the present disclosure are used to program (write) the resistive memory, and the distribution comparison diagram of the high and low resistance states of the resistive memory obtained by testing can be Referring to Figure 7.
  • using the solution of the embodiment of the present disclosure can make the distribution of the high-resistance state and the low-resistance state of the device concentrated, reduce the fluctuation, and significantly improve the uniformity of the device.
  • the resistive memory is tested after being baked at 150° C. for 5 hours.
  • Data retention performance a comparison chart of data retention characteristics obtained by testing is shown in Figure 8. It can be seen from FIG. 8 that, after the device is programmed with the solution according to the embodiment of the present disclosure, the retention capability of the device is significantly improved.
  • a third exemplary embodiment of the present disclosure provides an electronic device.
  • the above electronic device includes: one or more processors; and a storage medium for storing one or more programs.
  • the one or more processors can operate any one of the storage units described above, the electronic device is independent of the storage unit, or the electronic device is independent of the storage unit.
  • the device includes a storage unit.
  • the electronic device is independent of the resistive memory, or the electronic device The device includes a resistive memory.
  • the present disclosure provides an operation method and electronic device for a memory cell and a resistive memory.
  • a constant current is continuously applied on the basis of adaptive programming, so that in the Set process, the conductive filaments form
  • a constant small current is continued to flow through the device, so that on the basis of successful programming of the device, the filaments are formed more stably, thereby improving the ability to maintain the device in a low-resistance state.
  • a small constant voltage is continued to remove the oxygen vacancies in the gap, so that the high-resistance state retention characteristics of the device are improved.
  • the distribution of the high resistance state resistance value of the device is more concentrated, the uniformity of the device is improved, the soft failure of the device is reduced, and the durability of the device is improved.

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Abstract

一种存储单元和阻变存储器的操作方法、电子设备，上述存储单元的操作方法包括: 对阻变器件进行写入和擦除操作。写入操作包括: 在阻变器件上施加写入电压，并确定阻变器件的电阻值是否达到低阻态阈值; 在阻变器件的电阻值达到低阻态阈值的情况下，在阻变器件上施加恒定电流，该恒定电流在阻变器件上产生的电压值小于写入电压的电压值。擦除操作包括: 在阻变器件上施加擦除电压，并确定阻变器件的电阻值是否达到参考阻值; 在阻变器件的电阻值达到参考阻值的情况下，在阻变器件上施加恒定电压，恒定电压的电压值小于擦除电压的电压值。提高了器件在低阻态的保持能力，提高了阻变器件的均一性和数据保持特性，并且还提高了器件的耐久性。

Description

存储单元和阻变存储器的操作方法、电子设备 技术领域
本公开属于存储技术领域，涉及一种存储单元和阻变存储器的操作方法、电子设备。
背景技术
云计算、边缘计算等技术的飞速发展，使系统级芯片(SOC)对于嵌入式存储器在性能和功耗上提出了更高的需求，但随着半导体工艺的进一步微缩，特别是进入28nm工艺节点后，传统的嵌入式闪存与以高k金属栅(HKMG)和鳍式场效应晶体管(FinFET)为代表的先进逻辑工艺的集成难度进一步增大。不仅制备成本上大幅度增加，器件性能也由于器件尺寸的缩小而退化严重，因此传统式闪存很难延伸到40nm以下。
阻变存储器(RRAM)具有结构简单，尺寸小，集成度高等优点，其制备工艺独立于前段工艺(FEOL)，兼容HKMG，FinFET等先进逻辑工艺，所以是先进节点(28nm以下)的嵌入式非易失存储器的解决方案。
阻变存储器在不同极性的脉冲电压激励下会具有高阻态和低阻态，基于不同的阻态差异可以作为存储或者逻辑器件。然而，在写入操作或者擦除操作中，由于阻变器件的编程参数存在波动性，通常为了保证阻变器件的编程成功率，会选用较大的器件参数进行编程操作，如此会导致器件出现高阻态波动较大、器件的均一性较差的问题，同时还会导致器件的耐久性和数据保持特性降低。
因此，有必要提出一种能够提高阻变存储器的均一性和数据保持特性至少之一的操作方法。
发明内容
有鉴于此，本公开提供了一种存储单元和阻变存储器的操作方法、电子设备，以提高阻变存储器的均一性和数据保持特性至少之一。
本公开的第一个方面提供了一种存储单元的操作方法。存储单元包括：阻变器件。上述存储单元的操作方法包括：对阻变器件进行写入操作。该 写入操作包括：在阻变器件上施加用于写入的第一电压；在施加写入电压的期间，确定阻变器件的电阻值是否达到低阻态阈值；以及在阻变器件的电阻值达到低阻态阈值的情况下，在阻变器件上施加恒定电流，该恒定电流在阻变器件上产生的电压值小于第一电压的电压值。
根据本公开的实施例，上述写入操作还包括：在施加恒定电流的期间，确定阻变器件施加恒定电流的时长是否大于第一预设时长；如果阻变器件施加恒定电流的时长大于第一预设时长，在阻变器件上施加的恒定电流停止加载。
根据本公开的实施例，上述写入操作还包括：在施加恒定电流的期间，确定阻变器件的电压值是否大于预设电压值；在阻变器件的电压值大于预设电压值的情况下，在阻变器件上施加的恒定电流停止加载。
根据本公开的实施例，上述操作方法还包括：对阻变器件进行擦除操作。该擦除操作包括：在阻变器件上施加用于擦除的第二电压；在施加擦除电压的期间，确定阻变器件的电阻值是否达到参考阻值；在阻变器件的电阻值达到参考阻值的情况下，在阻变器件上施加恒定电压，恒定电压的电压值小于第二电压的电压值。
根据本公开的实施例，上述擦除操作还包括：在施加恒定电压的期间，确定阻变器件施加恒定电压的时长是否大于第二预设时长；如果阻变器件施加恒定电压的时长大于第二预设时长，在阻变器件上施加的恒定电压停止加载。
根据本公开的实施例，上述擦除操作还包括：在施加恒定电压的期间，确定阻变器件的通过电流是否小于预设电流值；在阻变器件的通过电流小于预设电流值的情况下，在阻变器件上施加的恒定电压停止加载。
根据本公开的实施例，上述存储单元还包括：与阻变器件串联连接的晶体管。其中，晶体管的栅极用于与字线连接，晶体管的源极用于与源极线连接，晶体管的漏极与阻变器件的一个电极端连接，阻变器件的另一个电极端用于与位线连接。
在阻变器件连接的晶体管对应的字线上施加特定脉冲，在阻变器件连接的晶体管对应的源线上保持低电平，在阻变器件连接的位线上保持高电平，以实现对阻变器件的写入操作。上述特定脉冲为第一电压和第三电流 先后连续加载的序列，所述第三电流的电流值等于所述恒定电流的电流值。
在阻变器件连接的晶体管对应的源线上施加另一特定脉冲，在阻变器件连接的晶体管对应的字线上保持高电平，在阻变器件连接的位线上保持低电平，以实现对阻变器件的擦除操作。另一特定脉冲为第二电压和第四电压先后连续加载的序列，第四电压的电压值等于恒定电压的电压值。
本公开的第二个方面提供了一种阻变存储器的操作方法。阻变存储器包括存储阵列，存储阵列包括至少两个存储单元。上述阻变存储器的操作方法包括：基于字线和位线选定目标存储单元；针对目标存储单元，执行如上所述的任一种存储单元的操作方法。
本公开的第三个方面提供了一种电子设备。上述电子设备包括：一个或多个处理器；以及用于存储一个或多个程序的存储介质。其中，当一个或多个程序被一个或多个处理器执行时，使得一个或多个处理器如上所述的任一种存储单元的操作方法，该电子设备独立于存储单元，或者，该电子设备包括存储单元。或者，当一个或多个程序被一个或多个处理器执行时，使得一个或多个处理器执行如上所述的阻变存储器的操作方法，该电子设备独立于阻变存储器，或者，该电子设备包括阻变存储器。
从上述技术方案可以看出，本公开实施例提供的存储单元和阻变存储器的操作方法、电子设备，至少具有以下有益效果：
(1)在写入操作中，基于写入的第一电压对阻变器件进行编程，可以在阻变材料层中形成导电细丝，在阻变器件达到低阻态阈值之后，阻变器件被编程成功(或者描述为设置/置位成功)，但是会存在形成的导电细丝的局部区域比较单薄，形成的导电细丝并不是很稳定，如果氧离子和氧空位发生复合，会造成驰豫现象；接着继续采用相对较小的恒定电流施加于阻变器件上，从而在阻变器件的设置(Set)过程中，促进了导电细丝形成的稳定性，提高了器件在低阻态的保持能力，提高了阻变器件的均一性和数据保持特性，并且还提高了器件的耐久性。
(2)在写入操作中，基于第一预设时长或者预设电压值的限定，来控制施加恒定电流的时长或者程度，在保证阻变器件的导电细丝形成更加稳定的同时还可以有效避免阻变器件由于恒定电流施加过久或者程度过大导致的阻变器件往高的电阻值方向移动。
(3)在擦除操作中，基于第二电压对阻变器件进行擦除，使得阻变器件中氧离子和氧空位产生复合，导致导电细丝的断裂，在阻变器件的电阻值达到参考阻值的情况下，阻变器件被擦除成功(或者描述为复位成功)，但是可能存在导电细丝不完全断裂的现象，在断裂开的间隙区域中可能存在氧空位；接着继续采用相对较小的恒定电压施加于阻变器件上，从而在阻变器件的复位(reset)过程中，能够将阻变材料层的间隙中的氧空位清除，使得器件的高阻态保持特性提高，从而使得器件高阻态电阻值的分布更加集中，提高了阻变器件的均一性和数据保持特性，减少器件的软失效，并且还提高了器件的耐久性。
(4)在擦除操作中，基于第二预设时长或者预设电流值的限定，来控制施加恒定电压的时长或者程度，在保证阻变器件的导电细丝断裂程度较为完全的同时还可以有效避免阻变器件由于恒定电压施加过久或者程度过大导致的阻变器件往更高的电阻值方向移动，以免造成下一次写入操作的能耗更高。
附图说明
图1为根据本公开一实施例所示的存储单元的操作方法对应的脉冲时序图。
图2为根据本公开一实施例所示的存储单元的操作方法的(a)示例性路径，(b)写入和擦除对应的阻变器件的状态示意；(c)为现有的操作方法中的过编程对应的阻变器件的状态示意，(d)为现有的操作方法中的编程不足对应的阻变器件的状态示意。
图3为根据本公开一实施例所示的存储单元的写入操作方法的流程图。
图4为根据本公开一实施例所示的存储单元的擦除操作方法的流程图。
图5为根据本公开一实施例所示的存储单元的结构示意图。
图6为根据本公开一实施例所示的存储单元为1T1R结构对应的字线、位线、源线和等效在阻变器件上的脉冲时序图。
图7为对比现有方案和本公开实施例所示的阻变存储器的操作方法对阻变存储器进行编程操作之后高低阻态的分布图。
图8为对比现有方案和本公开实施例所示的阻变存储器的操作方法对 阻变存储器进行编程操作之后，将阻变存储器在150℃烘烤5小时后测试得到的数据保持特性图。
具体实施方式
阻变存储器(RRAM)通常为具有多个存储单元的阵列结构，每个存储单元可以是1T-1R结构，即，包括一个晶体管和一个阻变器件的结构。阻变器件包括：阻变材料层，位于阻变材料层上下两侧的电极层。在不同的脉冲电压激励下，阻变材料层呈现不同的电阻特性，具有不同的阻态。在写入(也称为编程)操作下，对阻变存储器施加设置/置位(set)操作电压，RRAM中的氧离子向上电极处的储氧层移动，在阻变材料层中形成氧空位导电细丝，对应RRAM处于低阻态。在擦除操作下，对阻变存储器施加复位(Reset)操作电压，氧离子与氧空位复合，导致导电细丝断裂，对应RRAM处于高阻态。
由于阻变器件的编程参数存在波动性，为了保证阻变器件的编程成功率，一般会选用较大的器件参数进行编程。因此，对于存储阵列中的器件往往会出现过编程现象，形成的导电细丝更加粗壮。在这种情况下，在后续的擦除过程中，细丝断裂需要更高的能量，而且容易出现细丝不完全断裂的情况，可能出现软失效的现象，导致器件耐久性降低。器件的不完全擦除现象还会导致：器件的高阻态波动比较大，以及器件均一性变差。
有的研究提出采用自适应编程方式来减小器件的过编程，当阻变器件的电阻值达到低阻态阈值时，立即撤掉施加的电压，防止器件过编程。
然而，发明人在实现本公开构思的过程中发现：当形成细丝不稳定，或者断裂细丝的间隙区域存在残余氧离子时，器件的保持特性和稳定性会变差。尽管自适应编程可以减缓器件的退化速度，增长器件的寿命，但是在该编程条件下，器件在Set操作结束后，器件内的导电细丝虽然形成了，导电细丝并不是很稳定，氧离子和氧空位发生复合，造成驰豫现象，导致器件阻态发生改变，常常表现为低阻态保持能力差、器件工作不稳定的现象。对于自适应编程，器件在reset过程中，器件达到参考电阻值即停止电压激励，器件中残余细丝与电极之间的间隙中有残余的氧空位，在后续保持过程中，残余的氧空位会与重新连接细丝，导致电阻值变小，器件的 保持能力下降。
有鉴于此，本公开提出了一种存储单元的操作方法、阻变存储器的操作方法，同时还提供了一种电子设备，能够改善阻变器件的均一性、数据保持特性以及器件的耐久性。
为使本公开的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本公开进一步详细说明。
本公开的第一个示例性实施例提供了一种存储单元的操作方法。存储单元包括：阻变器件。
图1为根据本公开一实施例所示的存储单元的操作方法对应的脉冲时序图。图2为根据本公开一实施例所示的存储单元的操作方法的(a)示例性路径，(b)写入和擦除对应的阻变器件的状态示意；(c)为现有的操作方法中的过编程对应的阻变器件的状态示意，(d)为现有的操作方法中的编程不足对应的阻变器件的状态示意。图3为根据本公开一实施例所示的存储单元的写入操作方法的流程图。图1和图2中示意的脉冲时序图中，左右方向为时间轴，上下方向为电压轴。图1中的横向虚线示意了处于同一水平线，纵向虚线示意不同的操作阶段，包括：写入、读取、擦除和读取四个阶段。
参照图1、图2中(a)和(b)、图3所示，本公开实施例的存储单元的操作方法包括：对阻变器件进行写入操作。该写入操作包括以下步骤：S31～S33。
在步骤S31，在阻变器件上施加用于写入的第一电压。
在步骤S32，在施加写入电压的期间，确定阻变器件的电阻值是否达到低阻态阈值。
根据一实施例，在施加写入电压的期间，上述确定阻变器件的电阻值是否达到低阻态阈值，包括：在施加写入电压的期间，根据阻变器件的通过电流I pass1是否大于第一参考值I ref1来确定所述阻变器件的电阻值是否达到低阻态阈值。第一参考值I ref1和低阻态阈值R ref1之间具有以下关系：I ref1×R ref1＝V 1，V 1表示第一电压的电压值。
上述低阻态阈值可以是一个范围，那么对应第一参考值也是一个范围。在判定时，如果低阻态阈值为一个范围，可以采用低阻态阈值范围内的任 意一个数值计算出来的第一参考值进行判断，以确定进入恒定电流施加的时机。例如图1中采用曲线箭头示意的在写入期间的路径③、②、①所对应的三个不同的恒定电流的加载时机，图2中(a)示意了路径③所对应的写入、读取、擦除和读取各个阶段对应的脉冲时序走向。
在步骤S33，在阻变器件的电阻值达到低阻态阈值的情况下，在阻变器件上施加恒定电流，该恒定电流在阻变器件上产生的电压值小于第一电压的电压值。
示例性的，上述恒定电流在阻变器件上产生的电压值为第一电压的电压值的1/10～1/2，包含端点值。例如，恒定电流在阻变器件上产生的电压值为第一电压的电压值的3/10、1/3、2/5或1/2。
参照图1所示，在阻变器件的电阻值达到低阻态阈值的情况下，在阻变器件上施加恒定电流，恒定电流的电流值示意为I 3，该恒定电流在阻变器件上产生的电压值小于第一电压的电压值。在施加恒定电流的期间，是使得形成的导电细丝稳定化的处理过程，阻变器件本身的阻值可能会发生波动或者变化，上述恒定电流的电流值I 3的选取要满足：上述恒定电流在阻变器件上产生的电压值始终小于第一电压的电压值V 1。
相关技术中，为了保证阻变器件的编程成功率，一般会选用较大的器件参数进行编程。因此，对于存储阵列中的器件往往会出现过编程现象，形成的导电细丝更加粗壮，参照图2中(c)的左图所示。在这种情况下，在后续的擦除过程中，细丝断裂需要更高的能量，而且容易出现细丝不完全断裂的情况，参照图2中(c)的右图所示，可能出现软失效的现象，导致器件耐久性降低。
相关技术中，采用自适应编程方式来减小器件的过编程，当阻变器件的电阻值达到低阻态阈值时，立即撤掉施加的电压，防止器件过编程。在该编程条件下，器件在Set操作结束后，器件内的导电细丝虽然形成了，导电细丝并不是很稳定，存在编程不足的现象，参照图2中(d)的左图所示，氧离子和氧空位发生复合，造成驰豫现象，导致器件阻态发生改变，常常表现为低阻态保持能力差、器件工作不稳定的现象。器件在reset过程中，器件达到参考电阻值即停止电压激励，器件中残余细丝与电极之间的间隙中有残余的氧空位，参照图2中(d)的右图所示，在后续保持过 程中，残余的氧空位会与重新连接细丝，导致电阻值变小，器件的保持能力下降。
对比图2中(b)、(c)和(d)所示的器件状态可知，根据本公开的实施例，在写入操作中，基于写入的第一电压对阻变器件进行编程，可以在阻变材料层中形成导电细丝，在阻变器件达到低阻态阈值之后，阻变器件被设置/置位成功，但是会存在形成的导电细丝的局部区域比较单薄，形成的导电细丝并不是很稳定，如果氧离子和氧空位发生复合，会造成驰豫现象；因此本公开通过继续采用相对较小的恒定电流施加于阻变器件上，从而在阻变器件的设置(Set)过程中，促进了导电细丝形成的稳定性，参照图2中(b)的左图所示，提高了器件在低阻态的保持能力，提高了阻变器件的均一性和数据保持特性，并且还提高了器件的耐久性。
根据本公开的实施例，上述写入操作还包括：确定恒定电流是否停止加载的步骤。
参照图3所示，上述确定恒定电流是否停止加载的步骤可以包括：步骤S34a和S35a，或者，包括步骤S34b和S35b。
在步骤S34a，在施加恒定电流的期间，确定阻变器件施加恒定电流的时长是否大于第一预设时长。
在步骤S35a，如果阻变器件施加恒定电流的时长大于第一预设时长，在阻变器件上施加的恒定电流停止加载。
在步骤S34b，在施加恒定电流的期间，确定阻变器件的电压值是否大于预设电压值。
在步骤S35b，在阻变器件的电压值大于预设电压值的情况下，在阻变器件上施加的恒定电流停止加载。
在写入操作中，基于第一预设时长或者预设电压值的限定，来控制施加恒定电流的时长或者程度，在保证阻变器件的导电细丝形成更加稳定的同时还可以有效避免阻变器件由于恒定电流施加过久或者程度过大导致的阻变器件往高的电阻值方向移动。
上述第一预设时长、预设电压值可以根据实际需要进行设置，上述条件是避免恒定电流加载时间/程度过大，导致阻变器件的低阻态稳定后又增大，因此需要在合适的时机停止加载恒定电流。
图4为根据本公开一实施例所示的存储单元的擦除操作方法的流程图。
根据本公开的实施例，上述操作方法还包括：对阻变器件进行擦除操作。该擦除操作包括以下步骤：S41～S43。
在步骤S41，在阻变器件上施加用于擦除的第二电压。
在步骤S42，在施加擦除电压的期间，确定阻变器件的电阻值是否达到参考阻值。
根据一实施例，在施加擦除电压的期间，上述确定阻变器件的电阻值是否达到参考阻值，包括：在施加擦除电压的期间，根据阻变器件的通过电流I pass2是否大于第二参考值I ref2来确定所述阻变器件的电阻值是否达到参考阻值。第二参考值I ref2和参考阻值R ref2之间具有以下关系：I ref2×R ref2＝V 2，V 2表示第二电压的电压值。
上述参考阻值可以是一个范围，那么对应第二参考值也是一个范围。在判定时，如果参考阻值为一个范围，可以采用参考阻值范围内的任意一个数值计算出来的第二参考值进行判断，以确定进入恒定电压施加的时机。例如图1中采用曲线箭头示意的在擦除期间的路径③、②、①所对应的三个不同的恒定电压的加载时机。
在步骤S43，在阻变器件的电阻值达到参考阻值的情况下，在阻变器件上施加恒定电压，恒定电压的电压值小于第二电压的电压值。
参照图1所示，在阻变器件的电阻值达到参考阻值的情况下，在阻变器件上施加恒定电压，恒定电压的电压值示意为V 4，该恒定电压的电压值V 4小于第二电压的电压值V 2。
示例性的，上述恒定电压的电压值为第二电压的电压值的1/10～1/2，包含端点值。例如，恒定电压的电压值为第二电压的电压值的1/5、3/10、1/3或2/5。
对比图2中(b)、(c)和(d)所示的器件状态可知，根据本公开的实施例，在擦除操作中，基于第二电压对阻变器件进行擦除，使得阻变器件中氧离子和氧空位产生复合，导致导电细丝的断裂，在阻变器件的电阻值达到参考阻值的情况下，阻变器件被复位成功，但是可能存在导电细丝不完全断裂的现象，在断裂开的间隙区域中可能存在氧空位；接着继续采用相对较小的恒定电压施加于阻变器件上，从而在阻变器件的复位(reset) 过程中，能够将阻变材料层的间隙中的氧空位清除，使得器件的高阻态保持特性提高，参照图2中(b)的右图所示，从而使得器件高阻态电阻值的分布更加集中，提高了阻变器件的均一性和数据保持特性，减少器件的软失效，并且还提高了器件的耐久性。
根据本公开的实施例，上述擦除操作还包括：确定恒定电压是否停止加载的步骤。
参照图4所示，上述确定恒定电压是否停止加载的步骤可以包括：步骤S44a和S45a，或者，包括步骤S44b和S45b。
在步骤S44a，在施加恒定电压的期间，确定阻变器件施加恒定电压的时长是否大于第二预设时长。
在步骤S45a，如果阻变器件施加恒定电压的时长大于第二预设时长，在阻变器件上施加的恒定电压停止加载。
在步骤S44b，在施加恒定电压的期间，确定阻变器件的通过电流是否小于预设电流值。
在步骤S45b，在阻变器件的通过电流小于预设电流值的情况下，在阻变器件上施加的恒定电压停止加载。
在擦除操作中，基于第二预设时长或者预设电流值的限定，来控制施加恒定电压的时长或者程度，在保证阻变器件的导电细丝断裂程度较为完全的同时还可以有效避免阻变器件由于恒定电压施加过久或者程度过大导致的阻变器件往更高的电阻值方向移动，以免造成下一次写入操作的能耗更高。
上述第二预设时长、预设电流值可以根据实际需要进行设置，上述条件是避免恒定电压加载时间/程度过大，导致阻变器件的高阻态实现后又进一步增大，因此需要在合适的时机停止加载恒定电压。
图5为根据本公开一实施例所示的存储单元的结构示意图。
根据本公开的实施例，参照图5所示，上述存储单元包括：阻变器件，与阻变器件串联连接的晶体管。其中，晶体管的栅极用于与字线WL连接，晶体管的源极用于与源极线SL连接，晶体管的漏极与阻变器件的一个电极端连接，阻变器件的另一个电极端用于与位线BL连接。从阻变器件的一个电极端引出的等效电压为V O。
图6为根据本公开一实施例所示的存储单元为1T1R结构对应的字线、位线、源线和等效在阻变器件上的脉冲时序图。
参照图6所示，分别示意了字线WL、位线BL、源线SL和等效电压V O的时序图。在阻变器件连接的晶体管对应的字线WL上施加特定脉冲，在阻变器件连接的晶体管对应的源线SL上保持低电平，在阻变器件连接的位线BL上保持高电平，以实现对阻变器件的写入操作。上述特定脉冲为第一电压和第三电流先后连续加载的序列，所述第三电流的电流值等于所述恒定电流的电流值。
参照图6所示，在阻变器件连接的晶体管对应的源线SL上施加另一特定脉冲，在阻变器件连接的晶体管对应的字线WL上保持高电平，在阻变器件连接的位线BL上保持低电平，以实现对阻变器件的擦除操作。另一特定脉冲为第二电压和第四电压先后连续加载的序列，第四电压的电压值等于恒定电压的电压值。
在本公开的实施例中，上述操作方法也包括：在写入操作之后实施的读取操作以及在擦除操作之后实施的读取操作。上述读取操作与现有技术相同，这里不作详述。
基于相同的技术构思，本公开的第二个示例性实施例提供了一种阻变存储器的操作方法。阻变存储器包括存储阵列，存储阵列包括至少两个存储单元。
本实施例的阻变存储器的操作方法包括：基于字线和位线选定目标存储单元；针对目标存储单元，执行如上所述的任一种存储单元的操作方法。
在阻变存储器中，存储阵列为阵列化结构，可以基于译码器选中特定的行和列所对应的存储单元，该选中的存储单元为目标存储单元。针对目标存储单元执行第一个实施例所述的操作方法，基于上述操作方法进行写入、读取、擦除和读取之后的阻变存储器具有很好的阻态均一性和数据保持特性，并且具有很好的耐久性。
图7为对比现有方案和本公开实施例所示的阻变存储器的操作方法对阻变存储器进行编程操作之后高低阻态的分布图。图8为对比现有方案和本公开实施例所示的阻变存储器的操作方法对阻变存储器进行编程操作之后，将阻变存储器在150℃烘烤5小时后测试得到的数据保持特性图。
在一实例中，分别采用现有的自适应编程的方法和本公开实施例的操作方法对阻变存储器进行编程(写入)操作，测试得到的阻变存储器的高低阻态的分布对比图可以参照图7所示。由图7可知，采用本公开实施例的方案可以使得器件的高阻态和低阻态分布集中，降低波动性，明显提高器件的均一性。
在另一实例中，分别采用现有的自适应编程的方法和本公开实施例的操作方法对阻变存储器进行编程(写入)操作之后，将阻变存储器在150℃烘烤5小时后测试数据保持性能，测试得到的数据保持特性的对比图参照图8所示。由图8可知，采用本公开实施例的方案对器件进行编程操作后，对器件保持能力具有明显的改善作用。
本公开的第三个示例性实施例提供了一种电子设备。
上述电子设备包括：一个或多个处理器；以及用于存储一个或多个程序的存储介质。其中，当一个或多个程序被一个或多个处理器执行时，使得一个或多个处理器如上所述的任一种存储单元的操作方法，该电子设备独立于存储单元，或者，该电子设备包括存储单元。或者，当一个或多个程序被一个或多个处理器执行时，使得一个或多个处理器执行如上所述的阻变存储器的操作方法，该电子设备独立于阻变存储器，或者，该电子设备包括阻变存储器。
综上所述，本公开提供了一种存储单元和阻变存储器的操作方法、电子设备，对于Set过程，在自适应编程的基础上继续施加恒定电流，使得在Set过程中，导电细丝形成之后继续施加恒定的小电流流过器件，这样使得器件在编程成功的基础上，细丝形成得更加稳定，从而提高了器件在低阻态的保持能力。同理，对于Reset过程，导电细丝断裂之后，继续施加小恒压，可以将间隙中的氧空位清除，使得器件的高阻态保持特性提高。同时，采用本公开的方案，器件高阻态电阻值的分布更加集中，器件均一性提高，减少器件的软失效，提高器件的耐久性。
说明书与权利要求中所使用的序数例如“第一”、“第二”、“第三”等的用词，以修饰相应的元件，其本身并不意味着该元件有任何的序数，也不代表某一元件与另一元件的顺序、或是制造方法上的顺序，该些序数的使用仅用来使具有某命名的一元件得以和另一具有相同命名的元件能做 出清楚区分。
再者，单词“包含”或“包括”不排除存在未列在权利要求中的元件或步骤。位于元件之前的单词“一”或“一个”不排除存在多个这样的元件。
以上所述的具体实施例，对本公开的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本公开的具体实施例而已，并不用于限制本公开，凡在本公开的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (10)

  1. 一种存储单元的操作方法，其特征在于，所述存储单元包括：阻变器件；所述操作方法包括：对所述阻变器件进行写入操作，所述写入操作包括：
    在所述阻变器件上施加用于写入的第一电压；
    在施加写入电压的期间，确定所述阻变器件的电阻值是否达到低阻态阈值；以及
    在所述阻变器件的电阻值达到低阻态阈值的情况下，在所述阻变器件上施加恒定电流，所述恒定电流在所述阻变器件上产生的电压值小于所述第一电压的电压值。
  2. 根据权利要求1所述的操作方法，其特征在于，所述写入操作还包括：
    在施加恒定电流的期间，确定所述阻变器件施加恒定电流的时长是否大于第一预设时长；
    如果所述阻变器件施加恒定电流的时长大于第一预设时长，在所述阻变器件上施加的恒定电流停止加载。
  3. 根据权利要求1所述的操作方法，其特征在于，所述写入操作还包括：
    在施加恒定电流的期间，确定所述阻变器件的电压值是否大于预设电压值；
    在所述阻变器件的电压值大于预设电压值的情况下，在所述阻变器件上施加的恒定电流停止加载。
  4. 根据权利要求1所述的操作方法，其特征在于，还包括：对所述阻变器件进行擦除操作，所述擦除操作包括：
    在阻变器件上施加用于擦除的第二电压；
    在施加擦除电压的期间，确定所述阻变器件的电阻值是否达到参考阻值；
    在所述阻变器件的电阻值达到参考阻值的情况下，在所述阻变器件上施加恒定电压，所述恒定电压的电压值小于所述第二电压的电压值。
  5. 根据权利要求4所述的操作方法，其特征在于，所述擦除操作还包括：
    在施加恒定电压的期间，确定所述阻变器件施加恒定电压的时长是否大于第二预设时长；
    如果所述阻变器件施加恒定电压的时长大于第二预设时长，在所述阻变器件上施加的恒定电压停止加载。
  6. 根据权利要求4所述的操作方法，其特征在于，所述擦除操作还包括：
    在施加恒定电压的期间，确定所述阻变器件的通过电流是否小于预设电流值；
    在所述阻变器件的通过电流小于预设电流值的情况下，在所述阻变器件上施加的恒定电压停止加载。
  7. 根据权利要求1-3中任一项所述的操作方法，其特征在于，所述存储单元还包括：与所述阻变器件串联连接的晶体管，所述晶体管的栅极用于与字线连接，所述晶体管的源极用于与源极线连接，所述晶体管的漏极与所述阻变器件的一个电极端连接，所述阻变器件的另一个电极端用于与位线连接；
    其中，在所述阻变器件连接的晶体管对应的字线上施加特定脉冲，所述特定脉冲为第一电压和第三电流先后连续加载的序列，所述第三电流的电流值等于所述恒定电流的电流值；在所述阻变器件连接的晶体管对应的源线上保持低电平，在所述阻变器件连接的位线上保持高电平，以实现对所述阻变器件的写入操作。
  8. 根据权利要求4-6中任一项所述的操作方法，其特征在于，所述存储单元还包括：与所述阻变器件串联连接的晶体管，所述晶体管的栅极用于与字线连接，所述晶体管的源极用于与源极线连接，所述晶体管的漏极与所述阻变器件的一个电极端连接，所述阻变器件的另一个电极端用于与位线连接；
    其中，在所述阻变器件连接的晶体管对应的源线上施加另一特定脉冲，所述另一特定脉冲为第二电压和第四电压先后连续加载的序列，所述第四电压的电压值等于所述恒定电压的电压值；在所述阻变器件连接的晶体管 对应的字线上保持高电平，在所述阻变器件连接的位线上保持低电平，以实现对所述阻变器件的擦除操作。
  9. 一种阻变存储器的操作方法，其特征在于，所述阻变存储器包括存储阵列，所述存储阵列包括至少两个存储单元，所述操作方法包括：
    基于字线和位线选定目标存储单元；
    针对目标存储单元，执行如权利要求1-8中任一项所述的存储单元的操作方法。
  10. 一种电子设备，其特征在于，包括：
    一个或多个处理器；
    存储介质，用于存储一个或多个程序；
    其中，当所述一个或多个程序被所述一个或多个处理器执行时，使得所述一个或多个处理器执行权利要求1-8中任一项所述的存储单元的操作方法，所述电子设备独立于所述存储单元，或者，所述电子设备包括所述存储单元；或者，
    当所述一个或多个程序被所述一个或多个处理器执行时，使得所述一个或多个处理器执行权利要求9所述的阻变存储器的操作方法，所述电子设备独立于所述阻变存储器，或者，所述电子设备包括所述阻变存储器。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101882462A (zh) * 2009-05-08 2010-11-10 复旦大学 一种电阻随机存储器的置位操作方法
CN104240757A (zh) * 2014-09-01 2014-12-24 清华大学 一种阻变存储器存储单元的多值操作方法
CN105719691A (zh) * 2016-01-22 2016-06-29 清华大学 阻变存储器的操作方法及阻变存储器装置
US20190279714A1 (en) * 2013-12-16 2019-09-12 Micron Technology, Inc. Memory Systems and Memory Programming Methods

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101882462A (zh) * 2009-05-08 2010-11-10 复旦大学 一种电阻随机存储器的置位操作方法
US20190279714A1 (en) * 2013-12-16 2019-09-12 Micron Technology, Inc. Memory Systems and Memory Programming Methods
CN104240757A (zh) * 2014-09-01 2014-12-24 清华大学 一种阻变存储器存储单元的多值操作方法
CN105719691A (zh) * 2016-01-22 2016-06-29 清华大学 阻变存储器的操作方法及阻变存储器装置

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