WO2022062276A1 - 接口电路及电子装置 - Google Patents

接口电路及电子装置 Download PDF

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Publication number
WO2022062276A1
WO2022062276A1 PCT/CN2021/070501 CN2021070501W WO2022062276A1 WO 2022062276 A1 WO2022062276 A1 WO 2022062276A1 CN 2021070501 W CN2021070501 W CN 2021070501W WO 2022062276 A1 WO2022062276 A1 WO 2022062276A1
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WIPO (PCT)
Prior art keywords
current
voltage
transistor
output
mode
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PCT/CN2021/070501
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English (en)
French (fr)
Inventor
李婷
胡刚毅
李儒章
张勇
倪亚波
付东兵
王健安
陈光炳
Original Assignee
中国电子科技集团公司第二十四研究所
重庆吉芯科技有限公司
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Application filed by 中国电子科技集团公司第二十四研究所, 重庆吉芯科技有限公司 filed Critical 中国电子科技集团公司第二十四研究所
Priority to US17/925,323 priority Critical patent/US11936378B2/en
Publication of WO2022062276A1 publication Critical patent/WO2022062276A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017509—Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
    • H03K19/018528—Interface arrangements of complementary type, e.g. CMOS with at least one differential stage

Definitions

  • the present invention relates to the field of integrated circuits, and in particular to an interface circuit and an electronic device, which are used for signal transmission, and are especially suitable for circuits for high-speed data transmission.
  • the output common-mode feedback circuit is connected to the output driver, which increases the load of the output driver circuit, resulting in a low transmission rate;
  • Each output drive circuit is equipped with a common mode feedback loop, and the operational amplifier in each feedback loop will consume power, resulting in relatively large power consumption;
  • the present invention aims to provide an interface circuit and an electronic device for solving any of the above-mentioned defects of the existing interface circuit.
  • a first aspect of the present invention provides an interface circuit, comprising:
  • a programmable current array for generating a first current and a second current sent to the common mode differential mode generating circuit according to the input code, and generating a third current and a fourth current sent to the driving bias generating circuit according to the input code ;
  • the common-mode differential-mode generating circuit is connected to the output end of the programmable current array, and is used for generating a common-mode voltage according to the first current, and generating a high-level voltage and a low-level voltage according to the second current and the common-mode voltage.
  • level voltage wherein the difference between the high-level voltage and the low-level voltage is a differential mode voltage
  • the drive bias generating circuit is connected to the output end of the programmable current array and the common mode differential mode generating circuit respectively, and is used for simulating the load according to the third current and the fourth current, combining the load and the high-level voltage Generate bias voltage with low level voltage;
  • the output driving circuit is connected to the bias voltage of the driving bias generating circuit, and converts the input signal into a differential signal with configurable common mode voltage and differential mode amplitude.
  • a second aspect of the present invention provides an output circuit for use in an analog-to-digital converter circuit, the output circuit comprising the interface circuit of the above-mentioned first aspect of the present invention.
  • a third aspect of the present invention provides an analog-to-digital converter circuit comprising the output circuit of the above-mentioned third aspect of the present invention.
  • a fourth aspect of the present invention provides an integrated circuit, comprising: the interface circuit of the first aspect of the present invention; or the output circuit of the second aspect of the present invention; or the analog-to-digital converter circuit of the third aspect of the present invention.
  • the interface circuit and electronic device of the present invention have the following beneficial effects:
  • the common mode voltage, the high level voltage and the low level voltage are generated, wherein the gate is gated by adjusting the current control signal of the programmable current array
  • the common mode and differential mode generating circuit and the differential mode generating circuit make the magnitude of the output common mode voltage and the amplitude of the differential mode voltage configurable, and meet the design requirements of high-performance integrated circuits.
  • FIG. 1 is a schematic structural diagram of an interface circuit according to an embodiment of the present invention.
  • FIG. 2 shows a complete structural diagram of an interface circuit according to an embodiment of the present invention
  • FIG. 3 shows a circuit diagram of a programmable current array according to an embodiment of the present invention
  • FIG. 4 shows a circuit diagram of a programmable current array according to another embodiment of the present invention.
  • FIG. 5 shows a circuit diagram of a common mode differential mode generating circuit according to an embodiment of the present invention
  • FIG. 6 shows a circuit diagram of a high-low level generating circuit provided for another embodiment of the present invention.
  • FIG. 7 shows a circuit diagram of a programmable resistor string according to an embodiment of the present invention.
  • FIG. 8 shows a circuit diagram of a driving bias generating circuit according to an embodiment of the present invention.
  • FIG. 9 shows a circuit diagram of an output driving circuit according to an embodiment of the present invention.
  • FIG. 10 shows a circuit diagram of an electronic device according to an embodiment of the present invention.
  • FIG. 1 is a schematic structural diagram of an interface circuit according to an embodiment of the present invention, including:
  • the programmable current array 1 is used for generating a first current and a second current sent to a common mode differential mode generating circuit according to an input code, and generating a third current and a fourth current sent to the driving bias generating circuit according to the input code current;
  • the common-mode differential-mode generating circuit 2 is connected to the output end of the programmable current array, and is used for generating a common-mode voltage according to the first current, and generating a high-level voltage and a high-level voltage according to the second current and the common-mode voltage. a low-level voltage, wherein the difference between the high-level voltage and the low-level voltage is a differential mode voltage;
  • the drive bias generating circuit 3 is respectively connected to the output end of the programmable current array and the common mode differential mode generating circuit, and is used to simulate the load according to the third current and the fourth current, and combine the load, high level The voltage and the low-level voltage generate a bias voltage;
  • the output driving circuit 4 is connected to the bias voltage of the driving bias generating circuit, and converts the input signal into a differential signal with configurable common mode voltage and differential mode amplitude.
  • the common-mode voltage, the high-level voltage and the low-level voltage are generated through the cooperation between the programmable current array and the common-mode differential-mode generating circuit.
  • the current control signal is used to configure the current flowing into the common mode and differential mode generating circuit and the resistance for generating the voltage, so that the magnitude of the output common mode voltage and the amplitude of the differential mode voltage can be configured, which meets the design requirements of high performance integrated circuits.
  • the drive bias generation circuit 3 has a built-in analog load function and can generate bias voltage.
  • the output drive circuit can convert the input signal into common mode voltage and differential mode amplitude. Configured differential signaling.
  • the output driving circuit includes a plurality of output driving modules, and a mirror structure is adopted between the driving bias generating circuit and the output driving circuit, and the driving bias generating circuit and the output driving circuit are combined with the bias voltage to make the driving bias generating circuit and the output driving circuit
  • the working state is the same, and a differential signal with configurable common-mode voltage and differential-mode voltage amplitudes is generated, wherein the feedback loop and mirror structure of the operational amplifier in the driving bias generating circuit are used to determine the common mode of all the output driving modules. mode voltage.
  • the direct connection between the output common-mode feedback circuit and the output driving circuit is eliminated through the mirror structure, thereby reducing the parasitic capacitance and improving the interface speed; it is not necessary to match each output driving circuit with a common-mode feedback loop, and it is only necessary to design a common mode feedback loop.
  • the output common-mode voltage of each output driver circuit can be determined by mirroring, which greatly reduces the number of operational amplifiers and saves area and power consumption.
  • the programmable current array is composed of a current source array, and outputs a first current I c , a second current I d , a third current I p and a fourth current I n whose magnitudes of currents are controlled by switches.
  • the first current I c , the second current I d , the third current I p and the fourth current I n are generated in the same way, please refer to FIG. 3 , the specific connection relationship is: In parallel, and the positive terminals (positive poles) of the N current sources are connected to the power supply in parallel, and the negative terminal of each current source is connected to a switch correspondingly, and the switch is turned on or off by the control signal, wherein the control signal is determined by the input code, according to The control signal controls the magnitude of the current output by the current source array.
  • the signal k c1 [1] controls the switch corresponding to the current source I c [1], when k c1 [1] is a logic high level 1, the switch is turned on, and the current I c [1] flows out as the first current I Part of c , when k c1 [1] is logic low 0, the switch is off.
  • the first current I c is controlled by the signal k c1 [1] to control the switch corresponding to the current source I c [1], when k c1 [1] is a logic high level of 1
  • the switch is turned on, the current I c [1] flows out as a part of the first current I c , and when k c1 [1] is a logic low level of 0, the switch is turned off.
  • the current source array switches are controlled by input codes, that is, the current sources generate currents with controllable magnitudes according to different switch control signals, such as the first current I c , the second current I d , and the third current I . p and the fourth current I n meet various application requirements of users, improve the control accuracy of the output current, and expand the range of the output current.
  • FIG. 5 is a circuit diagram of a common-mode differential-mode generating circuit according to an embodiment of the present invention, which is described in detail as follows:
  • the common-mode level generating circuit includes a current source I c (ie, a first current I c ) and a first programmable resistor string, wherein the positive terminal of the current source I c is connected to the power supply, and the negative terminal of the current source I c is connected to the power supply
  • the first input terminal Vin1 of the first programmable resistor string, the control terminal of the first programmable resistor string is controlled by the control signal k c2 [1:j], and the second input terminal Vin2 of the first programmable resistor string is grounded, so
  • the first programmable resistor string output terminal outputs the common mode voltage V cm .
  • the first current I c flows through the first programmable resistor string to generate the common mode voltage V cm and send it to the high and low level generating module.
  • the common mode voltage V cm can be achieved by adjusting the control signal k c1 [1:n] of the first current I c and the level gating control signal k c2 [1:j], therefore, through the programmable current source array and The cooperation of the programmable resistor string realizes the flexible configuration of the "common mode voltage" of the output signal.
  • the number of configurable steps is n*j, which realizes the fine adjustment of the output common mode voltage V cm .
  • the high-low level generating circuit includes a current source I d (ie a second current I d ), a second programmable resistor string, a third programmable resistor string, a first operational amplifier AMP1 and a MOS transistor M 0 .
  • the current The positive terminal of the source I d is connected to the power supply, and the negative terminal of the current source I d is connected to the first input terminal Vin1 of the second programmable resistor string, the second input terminal Vin2 of the second programmable resistor string and the first input terminal of the third programmable resistor string.
  • the two input terminals Vin2 are connected in series, the control terminal of the second programmable resistor string is controlled by the control signal k d2 [1:j], and the control terminal of the third programmable resistor string is controlled by the control signal k d2 [1:j] , the negative terminal of the first operational amplifier AMP1 is connected between the second programmable resistor string and the third programmable resistor string, the output terminal of the first operational amplifier AMP1 is connected to the gate of the MOS transistor M0, and the MOS transistor M The source of 0 is grounded, the drain of the MOS transistor M 0 is connected to the first input terminal Vin1 of the third programmable resistor string, the output terminal of the second programmable resistor string outputs a high-level voltage V H , and the output terminal of the third programmable resistor string The output terminal outputs a high-level voltage VL .
  • the second current I d flows through the programmable resistor string 2 , the programmable capacitor array 3 and the transistor M 0 .
  • the operational amplifier AMP1 and its feedback loop the high-level voltage V H and the low-level voltage V H are obtained. level voltage VL .
  • the common mode voltage of the high-level voltage V H and the low-level voltage VL is determined by the feedback of the operational amplifier loop, that is, V cm .
  • the differential mode voltage amplitude (V H - V L ) can be achieved by adjusting the I d control signal k d1 [1:n] and the level gating control signal k d2 [1:j], thus, the adjustable number of steps For n*j, fine adjustment of the output common-mode voltage (V H -V L ) can be achieved.
  • FIG. 6 is a circuit diagram of a high-low level generating circuit provided by another embodiment of the present invention.
  • the high-low level generating circuit implemented by other means is described in detail as follows:
  • the difference between the first implementation and the above implementation is that the MOS transistor M 0 is changed from an NMOS transistor to a PMOS transistor, wherein the source of the PMOS transistor is connected to the first input terminal Vin1 of the third programmable resistor string, The drain of the PMOS transistor is grounded.
  • connection positions of the current source I d and the MOS transistor M 0 are replaced with each other.
  • the drain of the MOS transistor M 0 is connected to the power supply, and the source of the MOS transistor M 0
  • the first input terminal Vin1 of the second programmable resistor string is connected, the first input terminal Vin1 of the third programmable resistor string is connected to the positive terminal of the current source Id , and the negative terminal of the current source Id is grounded.
  • the MOS transistor M 0 is changed from an NMOS transistor to a PMOS transistor, wherein the drain of the PMOS transistor is connected to the first input terminal Vin1 of the second programmable resistor string, and the PMOS transistor The source of the tube is connected to the power supply.
  • the high-level voltage V H and the low-level voltage VL are generated by various implementations of the programmable current source array and the programmable resistor string, wherein the high-level voltage V H and the low-level voltage V are L , the common mode voltage is determined by the op amp loop feedback as V CM , and the differential mode voltage amplitude (V H - V L ) can be adjusted by adjusting the I d control signal k d1 [1:n] and the level gating control signal k d2 [1:j], therefore, the flexible configuration of the output signal "differential mode voltage" is realized by using the combination of the programmable current source array and the programmable resistor string.
  • the number of configurable steps is n*j. Fine adjustment of output common mode voltage (V H - V L ).
  • FIG. 7 is a circuit diagram of a programmable resistor string according to an embodiment of the present invention, wherein the structures of the first programmable resistor string, the second programmable resistor string and the third programmable resistor string are the same.
  • Any programmable resistor string includes a first resistor R 1 , a second resistor R 2 , ..., a jth resistor R j , a control switch k[1:j], a first input port Vin1, a second input terminal Vin2 and an output terminal Vout, where j is greater than or equal to 1.
  • the first input port Vin1 is respectively connected to one end of the jth resistor Rj and one end of the jth control switch k[j], in series from the jth resistor Rj to the first resistor R1, the first The other end of the resistor R1 is connected to the second input terminal Vin2; the j- 1th control switch k[j-1] is connected between the jth resistor Rj and the j-1th resistor Rj-1 until the first control switch k [1] is connected between the second resistor R 2 and the first resistor R 1 , and the other ends of the first control switch k[1] to the jth control switch k[j] are connected to the output terminal Vout.
  • FIG. 8 is a circuit diagram of a driving bias generating circuit according to an embodiment of the present invention, including:
  • the bias generating circuit 3 use the third current I p and the fourth current I n sent by the programmable capacitor array to simulate the load, and combine the high-level voltage V H and low-level voltage generated by the common mode differential mode generating circuit according to the load
  • the voltage VL generates the first bias voltage V b1 and the second bias voltage V b2 and sends them to the output driving circuit.
  • the drive bias generating circuit 3 includes a second operational amplifier AMP2, a third operational amplifier AMP3, and transistors M 1 to M 6 (wherein the first transistor M 1 , the third transistor M 3 and the fifth transistor M 5 is a PMOS transistor, the second transistor M 2 , the fourth transistor M 4 and the sixth transistor M 6 are NMOS transistors), the current source I p (ie, the third current I p ) and the current source In (ie, the third current I p ) Four currents In).
  • the positive terminal of the second operational amplifier AMP2 is connected to the high-level voltage V H of the output of the common mode differential mode generating circuit 2 , and the negative terminal of the second operational amplifier AMP2 is connected to the drains of the fifth transistor M 5 and the sixth transistor M 6 As well as the current source In (fourth current), the negative phase output terminal of the second operational amplifier AMP2 is connected to the gate of the first transistor M1 (the first bias voltage Vb1 ).
  • the positive terminal of the third operational amplifier AMP3 is connected to the low-level voltage VL of the output of the common mode differential mode generating circuit 2, and the negative terminal of the third operational amplifier AMP3 is connected to the drains of the third transistor M3 and the fourth transistor M4 and
  • the current source I p (third current) the non-inverting output terminal of the third operational amplifier AMP3 is connected to the gate of the second transistor M 2 (the second bias voltage V b2 ).
  • the gates of the third transistor M3 and the fourth transistor M4 are connected to a logic high level 1, and the gates of the fourth transistor M4 and the sixth transistor M6 are connected to a logic low level 0.
  • the outputted first bias voltage V b1 is determined by the feedback loop of the second operational amplifier AMP2
  • the outputted second bias voltage V b2 is determined by the feedback loop of the third operational amplifier AMP3 .
  • the current source I p and the current source In are used to simulate the current situation when the output has an actual load.
  • the actual load resistance since the gates of the third transistor M3 and the fourth transistor M4 are connected to The logic high level is 1, therefore, the third transistor M3 is turned off, the fourth transistor M4 is turned on, the current flows from the load to the ground through the fourth transistor M4 and the second transistor M2 , and the third current Ip is used for Simulate the current flowing into the fourth transistor M4 from the load; since the gates of the fifth transistor M5 and the sixth transistor M6 are connected to the logic high level 0, therefore, the fifth transistor M5 is turned on, and the sixth transistor M6 is turned off On, the current flows from the first transistor M1 and the fifth transistor M5 to the ground through the load, and the fourth current In is used to simulate the current flowing into the load from the fifth transistor M5.
  • transistors in the present application are preferably field effect transistors, and can also be replaced by bipolar transistors, which will not be repeated here.
  • V H V dH
  • the current source I p is equal to the current source I n , and since the signal amplitude (V H -V L ) is adjusted, the current source is unchanged due to the constant load impedance.
  • the overload current changes proportionally with the change of the output signal amplitude. Therefore, when adjusting the output signal amplitude (V H - VL ), I p and I n should be adjusted in equal proportions, so as to achieve accurate simulation of the load current.
  • FIG. 9 is a circuit diagram of an output driving circuit according to an embodiment of the present invention, including:
  • the output drive circuit includes an output drive circuit (output drive module) 41, an output drive circuit 42, . . . , and an output drive circuit 4m.
  • the output driver circuit 41 converts the CMOS input signals D1+ and D1- into differential pair signals D out1 + and D out1 - with configurable common mode voltage and differential mode amplitude;
  • the output driver circuit 42 converts the CMOS input signals D2+ and D2 -, converts into differential pair signals D out2 + and D out2 - with configurable common-mode voltage and differential-mode amplitude; ...; output driver circuit 4m, converts CMOS input signals Dm+ and Dm- into configurable common-mode voltage and The differential pair signals D outm + and D outm ⁇ of the differential mode amplitude are output.
  • the output driving module 41, the output driving module 42, . . . , and the output driving module 4m have the same structure, as shown in FIG. 9 , including transistors M7-M12, wherein the seventh transistor M7 , the ninth transistor M9 and the The eleventh transistor M 11 is a PMOS transistor, and the eighth transistor M 8 , the tenth transistor M 10 and the twelfth transistor M 12 are NMOS transistors.
  • the gate of the seventh transistor M7 is connected to the first bias voltage Vb1
  • the gate of the eighth transistor M8 is connected to the second bias voltage Vb2
  • the source of the seventh transistor M7 is connected to the power supply
  • the eighth transistor M8 The source is grounded;
  • the gates of the ninth transistor M9 and the tenth transistor M10 are connected to the digital input logic level D+, and the gates of the eleventh transistor M11 and the twelfth transistor M12 are connected to the digital input logic level D -, wherein the drain of the seventh transistor M7 is connected to the source of the ninth transistor M9 and the eleventh transistor M11, respectively, and the drain of the eighth transistor M8 is connected to the tenth transistor M10 and the twelfth transistor, respectively
  • the source of M12, the first output terminal Dout+ is connected to the drains of the eleventh transistor M11 and the twelfth transistor M12
  • the second output terminal Dout- is connected to the drains of the ninth transistor M9 and the tenth transistor M10
  • the device dimensions of the transistors M7-M12 are proportional to the dimensions and current density of the transistors M1 - M6 in the drive bias generation circuit 3, and the first bias voltage Vb1 and the second bias voltage Vb2 are also determined by
  • the drive bias generation circuit 3 is generated under the premise of configuring an analog load, so the working state of the output drive circuit is exactly the same as that of the drive bias generation circuit 3. Therefore, the output signal amplitude is:
  • V H is the high-level voltage
  • VL is the low-level voltage
  • (V dH -V dL ) is the output signal amplitude of the drive bias generating circuit.
  • the mirror structure is used between the drive bias generating circuit 3 and the output drive circuit 4 to achieve the exact same working state by combining the bias voltages V b1 and V b2 , so as to determine the output common mode of the output drive circuit 4 voltage and differential mode amplitude. Therefore, in the output driving circuit 4, it is no longer necessary to use an operational amplifier to determine its output common-mode voltage. For m output driving modules, it is only necessary to use an operational amplifier in the driving bias generating circuit 3 with an analog load to achieve The output common mode level and differential mode voltage of all output driver modules are determined by feedback and mirroring; while in the traditional structure, each output driver module needs to be equipped with an operational amplifier, that is, m operational amplifiers are required.
  • the present invention greatly reduces the number of operational amplifiers used, and saves area and power consumption.
  • the output driving circuit is not directly connected with the common mode feedback loop, which reduces the parasitic capacitance of the output node and improves the speed of the output driving circuit.
  • FIG. 10 it is an example of the structure of an electronic device using an interface circuit provided by an embodiment of the present invention, such as an electronic device such as a TV, a mobile phone, a tablet, or a computer with a display panel 580 such as LCD, LED, and OLED.
  • an electronic device such as a TV, a mobile phone, a tablet, or a computer with a display panel 580 such as LCD, LED, and OLED.
  • the serial data or clock signal from the host 550 is transmitted to the integrated circuit device 500 through a differential signal line (serial bus) of LVDS, and received by the interface circuit 510 (LVDS receiving circuit). Then, the interface circuit 510 supplies the memory controller 520 with a clock signal (or a clock signal in which the clock signal is sequentially doubled) sent from the host 550 . Then, the received serial data sent from the host computer 550 , that is, the image data, is supplied to the image processing unit 530 .
  • the image processing unit 530 performs various image processing, such as gamma correction, on the image data received from the host computer 550 .
  • the memory 560 (in a broad sense, a device that operates based on data received through an interface circuit or a clock signal) is used, and the image data before or after image processing is written into the memory 560 , or the image data is read from the memory 560 . read out.
  • a high-speed memory such as SDRAM or DDR SDRAM can be used, for example.
  • Writing data to or reading data from the memory 560 is realized by the control of the memory controller 520 (SDRAM).
  • the clock signal generation circuit 521 of the memory controller 520 generates a clock signal for sampling the read data from the memory 560 based on, for example, a clock signal from the interface circuit 510 . Alternatively, a clock signal required for writing data to the memory 560 may be generated.
  • the image data subjected to the image processing by the image processing unit 530 is transmitted to the display driver 570 through the transmission circuit 540 (a device that operates based on data or a clock signal received by the interface circuit). Then, the display driver 570 drives the display panel 580 according to the received image data, and performs control for displaying an image corresponding to the image data.
  • the transmission circuit 540 a device that operates based on data or a clock signal received by the interface circuit.
  • the configuration of the electronic equipment to which the interface circuit of the present embodiment is applied is not limited to the configuration shown in FIG. 10 , as long as it includes at least devices that operate according to data or clock signals received through the interface circuit (for example, a memory, a display driver, a display panel, etc.)
  • various equipment such as an information processing device, a portable information terminal, an AV device, a portable AV device, a game device, or a portable game device can be considered.
  • an interface circuit or differential interface circuit embodying the present invention may also be used in an analog-to-digital conversion circuit.
  • the circuits of the present invention may be implemented as integrated circuits, eg, integrated circuits on IC chips such as flip chips.
  • the present invention extends to integrated circuits and IC chips as described above, circuit boards including such IC chips, and communication networks (eg, Internet fiber optic networks and wireless networks) including such circuit boards and network equipment of such networks.
  • the present invention generates a common mode voltage, a high-level voltage and a low-level voltage through the cooperation between the programmable current array and the common mode differential mode generating circuit, wherein the programmable current array is adjusted by adjusting the programmable current array.
  • the common mode and differential mode generating circuit and the differential mode generating circuit are gated by the current control signal, so that the magnitude of the output common mode voltage and the amplitude of the differential mode voltage can be configured, which meets the design requirements of high-performance integrated circuits. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

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Abstract

一种接口电路及电子装置，包括：可编程电流阵列（1），用于根据输入编码产生送往共模差模产生电路（2）的第一电流、第二电流，及根据输入编码产生送往驱动偏置产生电路（3）的第三电流、第四电流；共模差模产生电路（2），用于根据第一电流产生共模电压，及根据第二电流与共模电压产生高电平电压与低电平电压；驱动偏置产生电路（3），用于根据第三电流与第四电流模拟负载，结合所述负载、高电平电压与低电平电压产生偏置电压；输出驱动电路（4），用于将输入信号转换成共模电压和差模幅度都可配置的差分信号并输出。通过可编程电流阵列（1）与共模差模产生电路（2）两者之间的配合，使得输出的共模电压的大小与差模电压的幅度都可统一配置，满足了高性能集成电路的设计需求。

Description

接口电路及电子装置 技术领域
本发明涉及集成电路领域，特别是涉及一种接口电路及电子装置，其应用于传输信号，特别适用于高速传输数据的电路。
背景技术
随着信息技术的迅速发展，需要对越来越多的数据进行采集和处理，因此对数据的传输也提出了新的要求，需要在各种模块之间实现高速、低功耗的数据传输。然而，传统的接口电路不能完全满足信号传输过程中的需求，存在以下三个方面的不足：
(1)输出共模反馈电路与输出驱动器相连，增加了输出驱动电路的负载，导致传输速率低；
(2)每个输出驱动电路搭配一个共模反馈环路，每个反馈环路中的运算放大器都会消耗功耗，导致功耗比较大；
(3)输出信号的共模电压、信号幅度等特征不可配置，使用灵活度较小。
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种接口电路及电子装置，用于解决现有接口电路上述任一缺陷的问题。
为实现上述目的及其他相关目的，本发明的第一方面提供了一种接口电路，包括：
可编程电流阵列，用于根据输入编码产生送往共模差模产生电路的第一电流、第二电流，以及根据所述输入编码产生送往驱动偏置产生电路的第三电流、第四电流；
所述共模差模产生电路，连接所述可编程电流阵列的输出端，用于根据所述第一电流产生共模电压，以及根据所述第二电流与共模电压产生高电平电压与低电平电压，其中，所述高电平电压与低电平电压之差为差模电压；
所述驱动偏置产生电路，分别连接所述可编程电流阵列与共模差模产生电路的输出端，用于根据所述第三电流与第四电流模拟负载，结合所述负载、高电平电压与低电平电压产生偏置电压；
输出驱动电路，连接所述驱动偏置产生电路的偏置电压，将输入信号转换成共模电压和差模幅度都可配置的差分信号。
本发明的第二方面提供了一种在模数转换器电路中使用的输出电路，该输出电路包括本 发明上述第一方面的接口电路。
本发明的第三方面提供了一种模数转换器电路，其包括本发明上述第三方面的输出电路。
本发明的第四方面提供了一种集成电路，包括：本发明第一方面的接口电路；或者本发明第二方面的输出电路；或者本发明第三方面的模数转换器电路。
如上所述，本发明的接口电路及电子装置，具有以下有益效果：
通过可编程电流阵列与共模差模产生电路两者之间的配合，产生共模电压、高电平电压与低电平电压，其中，利用调节所述可编程电流阵列的电流控制信号来选通所述共模差模产生电路和差模产生电路使得输出的共模电压的大小与差模电压的幅度都可配置，满足了高性能集成电路的设计需求。
附图说明
图1显示为本发明一实施例提供的一种接口电路的结构示意图；
图2显示为本发明一实施例提供的一种接口电路的完整结构图；
图3显示为本发明一实施例提供的一种可编程电流阵列的电路图；
图4显示为本发明另一实施例提供的一种可编程电流阵列的电路图；
图5显示为本发明一实施例提供的一种共模差模产生电路的电路图；
图6显示为本发明另一实施例提供的一种高低电平产生电路的电路图；
图7显示为本发明一实施例提供的一种可编程电阻串的电路图；
图8显示为本发明一实施例提供的一种驱动偏置产生电路的电路图；
图9显示为本发明一实施例提供的一种输出驱动电路的电路图；
图10显示为本发明一实施例提供的一种电子装置的电路图。
元件标号说明：
1        可编程电流阵列
2        共模差模产生电路
3        驱动偏置产生电路
4        输出驱动电路
5        电子装置
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加 以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。需说明的是，在不冲突的情况下，以下实施例及实施例中的特征可以相互组合。
需要说明的是，以下实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图式中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。
请参阅图1，为本发明一实施例提供的一种接口电路的结构示意图，包括：
可编程电流阵列1，用于根据输入编码产生送往共模差模产生电路的第一电流、第二电流，以及根据所述输入编码产生送往驱动偏置产生电路的第三电流、第四电流；
所述共模差模产生电路2，连接所述可编程电流阵列的输出端，用于根据所述第一电流产生共模电压，以及根据所述第二电流与共模电压产生高电平电压与低电平电压，其中，所述高电平电压与低电平电压之差为差模电压；
所述驱动偏置产生电路3，分别连接所述可编程电流阵列与共模差模产生电路的输出端，用于根据所述第三电流与第四电流模拟负载，结合所述负载、高电平电压与低电平电压产生偏置电压；
输出驱动电路4，连接所述驱动偏置产生电路的偏置电压，将输入信号转换成共模电压和差模幅度都可配置的差分信号。
在本实施例中，通过可编程电流阵列与共模差模产生电路两者之间的配合，产生共模电压、高电平电压与低电平电压，其中，利用调节所述可编程电流阵列的电流控制信号来配置流入所述共模差模产生电路的电流以及产生电压的电阻使得输出的共模电压的大小与差模电压的幅度都可配置，满足了高性能集成电路的设计需求。
详见图2，驱动偏置产生电路3自带模拟负载的功能，能够产生偏置电压，在偏置电压的供电情形下，输出驱动电路将输入信号转换成共模电压和差模幅度都可配置的差分信号。
需要说明的是，输出驱动电路包括多个输出驱动模块，所述驱动偏置产生电路与输出驱动电路之间采用镜像结构，结合所述偏置电压使得所述驱动偏置产生电路与输出驱动电路的工作状态相同，生成共模电压和差模电压幅度都可配置的差分信号，其中，利用所述驱动偏置产生电路中的运算放大器的反馈回路与镜像结构确定所有所述输出驱动模块的共模电压。
在本实施例中，通过镜像结构消除输出共模反馈电路与输出驱动电路的直接连接，减少了寄生电容，提升接口速度；无需每个输出驱动电路搭配一个共模反馈环路，只需设计公共 运放，通过镜像即可确定每个输出驱动电路的输出共模电压，极大的减小了运放的数量，节省了面积和功耗。
在另一个实施例中，所述可编程电流阵列由电流源阵列构成，输出由开关控制电流大小的第一电流I c、第二电流I d、第三电流I p和第四电流I n。
其中，需要说明的是，第一电流I c、第二电流I d、第三电流I p和第四电流I n以相同方式产生，请参阅图3，具体的连接关系：N个电流源的并联，且N个电流源的正端(正极)并联连接电源，每个电流源的负端对应连接一个开关，该开关受控制信号导通或断开，其中，控制信号由输入编码决定，根据控制信号控制电流源阵列输出的电流大小。例如，信号k c1[1]控制电流源I c[1]对应的开关，当k c1[1]为逻辑高电平1时，开关导通，电流I c[1]流出作为第一电流I c的一部分，当k c1[1]为逻辑低电平0时，开关关断。
Figure PCTCN2021070501-appb-000001
Figure PCTCN2021070501-appb-000002
Figure PCTCN2021070501-appb-000003
Figure PCTCN2021070501-appb-000004
在另一些实施例中，请参阅图4，例如，第一电流I c受信号k c1[1]控制电流源I c[1]对应的开关，当k c1[1]为逻辑高电平1时，开关导通，电流I c[1]流出作为第一电流I c的一部分，当k c1[1]为逻辑低电平0时，开关关断。
在本实施例中，通过输入编码控制电流源阵列开关，即，电流源根据不同的开关控制信号产生大小可控的电流，如，第一电流I c、第二电流I d、第三电流I p和第四电流I n，满足用户各种不同应用需求，提高了输出电流的控制精度，又能扩展输出电流的范围。
请参阅图5，为本发明一实施例提供的一种共模差模产生电路的电路图，详述如下：
使用可编程电流阵列送来的第一电流I c产生共模电压V cm，使用可编程电流阵列送来的第二电流I d以及共模电压V cm产生高电平电压V H和低电平电压V L。详见图5，包括共模电平产生电路和高低电平产生电路。
所述共模电平产生电路，包括电流源I c(即第一电流I c)和第一可编程电阻串，其中，电流源I c的正端接电源，电流源I c的负端连接第一可编程电阻串的第一输入端Vin1，该第一可编程电阻串的控制端受控制信号k c2[1:j]控制，第一可编程电阻串的第二输入端Vin2接地，所述第一可编程电阻串输出端输出共模电压V cm。
在本实施例中，第一电流I c流过第一可编程电阻串产生共模电压V cm送往高低电平产生模块。该共模电压V cm可以通过调节第一电流I c的控制信号k c1[1:n]和电平选通控制信号k c2[1:j]来实现，因此，通过可编程电流源阵列和可编程电阻串的配合，实现输出信号“共模电压”的灵活配置，可配置的步长个数为n*j，实现输出共模电压V cm的精细化调节。
所述高低电平产生电路，包括电流源I d(即第二电流I d)、第二可编程电阻串、第三可编程电阻串、第一运算放大器AMP1以及MOS管M 0，所述电流源I d的正端接电源，电流源I d的负端接第二可编程电阻串第一输入端Vin1，第二可编程电阻串的第二输入端Vin2与第三可编程电阻串的第二输入端Vin2串联连接，该第二可编程电阻串的控制端受控制信号k d2[1:j]控制，该第三可编程电阻串的控制端受控制信号k d2[1:j]控制，所述第一运算放大器AMP1的负端连接第二可编程电阻串与第三可编程电阻串之间，所述第一运算放大器AMP1的输出端连接MOS管M 0的栅极，MOS管M 0源极接地，MOS管M 0的漏极连接第三可编程电阻串的第一输入端Vin1，第二可编程电阻串的输出端输出高电平电压V H，第三可编程电阻串的输出端输出高电平电压V L。
在本实例中，第二电流I d流过可编程电阻串2和可编程电容阵列3和晶体管M 0，在运算放大器AMP1及其反馈环路的作用下，得到高电平电压V H和低电平电压V L。其中，高电平电压V H和低电平电压V L的共模电压由运放环路反馈确定，即V cm。差模电压幅度(V H-V L)可以通过调节I d控制信号k d1[1:n]和电平选通控制信号k d2[1:j]来实现，因此，可调节的步长数量为n*j，可以实现输出共模电压(V H-V L)的精细化调节。
请参阅图6，为本发明另一实施例提供的一种高低电平产生电路的电路图，通过其他方式实现的所述高低电平产生电路，详述如下：
第一种实施方式，与上述实施相比，不同点在于，该MOS管M 0由NMOS管变为了PMOS管，其中，PMOS管的源极连接第三可编程电阻串的第一输入端Vin1，PMOS管的漏极接地。
第二种实施方式，与上述实施相比，不同点在于，电流源I d与MOS管M 0的连接位置相互替换，例如，MOS管M 0的漏极连接电源，MOS管M 0的源极连接第二可编程电阻串第一输入端Vin1，第三可编程电阻串的的第一输入端Vin1连接电流源I d的正端，电流源I d的负端接地。
第三种实施方式，与第二种实施方式相比，该MOS管M 0由NMOS管变为了PMOS管，其中，PMOS管的漏极连接第二可编程电阻串的第一输入端Vin1，PMOS管的源极连接电源。
在本实施例中，通过可编程电流源阵列和可编程电阻串多种实施方式产生高电平电压V H和低电平电压V L，其中，高电平电压V H和低电平电压V L，的共模电压由运放环路反馈确定为V CM，差模电压幅度(V H-V L)可以通过调节I d控制信号k d1[1:n]和电平选通控制信号k d2[1:j] 来实现，因此，利用可编程电流源阵列和可编程电阻串的配合，实现输出信号“差模电压”的灵活配置，可配置的步长个数为n*j，实现输出共模电压(V H-V L)的精细化调节。
请参阅图7，为本发明一实施例提供的一种可编程电阻串的电路图，其中，第一可编程电阻串、第二可编程电阻串和第三可编程电阻串的结构相同，例如，任意一个可编程电阻串包括第一电阻R 1、第二电阻R 2、…、第j电阻R j，控制开关k[1:j],第一输入端口Vin1、第二输入端Vin2和输出端Vout，其中，j大于等于1。
需要说明的是，第一输入端口Vin1分别连接第j电阻R j的一端与第j控制开关k[j]的一端，从第j电阻R j至第一电阻R 1之间依次串联，第一电阻R 1的另一端连接第二输入端Vin2；第j-1控制开关k[j-1]连接在第j电阻R j和第j-1电阻R j-1之间直至第1控制开关k[1]连接在第2电阻R 2和第1电阻R 1之间，第1控制开关k[1]至第j控制开关k[j]的另一端连接输出端Vout。
在本实施例中，满足用户各种不同应用需求，提高了电阻的编程精度，又能扩展电阻的编程范围。
请参阅图8，为本发明一实施例提供的一种驱动偏置产生电路的电路图，包括：
驱动偏置产生电路3，使用可编程电容阵列送来的第三电流I p和第四电流I n模拟负载，根据负载结合共模差模产生电路产生的高电平电压V H和低电平电压V L生成第一偏置电压V b1和第二偏置电压V b2，并送往输出驱动电路。
其中，需要说明的是，驱动偏置产生电路3包括第二运算放大器AMP2，第三运算放大器AMP3，晶体管M 1-M 6(其中，第一晶体管M 1、第三晶体管M 3与第五晶体管M 5为PMOS晶体管，第二晶体管M 2、第四晶体管M 4与第六晶体管M 6为NMOS晶体管)，电流源I p(即，第三电流I p)和电流源I n(即，第四电流I n)。第二运算放大器AMP 2的正端连接共模差模产生电路2的输出的高电平电压V H，第二运算放大器AMP2的负端连接第五晶体管M 5和第六晶体管M 6的漏极以及电流源I n(第四电流)，第二运算放大器AMP2的负相输出端连接第一晶体管M 1的栅极(第一偏置电V b1)。第三运算放大器AMP3的正端连接共模差模产生电路2的输出的低电平电压V L，第三运算放大器AMP3的负端连接第三晶体管M 3和第四晶体管M 4的漏极以及电流源I p(第三电流)，第三运算放大器AMP3的正相输出端连接第二晶体管M 2的栅极(第二偏置电V b2)。第三晶体管M 3和第四晶体管M 4的栅极连接逻辑高电平1，第四晶体管M 4和第六晶体管M 6的栅极接逻辑低电平0。输出的第一偏置电压V b1由第二运算放大器AMP2反馈环路决定，输出的第二偏置电V b2由第三运算放大器AMP3反馈环路决定。
在本实施例中，电流源I p和电流源I n用于模拟输出带实际负载时的电流情况，当带实际 负载电阻时，由于第三晶体管M 3和第四晶体管M 4的栅极接逻辑高电平1，因此，第三晶体管M 3断开，第四晶体管M 4导通，电流从负载经过第四晶体管M 4和第二晶体管M 2流入到地，第三电流I p用于模拟从负载流入第四晶体管M 4的电流；由于第五晶体管M 5和第六晶体管M 6的栅极接逻辑高电平0，因此，第五晶体管M 5导通，第六晶体管M 6断开，电流从第一晶体管M1和第五晶体管M 5经过负载流入到地，第四电流I n用于模拟从第五晶体管M 5流入负载的电流。
需要说明的是，本申请中的晶体管优选为场效应晶体管，还可替换为双极晶体管，在此不再赘述。
由于第二运算放大器AMP2的反馈作用，使得V H＝V dH；由于第三运算放大器AMP3的反馈作用，使得V L＝V dL；因此，驱动偏置产生电路3的输出信号幅度(V dH-V dL)＝(V H-V L),也就是说，调节(V H-V L)就实现了对(V dH-V dL)的调节。
由于第三电流I p和第四电流I n用于模拟负载电流，因此电流源I p等于电流源I n,并且由于调节信号幅度(V H-V L)时，由于负载阻抗不变，流过负载的电流随输出信号幅度的变化而等比例的变化，因此调节输出信号幅度(V H-V L)时，应等比例的调节I p和I n，从而实现对负载电流的精确模拟。
请参阅图9，为本发明一实施例提供的一种输出驱动电路的电路图，包括：
输出驱动电路，详见图2，包括输出驱动电路(输出驱动模块)41，输出驱动电路42，…，输出驱动电路4m。输出驱动电路41，将CMOS输入信号D1+和D1-，转换成可配置共模电压和差模幅度的差分对信号D out1+和D out1-输出；输出驱动电路42，将CMOS输入信号D2+和D2-，转换成可配置共模电压和差模幅度的差分对信号D out2+和D out2-输出；…；输出驱动电路4m，将CMOS输入信号Dm+和Dm-，转换成可配置共模电压和差模幅度的差分对信号D outm+和D outm-输出。
其中，输出驱动模块41，输出驱动模块42，…，输出驱动模块4m结构相同，如图9所示，包含晶体管M 7-M 12，其中，第七晶体管M 7、第九晶体管M 9与第十一晶体管M 11为PMOS晶体管，第八晶体管M 8、第十晶体管M 10与第十二晶体管M 12为NMOS晶体管。
第七晶体管M 7的栅极连接第一偏置电压V b1，第八晶体管M 8的栅极连接第二偏置电压V b2，第七晶体管M 7的源极连接电源，第八晶体管M 8的源极接地；第九晶体管M 9和第十晶体管M 10的栅极连接数字输入逻辑电平D+，第十一晶体管M 11和第十二晶体管M 12的栅极连接数字输入逻辑电平D-，其中，第七晶体管M 7的漏极分别连接第九晶体管M 9和第十一晶体管M 11的源极，第八晶体管M 8的漏极分别连接第十晶体管M 10和第十二晶体管M 12的源极，第一输出端Dout+与第十一晶体管M 11和第十二晶体管M 12的漏极相接，第二输出端Dout-与第九晶体管M 9和第十 晶体管M 10的漏极相接。晶体管M 7-M 12的器件尺寸与驱动偏置产生电路3中的晶体管M 1-M 6的尺寸和电流密度成比例，且第一偏置电压V b1和第二偏置电压V b2也由驱动偏置产生电路3在配置了模拟负载的前提下产生，因此输出驱动电路的工作状态与驱动偏置产生电路3的工作状态完全一致，因此，输出信号幅度：
[(D out+)-(D out-)]＝(V dH-V dL)＝(V H-V L)
式中，V H为高电平电压，V L为低电平电压，(V dH-V dL)为驱动偏置产生电路输出信号幅度。
在本实施例中，驱动偏置产生电路3和输出驱动电路4之间采用镜像结构结合偏置电压V b1和V b2的方式实现完全相同的工作状态，从而确定输出驱动电路4的输出共模电压以及差模幅度。因此，输出驱动电路4中，不再需要使用运算放大器来确定其输出共模电压，对于m个输出驱动模块，只需要在带模拟负载的驱动偏置产生电路3中使用运算放大器，就可以实现通过反馈和镜像确定所有输出驱动模块的输出共模电平和差模电压；而传统结构中，需要每个输出驱动模块配一个运算放大器，也就是需要m个运算放大器。因此，本发明极大的减少运算放大器的使用数量，节省面积和功耗。输出驱动电路不与共模反馈环路直接连接，降低了输出节点的寄生电容，提升了输出驱动电路的速度。
参阅图10，为本发明一实施例提供的一种使用接口电路的电子设备，例如：LCD、LED、OLED等显示面板580的电视机或手机或平板或计算机等电子设备的构成例。
来自主机550的串行数据或时钟信号通过LVDS的差动信号线(串行总线)发送给集成电路装置500，且接口电路510(LVDS接收电路)接收。并且，接口电路510将从主机550输送的时钟信号(或者将该时钟信号依次加倍的时钟信号)提供给存储控制器520。并且，将从主机550输送的接收串行数据、即图像数据供给图像处理部530。
图像处理部530对从主机550接收的图像数据进行例如伽马校正等各种图像处理。并且，为了处理该图像，使用存储器560(广义上是根据通过接口电路接收的数据或者时钟信号进行动作的装置)，将图像处理前或图像处理后的图像数据写入存储器560、或者从存储器560读出。作为该存储器560，例如可以使用SDRAM或DDRSDRAM等高速存储器。通过存储控制器520(SDRAM)的控制来实现向这样的存储器560写入数据或者从存储器560读出数据。
存储控制器520的时钟信号生成电路521根据例如来自接口电路510的时钟信号，生成用于对来自存储器560的读出数据进行采样的时钟信号。或者也可以生成向存储器560写入数据所需要的时钟信号。
通过图像处理部530进行了图像处理后的图像数据通过发送电路540发送到显示驱动器 570(根据接口电路接收的数据或者时钟信号进行动作的装置)。并且，显示驱动器570根据接收的图像数据，驱动显示面板580，并进行用于显示对应于图像数据的图像的控制。
此外，适用本实施方式的接口电路的电子设备的结构并不仅限于图10所示的结构，只要是至少包括根据通过接口电路接收的数据或时钟信号进行动作的装置(例如，存储器、显示驱动器、显示面板等)的设备都可以。具体而言，作为可适用本实施方式的电子设备，可以考虑有信息处理装置、便携式信息终端、AV设备、便携式AV设备、游戏装置或者便携式游戏装置等各种设备。
如上所述，体现本发明的接口电路或差分接口电路还可以用于模数转换电路。
在另一些实施例中，本发明的电路可以实现为集成电路，例如，诸如倒装芯片的IC芯片上的集成电路。本发明扩展到如上所述的集成电路和IC芯片、包括这样的IC芯片的电路板以及包括这种电路板的通信网络(例如，互联网光纤网络和无线网络)和这样的网络的网络设备。
综上所述，本发明通过可编程电流阵列与共模差模产生电路两者之间的配合，产生共模电压、高电平电压与低电平电压，其中，利用调节所述可编程电流阵列的电流控制信号来选通所述共模差模产生电路和差模产生电路使得输出的共模电压的大小与差模电压的幅度都可配置，满足了高性能集成电路的设计需求。所以，本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (17)

  1. 一种接口电路，其特征在于，包括：
    可编程电流阵列，用于根据输入编码产生送往共模差模产生电路的第一电流、第二电流，以及根据所述输入编码产生送往驱动偏置产生电路的第三电流、第四电流；
    所述共模差模产生电路，连接所述可编程电流阵列的输出端，用于根据所述第一电流产生共模电压，以及根据所述第二电流与共模电压产生高电平电压与低电平电压，其中，所述高电平电压与低电平电压之差为差模电压；
    所述驱动偏置产生电路，分别连接所述可编程电流阵列与共模差模产生电路的输出端，用于根据所述第三电流与第四电流模拟负载，结合所述负载、高电平电压与低电平电压产生偏置电压；
    输出驱动电路，连接所述驱动偏置产生电路的偏置电压，用于将输入信号转换成共模电压和差模电压幅度都可配置的差分信号。
  2. 根据权利要求1所述的接口电路，其特征在于，所述可编程电流阵列由电流源阵列构成，输出由开关控制电流大小的第一电流、第二电流、第三电流和第四电流。
  3. 根据权利要求1所述的接口电路，其特征在于，所述共模差模产生电路包括依次相连的共模电平产生电路和高低电平产生电路；其中，通过调节所述第一电流的开关控制信号和共模电平产生电路的控制信号使得所述共模电平产生电路输出精确的共模电压；通过调节所述第二电流的开关控制信号和高低电平产生电路的控制信号使得所述高低电平产生电路输出精确的差模电压。
  4. 根据权利要求1或3所述的接口电路，其特征在于，所述共模电平产生电路，由第一电流与第一可编程电阻串构成，利用所述第一电流的开关控制信号和第一可编程电阻串的控制信号来实现精确输出共模电压。
  5. 根据权利要求1或3所述的接口电路，其特征在于，所述高低电平产生电路，由第二电流、第二可编程电阻串、第三可编程电阻串、第一运算放大器和第一MOS管构成，所述第二电流、第二可编程电阻串、第三可编程电阻串和第一MOS管依次相连，所述第一运算放大器的正端连接共模电压，其负端连接在第二可编程电阻串和第三可编程电阻串之间形成运放反馈环路，其中，利用所述第二电流的开关控制信号和第二、三可编程电阻串的控制信号来实现精确输出差模电压。
  6. 根据权利要求1所述的接口电路，其特征在于，所述驱动偏置产生电路利用第三电流与第四电流模拟带实际负载的电流，结合模拟的负载电流、高电平电压与低电平电压利用运算放大器反馈环路产生第一偏置电压与第二偏置电压。
  7. 根据权利要求1所述的接口电路，其特征在于，所述第三电流与第四电流利用负载阻抗不变特性，根据流过所述负载的电流随输出信号幅度的变化而等比例的变化，通过调节输出信号幅度同等比例的调整第三电流与第四电流，从而实现对负载电流的精确模拟。
  8. 根据权利要求6所述的接口电路，其特征在于，所述驱动偏置产生电路包括第二运算放大器、第三运算放大器和晶体管M 1～M 6；其中，所述第二运算放大器的正端连接高电平电压V H，第二运算放大器的负端连接第五晶体管M 5和第六晶体管M 6的漏极以及第四电流，第二运算放大器的负相输出端连接第一晶体管M 1的栅极并输出第一偏置电V b1；第三运算放大器的正端连接低电平电压V L，第三运算放大器的负端连接第三晶体管M 3和第四晶体管M 4的漏极以及第三电流，第三运算放大器的正相输出端连接第二晶体管M 2的栅极并输出第二偏置电V b2；第三晶体管M 3和第四晶体管M 4的栅极连接逻辑高电平，第五晶体管M 5和第六晶体管M 6的栅极接逻辑低电平。
  9. 根据权利要求6所述的接口电路，其特征在于，所述第一偏置电压由第二运算放大器的反馈环路确定，所述第二偏置电压由第三运算放大器的反馈环路确定。
  10. 根据权利要求8所述的接口电路，其特征在于，所述驱动偏置产生电路输出的信号幅度(V dH-V dL)＝(V H-V L)，其中，所述第二运算放大器的反馈环路，使得V H＝V dH；所述第三运算放大器的反馈环路，使得V L＝V dL。
  11. 根据权利要求1所述的接口电路，其特征在于，所述驱动偏置产生电路与输出驱动电路之间采用镜像结构，结合所述偏置电压使得所述输出驱动电路与驱动偏置产生电路的工作状态相同，生成共模电压和差模电压幅度都可配置的差分信号。
  12. 根据权利要求1或11所述的接口电路，其特征在于，所述输出驱动电路包括多个输出驱动模块，所述输出驱动模块的结构与驱动偏置产生电路的晶体管结构形成镜像，且所述输出驱动模块与驱动偏置产生电路的器件尺寸成比例，电流密度成比例，且器件尺寸之 比与电流密度之比相同。
  13. 根据权利要求12所述的接口电路，其特征在于，所述输出驱动模块包括晶体管M 7～M 12，第七晶体管M 7的栅极连接第一偏置电压V b1，第八晶体管M 8的栅极连接第二偏置电压V b2，第七晶体管M 7的源极连接电源，第八晶体管M 8的源极接地；第九晶体管M 9和第十晶体管M 10的栅极连接数字输入逻辑电平D+，第十一晶体管M 11和第十二晶体管M 12的栅极连接数字输入逻辑电平D-，第七晶体管M 7的漏极分别连接第九晶体管M 9和第十一晶体管M 11的源极，第八晶体管M 8的漏极分别连接第十晶体管M 10和第十二晶体管M 12的源极，第一输出端Dout+与第十一晶体管M 11和第十二晶体管M 12的漏极相接，第二输出端Dout-与第九晶体管M 9和第十晶体管M 10的漏极相接，且所述第一输出端Dout+与第二输出端Dout-之间的信号幅度为：
    [(D out+)-(D out-)]＝(V dH-V dL)＝(V H-V L)
    式中，V H为高电平电压，V L为低电平电压，(V dH-V dL)为驱动偏置产生电路输出信号幅度。
  14. 根据权利要求1或11所述的接口电路，其特征在于，还包括：利用所述驱动偏置产生电路中的运算放大器的反馈回路与镜像结构确定所有所述输出驱动模块的共模电压和差模电压。
  15. 一种在模数转换器电路中使用的输出电路，其特征在于，所述输出电路包括权利要求1至14中任一项所述的接口电路。
  16. 一种模数转换器电路，其特征在于，包括权利要求15所述的输出电路。
  17. 一种集成电路，所述集成电路包括：权利要求1至14中任一项所述的接口电路；或者权利要求15所述的输出电路；或者权利要求16所述的模数转换器电路。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117395761A (zh) * 2023-12-12 2024-01-12 深圳飞骧科技股份有限公司 电源和偏置可调的射频前端模组及射频芯片

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112152606B (zh) * 2020-09-28 2023-12-26 中国电子科技集团公司第二十四研究所 接口电路及电子装置
CN113110188B (zh) * 2021-04-21 2022-06-17 广州金升阳科技有限公司 一种can总线接收电路
CN114172506B (zh) * 2021-11-30 2023-10-03 北京时代民芯科技有限公司 一种驱动器输出摆幅、共模电压控制电路及控制方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4933644A (en) * 1988-12-23 1990-06-12 Texas Instruments, Incorporated Common-mode feedback bias generator for operational amplifiers
CN1638369A (zh) * 2003-12-30 2005-07-13 三星电子株式会社 用于减少二阶交互调制的方法
US20130069718A1 (en) * 2011-09-15 2013-03-21 Analog Devices, Inc. Apparatus and methods for electronic amplification
CN104467716A (zh) * 2014-12-18 2015-03-25 北京集创北方科技有限公司 一种输出共模电压恒定的全差分轨到轨放大器的设计
CN108964497A (zh) * 2017-05-19 2018-12-07 丰郅(上海)新能源科技有限公司 抑制共模干扰的逆变系统
CN112152606A (zh) * 2020-09-28 2020-12-29 中国电子科技集团公司第二十四研究所 接口电路及电子装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080136256A1 (en) * 2006-12-11 2008-06-12 Amit Gattani Network devices with solid state transformer and electronic load circuit to provide termination of open-drain transmit drivers of a physical layer module
US7532043B1 (en) * 2007-10-26 2009-05-12 National Semiconductor Corporation Signal detector output for cable driver applications
US8823454B2 (en) * 2012-03-30 2014-09-02 Freescale Semiconductor, Inc. Fully complementary self-biased differential receiver with startup circuit
CN102929319B (zh) * 2012-10-10 2014-09-10 清华大学 一种低压差线性稳压器
CN104113295A (zh) * 2014-04-30 2014-10-22 西安电子科技大学昆山创新研究院 一种低压全差分运算放大器电路
CN107066416B (zh) * 2016-12-20 2020-05-08 华为技术有限公司 串行通信系统的驱动电路及驱动方法
US10491436B1 (en) * 2018-06-20 2019-11-26 Xilinx, Inc. Method and system for generating a modulated signal in a transmitter

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4933644A (en) * 1988-12-23 1990-06-12 Texas Instruments, Incorporated Common-mode feedback bias generator for operational amplifiers
CN1638369A (zh) * 2003-12-30 2005-07-13 三星电子株式会社 用于减少二阶交互调制的方法
US20130069718A1 (en) * 2011-09-15 2013-03-21 Analog Devices, Inc. Apparatus and methods for electronic amplification
CN104467716A (zh) * 2014-12-18 2015-03-25 北京集创北方科技有限公司 一种输出共模电压恒定的全差分轨到轨放大器的设计
CN108964497A (zh) * 2017-05-19 2018-12-07 丰郅(上海)新能源科技有限公司 抑制共模干扰的逆变系统
CN112152606A (zh) * 2020-09-28 2020-12-29 中国电子科技集团公司第二十四研究所 接口电路及电子装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117395761A (zh) * 2023-12-12 2024-01-12 深圳飞骧科技股份有限公司 电源和偏置可调的射频前端模组及射频芯片
CN117395761B (zh) * 2023-12-12 2024-02-20 深圳飞骧科技股份有限公司 电源和偏置可调的射频前端模组及射频芯片

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