WO2022057844A1 - 设备同步校准方法、装置、设备及存储介质 - Google Patents

设备同步校准方法、装置、设备及存储介质 Download PDF

Info

Publication number
WO2022057844A1
WO2022057844A1 PCT/CN2021/118635 CN2021118635W WO2022057844A1 WO 2022057844 A1 WO2022057844 A1 WO 2022057844A1 CN 2021118635 W CN2021118635 W CN 2021118635W WO 2022057844 A1 WO2022057844 A1 WO 2022057844A1
Authority
WO
WIPO (PCT)
Prior art keywords
time stamp
synchronization
devices
calibration
deviation
Prior art date
Application number
PCT/CN2021/118635
Other languages
English (en)
French (fr)
Inventor
蒋文裕
龚桂强
王悦
Original Assignee
北京普源精电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 北京普源精电科技有限公司 filed Critical 北京普源精电科技有限公司
Priority to KR1020237012479A priority Critical patent/KR20230066106A/ko
Priority to JP2023517788A priority patent/JP2023541963A/ja
Priority to US18/026,672 priority patent/US20230341892A1/en
Priority to EP21868666.5A priority patent/EP4216019A1/en
Publication of WO2022057844A1 publication Critical patent/WO2022057844A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/14—Time supervision arrangements, e.g. real time clock
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Definitions

  • the embodiments of the present application relate to signal processing technologies, for example, to a device synchronization calibration method, apparatus, device, and storage medium.
  • the parallel mode and the series mode are usually used to align the channels between multiple devices.
  • the parallel mode is shown in Figure 1, that is, using a synchronization source (or called a synchronization machine) to connect multiple devices in parallel, and through the synchronization source, the synchronization signals and clock signals between multiple devices are strictly synchronized and aligned.
  • the serial mode is shown in Figure 2, that is, multiple devices are connected in series, and the delay of multiple devices is adjusted or supplemented by measuring the delay of the serial path.
  • the above two schemes both need to be synchronized based on the operating clock, and the clock synchronization is further divided into a parallel clock synchronization scheme and a serial clock synchronization scheme.
  • the parallel clock synchronization scheme can be understood as outputting multiple synchronous clocks to multiple devices from a standard clock source, so that the frequency and phase of the clocks of the multiple devices are kept consistent.
  • a complex clock source circuit needs to be used to ensure strict alignment, calibration and testing, and the circuit cost is high.
  • Serial clock synchronization can be understood as a clock source provides a clock, multiple devices are connected in series by clocks, and multiple devices use a phase locked loop (Phase Locked Loop, PLL) to perform phase detection and synchronization tracking of the clock to achieve multiple devices.
  • PLL Phase Locked Loop
  • the clock frequency is the same between.
  • due to the problem of clock path delay there will be a relatively fixed clock phase difference, which will lead to the accumulation of errors between multiple devices connected in series.
  • the present application provides a device synchronization calibration method, device, device and storage medium, aiming at realizing synchronization calibration among multiple devices through time stamp synchronization deviation.
  • an embodiment of the present application provides a device synchronization calibration method, which is applied to a controller, including: acquiring a time stamp synchronization deviation between at least two devices;
  • the synchronization calibration instruction is used to perform synchronization calibration on two devices corresponding to the synchronization deviation of any time stamp.
  • an embodiment of the present application provides a device synchronization calibration method, which is applied to a device and includes: acquiring a sampling signal;
  • the timestamp is sent to the controller.
  • an embodiment of the present application provides a device synchronization calibration device, including:
  • An acquisition module set to acquire the timestamp synchronization deviation between at least two devices
  • a judgment module configured to judge whether the time stamp synchronization deviation between the at least two devices is a set value
  • the generation module is set to generate a synchronization calibration instruction when the synchronization deviation of any time stamp is not the set value;
  • the synchronization calibration instruction is used to perform synchronization calibration on two devices corresponding to the synchronization deviation of any time stamp.
  • an embodiment of the present application provides a device synchronization calibration device, including:
  • the acquisition module is set to acquire the sampling signal
  • a processing module configured to process the sampled signal to generate a timestamp
  • a transmission module configured to send the timestamp to the controller.
  • an embodiment of the present application provides an electronic device, including: a memory, a processor, and a computer program stored in the memory and running on the processor, when the processor executes the computer program, the processor implements the following: The device synchronization calibration method provided by the above embodiment.
  • an embodiment of the present application provides a computer storage medium on which a computer program is stored, and when the computer program is executed by a processor, the device synchronization calibration method provided by the above embodiment is implemented.
  • Fig. 1 is the schematic diagram of a plurality of devices in parallel in the related art
  • Fig. 2 is a schematic diagram of a plurality of devices connected in series in the related art
  • FIG. 3 is a flowchart of a method for synchronizing calibration of equipment in an embodiment of the present application
  • FIG. 4 is a flowchart of a method for synchronizing calibration of equipment in an embodiment of the present application
  • FIG. 5 is a schematic diagram of a device synchronization calibration framework in an embodiment of the present application.
  • FIG. 6 is a schematic diagram of a time stamp in an embodiment of the present application.
  • FIG. 7 is a schematic diagram of a synchronization calibration result in an embodiment of the present application.
  • FIG. 8 is a flowchart of a device synchronization calibration method in an embodiment of the present application.
  • FIG. 9 is a flowchart of a device synchronization calibration method in an embodiment of the present application.
  • FIG. 10 is a flowchart of a method for synchronizing calibration of equipment in an embodiment of the present application
  • FIG. 11 is a schematic structural diagram of an apparatus for synchronizing and calibrating equipment in an embodiment of the present application.
  • FIG. 12 is a schematic structural diagram of an apparatus for synchronizing and calibrating equipment in an embodiment of the present application.
  • FIG. 13 is a schematic structural diagram of an electronic device in an embodiment of the present application.
  • FIG. 3 is a flowchart of a device synchronization calibration method provided by an embodiment of the present application. As shown in FIG. 3 , the method can be applied to a controller, and the method can include but is not limited to the following steps:
  • the time stamp synchronization deviation between the two devices in this step can be understood as the deviation between the time stamp intervals recorded by the two devices for different signals respectively. b Deviation between the intervals of time stamps recorded for the same two signals. When there are more than two devices, all devices can be combined in pairs to determine the time stamp synchronization deviation between the two devices in each combination.
  • controller may be a controller in an independent device, or may be a controller within the above-mentioned device.
  • the above-mentioned set value may be 0, or may be a fixed deviation value between two devices.
  • the time stamp synchronization deviation between the two devices is the set value, it means that the transmission channels of the two devices are kept synchronized.
  • the set value when the set value is 0, describe the interval between the time stamps of the two signals recorded by device a and the time stamps of the same two signals recorded by device b.
  • the deviation is 0, that is, the transmission channels of the two devices are synchronized.
  • the set value is a fixed deviation value, that is, there is a certain deviation between the transmission channel of device a and the transmission channel of device b, if the interval between the time stamps of the two signals recorded by device a is different from that of device b If the deviation between the time stamp intervals of the same two signals recorded is still the fixed deviation value, it means that the transmission channels between the two devices are kept synchronized.
  • Any time stamp synchronization deviation in this step may be understood as the time stamp synchronization deviation between the two devices corresponding to the synchronization deviation. If the synchronization deviation of any time stamp is not the set value, it means that the data transmission channel between the two devices corresponding to the synchronization deviation of any time stamp is out of synchronization.
  • the controller generates a synchronization calibration instruction.
  • the synchronous calibration instruction can be used to synchronously calibrate the two devices corresponding to any of the above-mentioned time stamp synchronization deviations.
  • the synchronous calibration instruction may carry a calibration deviation, and the controller may perform synchronous calibration on the corresponding two devices through the calibration deviation.
  • An embodiment of the present application provides a device synchronization calibration method, which can be applied to a controller, and includes acquiring the time stamp synchronization deviation between at least two devices; judging the time stamp between at least two devices Whether the synchronization deviation is the set value; if the synchronization deviation of any time stamp is not the set value, a synchronization calibration command is generated; wherein, the synchronization calibration command is used to synchronize the two devices corresponding to the synchronization deviation of any time stamp calibration. In this way, the synchronization delay between multiple devices can be effectively improved by the time stamp synchronization deviation.
  • step S301 may include, but is not limited to, the following steps:
  • the first trigger processing signal in this step may be the synchronization machine outputting the synchronization signal to the device a and the device b, which are respectively transmitted to the trigger module of the corresponding device via the input channels of the device a and the device b. signal generated later.
  • the manner of obtaining the first time stamp interval for the first trigger processing signal may be: obtaining the first time stamp recorded by any one of the two current devices for the first trigger processing signal, and obtaining the other device among the two current devices For the second time stamp recorded by the first trigger processing signal, obtain the time stamp interval between the current two devices for the first trigger processing signal according to the first time stamp and the second time stamp.
  • the signal transmitted by the input channel can be transmitted to the data processing module through the delay module, and after the trigger module transmits the first trigger processing signal to the data processing module, the data processing module delays the first trigger processing signal.
  • the signal transmitted by the time module is processed, and the current time stamp is recorded, which is the first time stamp.
  • the data processing module performs the same processing process and records the current time stamp as the second time stamp. In this way, the interval between the first timestamp and the second timestamp recorded by the device a and the device b respectively for the first trigger processing signal is the first timestamp interval.
  • the synchronization signal can be obtained by aligning the channels inside a device, for example, aligning the data channel and the trigger channel, using the channel-aligned device to calibrate the output of the synchronizing machine, and then aligning the calibrated synchronizing machine.
  • the output end of the device is connected to at least two devices, and the trigger source in the synchronization machine transmits the synchronization signal to the at least two devices.
  • the output end of the synchronization machine is connected to two devices, and transmits synchronization signals to the two devices.
  • S402 Acquire a second time stamp interval of the current two devices processing signals for the second trigger.
  • the second trigger processing signal in this step may be that after the synchronizing machine transmits another synchronizing signal to equipment a and equipment b, respectively, the second trigger processing signal in equipment a and equipment b
  • the trigger module generates a signal based on the synchronization signal.
  • the manner of obtaining the second time stamp interval for the second trigger processing signal may be: obtaining the third time stamp recorded by any one of the two current devices for the second trigger processing signal, and obtaining the other device among the two current devices For the fourth time stamp recorded by the second trigger processing signal, obtain the time stamp interval between the current two devices for the second trigger processing signal according to the third time stamp and the fourth time stamp.
  • the data processing module After the trigger module inside the device a transmits the second trigger processing signal to the data processing module, the data processing module receives the signal transmitted by the input channel transmitted by the delay module, and performs processing on the signal transmitted by the delay module for the second trigger processing signal. processing, while recording the first timestamp, after the trigger module inside the device b transmits the second trigger processing signal to the data processing module, the data processing module performs the same processing on the second trigger processing signal, and records the second timestamp, Then, the interval between the first timestamp and the second timestamp recorded by the device a and the device b respectively is the second timestamp interval.
  • the absolute value of the difference between the first time stamp interval and the second time stamp interval determined by the two current devices for the two synchronization signals is taken as the time stamp synchronization deviation.
  • the time stamp synchronization deviation Offset_ab between device a and device b can be determined by the following formula, namely:
  • Offset_ab
  • a.TS1 is the time stamp recorded by device a for the first trigger processing signal
  • b.TS1 is the time stamp recorded by device b for the first trigger processing signal
  • a.TS2 is the time stamp recorded by device a for the second trigger processing signal
  • is the first time stamp interval between device a and device b for the first trigger processing signal
  • is the second time stamp interval for device a and device b to process signals for the second trigger.
  • the above time stamp mainly contains two parts of information, one part is the count value generated by the working clock of each device, and the count value accumulated from the initial value (for example, 0) with the clock cycle as the step, and the other part is the fine trigger by signal trigger Judgment to obtain more accurate time and location information. That is, a.TS1, b.TS1, a.TS2, and b.TS2 are all composed of two parts, a coarse adjustment and a fine adjustment. Exemplarily, the two parts may be shown in FIG. 6 .
  • S404 Select two devices that are different from at least one of the current two devices from the at least two devices, and use the selected two devices as the current two devices.
  • the device a and device can be selected. At least one of two different devices in b, for example, select device a and device c, or device c and device d, etc., and use the selected two devices as the current two devices.
  • the above-mentioned steps S401 to S404 can be repeatedly performed. For example, for the selected device a and device c, after determining the time stamp synchronization deviation between the two devices, the device a and device a can be reselected. Two devices with different device c, and continue to determine the time stamp synchronization deviation between the selected two devices, until the time stamp synchronization deviation between all devices in at least two devices is obtained.
  • the controller may also send a synchronization calibration instruction to the two devices corresponding to any time stamp synchronization deviation, and/or send a synchronization calibration instruction to the synchronization machine.
  • the synchronous calibration command may include a previous-stage calibration command, and/or a subsequent-stage calibration command.
  • the previous-level calibration instruction is used to instruct the device corresponding to any timestamp synchronization deviation to adjust its own channel delay according to any timestamp synchronization deviation; or, the previous-level calibration instruction is used to instruct the synchronization machine to synchronize according to any timestamp
  • the deviation adjusts the delay of the channel corresponding to the synchronization deviation of any time stamp within itself, and the synchronization machine is connected to at least two devices through at least two channels within itself.
  • the previous-level calibration instruction can be used for the device corresponding to the time stamp synchronization deviation to adjust its own channel delay according to the time stamp synchronization deviation, or, by the synchronization
  • the machine adjusts the delay of the channel connected to the corresponding device according to the time stamp synchronization deviation.
  • the post-level calibration instruction is used to instruct the controller to perform delay compensation on the signal display mode according to any time stamp synchronization deviation.
  • Figure 7 shows the result of synchronizing the two devices through the synchronizing calibration command.
  • the measured signal in Figure 7 can be understood as the signal input by the synchro machine to the two devices at the connection point.
  • CLK.A and CLK.B are respectively It is the signal waveform sampled by the two devices to the measured signal
  • SYNC.A and SYNC.B are the signal waveforms after the two devices are synchronized.
  • FIG. 8 is a flowchart of a device synchronization calibration method provided by an embodiment of the present application. The method can be applied to a device. As shown in FIG. 8 , the method can include the following steps:
  • the sampling signal can be understood as a signal transmitted by a synchronizing machine connected to the device.
  • S802. Process the sampled signal to generate a time stamp.
  • the device may process the acquired sampled signal in two ways: coarse adjustment and fine adjustment. For example, rough adjustment processing is performed on the sampling signal, and fine adjustment processing is performed on the roughly adjusted sampling signal according to the trigger signal, and a timestamp is generated based on the finely adjusted sampling signal,
  • the trigger signal in the above process is generated by the device based on the sampling signal.
  • the controller can be a controller in an independent device, or can also be a controller inside the device. After the device generates the time stamp, the time stamp can be transmitted to the controller.
  • An embodiment of the present application provides a device synchronization calibration method, the method includes acquiring a sampling signal, processing the sampling signal to generate a time stamp, sending the time stamp to a controller, and receiving a synchronization calibration instruction sent by the controller, wherein the synchronization
  • the calibration command is used to synchronize the calibration of the device.
  • the controller can judge whether the corresponding device is synchronized through the timestamp.
  • the synchronization calibration command sent by the controller is received to calibrate the device, thereby effectively improving the synchronization delay between multiple devices. .
  • the synchronization calibration instruction may carry a time stamp synchronization deviation, and the time stamp synchronization deviation may be calculated by the controller according to the time stamp in the foregoing step S803.
  • the method may further include but not limited to the following steps:
  • the synchronization calibration instruction carries a time stamp synchronization deviation
  • the time stamp synchronization deviation may be calculated by the controller according to the time stamp in the foregoing step S803.
  • the method may further include but not limited to the following steps:
  • the synchronization calibration instruction is used to instruct the synchronization machine to adjust the delay of the channel corresponding to the time stamp synchronization deviation in the synchronization machine according to the time stamp synchronization deviation.
  • the synchronous machine can be connected to the device through any one of the at least two channels within itself, then the device can send a synchronization calibration instruction to the synchronous machine based on the channel, and the synchronous machine can adjust the channel connected to the device according to the synchronization calibration instruction. Perform calibration.
  • FIG. 11 is a device synchronization calibration apparatus provided by an embodiment of the present application. As shown in FIG. 11 , the apparatus may include: an acquisition module 1101 , a determination module 1102 , and a generation module 1103 ;
  • the obtaining module is set to obtain the time stamp synchronization deviation between at least two devices
  • the judgment module is set to judge whether the time stamp synchronization deviation between at least two devices is a set value
  • the generation module is set to generate a synchronization calibration instruction when the synchronization deviation of any time stamp is not the set value;
  • the synchronization calibration instruction is used to perform synchronization calibration on two devices corresponding to any time stamp synchronization deviation.
  • the above obtaining module may be configured to implement the following steps:
  • Step 1 Obtain the first time stamp interval of the current two devices for the first trigger processing signal
  • Step 2 Obtain the second time stamp interval of the current two devices for the second trigger processing signal:
  • Step 3 Determine the current timestamp synchronization deviation between the two devices according to the first timestamp interval and the second timestamp interval;
  • Step 4 Select two devices that are different from at least one of the current two devices from the at least two devices, and use the selected two devices as the current two devices;
  • the obtaining module may be configured to obtain the first time stamp recorded by any one of the current two devices for the first trigger processing signal or the second trigger processing signal; obtain the first time stamp that is recorded by the other device in the current two devices for the first trigger processing signal the second time stamp recorded by the signal or the second trigger processing signal; and obtaining, according to the first time stamp and the second time stamp, the time stamp interval of the current two devices processing the signal for the first trigger or the second trigger.
  • the above-mentioned synchronous calibration instruction may include a pre-level calibration instruction, and/or a post-level calibration instruction;
  • the previous-level calibration instruction is used to instruct the device corresponding to any timestamp synchronization deviation to adjust its own channel delay according to any timestamp synchronization deviation; or, the previous-level calibration instruction is used to instruct the synchronization machine to synchronize according to any timestamp The deviation adjusts the delay of the channel corresponding to the synchronization deviation of any timestamp within itself, and the synchronization machine is connected to at least two devices through at least two channels within itself;
  • the post-level calibration instruction is used to instruct the controller to perform delay compensation on the signal display mode according to any time stamp synchronization deviation.
  • the above apparatus may further include a transmission module
  • the transmission module is configured to send a synchronization calibration instruction to two devices corresponding to any time stamp synchronization deviation; and/or, to send a synchronization calibration instruction to the synchronization machine.
  • the above-mentioned device synchronization calibration device can execute the device synchronization calibration method provided in FIG. 3 and FIG. 4 , and has corresponding components and beneficial effects in the method.
  • FIG. 12 is a device synchronization calibration device provided by an embodiment of the present application. As shown in FIG. 12 , the device may include: an acquisition module 1201 , a processing module 1202 , a transmission module 1203 , and a calibration module 1104 ;
  • the acquisition module is set to acquire the sampling signal
  • the processing module is set to process the sampled signal to generate a timestamp
  • the transmission module is configured to send the time stamp to the controller; and receive the synchronous calibration instruction sent by the controller, wherein the synchronous calibration instruction is used to perform synchronous calibration on the device.
  • the above-mentioned processing module is configured to perform rough adjustment processing on the sampling signal; perform fine adjustment processing on the roughly adjusted sampling signal according to the trigger signal; and generate a timestamp according to the finely adjusted sampling signal;
  • the trigger signal is generated by the above-mentioned apparatus based on the sampling signal.
  • the synchronization calibration instruction carries a timestamp synchronization offset
  • the processing module is set to adjust its own channel delay according to the time stamp synchronization deviation.
  • the synchronization calibration instruction carries a time stamp synchronization deviation;
  • the above-mentioned transmission module is configured to send the synchronization calibration instruction to the synchronization machine;
  • the synchronization calibration instruction is used to instruct the synchronization machine to adjust the delay of the channel corresponding to the time stamp synchronization deviation in the synchronization machine according to the time stamp synchronization deviation.
  • the synchronous machine is connected to the above-mentioned device through any one of at least two channels inside itself.
  • the above device synchronization calibration device can execute the device synchronization calibration method provided in FIG. 7 and FIG. 8 , and has corresponding components and beneficial effects in the method.
  • FIG. 13 is a schematic structural diagram of an electronic device provided in Embodiment 13 of the present application.
  • the device includes a controller 1301, a memory 1302, an input device 1303, and an output device 1304; the number of controllers 1301 in the device can be is one or more, and a controller 1301 is taken as an example in FIG. 13; the controller 1301, memory 1302, input device 1303 and output device 1304 in the device can be connected through a bus or other means. In FIG. 13, the connection through the bus is example.
  • the memory 1302 can be configured to store software programs, computer-executable programs, and modules, such as the corresponding device synchronization calibration methods in the embodiments of FIGS. 3 , 4 , 8 , 9 and 10 .
  • Program instructions/modules eg, modules in the device synchronization calibration apparatus in the embodiments of FIG. 11 and FIG. 12 .
  • the controller 1301 executes various functional applications and data processing of the device by running the software programs, instructions and modules stored in the memory 1302, ie, implements the above-mentioned device synchronization calibration method.
  • the memory 1302 may mainly include a stored program area and a stored data area, wherein the stored program area may store an operating system, an application program required for at least one function; the stored data area may store data created according to the use of the terminal, and the like. Additionally, memory 1302 may include high-speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device. In some instances, memory 1302 may include memory located remotely from controller 1301, which may be connected to a terminal/server through a network. Examples of such networks include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.
  • the input device 1303 may be configured to receive input numerical or character information, and to generate key signal input related to user settings and function control of the device.
  • the output device 1304 may include a display device such as a display screen.
  • Embodiments of the present application further provide a storage medium containing computer-executable instructions, the computer-executable instructions are configured to execute a device synchronization calibration method when executed by a computer processor, and the method includes FIG. 3 , FIG. 4 , and FIG. 8 , the steps shown in the embodiments of FIG. 9 and FIG. 10 .
  • the present application can be implemented by means of software and necessary general-purpose hardware, and certainly can also be implemented by hardware.
  • the technical solutions of the present application can be embodied in the form of software products in essence or the parts that make contributions to related technologies, and the computer software products can be stored in a computer-readable storage medium, such as a computer floppy disk, Read-Only Memory (ROM), Random Access Memory (RAM), flash memory (FLASH), hard disk or optical disk, etc., including several instructions to make a computer device (which can be a personal computer, A server, or a network device, etc.) executes the methods described in the various embodiments of the present application.
  • the storage medium may be a non-transitory storage medium.
  • the solution shown in this application can be applied between synchronizing machines, devices and controllers.
  • the synchronization machine includes a trigger source.
  • the synchronization machine includes a trigger source.
  • the synchronization machine includes a trigger source.
  • the synchronization machine includes a trigger source.
  • the synchronization machine includes a trigger source.
  • the synchronization machine includes a trigger source.
  • the synchronization machine includes a trigger source.
  • the a and device b obtain the sampling signal respectively, and perform rough adjustment processing on the sampling signal to obtain the sampling signal after the rough adjustment processing; according to the trigger signal sent by the trigger source in the synchronous machine, the rough adjustment sampling signal is subjected to fine adjustment processing , a time stamp is generated according to the finely adjusted sampling signal, wherein the trigger signal is generated by device a or device b based on the sampling signal.
  • the signal under test can be understood as the signal input by the synchronous machine to the device a.
  • the device a samples the signal under test to form the sampling signal CLK.A.
  • the device a A trigger signal is also generated. Since the working clock of device a will first step by the clock cycle, a count value will be accumulated from the initial value, that is, the timestamp of device a will be roughly adjusted, and the roughly adjusted timestamp will be recorded.
  • device a will perform fine adjustment processing on the sampled signal after the rough adjustment according to the trigger signal to obtain more accurate time and position information, that is, finely adjust the time stamp of device a, record the fine adjustment time stamp after fine adjustment, and finally According to the superposition result of the coarse adjustment time stamp and the fine adjustment time stamp, the time stamp of device a is finally determined.
  • the trigger source in the synchronization machine sends a first synchronization signal to device a and device b. After device a and device b sample the first synchronization signal to obtain the sampled signal, The trigger modules in the two devices respectively generate a first trigger processing signal.
  • Device a obtains a rough adjustment time stamp based on the sampling signal, the controller obtains a fine adjustment time stamp based on the first trigger processing signal, and finally determines the first time stamp of device a for the first synchronization signal (or the first trigger processing signal); device b
  • the coarse adjustment time stamp is obtained based on the sampling signal, the controller obtains the fine adjustment time stamp based on the first trigger processing signal, and finally the second time stamp of the device b for the first synchronization signal (or the first trigger processing signal) is determined.
  • the controller records the interval between the first time stamp and the second time stamp of the device a and the device b for the first synchronization signal (or for the first trigger processing signal), and determines it as the first time stamp interval.
  • the trigger source in the synchronization machine sends a second synchronization signal to device a and device b, and device a and device b perform the same processing on the second synchronization signal.
  • the controller records the interval between the third time stamp and the fourth time stamp of device a and device b for the second synchronization signal (or for the second trigger processing signal), and determines it as the second time stamp interval.
  • the controller determines the time stamp synchronization deviation between device a and device b according to the first time stamp interval and the second time stamp interval. Determine whether the time stamp synchronization deviation between device a and device b is the set value. If the time stamp synchronization deviation is not the set value, the controller generates a synchronization calibration instruction for the synchronization calibration of device a and device b. .

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Hardware Redundancy (AREA)
  • Electric Clocks (AREA)

Abstract

本申请公开了一种设备同步校准方法、装置、设备及存储介质，该方法可以包括获取至少两台设备中每两台设备之间的时间戳同步偏差；判断每两台设备之间的时间戳同步偏差是否为设定值；基于任一时间戳同步偏差不为设定值的判断结果，生成同步校准指令；其中，同步校准指令用于对与任一时间戳同步偏差对应的两台设备进行同步校准。

Description

设备同步校准方法、装置、设备及存储介质
本申请要求在2020年9月17日提交中国专利局、申请号为202010980816.0的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及信号处理技术，例如涉及一种设备同步校准方法、装置、设备及存储介质。
背景技术
在对多个设备的多个通道进行同步或对齐时，通常需要先对单台设备中的一个或多个通道进行对齐，再对多个设备之间的通道进行对齐。其中，对多个设备之间的通道进行对齐通常采用并联方式和串联方式。并联方式如图1所示，即利用同步源(或称之为同步机)将多台设备用并联的方式连接，通过同步源对多台设备之间的同步信号和时钟信号进行严格的同步对齐。串联方式如图2所示，即是将多台设备进行串联，通过测量串联路径的延迟，调节或补充多台设备的延迟。
但是，上述两种方案都需要基于工作时钟进行同步，时钟同步又分为并行时钟同步方案和串行时钟同步方案。其中，并行时钟同步方案可以理解为由一个标准的时钟源输出多路同步时钟给多个设备，从而实现多个设备的时钟的频率和相位保持一致。这样在多个设备的场景下，需要使用复杂的时钟源电路才能保证严格的对齐校准和测试，电路成本较高。串行时钟同步可以理解为一个时钟源提供时钟，多个设备之间通过时钟串联，并且多台设备通过锁相环(Phase Locked Loop,PLL)对时钟进行鉴相和同步跟踪，实现多台设备之间的时钟频率相同。但由于时钟路径延迟的问题，会存在一个相对固定的时钟相位差，进而导致串联的多个设备之间的产生误差累计。
发明内容
本申请提供一种设备同步校准方法、装置、设备及存储介质，旨在通过时间戳同步偏差实现多台设备之间的同步校准。
第一方面，本申请实施例提供了一种设备同步校准方法，应用于控制器，包括：获取至少两台设备两两之间的时间戳同步偏差；
判断所述至少两台设备两两之间的时间戳同步偏差是否为设定值；
在任一时间戳同步偏差不为设定值的情况下，生成同步校准指令；
其中，所述同步校准指令用于对与所述任一时间戳同步偏差对应的两台设备进行同步校准。
第二方面，本申请实施例提供了一种设备同步校准方法，应用于设备，包括：获取采样信号；
对所述采样信号进行处理产生时间戳；
将所述时间戳发送至控制器。
第三方面，本申请实施例提供了一种设备同步校准装置，包括：
获取模块，设置为获取至少两台设备两两之间的时间戳同步偏差；
判断模块，设置为判断所述至少两台设备两两之间的时间戳同步偏差是否为设定值；
生成模块，设置为在任一时间戳同步偏差不为设定值的情况下，生成同步校准指令；
其中，所述同步校准指令用于对与所述任一时间戳同步偏差对应的两台设备进行同步校准。
第四方面，本申请实施例提供了一种设备同步校准装置，包括：
获取模块，设置为获取采样信号；
处理模块，设置为对所述采样信号进行处理产生时间戳；
传输模块，设置为将所述时间戳发送至控制器。
第五方面，本申请实施例提供了一种电子设备，包括：存储器、处理器及存储在存储器上并可在处理器上运行的计算机程序，所述处理器执行所述计算机程序时，实现如上述实施例提供的设备同步校准方法。
第六方面，本申请实施例提供了一种计算机存储介质，其上存储有计算机程序，当所述计算机程序被处理器执行时，实现如上述实施例提供的设备同步校准方法。
附图说明
图1为相关技术中多个设备并联的示意图；
图2为相关技术中多个设备串联的示意图；
图3为本申请实施例中的设备同步校准方法流程图；
图4为本申请实施例中的设备同步校准方法流程图；
图5为本申请实施例中的设备同步校准框架示意图；
图6为本申请实施例中的时间戳示意图；
图7为本申请实施例中的同步校准结果示意图；
图8为本申请实施例中的设备同步校准方法流程图；
图9为本申请实施例中的设备同步校准方法流程图；
图10为本申请实施例中的设备同步校准方法流程图；
图11为本申请实施例中的设备同步校准装置结构示意图；
图12为本申请实施例中的设备同步校准装置结构示意图；
图13为本申请实施例中的电子设备结构示意图。
具体实施方式
下面结合附图和实施例对本申请作进一步的详细说明。可以理解的是，此处所描述的具体实施例仅仅用于解释本申请，而非对本申请的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与本申请相关的部分而非全部结构。
图3为本申请实施例提供的一种设备同步校准方法的流程图，如图3所示，该方法可以应用于控制器中，该方法可以包括但不限于以下步骤：
S301、获取至少两台设备两两之间的时间戳同步偏差。
本步骤中两台设备之间的时间戳同步偏差可以理解为两台设备分别针对不同信号记录的时间戳的间隔之间的偏差，例如，设备a记录的两个信号的时间戳的间隔与设备b记录的相同两个信号的时间戳的间隔之间的偏差。当存在两台以上的设备时，可以对所有设备进行两两组合，确定每种组合中两台设备之间的时间戳同步偏差。
需要说明的是，上述控制器可以为独立的设备中的控制器，也可以为上述设备内部的控制器。
S302、判断至少两台设备两两之间的时间戳同步偏差是否为设定值。
示例性地，上述设定值可以为0，也可以为两台设备之间的固定偏差值。其中，在两台设备之间的时间戳同步偏差为设定值的情况下，表示两台设备的传 输通道保持同步。
例如，以设备a和设备b为例，在设定值为0的情况下，说明设备a记录的两个信号的时间戳的间隔与设备b记录的相同两个信号的时间戳的间隔之间的偏差为0，即这两台设备的传输通道同步。同样地，在设定值为固定偏差值，即设备a的传输通道与设备b的传输通道之间存在一定的偏差的情况下，若设备a记录的两个信号的时间戳的间隔与设备b记录的相同两个信号的时间戳的间隔之间的偏差仍为该固定偏差值，那么表示这两台设备之间的传输通道保持同步。
S303、在任一时间戳同步偏差不为设定值的情况下，生成同步校准指令。
本步骤中的任一时间戳同步偏差可以理解为与该同步偏差对应的两台设备之间的时间戳同步偏差。若任一时间戳同步偏差不为设定值，说明与该任一时间戳同步偏差对应的两台设备之间的数据传输通道不同步，此时，由控制器生成同步校准指令。该同步校准指令可以用于对与上述任一时间戳同步偏差对应的两台设备进行同步校准。
例如，该同步校准指令中可以携带有校准偏差，控制器可以通过该校准偏差对对应的两台设备进行同步校准。
本申请实施例提供了一种设备同步校准方法，该方法可以应用于控制器中，包括获取至少两台设备两两之间的时间戳同步偏差；判断至少两台设备两两之间的时间戳同步偏差是否为设定值；在任一时间戳同步偏差不为设定值的情况下，生成同步校准指令；其中，同步校准指令用于对与任一时间戳同步偏差对应的两台设备进行同步校准。这样，通过时间戳同步偏差，可以有效改善多台设备之间的同步有延迟的情况。
如图4所示，在一种实施例中，上述步骤S301的实现方式可以包括但不限于以下步骤：
S401、获取当前两台设备针对第一触发处理信号的第一时间戳间隔。
示例性地，如图5所示，本步骤中的第一触发处理信号可以为同步机输出同步信号至设备a和设备b，经由设备a和设备b的输入通道分别传输至对应设备的触发模块后产生的信号。
针对该第一触发处理信号的第一时间戳间隔的获取方式可以为，获取当前两台设备中任一设备针对第一触发处理信号记录的第一时间戳，获取当前两台设备中另一设备针对第一触发处理信号记录的第二时间戳，根据第一时间戳和第二时间戳获取当前两台设备针对第一触发处理信号的时间戳间隔。
例如，在设备a内部，输入通道传输的信号可以通过延时模块传输至数据处理模块，触发模块将第一触发处理信号传输至数据处理模块后，数据处理模块针对该第一触发处理信号对延时模块传输的信号进行处理，并记录当前的时间戳，即为第一时间戳。在设备b内部，触发模块将第一触发处理信号传输至数据处理模块后，数据处理模块执行相同的处理过程，并记录当前的时间戳为第二时间戳。这样，设备a和设备b分别针对第一触发处理信号记录的第一时间戳与第二时间戳之间的间隔即为第一时间戳间隔。
其中，同步信号的获取方式可以为，将一台设备内部的通道对齐，例如，将数据通道和触发通道对齐，利用通道对齐后的设备对同步机的输出进行校准，进而将校准后的同步机的输出端连接至至少两台设备，由同步机中的触发源向至少两台设备传输同步信号。如图5所示，该同步机的输出端连接两台设备，向这两台设备传输同步信号。
S402、获取当前两台设备针对第二触发处理信号的第二时间戳间隔。
同样地，按照上述步骤S401的实现方式，如图5所示，本步骤中的第二触发处理信号可以为同步机分别向设备a和设备b传输另一同步信号后，设备a和设备b中的触发模块基于该同步信号产生的信号。
针对该第二触发处理信号的第二时间戳间隔的获取方式可以为，获取当前两台设备中任一设备针对第二触发处理信号记录的第三时间戳，获取当前两台设备中另一设备针对第二触发处理信号记录的第四时间戳，根据第三时间戳和第四时间戳获取当前两台设备针对第二触发处理信号的时间戳间隔。
设备a内部的触发模块将第二触发处理信号传输至数据处理模块后，数据处理模块接收延时模块传输的输入通道传输的信号，并针对该第二触发处理信号对延时模块传输的信号进行处理，同时记录第一时间戳，设备b内部的触发模块将第二触发处理信号传输至数据处理模块后，数据处理模块针对该第二触发处理信号进行相同的处理，并记录第二时间戳，那么设备a和设备b分别记录的第一时间戳和第二时间戳之间的间隔即为第二时间戳间隔。
S403、根据第一时间戳间隔与第二时间戳间隔，确定当前两台设备之间的时间戳同步偏差。
将当前两台设备针对两个同步信号确定的第一时间戳间隔与第二时间戳间隔之间的差值的绝对值，作为时间戳同步偏差。
例如，假设当前两台设备为设备a和设备b，那么可以通过以下公式确定设备a与设备b之间的时间戳同步偏差Offset_ab，即为：
Offset_ab＝||(a.TS1-b.TS1)|-|(a.TS2-b.TS2)||   (1)
其中，a.TS1为设备a针对第一触发处理信号记录的时间戳，b.TS1为设备b针对第一触发处理信号记录的时间戳，a.TS2为设备a针对第二触发处理信号记录的时间戳，b.TS2为设备b针对第二触发处理信号记录的时间戳,|(a.TS1-b.TS1)|为设备a和设备b针对第一触发处理信号的第一时间戳间隔，|(a.TS2-b.TS2)|为设备a和设备b针对第二触发处理信号的第二时间戳间隔。
上述时间戳主要包含两部分信息，一部分是每台设备的工作时钟产生，以时钟周期为步进，从初始值(例如，为0)开始累积的计数值，另一部分是利用信号触发通过精细触发判断得到更准确的时间位置信息。即a.TS1、b.TS1、a.TS2、b.TS2均由粗调整和精细调整两部分组成，示例性地，该两部分可以如图6所示。
S404、在至少两台设备中选取与当前两台设备中至少一台不同的两台设备，并将选取的两台设备作为当前两台设备。
示例性地，假设存在4台设备，分别为设备a、设备b、设备c、设备d，若当前两台设备为设备a和设备b，那么在这四台设备中可以选取与设备a、设备b中至少一台不同的两台设备，例如，选取设备a与设备c，或者设备c与设备d等，将选取的两台设备作为当前两台设备。
S405、重复执行上述步骤S401至步骤S404，直至获取至少两台设备两两之间的时间戳同步偏差。
步骤S404中选取当前两台设备后，可以重复执行上述步骤S401至步骤S404，例如针对选取的设备a和设备c，确定两台设备之间的时间戳同步偏差后，可以重新选取与设备a、设备c不同的两台设备，并继续确定选取后的两台设备之间的时间戳同步偏差，直至获取至少两台设备中所有设备两两之间的时间戳同步偏差。在一种实施例中，在上述步骤S303之后，控制器还可以向与任一时间戳同步偏差对应的两台设备发送同步校准指令，和/或，向同步机发送同步校准指令。该同步校准指令可以包括前级校准指令，和/或，后级校准指令。
其中，前级校准指令用于指示与任一时间戳同步偏差对应的设备根据任一时间戳同步偏差调整自身的通道延时；或者，前级校准指令用于指示同步机根据任一时间戳同步偏差调整自身内部与任一时间戳同步偏差对应的通道的延时，同步机通过自身内部的至少两个通道分别与至少两台设备连接。也即，在时间 戳同步偏差不为设定值的情况下，该前级校准指令可以用于与该时间戳同步偏差对应的设备根据时间戳同步偏差调整自身的通道延时，或者，由同步机根据时间戳同步偏差对与对应设备连接的通道的延时进行调整。
后级校准指令用于指示控制器根据任一时间戳同步偏差对信号显示方式进行延时补偿。
通过同步校准指令对两台设备进行同步校准后的结果如图7所示，图7中的被测信号可以理解为同步机输入至连接点两台设备的信号，CLK.A和CLK.B分别为两台设备对被测信号采样的信号波形，SYNC.A和SYNC.B分别为两台设备同步后的信号波形。
图8为本申请实施例提供的一种设备同步校准方法的流程图，该方法可以应用于设备中，如图8所示，该方法可以包括以下步骤：
S801、获取采样信号。
该采样信号可以理解为与设备连接的同步机传输的信号。
S802、对采样信号进行处理产生时间戳。
示例性地，本申请实施例中，设备对获取的采样信号的处理方式可以包括粗调和微调两种方式。例如，对采样信号进行粗调整处理，并根据触发信号对粗调整后的采样信号进行微调整处理，基于微调整后的采样信号产生时间戳，
其中，上述过程中的触发信号是设备基于采样信号生成的。
S803、将时间戳发送至控制器。
该控制器可以为独立的设备中的控制器，或者，也可以为设备内部的控制器。设备产生时间戳之后，可以将该时间戳传输至控制器。
S804、接收控制器发送的同步校准指令，其中所述同步校准指令用于对设备进行同步校准。
本申请实施例提供一种设备同步校准方法，该方法包括获取采样信号，对采样信号进行处理产生时间戳，并将时间戳发送至控制器，接收控制器发送的同步校准指令，其中所述同步校准指令用于对设备进行同步校准。这样可以由控制器通过时间戳判断对应设备是否同步，在设备不同步的情况下，接收控制器发送的同步校准指令对设备进行校准，在从而有效改善多台设备之间的同步有延迟的情况。
在一种实施例中，该同步校准指令中可以携带有时间戳同步偏差，该时间戳同步偏差可以为控制器根据上述步骤S803中的时间戳计算得到的。
如图9所示，在上述步骤S804之后，该方法还可以包括但不限于以下步骤：
S901、根据时间戳同步偏差调整时间戳同步偏差对应的设备的通道延时。
在一种实施例中，该同步校准指令中携带有时间戳同步偏差，该时间戳同步偏差可以为控制器根据上述步骤S803中的时间戳计算得到的。如图10所示，在上述步骤S804之后，该方法还可以包括但不限于以下步骤：
S1001、将同步校准指令发送至同步机。
其中，所述同步校准指令用于指示同步机根据所述时间戳同步偏差调整所述同步机内部与所述时间戳同步偏差对应的通道的延时。该同步机可以通过自身内部的至少两个通道中的任意一个通道与设备连接，那么设备可以基于该通道将同步校准指令发送至同步机，由同步机根据该同步校准指令对与设备连接的通道进行校准。
图11为本申请实施例提供的一种设备同步校准装置，如图11所示，该装置可以包括：获取模块1101、判断模块1102、生成模块1103；
其中，获取模块，设置为获取至少两台设备两两之间的时间戳同步偏差；
判断模块，设置为判断至少两台设备两两之间的时间戳同步偏差是否为设定值；
生成模块，设置为在任一时间戳同步偏差不为设定值的情况下，生成同步校准指令；
其中，同步校准指令用于对与任一时间戳同步偏差对应的两台设备进行同步校准。
示例性地，上述获取模块，可以设置为实现以下步骤：
步骤一：获取当前两台设备针对第一触发处理信号的第一时间戳间隔；
步骤二：获取当前两台设备针对第二触发处理信号的第二时间戳间隔：
步骤三：根据第一时间戳间隔与第二时间戳间隔，确定当前两台设备之间的时间戳同步偏差；
步骤四：在至少两台设备中选取与当前两台设备中至少一台不同的两台设备，并将选取的两台设备作为当前两台设备；
重复执行上述步骤一至步骤四，直至获取至少两台设备中所有设备两两之间的时间戳同步偏差。
例如，获取模块，可以设置为获取当前两台设备中任一设备针对第一触发处理信号或第二触发处理信号记录的第一时间戳；获取当前两台设备中另一设 备针对第一触发处理信号或第二触发处理信号记录的第二时间戳；以及，根据第一时间戳和第二时间戳获取当前两台设备针对第一触发或第二触发处理信号的时间戳间隔。
例如，上述同步校准指令可以包括前级校准指令，和/或，后级校准指令；
其中，前级校准指令用于指示与任一时间戳同步偏差对应的设备根据任一时间戳同步偏差调整自身的通道延时；或者，前级校准指令用于指示同步机根据任一时间戳同步偏差调整自身内部与任一时间戳同步偏差对应的通道的延时，同步机通过自身内部的至少两个通道分别与至少两台设备连接；
后级校准指令用于指示控制器根据任一时间戳同步偏差对信号显示方式进行延时补偿。
在一种示例中，上述装置还可以包括传输模块；
该传输模块，设置为向与任一时间戳同步偏差对应的两台设备发送同步校准指令；和/或，向同步机发送同步校准指令。
上述设备同步校准装置可以执行图3、图4所提供的设备同步校准方法，具备该方法中相应的器件和有益效果。
图12为本申请实施例提供的一种设备同步校准装置，如图12所示，该装置可以包括：获取模块1201、处理模块1202、传输模块1203，以及校准模块1104；
其中，获取模块，设置为获取采样信号；
处理模块，设置为对采样信号进行处理产生时间戳；
传输模块，设置为将时间戳发送至控制器；接收所述控制器发送的同步校准指令，其中所述同步校准指令用于对设备进行同步校准。
在一种示例中，上述处理模块，设置为对采样信号进行粗调整处理；根据触发信号对粗调整后的采样信号进行微调整处理；以及，根据微调整后的采样信号产生时间戳；
其中，触发信号是上述装置基于采样信号生成的。
在一种示例中，该同步校准指令中携带有时间戳同步偏差；
处理模块，设置为根据时间戳同步偏差调整自身的通道延时。
在一种示例中，该同步校准指令中携带有时间戳同步偏差；上述传输模块，设置为将同步校准指令发送至同步机；
其中，所述同步校准指令用于指示同步机根据所述时间戳同步偏差调整所 述同步机内部与所述时间戳同步偏差对应的通道的延时。该同步机通过自身内部的至少两个通道中的任意一个通道与上述装置连接。
上述设备同步校准装置可以执行图7、图8所提供的设备同步校准方法，具备该方法中相应的器件和有益效果。
图13为本申请实施例13提供的一种电子设备的结构示意图，如图13所示，该设备包括控制器1301、存储器1302、输入装置1303、输出装置1304；设备中控制器1301的数量可以是一个或多个，图13中以一个控制器1301为例；设备中的控制器1301、存储器1302、输入装置1303和输出装置1304可以通过总线或其他方式连接，图13中以通过总线连接为例。
存储器1302作为一种计算机可读存储介质，可设置为存储软件程序、计算机可执行程序以及模块，如图3、图4、图8、图9、图10实施例中的设备同步校准方法对应的程序指令/模块(例如，图11、图12实施例中设备同步校准装置中的模块)。控制器1301通过运行存储在存储器1302中的软件程序、指令以及模块，从而执行设备的多种功能应用以及数据处理，即实现上述的设备同步校准方法。
存储器1302可主要包括存储程序区和存储数据区，其中，存储程序区可存储操作系统、至少一个功能所需的应用程序；存储数据区可存储根据终端的使用所创建的数据等。此外，存储器1302可以包括高速随机存取存储器，还可以包括非易失性存储器，例如至少一个磁盘存储器件、闪存器件、或其他非易失性固态存储器件。在一些实例中，存储器1302可包括相对于控制器1301远程设置的存储器，这些远程存储器可以通过网络连接至终端/服务器。上述网络的实例包括但不限于互联网、企业内部网、局域网、移动通信网及其组合。
输入装置1303可设置为接收输入的数字或字符信息，以及产生与设备的用户设置以及功能控制有关的键信号输入。输出装置1304可包括显示屏等显示装置。
本申请实施例还提供一种包含计算机可执行指令的存储介质，该计算机可执行指令在由计算机处理器执行时设置为执行一种设备同步校准方法，该方法包括图3、图4、图8、图9、图10实施例所示的步骤。
通过以上关于实施方式的描述，所属领域的技术人员可以清楚地了解到，本申请可借助软件及必需的通用硬件来实现，当然也可以通过硬件实现。基于这样的理解，本申请的技术方案本质上或者说对相关技术做出贡献的部分可以 以软件产品的形式体现出来，该计算机软件产品可以存储在计算机可读存储介质中，如计算机的软盘、只读存储器(Read-Only Memory,ROM)、随机存取存储器(Random Access Memory,RAM)、闪存(FLASH)、硬盘或光盘等，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请多个实施例所述的方法。存储介质可以是非暂态存储介质。
示例性的，本申请所示的方案可以应用于同步机，设备以及控制器之间。其中，同步机中包括触发源。假设存在4台设备，分别为设备a、设备b、设备c、设备d。选取设备a和设备b为当前两台设备，要对这两台设备进行同步校准。设备a和设备b分别获取采样信号，并对采样信号进行粗调整处理，得到粗调整处理后的采样信号；根据同步机中的触发源发送的触发信号对粗调整后的采样信号进行微调整处理，根据微调整后的采样信号产生时间戳，其中触发信号是设备a或设备b基于采样信号生成的。
例如，被测信号可以理解为同步机输入至设备a的信号，设备a对被测信号进行采样，形成采样信号CLK.A，在设备a的工作过程中，基于采样信号CLK.A，设备a还会产生触发信号。由于设备a本身的工作时钟会首先以时钟周期为步进，从初始值开始累积一个计数值，即对设备a的时间戳进行粗调整，记录粗调整时间戳。之后设备a会根据触发信号对粗调整之后的采样信号进行微调整处理，获得更准确的时间位置信息，即对设备a的时间戳进行精细调整，记录精细调整后的微调整时间戳，并最终根据粗调整时间戳和微调整时间戳的叠加结果，最终确定设备a的时间戳。
在确定设备a和设备b的时间戳同步偏差时，同步机中的触发源向设备a和设备b发送第一同步信号，设备a和设备b在对第一同步信号进行采样获得采样信号后，两台设备中的触发模块会分别生成一个第一触发处理信号。设备a基于采样信号获取粗调整时间戳，控制器基于第一触发处理信号获取微调整时间戳，最终确定设备a针对第一同步信号(或者第一触发处理信号)的第一时间戳；设备b基于采样信号获取粗调整时间戳，控制器基于第一触发处理信号获取微调整时间戳，最终确定设备b针对第一同步信号(或者第一触发处理信号)的第二时间戳。控制器记录设备a和设备b针对第一同步信号(或者针对第一触发处理信号)的第一时间戳与第二时间戳之间的间隔，将其确定为第一时间戳间隔。同样，同步机中的触发源向设备a和设备b发送第二同步信号，设备a和设备b对第二同步信号进行相同的处理，控制器可以得到设备a针对第 二同步信号(或者第二触发处理信号)的第三时间戳，设备b针对第二同步信号(或者第二触发处理信号)的第四时间戳。控制器记录设备a和设备b针对第二同步信号(或者针对第二触发处理信号)的第三时间戳与第四时间戳之间的间隔，将其确定为第二时间戳间隔。
控制器根据第一时间戳间隔和第二时间戳间隔确定设备a和设备b之间的时间戳同步偏差。判断设备a和设备b之间的时间戳同步偏差是否为设定值，在时间戳同步偏差不为设定值的情况下，控制器生成同步校准指令，用于设备a和设备b进行同步校准。

Claims (13)

  1. 一种设备同步校准方法，应用于控制器，包括：
    获取至少两台设备中每两台设备之间的时间戳同步偏差；
    判断所述每两台设备之间的时间戳同步偏差是否为设定值；
    基于任一时间戳同步偏差不为设定值的判断结果，生成同步校准指令；
    其中，所述同步校准指令用于对与所述任一时间戳同步偏差对应的两台设备进行同步校准。
  2. 根据权利要求1所述的方法，其中，所述获取至少两台设备中每两台设备之间的时间戳同步偏差，包括：
    获取当前两台设备针对第一触发处理信号的第一时间戳间隔；
    获取所述当前两台设备针对第二触发处理信号的第二时间戳间隔；
    根据所述第一时间戳间隔与所述第二时间戳间隔，确定所述当前两台设备之间的时间戳同步偏差；
    在所述至少两台设备中选取与当前两台设备中至少一台不同的两台设备，并将选取的两台设备作为当前两台设备；
    返回执行所述获取当前两台设备针对第一触发处理信号的第一时间戳间隔；获取所述当前两台设备针对第二触发处理信号的第二时间戳间隔；根据所述第一时间戳间隔与所述第二时间戳间隔，确定所述当前两台设备之间的时间戳同步偏差；在所述至少两台设备中选取与当前两台设备中至少一台不同的两台设备，并将选取的两台设备作为当前两台设备的步骤，直至获取所述至少两台设备中每两台设备之间的时间戳同步偏差。
  3. 根据权利要求2所述方法，其中，所述获取当前两台设备针对第一触发处理信号的第一时间戳间隔，包括：
    获取所述当前两台设备中任一设备针对第一触发处理信号记录的第一时间戳；
    获取所述当前两台设备中另一设备针对所述第一触发处理信号记录的第二时间戳；
    根据所述第一时间戳和所述第二时间戳获取所述当前两台设备针对所述第一触发处理信号的第一时间戳间隔；
    所述获取所述当前两台设备针对第二触发处理信号的第二时间戳间隔，包括：
    获取所述当前两台设备中任一设备针对第二触发处理信号记录的第三时间戳；
    获取所述当前两台设备中另一设备针对所述第二触发处理信号记录的第四时间戳；
    根据所述第三时间戳和第四时间戳获取所述当前两台设备针对所述第二触发处理信号的第二时间戳间隔。
  4. 根据权利要求1所述的方法，其中，所述同步校准指令包括前级校准指令，和后级校准指令中的至少一种；
    所述前级校准指令用于指示与所述任一时间戳同步偏差对应的设备根据所述任一时间戳同步偏差调整自身的通道延时；
    或者，所述前级校准指令用于指示同步机根据所述任一时间戳同步偏差调整自身内部与所述任一时间戳同步偏差对应的通道的延时，所述同步机通过自身内部的至少两个通道分别与所述至少两台设备连接；
    所述后级校准指令用于指示所述控制器根据所述任一时间戳同步偏差对信号显示方式进行延时补偿。
  5. 根据权利要求1或4所述的方法，在所述同步校准指令包括前级校准指令的情况下，在生成同步校准指令之后，所述方法还包括以下至少之一：
    向与所述任一时间戳同步偏差对应的两台设备发送所述同步校准指令；和向同步机发送所述同步校准指令。
  6. 一种设备同步校准方法，应用于设备，包括：
    获取采样信号；
    对所述采样信号进行处理产生时间戳；
    将所述时间戳发送至控制器；
    接收所述控制器发送的同步校准指令，其中所述同步校准指令用于对设备进行同步校准。
  7. 根据权利要求6所述的方法，其中，对所述采样信号进行处理产生时间戳，包括：
    对所述采样信号进行粗调整处理；
    根据触发信号对粗调整后的采样信号进行微调整处理；
    根据微调整后的采样信号产生时间戳；
    其中，所述触发信号是所述设备基于所述采样信号生成的。
  8. 根据权利要求6或7所述的方法，其中，所述同步校准指令中携带有时间戳同步偏差，所述方法还包括：
    根据所述时间戳同步偏差调整所述时间戳同步偏差对应的设备的通道延时。
  9. 根据权利要求6或7所述的方法，其中，所述同步校准指令中携带有时间戳同步偏差，所述方法还包括：
    将所述同步校准指令发送至同步机，其中，所述同步校准指令用于指示所述同步机根据所述时间戳同步偏差调整所述同步机内部与所述时间戳同步偏差对应的通道的延时，所述同步机通过自身内部的至少两个通道中的任意一个通道与所述设备连接。
  10. 一种设备同步校准装置，包括：
    获取模块，设置为获取至少两台设备中每两台设备之间的时间戳同步偏差；
    判断模块，设置为判断所述每两台设备之间的时间戳同步偏差是否为设定值；
    生成模块，设置为基于任一时间戳同步偏差不为设定值的判断结果，生成同步校准指令；
    其中，所述同步校准指令用于对与所述任一时间戳同步偏差对应的两台设备进行同步校准。
  11. 一种设备同步校准装置，包括：
    获取模块，设置为获取采样信号；
    处理模块，设置为对所述采样信号进行处理产生时间戳；
    传输模块，设置为将所述时间戳发送至控制器；接收所述控制器发送的同步校准指令，其中所述同步校准指令用于对设备进行同步校准。
  12. 一种电子设备，包括：存储器、处理器及存储在存储器上并可在处理器上运行的计算机程序，所述处理器执行所述计算机程序时，实现如权利要求1-5任一项所述的设备同步校准方法，或者，权利要求6-9任一项所述的设备同步校准方法。
  13. 一种计算机存储介质，存储有计算机程序，所述计算机程序被处理器执行时，实现如权利要求1-5任一项所述的设备同步校准方法，或者，权利要求6-9任一项所述的设备同步校准方法。
PCT/CN2021/118635 2020-09-17 2021-09-16 设备同步校准方法、装置、设备及存储介质 WO2022057844A1 (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1020237012479A KR20230066106A (ko) 2020-09-17 2021-09-16 설비 동기화 교정 방법, 장치, 설비 및 저장 매체
JP2023517788A JP2023541963A (ja) 2020-09-17 2021-09-16 機器同期校正方法、装置、機器及び記憶媒体
US18/026,672 US20230341892A1 (en) 2020-09-17 2021-09-16 Device synchronous calibration method and apparatus, devices, and storage medium
EP21868666.5A EP4216019A1 (en) 2020-09-17 2021-09-16 Device synchronous calibration method and apparatus, devices, and storage medium

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010980816.0 2020-09-17
CN202010980816.0A CN112214065B (zh) 2020-09-17 2020-09-17 设备同步校准方法、装置、设备及存储介质

Publications (1)

Publication Number Publication Date
WO2022057844A1 true WO2022057844A1 (zh) 2022-03-24

Family

ID=74050428

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/118635 WO2022057844A1 (zh) 2020-09-17 2021-09-16 设备同步校准方法、装置、设备及存储介质

Country Status (6)

Country Link
US (1) US20230341892A1 (zh)
EP (1) EP4216019A1 (zh)
JP (1) JP2023541963A (zh)
KR (1) KR20230066106A (zh)
CN (1) CN112214065B (zh)
WO (1) WO2022057844A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115932351A (zh) * 2023-03-09 2023-04-07 深圳市鼎阳科技股份有限公司 一种示波器级联的延时校正方法、示波器、终端及介质

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112214065B (zh) * 2020-09-17 2022-10-21 北京普源精电科技有限公司 设备同步校准方法、装置、设备及存储介质
CN113390452B (zh) * 2021-06-16 2023-08-18 北京康斯特仪表科技股份有限公司 一种开关型仪表校准方法及装置
CN113726466B (zh) * 2021-07-21 2023-12-01 歌尔股份有限公司 一种可穿戴设备及其信号采集方法
CN114006674B (zh) * 2021-12-31 2022-04-01 深圳市海清视讯科技有限公司 出勤设备的校时方法、装置、设备及存储介质
TWI835438B (zh) * 2022-11-29 2024-03-11 瑞昱半導體股份有限公司 媒體通訊系統及其具有訊號同步機制的媒體通訊裝置及方法
CN116887077B (zh) * 2023-09-07 2023-11-24 南通市计量检定测试所 一种大型设备多仪器同步采集数据分析处理方法
CN117713983B (zh) * 2024-02-05 2024-05-07 浙江华创视讯科技有限公司 时钟同步监测方法、装置、级联系统和计算机设备

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101515831A (zh) * 2008-02-22 2009-08-26 杭州华三通信技术有限公司 一种时间同步传递方法、系统及装置
CN109547146A (zh) * 2019-01-14 2019-03-29 北京邮电大学 一种基于超宽带无线通信的无线时钟同步方法及装置
US10411793B1 (en) * 2018-06-20 2019-09-10 Goodrich Corporation Data transport and time synchronization for ISR systems
CN111102689A (zh) * 2019-12-11 2020-05-05 珠海格力电器股份有限公司 时钟同步的调整方法及装置
CN112214065A (zh) * 2020-09-17 2021-01-12 北京普源精电科技有限公司 设备同步校准方法、装置、设备及存储介质

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9306693B2 (en) * 2013-11-15 2016-04-05 Broadcom Corporation Time synchronization architecture in a network device
CN105099647A (zh) * 2014-05-16 2015-11-25 中兴通讯股份有限公司 一种同步方法、控制器、同步节点及同步网络
CN104836654B (zh) * 2015-04-15 2018-06-22 浙江大学 一种基于Ethernet POWERLINK的时钟同步方法
CN109842603A (zh) * 2017-11-29 2019-06-04 北京通号国铁城市轨道技术有限公司 一种时间同步方法及装置
CN108923876B (zh) * 2018-06-27 2020-11-27 北京旷视机器人技术有限公司 时间同步方法、装置及系统
CN111008239B (zh) * 2018-10-07 2023-03-24 上海希路智能科技有限公司 一种异步系统的数据同步方法、系统及终端设备
CN109327899A (zh) * 2018-10-11 2019-02-12 恒大法拉第未来智能汽车（广东）有限公司 一种车载设备同步时间的方法、装置和同步时间系统
CN109194436B (zh) * 2018-11-01 2020-08-07 百度在线网络技术（北京）有限公司 传感器时间戳同步测试方法、装置、设备、介质及车辆
CN109379160A (zh) * 2018-12-30 2019-02-22 广东大普通信技术有限公司 一种时钟校准服务器及方法
CN109818702A (zh) * 2019-03-04 2019-05-28 西安电子科技大学 一种ieee802.1as时钟同步功能实现系统以及实现方法
CN110719135A (zh) * 2019-10-17 2020-01-21 Ut斯达康通讯有限公司 时间校准方法、系统及电子装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101515831A (zh) * 2008-02-22 2009-08-26 杭州华三通信技术有限公司 一种时间同步传递方法、系统及装置
US10411793B1 (en) * 2018-06-20 2019-09-10 Goodrich Corporation Data transport and time synchronization for ISR systems
CN109547146A (zh) * 2019-01-14 2019-03-29 北京邮电大学 一种基于超宽带无线通信的无线时钟同步方法及装置
CN111102689A (zh) * 2019-12-11 2020-05-05 珠海格力电器股份有限公司 时钟同步的调整方法及装置
CN112214065A (zh) * 2020-09-17 2021-01-12 北京普源精电科技有限公司 设备同步校准方法、装置、设备及存储介质

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115932351A (zh) * 2023-03-09 2023-04-07 深圳市鼎阳科技股份有限公司 一种示波器级联的延时校正方法、示波器、终端及介质

Also Published As

Publication number Publication date
CN112214065A (zh) 2021-01-12
CN112214065B (zh) 2022-10-21
JP2023541963A (ja) 2023-10-04
KR20230066106A (ko) 2023-05-12
EP4216019A1 (en) 2023-07-26
US20230341892A1 (en) 2023-10-26

Similar Documents

Publication Publication Date Title
WO2022057844A1 (zh) 设备同步校准方法、装置、设备及存储介质
US20220182164A1 (en) Method of remotely monitoring the timing performance of a ptp slave
US10868664B2 (en) Minimizing timestamp error in PTP systems
EP3002593B1 (en) Multi-scope control and synchronization system
JP2007212453A (ja) トリガ分配装置
WO2017219881A1 (zh) 一种基于1588的时间同步方法及装置
US20120191418A1 (en) Structure and method of data synchronization for muti measuring apparatus
WO2018040856A1 (zh) 多屏显示装置的视频处理单元输出同步性检测方法和系统
US20110016232A1 (en) Time stamping apparatus and method for network timing synchronization
TWI726448B (zh) 利用對準標記實現時間戳記的奈秒精度及其形成方法
CN117054715A (zh) 一种多台数字示波器的采样同步方法
CN113711057A (zh) 用于同步多个测试和测量仪器的系统和方法
KR101449615B1 (ko) 복수의 측정 채널 어셈블리 및/또는 측정 장치의 동기화 방법, 및 적합한 측정 장치
JP2018125768A (ja) データ伝送装置及びプログラム
CN114326925A (zh) 一种信号同步输出方法、装置、设备及介质
TWI400596B (zh) 同步接收電路及方法
CN104901844A (zh) 基于pcie的高精度时间戳获取方法、装置及网卡
US20240171295A1 (en) Communication apparatus, control method for communication apparatus, and storage medium
US20230275679A1 (en) Method and apparatus for synchronizing signals of signal measuring devices
CN117784580B (zh) 提升ptp点对点授时精度的方法和授时装置
WO2022160283A1 (zh) 一种采样方法、采样电路及分布式网络的时钟同步方法
CN112019288B (zh) 时间同步方法、业务单板及网络设备
CN117784580A (zh) 提升ptp点对点授时精度的方法和授时装置
US9673971B2 (en) Automatic clock calibration of a remote unit using phase drift
JP2021158608A (ja) 計測システム、及びその制御方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21868666

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2023517788

Country of ref document: JP

Kind code of ref document: A

ENP Entry into the national phase

Ref document number: 20237012479

Country of ref document: KR

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 2021868666

Country of ref document: EP

Effective date: 20230417