WO2022160283A1 - 一种采样方法、采样电路及分布式网络的时钟同步方法 - Google Patents

一种采样方法、采样电路及分布式网络的时钟同步方法 Download PDF

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WO2022160283A1
WO2022160283A1 PCT/CN2021/074484 CN2021074484W WO2022160283A1 WO 2022160283 A1 WO2022160283 A1 WO 2022160283A1 CN 2021074484 W CN2021074484 W CN 2021074484W WO 2022160283 A1 WO2022160283 A1 WO 2022160283A1
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sampling
signal
value
clock signal
clock
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PCT/CN2021/074484
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English (en)
French (fr)
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陈振华
陈井凤
吴松林
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华为技术有限公司
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Priority to CN202180088633.0A priority Critical patent/CN116671193B/zh
Priority to PCT/CN2021/074484 priority patent/WO2022160283A1/zh
Publication of WO2022160283A1 publication Critical patent/WO2022160283A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W56/00—Synchronisation arrangements

Definitions

  • the present application relates to the technical field of distributed networks, and in particular, to a sampling method, a sampling circuit and a clock synchronization method for a distributed network.
  • each node of the distributed network is provided with a clock module and a processing module, wherein the processing module is used to process the relevant protocols of IEEE 1588 messages, collect relevant time stamps, and send the time stamps to the clock module.
  • the module is used to calculate the clock information based on the timestamp, and then adjust the local real-time clock to achieve clock synchronization.
  • the clock module periodically sends time stamp information and pulse per second (PPS) information to the processing module, so that the real-time clock of the processing module is synchronized with the clock module.
  • PPS pulse per second
  • the IEEE 1588 synchronization system requires very high precision, and the required precision is nanoseconds at present.
  • the sampling accuracy of the PPS information is an important factor affecting the accuracy of the entire IEEE 1588 synchronization system.
  • the sampling accuracy of PPS information completely depends on the clock frequency of the sampling clock, that is to say, the sampling accuracy of PPS information can only be improved by increasing the clock frequency of the sampling clock.
  • the sampling accuracy of the clock frequency of 1 GHz is required
  • the clock can make the sampling accuracy of PPS information reach 1ns.
  • the clock frequency of the sampling clock cannot be increased infinitely, which makes it difficult to improve the sampling accuracy of the PPS information.
  • the present application provides a sampling method, a sampling circuit and a clock synchronization method for a distributed network, so as to improve sampling accuracy.
  • the present application provides a sampling method, comprising: receiving timestamp information and pulse-per-second information; sampling the pulse-per-second information by using a first clock signal and a second clock signal to obtain the first sampling signal and the second pulse, respectively sampling signal; wherein, the period of the first clock signal and the second clock signal are the same, and the phase difference between the first clock signal and the second clock signal is 180°; taking the first transition edge of the first sampling signal as the sampling point, Determine the first sampling value of the first sampling signal at the sampling point, and determine the second sampling value of the second sampling signal at the sampling point of the first sampling signal; the first transition edge is the transition from the first value to the first The transition edge of the binary value; compare the similarities and differences between the first sampling value and the second sampling value, if the first sampling value is the same as the second sampling value, after adjusting the timestamp information, the clock is performed based on the adjusted timestamp information. Synchronization; if the first sample value and the second sample value are different, perform clock synchronization
  • the first clock signal and the second clock signal are used to sample the second pulse information, and the first sampling signal and the second sampling signal are obtained respectively; wherein, the difference between the first clock signal and the second clock signal is The period is the same, and the phase difference between the first clock signal and the second clock signal is 180°. According to the obtained first sampling signal and the second sampling signal, the position of the transition edge of the second pulse information can be determined, and the position of the second pulse information can be determined.
  • the transition edge differs from the sampling point by 0 to 0.5 cycles of the first clock signal, or differs from the first clock signal by 0.5 to 1 cycle, that is, sampling the sampling method in the embodiment of the present application, which can not only determine the transition of the pulse-per-second information In which cycle of the first clock signal the transition edge is located, it can be further determined whether the transition edge of the second pulse information P is located in the first half cycle or the second half cycle of the cycle, and the sampling accuracy can be reduced to 0.5 clock cycles. , which doubles the sampling accuracy.
  • using the first clock signal and the second clock signal to sample the second pulse information to obtain the first sampling signal and the second sampling signal respectively including: A sampling value of the second pulse information at a transition edge to obtain a first sampling signal; determining the sampling value of the second pulse information at each first transition edge of the second clock signal to obtain a second sampling signal.
  • the above sampling method provided by the embodiment of the present application may further include: sampling the detection signal N times by using the first clock signal and the second clock signal to obtain N groups of sampling results; each group of sampling results includes the first sampling signal and the second sampling signal; wherein, the detection signal is a random signal uniformly distributed in the time domain; for each group of sampling results, perform: taking the first transition edge of the first sampling signal as the sampling point, determine that the first sampling signal is sampling The first sampling value at the point, and the second sampling value when the second sampling signal is determined at the sampling point of the first sampling signal; the N groups of sampling results include: n1 groups of first sampling results and n2 groups of second sampling results; wherein , the first sampling value in the first sampling result is the same as the second sampling value; the first sampling value in the second sampling result is different from the second sampling value; according to
  • the detection signal is a random signal with uniform distribution in the time domain
  • the number of first sampling results is n1 It is basically the same as the number n2 of the second sampling results. If the phase of the first clock signal and the second clock signal drifts, the total number of sampling results N, the number n1 of the first sampling results and the second sampling results n2 can be used to determine It reflects the phase shift between the first clock signal and the second clock signal. Then, the phases of the first clock signal and the second clock signal are adjusted according to the phase shift amount, so that the phase difference between the first sampling signal and the second sampling signal is maintained at 180°.
  • phase shift amount S of the first clock signal and the second clock signal can be determined according to the following formula:
  • the clock frequency of the first clock signal may be 1 GHz;
  • the detection signal may be a signal obtained by dividing a clock signal by two with a clock frequency of 999 MHz, that is, the detection signal may be a pseudo-random signal. Using the signal after frequency division by two as the detection signal can make the period of the detection signal larger, and ensure that the high phase and the low phase of the detection signal can be sampled.
  • the present application also provides a clock synchronization method for a distributed network, wherein each node of the distributed network includes a clock module and a processing module.
  • the above clock synchronization method may include: the clock module sends the timestamp information and the pulse-per-second information to the processing module; the processing module executes any of the above sampling methods to sample the pulse-per-second information; wherein, if the first sample obtained by the processing module sampling If the value is the same as the second sampling value, the processing module adds 1 clock cycle to the data of the timestamp information and updates it to the internal real-time clock; if the first sampling value obtained by the processing module is different from the second sampling value, the processing module will process The module directly updates the data of the timestamp information to the internal real-time clock.
  • the processing module uses the above sampling method to sample the pulse-per-second information. Since the sampling accuracy of the above sampling method is high, the pulse-per-second information collected by the processing module is more accurate, and further, the time synchronization of the processing module is achieved. more precise.
  • the present application also provides a sampling circuit, which may include: a first sampling module, a second sampling module, a first sampling value extraction module, and a second sampling value extraction module; wherein the first sampling module is used for Receive the first clock signal and the pulse-per-second information, use the first clock signal to sample the pulse-per-second information, and output the first sampling signal; the second sampling module is used for receiving the second clock signal and the pulse-per-second information, using the second clock signal Sampling the second pulse information, and outputting a second sampling signal; a first sampling value extraction module, electrically connected to the first sampling module, for determining the first sampling value of the first sampling signal at the sampling point, and outputting the first sampling value
  • the sampling point is the first jumping edge of the first sampling signal, and the first jumping edge is the jumping edge that jumps from the first numerical value to the second numerical value; the second sampling value extraction module is electrically connected with the second sampling module , for determining the second sampling value of the second sampling signal at the sampling point of the first sampling signal, and
  • the first sampling module and the second sampling module are used to sample the second pulse information respectively, and the first sampling signal and the second sampling signal can be obtained, and the first sampling value extraction module can obtain the first sampling signal.
  • the first sampling value of the sampling signal at the sampling point, the second sampling value of the first sampling signal at the sampling point can be obtained through the second sampling value extraction module, and subsequently, according to the first sampling value and the second sampling value, to It is determined whether the transition edge of the second pulse information differs from the sampling point by 0 to 0.5 cycles of the first clock signal or by 0.5 to 1 cycle of the first clock signal, which improves the sampling accuracy.
  • the sampling circuit in this embodiment of the present application may further include: a detection signal generation module and a counting module; wherein, The detection signal generation module is electrically connected with the first sampling module and the second sampling module, and is used for generating detection signals; the counting module is electrically connected with the first sampling value extraction module and the second sampling value extraction module, and is used for counting the total sampling results.
  • the counting module counts the total number N of sampling results, the number n1 of the first sampling results, and the number n2 of the second sampling results, so as to determine the phase drift between the first clock signal and the second clock signal Furthermore, the phases of the first clock signal and the second clock signal can be adjusted according to the phase shift amount, so that the phase difference between the first sampling signal and the second sampling signal is maintained at 180°.
  • the above counting module may include: a first counter, a second counter, and a third counter; wherein, the first counter is electrically connected to the first sampling value extraction module, and is used to count the total sampling results. the number N; the second counter is electrically connected with the first sampling value extraction module and the second sampling value extraction module, and is used to count the number of the first sampling results; the third counter is connected with the first sampling value extraction module and the second sampling value extraction module The electrical connection is used to count the number of the second sampling results.
  • the above-mentioned sampling circuit provided in the embodiment of the present application may further include: an enabling switch electrically connected to the counting module.
  • the enable switch is used to receive the enable control signal.
  • the method of calculating the average value by multiple counts may be used to reduce the influence of errors on the adjustment result.
  • FIG. 1 is a flowchart of a sampling method provided by an embodiment of the present application.
  • FIG. 2 is a sequence diagram corresponding to the sampling method provided by the implementation of the present application.
  • FIG. 3 is another sequence diagram of the sampling method provided by the embodiment of the present application.
  • FIG. 5 is a timing diagram of a first clock signal and a detection signal
  • FIG. 6 is a schematic structural diagram of a node in a distributed network in an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a sampling circuit provided by an embodiment of the present application.
  • FIG. 8 is another schematic structural diagram of a sampling circuit provided by an embodiment of the present application.
  • P-second pulse information clk1-first clock signal; clk2-second clock signal; Q1-first sampling signal; Q2-second sampling signal; A-sampling point; 201-clock module; 202-processing module; U1 - the first interface; U2 - the second interface; U3 - the third interface; 31 - the first sampling module; 311 - the first register; 32 - the second sampling module; 321 - the second register; 33 - the first sampling value extraction module; 331-third register; 332-first NOT gate device; 333-first AND gate device; 34-second sampling value extraction module; 341-fourth register; 35-detection signal generation module; 351-fifth Register; 352-second NOT gate device; 36-counting module; 361-first counter; 362-second counter; 363-third counter; 364-second AND gate device; 365-third AND gate device; 366 -The third NOT gate device; 37-Enable switch.
  • the sampling method provided in the embodiment of the present application can be applied to an IEEE 1588 synchronization system, so as to improve the sampling accuracy of the PPS information in the IEEE 1588 synchronization system, thereby improving the accuracy of the IEEE 1588 synchronization system.
  • the sampling method provided in the embodiment of the present application can also be applied to other scenarios, and the sampling method in the present application can also sample other signals, and the application scenarios of the sampling method provided in the embodiment of the present application are not limited here.
  • FIG. 1 is a flowchart of a sampling method provided by an embodiment of the present application
  • FIG. 2 is a sequence diagram corresponding to the sampling method provided by the implementation of the present application.
  • the sampling method in the embodiment of the present application may include:
  • the phase difference between the first clock signal clk1 and the second clock signal clk2 is approximately 180°.
  • the first clock signal clk1 and the second clock signal clk2 need to be synchronized to ensure high sampling accuracy.
  • the clock frequency of the first clock signal clk1 may be 1 GHz or 500 MHz.
  • the clock frequency of the first clock signal clk1 may also be other values, which is not limited here.
  • the sampling point A all refers to the first transition edge of the first sampling signal Q1, wherein the first transition edge is the transition from the first value to the second value Edge
  • the first transition edge can be a rising edge, that is, a transition edge from a low level (0) to a high level (1)
  • the first transition edge can also be a falling edge, that is The transition edge from a high level (1) to a low level (0) is described in this application by taking the first transition edge as a rising edge as an example for the convenience of description.
  • each node may include a clock module and a processing module, and the above steps S101 to S104 may be performed in the processing module, that is, the clock module periodically sends time stamp information and second pulse information to the processing module , the processing module triggers the processing module to execute the above steps S101 to S104 when receiving the timestamp information and the second pulse information.
  • the first clock signal and the second clock signal are used to sample the second pulse information, and the first sampling signal and the second sampling signal are obtained respectively; wherein, the difference between the first clock signal and the second clock signal is The period is the same, and the phase difference between the first clock signal and the second clock signal is 180°. According to the obtained first sampling signal and the second sampling signal, the position of the transition edge of the second pulse information can be determined, and the position of the second pulse information can be determined.
  • the transition edge differs from the sampling point by 0 to 0.5 cycles of the first clock signal, or differs from the first clock signal by 0.5 to 1 cycle, that is, sampling the sampling method in the embodiment of the present application, which can not only determine the transition of the pulse-per-second information In which cycle of the first clock signal the transition edge is located, it can be further determined whether the transition edge of the second pulse information P is located in the first half cycle or the second half cycle of the cycle.
  • a clock signal is used to sample the second pulse information, which can only determine which cycle the transition edge of the second pulse information is located in, and the sampling accuracy is one clock cycle. Therefore, compared with using a clock signal to sample the second pulse information For sampling, the dual-phase sampling method is adopted in this embodiment of the present application, which can reduce the sampling accuracy to 0.5 clock cycles and increase the sampling accuracy to twice the original.
  • the first sampled value is the same as the second sampled value
  • clock synchronization is performed based on the adjusted time stamp information; if the first sample value and the second sample value are different, the time stamp Information is clocked. Since the transition edge of the second pulse information can be more accurately determined in the embodiment of the present application, furthermore, the clock synchronization can be made more accurate.
  • the foregoing step S102 may include:
  • the sampling values of the second pulse information P are: 0, 1, 1, and 1, respectively, and the time sequence of the first sampling signal Q1 can be obtained according to the determined sampling values.
  • the second The sampling values of the pulse information P are respectively: 0, 1, and 1, and the timing sequence of the second sampling signal Q2 can be obtained according to the determined sampling values.
  • the transition edge of the second pulse information P differs from the sampling point A by 0 to 0.5 cycles of the first clock signal, that is, the transition edge of the second pulse information P is located in the area T2 in the figure.
  • the first sampling value of a sampled signal Q1 at sampling point A is 1, and the second sampling value of the second sampling signal Q2 at sampling point A is 0, that is, the first sampling value is different from the second sampling value.
  • FIG. 3 is another timing diagram of the sampling method provided by the embodiment of the present application. As shown in FIG. 3 , the transition edge of the second pulse information P differs from the sampling point A by 0.5 to 1 period of the first clock signal clk1, that is, seconds The transition edge of the pulse information P is located in the area T1 in the figure.
  • the first sampling value of the first sampling signal Q1 at the sampling point A is 1, and the second sampling value of the second sampling signal Q2 at the sampling point A is 1, that is, the first sample value is the same as the second sample value. Therefore, in the above step S104, by comparing the magnitudes of the first sampling value and the second sampling value, it is possible to determine whether the transition edge of the second pulse information P differs from the sampling point by 0 to 0.5 cycles of the first clock signal clk1, or whether The difference is 0.5 ⁇ 1 period of the first clock signal clk1 .
  • the sampling method in the embodiment of the present application can not only determine which cycle of the first clock signal clk1 the transition edge of the second pulse information P is located in, but also can further determine that the transition edge of the second pulse information P is located in this cycle In the first half cycle or the second half cycle, the sampling accuracy is improved.
  • the first sampling value is 1.
  • the second sampling value can be determined by judging The specific value of the value is used to determine the similarities and differences between the first sampling value and the second sampling value. For example, when the second sampling value is 1, it can be determined that the first sampling value is the same as the second sampling value, and when the second sampling value is 0, It may be determined that the first sample value is different from the second sample value.
  • other methods may also be used to compare the similarities and differences between the first sampling value and the second sampling value, which are not limited here.
  • FIG 4 is a timing diagram after the phase of the first clock signal and the second clock signal drifts.
  • the phase of the first clock signal clk1 and the second clock signal clk2 drifts, so that the size difference between the area T1 and the area T2 is large, the area T1 becomes smaller, and the area T2 becomes larger, that is, the determined jump of the second pulse information.
  • the difference between the changing edge and the sampling point is no longer 0 to 0.5 cycles of the first clock signal, or 0.5 to 1 cycle of the first clock signal, thereby affecting the sampling accuracy of the second pulse information.
  • the above sampling method may further include:
  • the detection signal is sampled N times by the first clock signal and the second clock signal to obtain N groups of sampling results; each group of sampling results includes the first sampling signal and the second sampling signal; wherein the detection signal is uniformly distributed in the time domain random signal;
  • Perform for each group of sampling results take the first transition edge of the first sampling signal as the sampling point, determine the first sampling value of the first sampling signal at the sampling point, and determine the second sampling signal at the sampling point of the first sampling signal. The second sampling value at the sampling point;
  • the N groups of sampling results include: n1 groups of first sampling results and n2 groups of second sampling results; wherein, the first sampling values in the first sampling results are the same as the second sampling values; the first sampling values in the second sampling results are the same as The second sampling values are different; according to the total number N of sampling results, the number n1 of the first sampling results, and the number n2 of the second sampling results, determine the phase shift amount of the first clock signal and the second clock signal, and according to the phase shift amount The phases of the first clock signal and the second clock signal are adjusted.
  • the above steps S102 to S104 are performed N times with the detection signal as the second pulse information. Since the detection signal is a random signal uniformly distributed in the time domain, after sampling the detection signal N times, if the first clock signal and the second The phase of the clock signal does not drift, then in the N groups of sampling results, the number n1 of the first sampling results and the number n2 of the second sampling results are basically the same.
  • the total amount of sampling results N, the number of first sampling results n1 and the second sampling results n2 are used to reflect the phase shift amount of the first clock signal and the second clock signal.
  • the phases of the first clock signal and the second clock signal are adjusted according to the amount of phase drift, so that the phase difference between the first sampling signal and the second sampling signal is maintained at 180°.
  • the phase of the clock signal is adjusted accordingly, or the second clock signal may also be adjusted, or both are adjusted simultaneously, which is not limited here.
  • the phase shift amount S of the first clock signal and the second clock signal may be determined according to the following formula:
  • the total number N of sampling results is 1000, wherein the number n1 of the first sampling results is 600, and the number n2 of the second sampling results is 400.
  • the clock frequency of the first clock signal may be 1 GHz;
  • the detection signal may be a signal obtained by dividing the clock signal by two with a clock frequency of 999 MHz, that is, the detection signal
  • the signal may be a pseudo-random signal. Using the signal after frequency division by two as the detection signal can make the period of the detection signal larger, and ensure that the high phase and the low phase of the detection signal can be sampled.
  • FIG. 5 is a timing diagram of the first clock signal and the detection signal. As shown in FIG. 5, the period of the first clock signal is 1 ns.
  • the first clock signal clk1 and the detection signal The edges of the signal P1 are aligned.
  • the difference between the first clock signal clk1 and the edge of the detection signal P1 is 1/999ns
  • the third rising edge of the first clock signal clk1 The edge difference between the first clock signal clk1 and the detection signal P1 is 2/999ns.
  • the difference between the first clock signal clk1 and the edge of the detection signal P1 is i/999ns.
  • the detection signal P1 has a granularity of 1/999ns and is evenly distributed in one cycle of the first clock signal clk1. Therefore, the detection signal P1 is sampled N times according to the total number of sampling results N and the number of first sampling results.
  • the n1 and the second sampling result n2 are used to reflect the phase shift of the first clock signal and the second clock signal.
  • FIG. 6 is a schematic structural diagram of a node in a distributed network in an embodiment of the present application. As shown in FIG. 6 , the distributed network Each node includes a clock module 201 and a processing module 202, and both the clock module 201 and the processing module 202 are provided with a real-time clock inside.
  • the clock module 201 and the processing module 202 are connected by electrical signals through a first interface U1 and a second interface U2, wherein the first interface U1 is a single-wire interface, and the second interface U2 is a two-wire bidirectional bus interface, wherein the first interface U1 can use
  • the second interface U2 can be used to transmit time stamp information.
  • Different nodes can be connected by electrical signals through the third interface U3, and the third interface U3 can be used to transmit IEEE 1588 protocol packets.
  • one of the multiple nodes serves as the master node (master), and the rest of the nodes serve as slave nodes (slave).
  • the master node can synchronize the reference time to all slave nodes.
  • the processing module of the master node sends IEEE 1588 protocol packets to the processing module of the slave node.
  • the slave node can collect timestamps according to the received protocol packets and send the timestamps to the clock module.
  • the clock module of the slave node can The time stamp determines the time deviation from the master node. After the slave node receives protocol packets for many times, the frequency deviation from the master node can be obtained.
  • the clock module of the slave node can obtain the time deviation and frequency deviation from the master node according to the Its own real-time clock can be adjusted so that the clock module of the slave node is synchronized with the reference time of the master node. Then, the processing module in the slave node sends the timestamp to the clock module, and the clock module adjusts its own real-time clock according to the comparison between the timestamp and the reference time. After that, the clock module sends the timestamp information and the second pulse information to the processing module. The processing module adjusts its own real-time clock according to the time stamp information and the second pulse information, so that the processing module and the clock template realize clock synchronization.
  • the clock module 201 sends the timestamp information and the second pulse information to the processing module 202;
  • the processing module 202 executes the above sampling method, that is, at least executes the above step S101 to the above step S104, to sample the pulse-per-second information;
  • the processing module 202 adds 1 clock cycle to the data of the timestamp information and updates it to the internal real-time clock; if the processing module 202 obtains the sampling value The first sampling value of is different from the second sampling value, the processing module 202 directly updates the data of the timestamp information to the internal real-time clock.
  • the processing module 202 uses the above sampling method to sample the pulse-per-second information. Since the sampling accuracy of the above sampling method is high, the pulse-per-second information collected by the processing module 202 is more accurate, and further, the processing module 202 time synchronization is more accurate.
  • FIG. 7 is a schematic structural diagram of the sampling circuit provided by the embodiment of the present application.
  • the sampling circuit in the embodiment of the present application may include:
  • the first sampling module 31 is configured to receive the first clock signal clk1 and the second pulse information P, use the first clock signal clk1 to sample the second pulse information P, and output the first sampling signal Q1;
  • the second sampling module 32 is configured to receive the second clock signal clk2 and the second pulse information P, use the second clock signal clk2 to sample the second pulse information P, and output the second sampling signal Q2;
  • the first sampling value extraction module 33 is electrically connected to the first sampling module 31, and is used for determining the first sampling value q1 of the first sampling signal Q1 at the sampling point, and outputting the first sampling value q1; the sampling point is the first sampling signal
  • the first transition edge of Q1 is the transition edge from the first value to the second value;
  • the second sampling value extraction module 34 is electrically connected to the second sampling module 32, and is used for determining the second sampling value q2 of the second sampling signal Q2 at the sampling point of the first sampling signal Q1, and outputting the second sampling value q2.
  • the first sampling module and the second sampling module are used to sample the second pulse information respectively, and the first sampling signal and the second sampling signal can be obtained, and the first sampling value extraction module can obtain the first sampling signal.
  • the first sampling value of the sampling signal at the sampling point, the second sampling value of the first sampling signal at the sampling point can be obtained through the second sampling value extraction module, and subsequently, according to the first sampling value and the second sampling value, to It is determined whether the transition edge of the second pulse information differs from the sampling point by 0 to 0.5 cycles of the first clock signal, or is different from 0.5 to 1 cycle of the first clock signal.
  • the first sampling module 31 may include a plurality of first registers 311 .
  • the second sampling module 32 may include a plurality of second registers 321 .
  • the first sample value extraction module 33 may include: a third register 331 , a first NOT gate device 332 and a first AND gate device 333 .
  • the second sample value extraction module 34 may include a fourth register 341 .
  • FIG. 8 is another schematic structural diagram of the sampling circuit provided by the embodiment of the present application. As shown in FIG. 8 , in order to monitor the phases of the first clock signal and the second clock signal, the above-mentioned sampling circuit provided by the embodiment of the present application, Can also include:
  • the detection signal generation module 35 is electrically connected with the first sampling module 31 and the second sampling module 32, and is used to generate the detection signal P1, for example, the detection signal generation module 35 can divide the clock signal whose clock frequency is 999MHz by two, to obtain the detection signal P1.
  • the detection signal generation module 35 may include: a fifth register 351 and a second NOT gate device 352 .
  • the counting module 36 is electrically connected to the first sampling value extracting module 33 and the second sampling value extracting module 34, and is used to count the total number N of sampling results, the number n1 of the first sampling results, and the number n2 of the second sampling results.
  • the counting module counts the total number N of sampling results, the number n1 of the first sampling results, and the number n2 of the second sampling results, so as to determine the phase drift between the first clock signal and the second clock signal Furthermore, the phases of the first clock signal and the second clock signal can be adjusted according to the phase shift amount, so that the phase difference between the first sampling signal and the second sampling signal is maintained at 180°.
  • the counting module 36 includes: a first counter 361 , a second counter 362 , and a third counter 363 ;
  • the first counter 361 is electrically connected to the first sampling value extraction module 33, and is used to count the total number N of sampling results, and the first sampling value extraction module 33 is used to determine the first sampling value q1 of the first sampling signal Q1 at the sampling point, The first counter 361 may determine the total number N of sampling results according to the number of first sampling values q1 output by the first sampling value extracting module 33 .
  • the second counter 362 is electrically connected to the first sampling value extracting module 33 and the second sampling value extracting module 34, and is used to count the number n1 of the first sampling results.
  • the second counter 362 is electrically connected to the first sampling value extracting module 33 and the second sampling value extracting module 34 through the second AND gate device 364.
  • the third counter 363 is electrically connected to the first sampling value extracting module 33 and the second sampling value extracting module 34, and is used to count the number n2 of second sampling results.
  • the third counter 363 is electrically connected to the first sampling value extraction module 33 and the second sampling value extraction module 34 through the third AND gate device 365 , and the second sampling value extraction module 34 is connected to the third AND gate through the third NOT gate device 366
  • the device 365 is electrically connected, and when it is detected that the first sampled value q1 output by the first sampled value extraction module 33 is different from the second sampled value q2 output by the second sampled value extraction module 34, a count is performed, and finally a second sampling result is obtained. Quantity n2.
  • the above-mentioned sampling circuit may further include: an enable switch 37 electrically connected to the counting module 36 , and the enable switch 37 is configured to receive an enable control signal En.
  • the enable switch 37 is configured to receive an enable control signal En.
  • the method of calculating the average value by multiple counts may be used to reduce the influence of errors on the adjustment result.

Abstract

本申请提供一种采样方法、采样电路及分布式网络的时钟同步方法，采样方法包括：接收时戳信息和秒脉冲信息；采用第一时钟信号和第二时钟信号对秒脉冲信息进行采样，分别得到第一采样信号和第二采样信号；第一时钟信号与第二时钟信号的周期相同、相位差为180°；确定第一采样信号在采样点时的第一采样值，以及第二采样信号在采样点时的第二采样值；比较第一采样值与第二采样值的异同，如果第一采样值与第二采样值相同，则对时戳信息进行调整后，基于调整后的时戳信息进行时钟同步；如果第一采样值与第二采样值不同，则基于时戳信息进行时钟同步。本申请采用双相位采样方法，可以提高采样精度，进而提高时钟同步的精确度。

Description

一种采样方法、采样电路及分布式网络的时钟同步方法 技术领域
本申请涉及分布式网络技术领域，特别涉及一种采样方法、采样电路及分布式网络的时钟同步方法。
背景技术
网络测量和控制系统的精密时钟同步协议标准(standard for a precision clock synchronization protocol for networked measurement and control systems，IEEE 1588)可以精确地将分布式网络通讯中各节点的实时时钟同步起来，在IEEE 1588同步系统中，分布式网络的各个节点都设有时钟模块和处理模块，其中，处理模块用于进行IEEE 1588报文的相关协议处理并收集相关时间戳，以及将时间戳上送给时钟模块，时钟模块用于基于时间戳进行时钟信息的运算，进而调整本地实时时钟，以实现时钟同步。时钟模块会周期性地向处理模块发送时戳信息和秒脉冲信息(Pulse Per Second，PPS)，从而使处理模块的实时时钟与时钟模块同步。
IEEE 1588同步系统对精度要求非常高，目前要求精度为纳秒级，其中，PPS信息的采样精度是整个IEEE 1588同步系统精度的重要影响因素。在相关技术中，PPS信息的采样精度完全依赖于采样时钟的时钟频率，也就是说，只能通过提高采样时钟的时钟频率，来提高PPS信息的采样精度，例如，需要时钟频率为1GHz的采样时钟，才能使PPS信息的采样精度达到1ns。但是，由于时序收敛的问题，采样时钟的时钟频率不能无限提高，使PPS信息的采样精度难以提高。
发明内容
本申请提供了一种采样方法、采样电路及分布式网络的时钟同步方法，用以提高采样精度。
第一方面，本申请提供了一种采样方法，包括：接收时戳信息和秒脉冲信息；采用第一时钟信号和第二时钟信号对秒脉冲信息进行采样，分别得到第一采样信号和第二采样信号；其中，第一时钟信号和第二时钟信号的周期相同，且第一时钟信号与第二时钟信号的相位差为180°；以第一采样信号的第一跳变沿为采样点，确定第一采样信号在采样点时的第一采样值，以及确定第二采样信号在第一采样信号的采样点时的第二采样值；第一跳变沿为从第一数值跳变为第二数值的跳变沿；比较第一采样值与第二采样值的异同，如果第一采样值与第二采样值相同，则对时戳信息进行调整后，基于调整后的时戳信息进行时钟同步；如果第一采样值和第二采样值不同，则基于时戳信息进行时钟同步。
本申请实施例提供的采样方法，采用第一时钟信号和第二时钟信号对秒脉冲信息进行采样，分别得到第一采样信号和第二采样信号；其中，第一时钟信号和第二时钟信号的周期相同，且第一时钟信号与第二时钟信号的相位差为180°，根据得到的第一采样信号和第二采样信号可以确定秒脉冲信息的跳变沿位置，即可以确定秒脉冲信息的跳变沿与采样点相差0～0.5个第一时钟信号的周期，还是相差0.5～1个第一时钟信号的周期，即采样本申请实施例中的采样方法，不仅可以确定秒脉冲信息的跳变沿位于第一时钟信号的哪个周 期内，还可以进一步确定秒脉冲信息P的跳变沿位于该周期的前半个周期内，还是后半个周期内，可以将采样精度缩小到0.5个时钟周期，将采样精度提高为原来的两倍。
在一种可能的实现方式中，上述采用第一时钟信号和第二时钟信号对秒脉冲信息进行采样，分别得到第一采样信号和第二采样信号，包括；确定在第一时钟信号的各第一跳变沿处秒脉冲信息的采样值，得到第一采样信号；确定在第二时钟信号的各第一跳变沿处秒脉冲信息的采样值，得到第二采样信号。
在实际应用过程中，第一时钟信号与第二时钟信号的相位可能会出现漂移，为了对第一时钟信号与第二时钟信号的相位进行监测，并实时调整第一时钟信号与第二时钟信号的相位，本申请实施例提供的上述采样方法，还可以包括：采用第一时钟信号和第二时钟信号对检测信号进行N次采样，得到N组采样结果；每一组采样结果包括第一采样信号和第二采样信号；其中，检测信号为时域均匀分布的随机信号；针对每一组采样结果执行：以第一采样信号的第一跳变沿为采样点，确定第一采样信号在采样点时的第一采样值，以及确定第二采样信号在第一采样信号的采样点时的第二采样值；N组采样结果包括：n1组第一采样结果和n2组第二采样结果；其中，第一采样结果中的第一采样值与第二采样值相同；第二采样结果中的第一采样值与第二采样值不同；根据采样结果总数量N，第一采样结果的数量n1，以及第二采样结果的数量n2，确定第一时钟信号与第二时钟信号的相位漂移量，并根据相位漂移量对第一时钟信号和第二时钟信号的相位进行调整。
由于检测信号为时域均匀分布的随机信号，对检测信号进行N次采样后，如果第一时钟信号与第二时钟信号的相位未漂移，则N组采样结果中，第一采样结果的数量n1与第二采样结果的数量n2基本一致，如果第一时钟信号与第二时钟信号的相位发生漂移，则可以通过采样结果总量N、第一采样结果的数量n1及第二采样结果n2，来反应第一时钟信号与第二时钟信号的相位漂移量。然后，根据相位漂移量对第一时钟信号和第二时钟信号的相位进行调整，使第一采样信号与第二采样信号之间的相位差保持180°。
在一种可能的实现方式中，可以按以下公式确定第一时钟信号与第二时钟信号的相位漂移量S：
S＝(n1-n2)*360°/(2*N)。
在一种可能的实现方式中，上述第一时钟信号的时钟频率可以为1GHz；检测信号可以为时钟频率为999M Hz的时钟信号经二分频得到的信号，即检测信号可以为伪随机信号。采用二分频后的信号作为检测信号，可以使检测信号的周期较大，保证检测信号的高相位和低相位能够被采样到。
第二方面，本申请还提供了一种分布式网络的时钟同步方法，其中，该分布式网络的每一个节点包括时钟模块及处理模块。上述时钟同步方法，可以包括：时钟模块将时戳信息及秒脉冲信息发送至处理模块；处理模块执行上述任一采样方法，对秒脉冲信息进行采样；其中，若处理模块采样得到的第一采样值与第二采样值相同，则处理模块将时戳信息的数据加上1个时钟周期后更新到内部实时时钟中；若处理模块采样得到的第一采样值与第二采样值不同，则处理模块将时戳信息的数据直接更新到内部实时时钟中。
本申请实施例中，处理模块采用上述采样方法对秒脉冲信息进行采样，由于上述采样方法的采样精度较高，因而，处理模块采集到的秒脉冲信息更加准确，进而，使处理模块的时间同步更加精确。
第三方面，本申请还提供了一种采样电路，可以包括：第一采样模块、第二采样模块、 第一采样值提取模块及第二采样值提取模块；其中，第一采样模块，用于接收第一时钟信号及秒脉冲信息，采用第一时钟信号对秒脉冲信息进行采样，输出第一采样信号；第二采样模块，用于接收第二时钟信号及秒脉冲信息，采用第二时钟信号对秒脉冲信息进行采样，输出第二采样信号；第一采样值提取模块，与第一采样模块电连接，用于确定第一采样信号在采样点时的第一采样值，输出第一采样值；采样点为第一采样信号的第一跳变沿，第一跳变沿为从第一数值跳变为第二数值的跳变沿；第二采样值提取模块，与第二采样模块电连接，用于确定第二采样信号在第一采样信号的采样点时的第二采样值，输出第二采样值。
本申请实施例提供的采样电路，采用第一采样模块和第二采样模块分别对秒脉冲信息进行采样，可以得到第一采样信号和第二采样信号，通过第一采样值提取模块可以得到第一采样信号在采样点时的第一采样值，通过第二采样值提取模块可以得到第一采样信号在采样点时的第二采样值，后续，可以根据第一采样值与第二采样值，来确定秒脉冲信息的跳变沿与采样点相差0～0.5个第一时钟信号的周期，还是相差0.5～1个第一时钟信号的周期，提高了采样精度。
在一种可能的实现方式中，为了实现对第一时钟信号与第二时钟信号的相位进行监测，本申请实施例提供的上述采样电路，还可以包括：检测信号生成模块及计数模块；其中，检测信号生成模块，与第一采样模块和第二采样模块电连接，用于生成检测信号；计数模块，与第一采样值提取模块和第二采样值提取模块电连接，用于统计采样结果总数量N，第一采样结果的数量n1，以及第二采样结果的数量n2。
本申请实施例中的采样电路，通过计数模块统计采样结果总数量N、第一采样结果的数量n1、以及第二采样结果的数量n2，可以确定第一时钟信号与第二时钟信号的相位漂移量，进而，可以根据相位漂移量对第一时钟信号和第二时钟信号的相位进行调整，使第一采样信号与第二采样信号之间的相位差保持180°。
在一种可能的实现方式中，上述计数模块，可以包括：第一计数器，第二计数器，以及第三计数器；其中，第一计数器与第一采样值提取模块电连接，用于统计采样结果总数量N；第二计数器与第一采样值提取模块、第二采样值提取模块电连接，用于统计第一采样结果的数量；第三计数器与第一采样值提取模块、第二采样值提取模块电连接，用于统计第二采样结果的数量。
在一种可能的实现方式中，本申请实施例提供的上述采样电路，还可以包括：与计数模块电连接的使能开关。使能开关用于接收使能控制信号，当使能控制信号有效时，控制计数模块开始计数，当使能控制信号无效时，控制计数模块停止计数。在具体实施时，可以采用多次计数求取平均值的方式，以减小误差对调整结果的影响。
附图说明
图1为本申请实施例提供的采样方法的流程图；
图2为本申请实施提供的采样方法对应的时序图；
图3为本申请实施例提供的采样方法的另一时序图；
图4为第一时钟信号与第二时钟信号的相位发生漂移后的时序图；
图5为第一时钟信号与检测信号的时序图；
图6为本申请实施例中分布式网络中的一个节点的结构示意图；
图7为本申请实施例提供的采样电路的结构示意图；
图8为本申请实施例提供的采样电路的另一结构示意图。
附图标记：
P-秒脉冲信息；clk1-第一时钟信号；clk2-第二时钟信号；Q1-第一采样信号；Q2-第二采样信号；A-采样点；201-时钟模块；202-处理模块；U1-第一接口；U2-第二接口；U3-第三接口；31-第一采样模块；311-第一寄存器；32-第二采样模块；321-第二寄存器；33-第一采样值提取模块；331-第三寄存器；332-第一非门器件；333-第一与门器件；34-第二采样值提取模块；341-第四寄存器；35-检测信号生成模块；351-第五寄存器；352-第二非门器件；36-计数模块；361-第一计数器；362-第二计数器；363-第三计数器；364-第二与门器件；365-第三与门器件；366-第三非门器件；37-使能开关。
具体实施方式
本申请实施例提供的采样方法可以应用于IEEE 1588同步系统中，以提高IEEE 1588同步系统中PPS信息的采样精度，进而提高IEEE 1588同步系统的精度。当然，本申请实施例提供的采样方法也可以应用于其他场景中，本申请中的采样方法也可以对其他信号进行采样，此处不对本申请实施例提供的采样方法的应用场景进行限定。
为了使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请作进一步地详细描述。应注意的是，在本说明书中，相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义，则在随后的附图中不需要对其进行进一步定义和解释。
本申请实施例的描述中，“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。字符“/”一般表示前后关联对象是一种“或”的关系。本申请中所涉及的至少一个是指一个或多个；多个，是指两个或两个以上。另外，需要理解的是，在本申请的描述中，“第一”、“第二”等词汇，仅用于区分描述的目的，而不能理解为指示或暗示相对重要性，也不能理解为指示或暗示顺序。
图1为本申请实施例提供的采样方法的流程图，图2为本申请实施提供的采样方法对应的时序图，结合图1和图2，本申请实施例中的采样方法，可以包括：
S101、接收时戳信息和秒脉冲信息；
S102、采用第一时钟信号clk1和第二时钟信号clk2对秒脉冲信息P进行采样，分别得到第一采样信号Q1和第二采样信号Q2；其中，第一时钟信号clk1和第二时钟信号clk2的周期相同，且第一时钟信号clk1与第二时钟信号clk2的相位差为180°。应该说明的是，本申请实施例中第一时钟信号clk1与第二时钟信号clk2的相位差为180°指的是，第一时钟信号clk1与第二时钟信号clk2的相位差在一定的偏差范围内为180°，或者，可以理解为第一时钟信号clk1与第二时钟信号clk2的相位差近似为180°。并且，第一时钟信号clk1与第二时钟信号clk2需保持同步，以保证采样精度较高。可选地，为了使采样精度较高，第一时钟信号clk1的时钟频率可以为1G Hz或500M Hz，当然，第一时钟信号clk1的时钟频率也可以为其他数值，此处不做限定。
S103、以第一采样信号Q1的第一跳变沿为采样点A，确定第一采样信号Q1在采样点A时的第一采样值，以及确定第二采样信号Q2在第一采样信号Q1的采样点A时的第二 采样值。应该说明的是，在本申请实施例中，采样点A均指第一采样信号Q1的第一跳变沿，其中，第一跳变沿为从第一数值跳变为第二数值的跳变沿，例如，第一跳变沿可以为上升沿，即从低电平(0)跳变为高电平(1)的跳变沿，当然，第一跳变沿也可以为下降沿，即从高电平(1)跳变为低电平(0)的跳变沿，为了便于说明，在本申请中均以第一跳变沿为上升沿为例进行说明。
S104、比较第一采样值与第二采样值的异同，如果第一采样值与第二采样值相同，表示秒脉冲信息P的跳变沿与采样点A相差0.5～1个第一时钟信号clk1的周期，则对时戳信息进行调整后，基于调整后的时戳信息进行时钟同步；如果第一采样值和第二采样值不同，表示秒脉冲信息P的跳变沿与采样点A相差0～0.5个第一时钟信号clk1的周期，则基于时戳信息进行时钟同步。
在分布式网络中，每一个节点可以包括时钟模块和处理模块，上述步骤S101至步骤S104可以在处理模块中执行，也就是说，时钟模块周期性地向处理模块发送时戳信息和秒脉冲信息，处理模块在接收时戳信息和秒脉冲信息时，触发处理模块执行上述步骤S101至步骤S104。
本申请实施例提供的采样方法，采用第一时钟信号和第二时钟信号对秒脉冲信息进行采样，分别得到第一采样信号和第二采样信号；其中，第一时钟信号和第二时钟信号的周期相同，且第一时钟信号与第二时钟信号的相位差为180°，根据得到的第一采样信号和第二采样信号可以确定秒脉冲信息的跳变沿位置，即可以确定秒脉冲信息的跳变沿与采样点相差0～0.5个第一时钟信号的周期，还是相差0.5～1个第一时钟信号的周期，即采样本申请实施例中的采样方法，不仅可以确定秒脉冲信息的跳变沿位于第一时钟信号的哪个周期内，还可以进一步确定秒脉冲信息P的跳变沿位于该周期的前半个周期内，还是后半个周期内。而相关技术中采用一个时钟信号对秒脉冲信息进行采样，只能确定秒脉冲信息的跳变沿位于哪个周期内，采样精度为一个时钟周期，因此，相比于采用一个时钟信号对秒脉冲信息进行采样，本申请实施例中采用双相位采样方法，可以将采样精度缩小到0.5个时钟周期，将采样精度提高为原来的两倍。
并且，如果第一采样值与第二采样值相同，则对时戳信息进行调整后，基于调整后的时戳信息进行时钟同步；如果第一采样值和第二采样值不同，则基于时戳信息进行时钟同步。由于本申请实施例中可以更精确的确定秒脉冲信息的跳变沿，进而，可以使时钟同步更加精确。
继续参照图1和图2，本申请实施例提供的上述采样方法中，上述步骤S102，可以包括：
确定在第一时钟信号clk1的各第一跳变沿处秒脉冲信息P的采样值，得到第一采样信号Q1，例如在图2中，在第一时钟信号clk1的各第一跳变沿处秒脉冲信息P的采样值分别为：0、1、1、1，根据确定出的各采样值可以得到第一采样信号Q1的时序。
确定在第二时钟信号clk2的各第一跳变沿处秒脉冲信息P的采样值，得到第二采样信号Q2，例如图2中，在第二时钟信号clk2的各第一跳变沿处秒脉冲信息P的采样值分别为：0、1、1，根据确定出的各采样值可以得到第二采样信号Q2的时序。
如图2所示，秒脉冲信息P的跳变沿与采样点A相差0～0.5个第一时钟信号的周期，即秒脉冲信息P的跳变沿位于图中区域T2中，此时，第一采样信号Q1在采样点A时的第一采样值为1，第二采样信号Q2在采样点A时的第二采样值为0，即第一采样值与第二 采样值不同。图3为本申请实施例提供的采样方法的另一时序图，如图3所示，秒脉冲信息P的跳变沿与采样点A相差0.5～1个第一时钟信号clk1的周期，即秒脉冲信息P的跳变沿位于图中区域T1中，此时，第一采样信号Q1在采样点A时的第一采样值为1，第二采样信号Q2在采样点A时的第二采样值为1，即第一采样值与第二采样值相同。因此，在上述步骤S104中，可以通过比较第一采样值与第二采样值的大小，来确定秒脉冲信息P的跳变沿与采样点相差0～0.5个第一时钟信号clk1的周期，还是相差0.5～1个第一时钟信号clk1的周期。也就是说，本申请实施例中的采样方法，不仅可以确定秒脉冲信息P的跳变沿位于第一时钟信号clk1的哪个周期内，还可以进一步确定秒脉冲信息P的跳变沿位于该周期的前半个周期内，还是后半个周期内，从而提高了采样精度。
以图2和图3所示的时序图为例，无论秒脉冲信息P的跳变沿位于区域T1还是区域T2，第一采样值均为1，在上述步骤S104中，可以通过判断第二采样值的具体数值，来确定第一采样值与第二采样值的异同，例如，第二采样值为1时，可以确定第一采样值与第二采样值相同，第二采样值为0时，可以确定第一采样值与第二采样值不同。当然，在上述步骤S104中，也可以采用其他方式比较第一采样值与第二采样值的异同，此处不做限定。
在实际应用过程中，第一时钟信号与第二时钟信号的相位可能会出现漂移，图4为第一时钟信号与第二时钟信号的相位发生漂移后的时序图，如图4所示，由于第一时钟信号clk1与第二时钟信号clk2的相位发生漂移，使区域T1与区域T2的大小差异较大，区域T1变小，区域T2变大，也就是说，确定出的秒脉冲信息的跳变沿与采样点的差异不再是0～0.5个第一时钟信号的周期，或0.5～1个第一时钟信号的周期，从而影响秒脉冲信息的采样精度。
为了对第一时钟信号与第二时钟信号的相位进行监测，并实时调整第一时钟信号与第二时钟信号的相位，本申请实施例提供的上述采样方法，还可以包括：
采用第一时钟信号和第二时钟信号对检测信号进行N次采样，得到N组采样结果；每一组采样结果包括第一采样信号和第二采样信号；其中，检测信号为时域均匀分布的随机信号；
针对每一组采样结果执行：以第一采样信号的第一跳变沿为采样点，确定第一采样信号在采样点时的第一采样值，以及确定第二采样信号在第一采样信号的采样点时的第二采样值；
N组采样结果包括：n1组第一采样结果和n2组第二采样结果；其中，第一采样结果中的第一采样值与第二采样值相同；第二采样结果中的第一采样值与第二采样值不同；根据采样结果总数量N，第一采样结果的数量n1，以及第二采样结果的数量n2，确定第一时钟信号与第二时钟信号的相位漂移量，并根据相位漂移量对第一时钟信号和第二时钟信号的相位进行调整。
也就是说，以检测信号作为秒脉冲信息，执行N次上述步骤S102～S104，由于检测信号为时域均匀分布的随机信号，对检测信号进行N次采样后，如果第一时钟信号与第二时钟信号的相位未漂移，则N组采样结果中，第一采样结果的数量n1与第二采样结果的数量n2基本一致，如果第一时钟信号与第二时钟信号的相位发生漂移，则可以通过采样结果总量N、第一采样结果的数量n1及第二采样结果n2，来反应第一时钟信号与第二时钟信号的相位漂移量。然后，根据相位漂移量对第一时钟信号和第二时钟信号的相位进行调 整，使第一采样信号与第二采样信号之间的相位差保持180°，例如，可以根据相位漂移量对第一时钟信号的相位进行相应的调整，或者，也可以对第二时钟信号进行调整，或者，将二者同时进行调整，此处不做限定。
可选地，本申请实施例提供的上述采样方法中，可以按以下公式确定第一时钟信号与第二时钟信号的相位漂移量S：
S＝(n1-n2)*360°/(2*N)。
例如，对检测信号进行N次采样后，采样结果的总数量N为1000，其中，第一采样结果的数量n1为600，第二采样结果的数量n2为400，根据上述公式可知，第一时钟信号与第二时钟信号的相位漂移量S＝36°。
其中，采样结果的总数量N与第一时钟信号的一个周期对应，若第一时钟信号和第二时钟信号的相位未出现漂移，则第一采样结果的数量与第二采样结果的数量相同，即n1＝n2＝N/2。若第一时钟信号和第二时钟信号的相位出现漂移，则第一采样结果的数量与第二采样结果的数量不同，与第一时钟信号和第二时钟信号的相位未出现漂移时相比，第一采样结果(或第二采样结果)的变化量为(n1-n2)/2。
将第一时钟信号的一个周期的总相位(360°)分为N份，若第一采样结果的数量n1(或第二采样结果的数量n2)的变化量为1，则对应的相位漂移量为360°/N，因此，可以通过第一采样结果的数量n1(或第二采样结果的数量n2)的变化量(n1-n2)/2，与变化量为1对应的相位漂移量为360°/N的乘积，确定第一时钟信号与第二时钟信号的相位漂移量S，即S＝{(n1-n2)/2}*360°/N。
在具体实施时，本申请实施例提供的上述采样方法中，上述第一时钟信号的时钟频率可以为1GHz；检测信号可以为时钟频率为999M Hz的时钟信号经二分频得到的信号，即检测信号可以为伪随机信号。采用二分频后的信号作为检测信号，可以使检测信号的周期较大，保证检测信号的高相位和低相位能够被采样到。图5为第一时钟信号与检测信号的时序图，如图5所示，第一时钟信号的周期为1ns，在第一时钟信号clk1的第一个上升沿处，第一时钟信号clk1与检测信号P1的边沿对齐，在第一时钟信号clk1的第二个上升沿处，第一时钟信号clk1与检测信号P1的边沿相差1/999ns，在第一时钟信号clk1的第三个上升沿处，第一时钟信号clk1与检测信号P1的边沿相差2/999ns，在第一时钟信号clk1的第i+1个上升沿处，第一时钟信号clk1与检测信号P1的边沿相差i/999ns，在第一时钟信号clk1的第1000个上升沿处，第一时钟信号clk1与检测信号P1的边沿再次对齐。因此，检测信号P1以1/999ns为粒度，均匀分布在第一时钟信号clk1的一个周期内，因而，对检测信号P1进行N次采样，可以根据采样结果总量N、第一采样结果的数量n1及第二采样结果n2，来反应第一时钟信号与第二时钟信号的相位漂移量。
基于同一技术构思，本申请实施例还提供了一种分布式网络的时钟同步方法，图6为本申请实施例中分布式网络中的一个节点的结构示意图，如图6所示，分布式网络的每一个节点包括时钟模块201及处理模块202，时钟模块201与处理模块202的内部均设有实时时钟。时钟模块201与处理模块202通过第一接口U1及第二接口U2电信号连接，其中，第一接口U1为单线接口，第二接口U2为两线双向总线接口，其中，第一接口U1可以用于传输秒脉冲信息，第二接口U2可以用于传输时戳信息。不同的节点之间可以通过第三接口U3实现电信号连接，第三接口U3可以用于传输IEEE 1588的协议报文。
在分布式网络中，多个节点中有一个节点作为主节点(master)，其余的节点作为从节 点(slave)，主节点可以将基准时间同步给所有的从节点。主节点的处理模块向从节点的处理模块发送IEEE 1588的协议报文，从节点可以根据接收到的协议报文收集时间戳，并将时间戳上送给时钟模块，从节点的时钟模块可以根据时间戳确定与主节点之间的时间偏差，从节点经多次接收协议报文后，可以得到与主节点之间的频率偏差，从节点的时钟模块根据与主节点的时间偏差及频率偏差，可以对自身的实时时钟进行调整，从而使从节点的时钟模块与主节点的基准时间同步。然后，从节点中的处理模块将时间戳发送给时钟模块，时钟模块根据时间戳与基准时间比较，来调节自身的实时时钟，之后，时钟模块将时戳信息与秒脉冲信息发送给处理模块，处理模块根据时戳信息与秒脉冲信息调节自身的实时时钟，从而使处理模块与时钟模板实现时钟同步。
本申请实施例提供的时钟同步方法，可以包括：
参照图6，时钟模块201将时戳信息及秒脉冲信息发送至处理模块202；
处理模块202执行上述采样方法，即至少执行上述步骤S101至上述步骤S104，对秒脉冲信息进行采样；
其中，若处理模块202采样得到的第一采样值与第二采样值相同，则处理模块202将时戳信息的数据加上1个时钟周期后更新到内部实时时钟中；若处理模块202采样得到的第一采样值与第二采样值不同，则处理模块202将时戳信息的数据直接更新到内部实时时钟中。
本申请实施例中，处理模块202采用上述采样方法对秒脉冲信息进行采样，由于上述采样方法的采样精度较高，因而，处理模块202采集到的秒脉冲信息更加准确，进而，使处理模块202的时间同步更加精确。
基于同一技术构思，本申请实施例还提供了一种采样电路，图7为本申请实施例提供的采样电路的结构示意图，如图7所示，本申请实施例中的采样电路，可以包括：
第一采样模块31，用于接收第一时钟信号clk1及秒脉冲信息P，采用第一时钟信号clk1对秒脉冲信息P进行采样，输出第一采样信号Q1；
第二采样模块32，用于接收第二时钟信号clk2及秒脉冲信息P，采用第二时钟信号clk2对秒脉冲信息P进行采样，输出第二采样信号Q2；
第一采样值提取模块33，与第一采样模块31电连接，用于确定第一采样信号Q1在采样点时的第一采样值q1，输出第一采样值q1；采样点为第一采样信号Q1的第一跳变沿，第一跳变沿为从第一数值跳变为第二数值的跳变沿；
第二采样值提取模块34，与第二采样模块32电连接，用于确定第二采样信号Q2在第一采样信号Q1的采样点时的第二采样值q2，输出第二采样值q2。
本申请实施例提供的采样电路，采用第一采样模块和第二采样模块分别对秒脉冲信息进行采样，可以得到第一采样信号和第二采样信号，通过第一采样值提取模块可以得到第一采样信号在采样点时的第一采样值，通过第二采样值提取模块可以得到第一采样信号在采样点时的第二采样值，后续，可以根据第一采样值与第二采样值，来确定秒脉冲信息的跳变沿与采样点相差0～0.5个第一时钟信号的周期，还是相差0.5～1个第一时钟信号的周期。
继续参照图7，第一采样模块31可以包括多个第一寄存器311。第二采样模块32可以包括多个第二寄存器321。第一采样值提取模块33可以包括：第三寄存器331、第一非门器件332及第一与门器件333。第二采样值提取模块34可以包括第四寄存器341。
图8为本申请实施例提供的采样电路的另一结构示意图，如图8所示，为了实现对第一时钟信号与第二时钟信号的相位进行监测，本申请实施例提供的上述采样电路，还可以包括：
检测信号生成模块35，与第一采样模块31和第二采样模块32电连接，用于生成检测信号P1，例如，检测信号生成模块35可以对时钟频率为999M Hz的时钟信号进行二分频，以得到检测信号P1。检测信号生成模块35可以包括：第五寄存器351及第二非门器件352。
计数模块36，与第一采样值提取模块33和第二采样值提取模块34电连接，用于统计采样结果总数量N，第一采样结果的数量n1，以及第二采样结果的数量n2。
本申请实施例中的采样电路，通过计数模块统计采样结果总数量N、第一采样结果的数量n1、以及第二采样结果的数量n2，可以确定第一时钟信号与第二时钟信号的相位漂移量，进而，可以根据相位漂移量对第一时钟信号和第二时钟信号的相位进行调整，使第一采样信号与第二采样信号之间的相位差保持180°。
可选地，本申请实施例提供的上述采样电路中，继续参照图8，计数模块36，包括：第一计数器361，第二计数器362，以及第三计数器363；
第一计数器361与第一采样值提取模块33电连接，用于统计采样结果总数量N，第一采样值提取模块33用于确定第一采样信号Q1在采样点时的第一采样值q1，第一计数器361可以根据第一采样值提取模块33输出的第一采样值q1的数量，确定采样结果总数量N。
第二计数器362与第一采样值提取模块33、第二采样值提取模块34电连接，用于统计第一采样结果的数量n1。第二计数器362通过第二与门器件364与第一采样值提取模块33、第二采样值提取模块34电连接，当检测到第一采样值提取模块33输出的第一采样值q1与第二采样值提取模块34输出的第二采样值q2相同时进行一次计数，最终得到第一采样结果的数量n1。
第三计数器363与第一采样值提取模块33、第二采样值提取模块34电连接，用于统计第二采样结果的数量n2。第三计数器363通过第三与门器件365与第一采样值提取模块33、第二采样值提取模块34电连接，且第二采样值提取模块34通过第三非门器件366与第三与门器件365电连接，当检测到第一采样值提取模块33输出的第一采样值q1与第二采样值提取模块34输出的第二采样值q2不同时进行一次计数，最终得到第二采样结果的数量n2。
此外，继续参照图8，本申请实施例提供的上述采样电路，还可以包括：与计数模块36电连接的使能开关37，使能开关37用于接收使能控制信号En，当使能控制信号En有效时，控制计数模块36开始计数，当使能控制信号En无效时，控制计数模块36停止计数。在具体实施时，可以采用多次计数求取平均值的方式，以减小误差对调整结果的影响。
尽管已描述了本申请的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本申请范围的所有变更和修改。
显然，本领域的技术人员可以对本申请实施例进行各种改动和变型而不脱离本申请实施例的精神和范围。这样，倘若本申请实施例的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (10)

  1. 一种采样方法，其特征在于，包括：
    接收时戳信息和秒脉冲信息；
    采用第一时钟信号和第二时钟信号对所述秒脉冲信息进行采样，分别得到第一采样信号和第二采样信号；其中，所述第一时钟信号和所述第二时钟信号的周期相同，且所述第一时钟信号与所述第二时钟信号的相位差为180°；
    以所述第一采样信号的第一跳变沿为采样点，确定所述第一采样信号在所述采样点时的第一采样值，以及确定所述第二采样信号在所述第一采样信号的所述采样点时的第二采样值；所述第一跳变沿为从第一数值跳变为第二数值的跳变沿；
    比较所述第一采样值与所述第二采样值的异同，如果所述第一采样值与所述第二采样值相同，则对所述时戳信息进行调整后，基于调整后的所述时戳信息进行时钟同步；如果所述第一采样值和所述第二采样值不同，则基于所述时戳信息进行时钟同步。
  2. 如权利要求1所述的采样方法，其特征在于，所述采用第一时钟信号和第二时钟信号对所述秒脉冲信息进行采样，分别得到第一采样信号和第二采样信号，包括；
    确定在所述第一时钟信号的各所述第一跳变沿处所述秒脉冲信息的采样值，得到所述第一采样信号；
    确定在所述第二时钟信号的各所述第一跳变沿处所述秒脉冲信息的采样值，得到所述第二采样信号。
  3. 如权利要求1所述的采样方法，其特征在于，还包括：
    采用所述第一时钟信号和所述第二时钟信号对检测信号进行N次采样，得到N组采样结果；每一组所述采样结果包括第一采样信号和第二采样信号；其中，所述检测信号为时域均匀分布的随机信号；
    针对每一组所述采样结果执行：以所述第一采样信号的第一跳变沿为采样点，确定所述第一采样信号在所述采样点时的第一采样值，以及确定所述第二采样信号在所述第一采样信号的所述采样点时的第二采样值；
    所述N组采样结果包括：n1组第一采样结果和n2组第二采样结果；其中，所述第一采样结果中的所述第一采样值与所述第二采样值相同；所述第二采样结果中的所述第一采样值与所述第二采样值不同；根据所述采样结果总数量N，所述第一采样结果的数量n1，以及所述第二采样结果的数量n2，确定所述第一时钟信号与所述第二时钟信号的相位漂移量，并根据所述相位漂移量对所述第一时钟信号和所述第二时钟信号的相位进行调整。
  4. 如权利要求3所述的采样方法，其特征在于，按以下公式确定所述第一时钟信号与所述第二时钟信号的相位漂移量S：
    S＝(n1-n2)*360°/(2*N)。
  5. 如权利要求3所述的采样方法，其特征在于，所述第一时钟信号的时钟频率为1GHz；
    所述检测信号为时钟频率为999M Hz的时钟信号经二分频得到的信号。
  6. 一种分布式网络的时钟同步方法，其特征在于，所述分布式网络的每一个节点包括时钟模块及处理模块；
    所述时钟同步方法，包括：
    所述时钟模块将时戳信息及秒脉冲信息发送至所述处理模块；
    所述处理模块执行如权利要求1～5任一项所述的采样方法，对所述秒脉冲信息进行采样；
    其中，若所述处理模块采样得到的第一采样值与第二采样值相同，则所述处理模块将所述时戳信息的数据加上1个时钟周期后更新到内部实时时钟中；若所述处理模块采样得到的所述第一采样值与所述第二采样值不同，则所述处理模块将所述时戳信息的数据直接更新到内部实时时钟中。
  7. 一种采样电路，其特征在于，包括：
    第一采样模块，用于接收第一时钟信号及秒脉冲信息，采用所述第一时钟信号对所述秒脉冲信息进行采样，输出第一采样信号；
    第二采样模块，用于接收第二时钟信号及所述秒脉冲信息，采用所述第二时钟信号对所述秒脉冲信息进行采样，输出第二采样信号；
    第一采样值提取模块，与所述第一采样模块电连接，用于确定所述第一采样信号在采样点时的第一采样值，输出所述第一采样值；所述采样点为所述第一采样信号的第一跳变沿，所述第一跳变沿为从第一数值跳变为第二数值的跳变沿；
    第二采样值提取模块，与所述第二采样模块电连接，用于确定所述第二采样信号在所述第一采样信号的所述采样点时的第二采样值，输出所述第二采样值。
  8. 如权利要求7所述的采样电路，其特征在于，还包括：
    检测信号生成模块，与所述第一采样模块和所述第二采样模块电连接，用于生成检测信号；
    计数模块，与所述第一采样值提取模块和所述第二采样值提取模块电连接，用于统计采样结果总数量N，第一采样结果的数量n1，以及第二采样结果的数量n2。
  9. 如权利要求8所述的采样电路，其特征在于，所述计数模块，包括：第一计数器，第二计数器，以及第三计数器；
    所述第一计数器与所述第一采样值提取模块电连接，用于统计所述采样结果总数量N；
    所述第二计数器与所述第一采样值提取模块、所述第二采样值提取模块电连接，用于统计所述第一采样结果的数量；
    所述第三计数器与所述第一采样值提取模块、所述第二采样值提取模块电连接，用于统计所述第二采样结果的数量。
  10. 如权利要求8所述的采样电路，其特征在于，还包括：与所述计数模块电连接的使能开关。
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