WO2017219881A1 - 一种基于1588的时间同步方法及装置 - Google Patents

一种基于1588的时间同步方法及装置 Download PDF

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Publication number
WO2017219881A1
WO2017219881A1 PCT/CN2017/087861 CN2017087861W WO2017219881A1 WO 2017219881 A1 WO2017219881 A1 WO 2017219881A1 CN 2017087861 W CN2017087861 W CN 2017087861W WO 2017219881 A1 WO2017219881 A1 WO 2017219881A1
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rising edge
clock
packet
line clock
timestamp
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PCT/CN2017/087861
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English (en)
French (fr)
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李霞
刘峰
何力
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中兴通讯股份有限公司
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Publication of WO2017219881A1 publication Critical patent/WO2017219881A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0658—Clock or time synchronisation among packet nodes
    • H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0658—Clock or time synchronisation among packet nodes
    • H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
    • H04J3/067—Details of the timestamp structure

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  • the present disclosure relates to the field of communications, and in particular, to a time synchronization method and apparatus based on 1588.
  • the high-precision time synchronization based on the 1588v2 technology can only meet the time synchronization requirement of the us-scale, but cannot meet the above-mentioned several hundred ns or even higher precision time synchronization requirements.
  • the technical problem solved by the technical solution provided by the embodiment of the present disclosure is to overcome the problems and defects of low synchronization precision existing in the related synchronization technology.
  • a 1588-based time synchronization method includes:
  • the generated time stamp is compensated for by the phase difference and the time difference to be consistent with the line clock.
  • the method before the step of determining, according to the line clock, the time difference between the rising edge of the packet header flag of the 1588 packet and the rising edge of the current period of the line clock, the method further includes:
  • the packet header flag of the 1588 packet is generated on the line clock, and the generated packet header flag is sent to the system clock domain.
  • the step of determining, according to the line clock, the time difference between the rising edge of the packet header flag of the 1588 packet and the rising edge of the current period of the line clock includes:
  • the step of generating a timestamp associated with the 1588 packet under the system clock includes:
  • the step of using the phase difference and the time difference to compensate the generated timestamp to be consistent with the line clock comprises:
  • phase difference is greater than the time difference, subtracting the time stamp from the phase difference to obtain a compensated time stamp
  • time stamp is subtracted from the phase difference and the system clock period to obtain a compensated time stamp.
  • a storage medium stores a program for implementing the above-described 1588-based time synchronization method.
  • a 1588-based time synchronization apparatus includes:
  • phase difference detecting module configured to obtain a phase difference between the system clock and the line clock according to a system clock and a line clock.
  • the rising edge detection module determines, according to the line clock, the time difference between the rising edge corresponding to the packet header flag of the 1588 packet and the rising edge of the current period of the line clock;
  • a timestamp sampling module configured to generate a timestamp associated with the 1588 packet under a system clock
  • a timestamp compensation module configured to compensate the generated timestamp with the line clock by using the phase difference and the time difference.
  • the method further comprises:
  • the PMA/PCS module is configured to generate a packet header flag of the 1588 packet under a line clock, and send the generated packet header flag to a system clock domain.
  • the rising edge detection module detects, according to the line clock, a rising edge corresponding to the packet header flag and a rising edge of a current period of the line clock, and according to the detected packet header flag A rising edge and a rising edge of a current period of the line clock determine a time difference between a rising edge of the message header flag and a rising edge of a current period of the line clock.
  • the timestamp sampling module is configured to receive the packet header flag at a system clock, and perform timestamp sampling on the received packet header flag to obtain a time associated with the 1588 packet. stamp.
  • the time stamp compensation module compares the phase difference with the time difference, and if the phase difference is greater than the time difference, subtracting the time stamp from the phase difference to obtain a compensated time stamp. Otherwise, the time stamp is subtracted from the phase difference and the system clock period to obtain a compensated time stamp.
  • the compensated timestamp is consistent with the line clock to achieve high-precision time synchronization.
  • FIG. 1 is a block diagram of a 1588-based time synchronization method according to a first embodiment of the present disclosure
  • FIG. 2 is a block diagram of a 1588-based time synchronization apparatus according to a second embodiment of the present disclosure
  • FIG. 3 is a block diagram of a 1588-based time synchronization apparatus according to a third embodiment of the present disclosure.
  • FIG. 5 is a timing diagram of the sof after the system clock according to the fourth embodiment of the present disclosure.
  • FIG. 6 is a block diagram of applying a device to a GE electrical port according to a fourth embodiment of the present disclosure.
  • FIG. 1 is a block diagram of a 1588-based time synchronization method according to a first embodiment of the present disclosure. As shown in FIG. 1, the steps include:
  • Step S101 Obtain a phase difference between the system clock and the line clock according to the system clock and the line clock.
  • the phase difference between the system clock and the line clock is obtained by performing phase difference detection on the system clock and the line clock.
  • Step S102 Determine, under the line clock, a time difference between a rising edge corresponding to the packet header flag of the 1588 packet and a rising edge of the current period of the line clock.
  • a packet header flag of the 1588 packet is generated under the line clock, and the generated packet header flag is sent to the system clock domain. Then, under the line clock, detecting a rising edge corresponding to the packet header flag and a rising edge of a current period of the line clock, and according to the detected rising edge of the packet header flag and the current line clock A rising edge of the period determines a time difference between a rising edge of the message header flag and a rising edge of the current period of the line clock. That is to say, under the line clock, a message header flag is generated, and the time difference between the rising edge of the message header flag and the rising edge of the current period of the line clock is detected or measured, so that the obtained time difference is used to determine the compensation value.
  • Step S103 Generate a timestamp associated with the 1588 packet under the system clock.
  • the packet header is received, and the timestamp is sampled by the timestamp of the received packet header, and the timestamp associated with the 1588 packet is obtained, that is, the packet header is received in the system clock domain.
  • the first rising edge of the system clock corresponds to the time.
  • Step S104 Using the phase difference, the generated timestamp is compensated to be consistent with the line clock.
  • phase difference For example, comparing the phase difference with the time difference, if the phase difference is greater than the time difference, subtracting the time stamp from the phase difference to obtain the compensated time stamp; otherwise, subtracting the time stamp from the phase difference and the system clock period to obtain The timestamp after compensation.
  • the obtained timestamp is added to the 1588 packet as the sending time of the 1588 packet.
  • the obtained compensated timestamp is saved as the receiving time of the received 1588 packet.
  • the storage medium may be a ROM/RAM, a magnetic disk, an optical disk, or the like.
  • FIG. 2 is a block diagram of a 1588-based time synchronization apparatus according to a second embodiment of the present disclosure. As shown in FIG. 2, the method includes:
  • the phase difference detecting module is configured to obtain a phase difference between the system clock and the line clock according to the system clock and the line clock.
  • the rising edge detection module determines the time difference between the rising edge of the packet header flag of the 1588 packet and the rising edge of the current period of the line clock under the line clock.
  • a timestamp sampling module is configured to generate a timestamp associated with the 1588 packet at a system clock.
  • the timestamp compensation module is configured to compensate the generated timestamp by using the phase difference and the time difference to make it consistent with the line clock.
  • the PMA/PCS module is configured to generate a packet header flag of the 1588 packet under the line clock, and send the generated packet header flag to the system clock domain.
  • An exemplary working principle of the device is as follows:
  • the PMA/PCS module receives the signal from the line interface and performs corresponding processing to obtain the received message, and generates the packet header flag of the received message, and sends it to the timestamp sampling module and the rising edge detection module.
  • the rising edge detection module determines the time difference between the rising edge of the packet header flag and the rising edge of the current period of the line clock by detecting the rising edge of the packet header flag and the rising edge of the current period of the line clock under the line clock. And sent to the timestamp compensation module.
  • the timestamp sampling module receives the packet header flag, and performs timestamp sampling on the received packet header flag at the system time, and obtains a timestamp associated with the 1588 packet, and sends the timestamp to the timestamp compensation module.
  • the stamp is the rising edge time of the rising edge of the next cycle of the system clock after receiving the message header flag.
  • the time stamp compensation module compares the phase difference and the time difference. If the phase difference is greater than the time difference, the time stamp is subtracted from the phase difference to obtain a compensated time stamp. Otherwise, the time stamp is subtracted from the phase difference and the system clock period to obtain compensation. Timestamp. Finally, the compensated timestamp is saved as the reception time of the received message.
  • the received packet is the received 1588 packet.
  • the PMA/PCS module In the packet sending direction, when the PMA/PCS module receives the sent packet, it generates the packet header flag of the sent packet, and sends it to the timestamp sampling module and the rising edge detection module.
  • the rising edge detection module determines the time difference between the rising edge of the packet header flag and the rising edge of the current period of the line clock by detecting the rising edge of the packet header flag and the rising edge of the current period of the line clock under the line clock. And sent to the timestamp compensation module.
  • the timestamp sampling module receives the packet header flag, and performs timestamp sampling on the received packet header flag at the system time, and obtains a timestamp associated with the 1588 packet, and sends the timestamp to the timestamp compensation module.
  • the stamp is the rising edge time of the rising edge of the next cycle of the system clock after receiving the message header flag.
  • the time stamp compensation module compares the phase difference with the time difference, if the phase difference is greater than The time difference is subtracted from the time stamp and the phase difference to obtain the compensated time stamp. Otherwise, the time stamp is subtracted from the phase difference and the system clock period to obtain the compensated time stamp. Finally, the compensated timestamp is added to the transmitted message as the time of transmission of the transmitted message.
  • the above sent packet is the transmitted 1588 packet.
  • the 1588-based time synchronization device provided by the present disclosure has high precision and can achieve synchronization of ns level or even ps level.
  • the system includes a 1588 transceiver module, a 1588 message parsing and time stamp processing module, an interface conversion module, and a PMA/PCS.
  • the module, the time stamp sampling module and the clock circuit also include a phase difference detection module of the line clock and the system clock, a rising edge detection module, a comparison module and a time stamp compensation module.
  • the time stamp compensation module of the embodiment of FIG. 2 is divided into two parts, one is a comparison module for comparing the phase difference and the time difference, and the other is a time stamp compensation module for compensating the time stamp.
  • the 1588 transceiver module is responsible for sending and receiving 1588 packets. After the 1588 packet parsing and timestamp processing module parses out the 1588 packet, the timestamp is added to the packet sent by the 1588 transceiver module, and the storage is from the interface conversion module.
  • the timestamp and timestamp of the message are obtained from the timestamp compensation module; the interface conversion module mainly performs interface conversion to convert the PMA/PCS message to the system clock domain; the PMA/PCS module converts the signal received from the line interface
  • the 8-bit data is sent to the interface conversion module, and the message received from the interface conversion module is converted into a signal and sent to the line interface, and the PMA/PCS module generates the packet header flag receive_sof and send_sof for sending and receiving packets to the timestamp sampling module.
  • the time stamp is sampled and sent to the rising edge detection module to determine the time difference between the rising edge corresponding to the receive_sof or send_sof and the rising edge of the current period of the line clock.
  • the timestamp of the timestamp sampling module is generated by the system clock; the phase difference detection module performs phase difference detection on the system clock and the line clock to obtain the phase difference between the two, and sends the phase difference to the comparison module; the comparison module compares the phase difference and the time difference, time The stamp compensation module compensates the time stamp of the time stamp sampling module according to the comparison result of the comparison module, and obtains a high-precision time stamp.
  • the clock circuit is used to synchronize the source device clock and generate the system clock.
  • Receive_sof and send_sof (hereinafter collectively referred to as sof) are generated in the line clock domain, and their rising edges are generally lagging behind the line clock.
  • the sof of the actual message should be aligned with the rising edge of the line clock, so the phase difference between the line clock and the system clock should be compensated instead of the difference between the generated sof and the rising edge of the system clock.
  • An exemplary compensation method the time of the sof lag line clock is recorded as ⁇ t2, and the phase difference between the line clock and the system clock is recorded as ⁇ t1.
  • the PMA/PCS module processes the signal received from the line interface, and sends the received packet to the interface conversion module; generates the packet header flag receive_sof, and sends the receive_sof to the rising edge.
  • Detection module and time stamp sampling module The rising edge detection module measures the time difference between the rising edge corresponding to the receive_sof and the rising edge of the current period of the line clock under the line clock, and sends it to the comparison module.
  • the timestamp sampling module performs timestamp sampling on the received receive_sof at the system clock, and obtains the time associated with the 1588 packet.
  • the timestamp is the rising edge time of the rising edge of the next cycle of the system clock after receiving receive_sof.
  • the time stamp compensation module compensates the time stamp from the time stamp sampling module by using the comparison module to compare the phase difference and the time difference, and obtains a high-precision time stamp, that is, if the phase difference is greater than the time difference, the time stamp is The phase difference is subtracted, and the compensated timestamp is obtained. Otherwise, the timestamp is subtracted from the phase difference and the system clock period to obtain the compensated timestamp, and the compensated timestamp is sent to the 1588 message parsing and timestamp processing module. .
  • the 1588 packet parsing and timestamp processing module receives the received packet from the line clock domain to the system clock domain by the interface conversion module. If the packet is parsed as 1588, the packet is saved from the timestamp compensation module. The timestamp after the compensation is used as the receiving time of the 1588 message.
  • 1588 packet parsing and time stamp processing module receives the sending packet from the 1588 transceiver module and sends the packet to the interface conversion module.
  • the interface conversion module converts the message from the system clock domain to the line clock domain and sends it to the PMA/PCS module.
  • the PMA/PCS module receives the sent packet from the interface conversion module, it generates the packet header flag send_sof of the sent packet, and sends it to the rising edge detection module and the timestamp sampling module.
  • the rising edge detection module measures the time difference between the rising edge corresponding to the send_sof and the rising edge of the current period of the line clock under the line clock, and sends it to the comparison module.
  • the timestamp sampling module performs timestamp sampling on the received send_sof under the system clock, and obtains a timestamp associated with the 1588 message, and sends the timestamp to the timestamp compensation module, where the timestamp is after the send_sof is received, the system clock The rising edge time corresponding to the rising edge of the next cycle.
  • the time stamp compensation module uses the comparison module to compare the phase difference and the time difference to perform time stamp compensation. For example, if the phase difference is greater than the time difference, the time stamp is subtracted from the phase difference to obtain a compensated time stamp. Otherwise, The timestamp is subtracted from the phase difference and the system clock period to obtain a compensated timestamp.
  • the timestamp compensation module sends the compensated timestamp to the 1588 message parsing and timestamp processing module. After the packet is of a certain length, the 1588 packet parsing and timestamp processing module adds the compensated timestamp obtained by the timestamp compensation module to the 1588 packet after determining that the sent packet is a 1588 packet. As the sending time of the 1588 message.
  • Phase difference detection can be realized by high frequency clock or TDC technology, which can make 1588 synchronization accuracy reach ns level, even ps level.
  • Figure 6 is a block diagram of a device for applying a device to a GE electrical port according to a fourth embodiment of the present disclosure. As shown in Figure 6, the device of the embodiment of the present disclosure is applied to a GE electrical port, and the hardware module portion thereof includes:
  • PMA/PCS module Receive direction, receive signals from GE electrical ports, perform AD conversion, digital equalization, and decode, obtain 8bit parallel data, and generate receive message header flag receive_sof; send direction, encode 8bit parallel data, shape Then, the DA is converted into an analog signal, which is sent out through the GE electrical port, and generates a send message header flag send_sof; to ensure that send_sof/receive_sof, there is no fifo between the generated location and the GE electrical port.
  • Interface conversion module performs clock domain and bus conversion, that is, performs signal conversion between the system clock domain and the line clock domain.
  • the 1588 packet parsing and timestamp processing module is responsible for packet parsing. After the 1588 packet is identified, the corresponding timestamp is processed.
  • 1588 transceiver module including the sending, response, and termination of 1588 packets.
  • Timestamp sampling module First, there is a timestamp counter under the 125M clock of the system. When the receive_sof or send_sof arrives, the rising edge timestamp is recorded, and the timestamp of the record is sent to the timestamp compensation module for compensation.
  • Phase difference detection module detects the phase difference between the system 125M clock and the line 125M clock.
  • the phase difference is a fixed value when the clock is locked.
  • the detection requires high precision and can be realized by a high frequency clock or TDC technology.
  • the rising edge detection module determines the time difference between the rising edge corresponding to send_sof and the rising edge of the current period of the line clock under the line clock.
  • Comparison module compares the phase difference determined by the phase difference detection module with the time difference determined by the rising edge detection module.
  • Timestamp compensation module The generation of sof and timestamp sampling use different low frequency clocks with low precision. It is necessary to compensate the phase difference between the two clocks. The higher the phase difference precision, the more accurate the time stamp after compensation. When compensating, the compensation method that is not used can be used according to the comparison result of the comparison module.
  • the accuracy of the timestamp sampling is 8 ns, and when the phase difference detection accuracy reaches 100 ps, the compensated timestamp precision can be increased to 100 ps.
  • Phase-locked loop and clock chip (equivalent to clock circuit): Synchronize the source device clock and generate the system clock.
  • the accuracy of the clock synchronization and the stability of the generated system clock directly affect the phase difference detection accuracy, which in turn affects the time stamp accuracy and time synchronization accuracy. Therefore, a high-performance phase-locked loop and a clock chip are required.
  • the 1588-based time synchronization method compensates the timestamp associated with the 1588 message by utilizing the phase difference between the system clock and the line clock, so that the compensated timestamp is consistent with the line clock, and the high-precision time is achieved.
  • the purpose of synchronization is a simple and small period of time.

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Abstract

本公开涉及一种基于1588的时间同步方法及系统，涉及通信领域，所述方法包括：通过对系统时钟和线路时钟的相位差进行检测处理，得到所述系统时钟和所述线路时钟之间的相位差；在线路时钟下，确定1588报文的报文头标志对应的上升沿与线路时钟当前周期的上升沿的时间差；在系统时钟下，生成与所述1588报文相关的时间戳；利用所述相位差和所述时间差，对所生成的时间戳进行补偿，使之与线路时钟一致。通过对与1588报文相关的时间戳进行补偿，使补偿后的时间戳与线路时钟一致，达到高精度时间同步的目的。

Description

一种基于1588的时间同步方法及装置 技术领域
本公开涉及通信领域，特别涉及一种基于1588的时间同步方法及装置。
背景技术
随着通信技术的不断发展，对时间同步性能提出了更高的要求，比如，近期人们提出的利用基站提供定位服务要求，时间精度要求在±200ns左右，长期演进技术的升级版(Long Term Evolution-Advanced，LTE-Advanced)的关键技术多点协同传输处理(Coordinated Multipoint Joint Processing，CoMP-JP)中要求相邻基站间的相对时间精度在±500ns左右；未来第五代移动通信技术(The 5th Generation Mobile Communication Technology，5G)系统，可能需要几百ns量级的超高精度时间同步需求；又如，更远期的量子通信技术，需要精度极高的时间测量技术，以降低量子通信系统的误码率，提高其成码率，可能需要百ns以内的时间同步精度。
目前，基于1588v2技术实现的高精度时间同步，只能满足us量级的时间同步需求，但无法满足上述几百ns甚至更高精度的时间同步需求。
发明内容
根据本公开实施例提供的技术方案解决的技术问题是克服相关同步技术中存在的同步精度较低的问题和缺陷。
根据本公开实施例提供的一种基于1588的时间同步方法，包括：
根据系统时钟和线路时钟，得到所述系统时钟和所述线路时钟之间的相位差；
在线路时钟下，确定1588报文的报文头标志对应的上升沿与线路时钟当前周期的上升沿的时间差；
在系统时钟下，生成与所述1588报文相关的时间戳；
利用所述相位差和所述时间差，对所生成的时间戳进行补偿，使之与线路时钟一致。
优选地，所述在线路时钟下，确定1588报文的报文头标志对应的上升沿与线路时钟当前周期的上升沿的时间差的步骤之前，还包括：
在线路时钟下，生成所述1588报文的报文头标志，并将所生成的报文头标志发送至系统时钟域。
优选地，所述在线路时钟下，确定1588报文的报文头标志对应的上升沿与线路时钟当前周期的上升沿的时间差的步骤包括：
在线路时钟下，检测所述报文头标志对应的上升沿和所述线路时钟的当前周期的上升沿；
根据检测到的所述报文头标志对应的上升沿和所述线路时钟的当前周期的上升沿，确 定所述报文头标志对应的上升沿和所述线路时钟的当前周期的上升沿的时间差。
优选地，所述在系统时钟下，生成与所述1588报文相关的时间戳的步骤包括：
在系统时钟下，接收所述报文头标志，并通过对所收到的报文头标志进行时间戳采样，得到与所述1588报文相关的时间戳。
优选地，所述利用所述相位差和所述时间差，对所生成的时间戳进行补偿，使之与线路时钟一致的步骤包括：
比较所述相位差与所述时间差；
若所述相位差大于所述时间差，则将所述时间戳与所述相位差相减，得到补偿后的时间戳；
否则，将所述时间戳与所述相位差、系统时钟周期相减，得到补偿后的时间戳。
根据本公开实施例提供的存储介质，其存储用于实现上述基于1588的时间同步方法的程序。
根据本公开实施例提供的一种基于1588的时间同步装置，包括：
相位差检测模块，用于根据系统时钟和线路时钟，得到所述系统时钟和所述线路时钟之间的相位差。
上升沿检测模块，在线路时钟下，确定1588报文的报文头标志对应的上升沿与线路时钟当前周期的上升沿的时间差；
时间戳采样模块，用于在系统时钟下，生成与所述1588报文相关的时间戳；
时间戳补偿模块，用于利用所述相位差和所述时间差，对所生成的时间戳进行补偿，使之与线路时钟一致。
优选地，还包括：
PMA/PCS模块，用于在线路时钟下，生成所述1588报文的报文头标志，并将所生成的报文头标志发送至系统时钟域。
优选地，所述上升沿检测模块在线路时钟下，检测所述报文头标志对应的上升沿和所述线路时钟的当前周期的上升沿，并根据检测到的所述报文头标志对应的上升沿和所述线路时钟的当前周期的上升沿，确定所述报文头标志对应的上升沿和所述线路时钟的当前周期的上升沿的时间差。
优选地，所述时间戳采样模块用于在系统时钟下，接收所述报文头标志，并通过对所收到的报文头标志进行时间戳采样，得到与所述1588报文相关的时间戳。
优选地，所述时间戳补偿模块比较所述相位差与所述时间差，若所述相位差大于所述时间差，则将所述时间戳与所述相位差相减，得到补偿后的时间戳，否则将所述时间戳与所述相位差、系统时钟周期相减，得到补偿后的时间戳。
本公开实施例提供的技术方案具有如下有益效果：
通过利用系统时钟和线路时钟的相位差对与1588报文相关的时间戳进行补偿，使补偿后的时间戳与线路时钟一致，达到高精度时间同步的目的。
附图说明
图1是本公开第一实施例提供的基于1588的时间同步方法框图；
图2是本公开第二实施例提供的基于1588的时间同步装置框图；
图3是本公开第三实施例提供的基于1588的时间同步装置的模块框图；
图4是本公开第四实施例提供的sof在线路时钟和系统时钟之间时的时序图；
图5是本公开第四实施例提供的sof在系统时钟后的时序图；
图6是本公开第四实施例提供的将装置应用到GE电口的框图。
具体实施方式
以下结合附图对本公开的优选实施例进行详细说明，应当理解，以下所说明的优选实施例仅用于说明和解释本公开，并不用于限定本公开。
图1是本公开第一实施例提供的基于1588的时间同步方法框图，如图1所示，步骤包括：
步骤S101：根据系统时钟和线路时钟，得到系统时钟和线路时钟之间的相位差。
示例性而言，通过对系统时钟和线路时钟进行相位差检测，得到系统时钟和线路时钟之间的相位差。
步骤S102：在线路时钟下，确定1588报文的报文头标志对应的上升沿与线路时钟当前周期的上升沿的时间差。
在确定所述时间差之前，在线路时钟下，生成1588报文的报文头标志，并将所生成的报文头标志发送至系统时钟域。然后，在线路时钟下，检测所述报文头标志对应的上升沿和线路时钟的当前周期的上升沿，并根据检测到的所述报文头标志对应的上升沿和所述线路时钟的当前周期的上升沿，确定所述报文头标志对应的上升沿和所述线路时钟的当前周期的上升沿的时间差。也就是说，在线路时钟下，生成报文头标志，并检测或测量报文头标志上升沿与线路时钟当前周期上升沿的时间差，以便利用所得到的时间差，决定补偿值。
步骤S103：在系统时钟下，生成与所述1588报文相关的时间戳。
在系统时钟域下，接收报文头标志，并通过对所收到的报文头标志进行时间戳采样，得到与1588报文相关的时间戳，即在系统时钟域下，收到报文头标志后，系统时钟的第一个上升沿对应的时间。
步骤S104：利用相位差，对所生成的时间戳进行补偿，使之与线路时钟一致。
示例性而言，比较相位差与时间差，若相位差大于时间差，则将时间戳与相位差相减，得到补偿后的时间戳；否则，将时间戳与相位差、系统时钟周期相减，得到补偿后的时间戳。
对于报文发送方向，将所得到的补偿后的时间戳添加到所述1588报文中作为所述1588报文的发送时间。
对于报文接收方向，保存所得到的补偿后的时间戳，作为收到的1588报文的接收时间。
本领域普通技术人员可以理解，实现上述实施例方法中的全部或部分步骤是可以通过程序来指令相关的硬件来完成，所述的程序可以存储于计算机可读取存储介质中，该程序在执行时，包括步骤S101至步骤S104。其中，所述的存储介质可以为ROM/RAM、磁碟、光盘等。
图2是本公开第二实施例提供的基于1588的时间同步装置框图，如图2所示，包括：
相位差检测模块，用于根据系统时钟和线路时钟，得到系统时钟和线路时钟之间的相位差。
上升沿检测模块，在线路时钟下，确定1588报文的报文头标志对应的上升沿与线路时钟当前周期的上升沿的时间差。
时间戳采样模块，用于在系统时钟下，生成与所述1588报文相关的时间戳。
时间戳补偿模块，用于利用相位差和所述时间差，对所生成的时间戳进行补偿，使之与线路时钟一致。
还包括：
PMA/PCS模块，用于在线路时钟下，生成1588报文的报文头标志，并将所生成的报文头标志发送至系统时钟域。
所述装置的示例性工作原理如下：
报文接收方向：PMA/PCS模块从线路接口收到信号并进行相应处理，得到接收报文，并生成所述接收报文的报文头标志，发送至时间戳采样模块和上升沿检测模块。上升沿检测模块在线路时钟下通过检测报文头标志对应的上升沿和线路时钟的当前周期的上升沿，确定报文头标志对应的上升沿和所述线路时钟的当前周期的上升沿的时间差，并发送至时间戳补偿模块。时间戳采样模块收到报文头标志，在系统时间下对所收到的报文头标志进行时间戳采样，得到与1588报文相关的时间戳，并发送至时间戳补偿模块，所述时间戳即收到报文头标志后，系统时钟的下一周期上升沿对应的上升沿时间。时间戳补偿模块比较相位差与时间差，若相位差大于时间差，则将时间戳与相位差相减，得到补偿后的时间戳，否则将时间戳与相位差、系统时钟周期相减，得到补偿后的时间戳。最后，保存该补偿后的时间戳，作为该接收报文的接收时间。上述接收报文为接收的1588报文。
报文发送方向，PMA/PCS模块收到发送报文时，生成所述发送报文的报文头标志，并发送至时间戳采样模块和上升沿检测模块。上升沿检测模块在线路时钟下通过检测报文头标志对应的上升沿和线路时钟的当前周期的上升沿，确定报文头标志对应的上升沿和所述线路时钟的当前周期的上升沿的时间差，并发送至时间戳补偿模块。时间戳采样模块收到报文头标志，在系统时间下对所收到的报文头标志进行时间戳采样，得到与1588报文相关的时间戳，并发送至时间戳补偿模块，所述时间戳即收到报文头标志后，系统时钟的下一周期上升沿对应的上升沿时间。时间戳补偿模块比较相位差与时间差，若相位差大于 时间差，则将时间戳与相位差相减，得到补偿后的时间戳，否则将时间戳与相位差、系统时钟周期相减，得到补偿后的时间戳。最后，该补偿后的时间戳将添加至发送报文中，作为该发送报文的发送时间。上述发送报文为发送的1588报文。
本公开提供的基于1588的时间同步装置，精度高，可达到ns级甚至ps级的同步。
图3是本公开第三实施例提供的基于1588的时间同步装置的模块框图，如图3所示，包括1588收发包模块、1588报文解析及时间戳处理模块、接口转换模块、PMA/PCS模块、时间戳采样模块和时钟电路，还包括线路时钟和系统时钟的相位差检测模块、上升沿检测模块、比较模块和时间戳补偿模块。本实施例将图2实施例的时间戳补偿模块分为两部分，一部分为用于比较相位差和时间差的比较模块，一部分为用于补偿时间戳的时间戳补偿模块。
其中，1588收发包模块负责1588报文的发送和接收；1588报文解析及时间戳处理模块解析出1588报文后，添加时间戳到1588收发包模块发送的报文中，存储来自接口转换模块的报文的时间戳，时间戳均从时间戳补偿模块获取；接口转换模块主要进行接口转换，将PMA/PCS的报文转换到系统时钟域；PMA/PCS模块将从线路接口接收的信号转换成8bit数据，发给接口转换模块，从接口转换模块接收的报文转换成信号发送到线路接口，同时PMA/PCS模块生成收发报文的报文头标志receive_sof和send_sof送给时间戳采样模块进行时间戳采样，并送至上升沿检测模块确定receive_sof或send_sof对应的上升沿和所述线路时钟的当前周期的上升沿的时间差。时间戳采样模块进行采样的时间戳由系统时钟生成；相位差检测模块对系统时钟和线路时钟进行相位差检测，得到二者的相位差，送给比较模块；比较模块比较相位差和时间差，时间戳补偿模块根据所述比较模块的比较结果对时间戳采样模块的时间戳进行相应补偿，得到高精度的时间戳。时钟电路用来同步源端装置时钟，并生成系统时钟。
receive_sof和send_sof(下面统称sof)在线路时钟域生成，其上升沿一般都会比线路时钟滞后。而实际报文的sof应该与线路时钟上升沿对齐，所以要补偿线路时钟和系统时钟的相位差，而不是生成的sof与系统时钟上升沿的差。
示例性补偿方式：sof滞后线路时钟的时间记为Δt2，线路时钟与系统时钟的相位差记为Δt1。图4是本公开第四实施例提供的sof在线路时钟和系统时钟之间时的时序图，如图4所示，当0≤Δt2<Δt1时，时间戳记为为t2-Δt1；图5是本公开第四实施例提供的sof在系统时钟后的时序图，如图5所示，当Δt2>＝Δt1时，时间戳记为t3-Tclk_sys-Δt1，Tclk_sys为clk_sys的时钟周期。
对于报文接收方向：PMA/PCS模块对从线路接口收到的信号进行处理，并将得到的接收报文发送至接口转换模块；生成报文的报文头标志receive_sof，将receive_sof发送至上升沿检测模块和时间戳采样模块。上升沿检测模块在线路时钟下测量receive_sof对应的上升沿和所述线路时钟的当前周期的上升沿的时间差，并发送至比较模块。时间戳采样模块在系统时钟下对所收到的receive_sof进行时间戳采样，得到与1588报文相关的时间 戳，并发送至时间戳补偿模块，所述时间戳即收到receive_sof后，系统时钟的下一周期上升沿对应的上升沿时间。时间戳补偿模块利用比较模块对相位差和时间差的比较结果，对来自时间戳采样模块的时间戳进行补偿，得到高精度的时间戳，也就是说，若相位差大于时间差，则将时间戳与相位差相减，得到补偿后的时间戳，否则将时间戳与相位差、系统时钟周期相减，得到补偿后的时间戳，该补偿后的时间戳发送至1588报文解析及时间戳处理模块。最后，1588报文解析及时间戳处理模块收到接口转换模块从线路时钟域转换到系统时钟域的接收报文，若解析出该报文为1588报文，则保存从时间戳补偿模块得到的补偿后的时间戳，作为该1588报文的接收时间。
对于报文发送方向：1588报文解析及时间戳处理模块收到来自1588收发包模块的发送报文，并将该报文发送至接口转换模块。接口转换模块将该报文从系统时钟域转换到线路时钟域后，发送至PMA/PCS模块。PMA/PCS模块从接口转换模块收到发送报文时，生成该发送报文的报文头标志send_sof，并发送至上升沿检测模块和时间戳采样模块。上升沿检测模块在线路时钟下测量send_sof对应的上升沿和所述线路时钟的当前周期的上升沿的时间差，并发送至比较模块。时间戳采样模块在系统时钟下对所收到的send_sof进行时间戳采样，得到与1588报文相关的时间戳，并发送至时间戳补偿模块，所述时间戳即收到send_sof后，系统时钟的下一周期上升沿对应的上升沿时间。时间戳补偿模块利用比较模块对相位差和时间差的比较结果，进行时间戳补偿，示例性而言，若相位差大于时间差，则将时间戳与相位差相减，得到补偿后的时间戳，否则将时间戳与相位差、系统时钟周期相减，得到补偿后的时间戳，时间戳补偿模块将该补偿后的时间戳发送至1588报文解析及时间戳处理模块。由于报文具有一定长度，因此1588报文解析及时间戳处理模块在确定该发送报文为1588报文后，将从时间戳补偿模块得到的补偿后的时间戳添加至该1588报文中，作为该1588报文的发送时间。
相位差检测精度越高，时间戳精度越高，1588时间同步的精度也越高。相位差检测可采用高频率时钟或TDC技术来实现，可使1588同步精度达到ns级，甚至ps级。
图6是本公开第四实施例提供的将装置应用到GE电口的框图，如图6所示，将本公开实施例的装置应用到GE电口，其硬件模块部分包括：
PMA/PCS模块：接收方向，从GE电口接收信号，进行AD转换，数字均衡，解码，得到8bit的并行数据，同时生成接收报文头标志receive_sof；发送方向，将8bit并行数据进行编码，整形，然后DA转换成模拟信号，通过GE电口发送出去，并生成发送报文头标志send_sof；要保证send_sof/receive_sof，生成位置与GE电口之间没有fifo。
接口转换模块：进行时钟域和总线转换，即进行系统时钟域和线路时钟域之间的信号转换。
1588报文解析及时间戳处理模块：负责报文解析，识别到1588报文后，进行相应的时间戳处理。
1588收发包模块：包括1588报文的发送、响应及终结。
时间戳采样模块：首先，有一个系统125M时钟下的时间戳计数器，当receive_sof或send_sof到来时记录其上升沿时间戳，记录的时间戳，送到时间戳补偿模块进行补偿。
相位差检测模块：检测系统125M时钟和线路125M时钟的相位差，该相位差在时钟锁定时是固定值，其检测需要高精度，可用高频率时钟或TDC技术来实现。
上升沿检测模块：在线路时钟下确定send_sof对应的上升沿和所述线路时钟的当前周期的上升沿的时间差。
比较模块：比较相位差检测模块确定的相位差和上升沿检测模块确定的时间差。
时间戳补偿模块：sof的生成和时间戳采样使用不同的低频时钟，精度较低，需要补偿两个时钟的相位差，相位差精度越高，补偿后的时间戳越精准。补偿时，可根据比较模块的比较结果，采用不用的补偿方式。
本实施例中，时间戳采样的精度是8ns，当相位差检测精度达到100ps时，补偿后的时间戳精度即可提高到100ps。
锁相环和时钟芯片(相当于时钟电路)：同步源端装置时钟，并生成系统时钟。时钟同步精度及所产生的系统时钟的稳定性，直接影响相位差检测精度，进而影响时间戳精度和时间同步精度，因此需要高性能的锁相环和时钟芯片。
尽管上文对本公开进行了详细说明，但是本公开不限于此，本技术领域技术人员可以根据本公开的原理进行各种修改。因此，凡按照本公开原理所作的修改，都应当理解为落入本公开的保护范围。
工业实用性
本公开实施例提供的基于1588的时间同步方法，通过利用系统时钟和线路时钟的相位差对与1588报文相关的时间戳进行补偿，使补偿后的时间戳与线路时钟一致，达到高精度时间同步的目的。

Claims (11)

  1. 一种基于1588的时间同步方法，包括：
    根据系统时钟和线路时钟，得到所述系统时钟和所述线路时钟之间的相位差；
    在线路时钟下，确定1588报文的报文头标志对应的上升沿与线路时钟当前周期的上升沿的时间差；
    在系统时钟下，生成与所述1588报文相关的时间戳；
    利用所述相位差和所述时间差，对所生成的时间戳进行补偿，使之与线路时钟一致。
  2. 根据权利要求1所述的方法，所述在线路时钟下，确定1588报文的报文头标志对应的上升沿与线路时钟当前周期的上升沿的时间差的步骤之前，还包括：
    在线路时钟下，生成所述1588报文的报文头标志，并将所生成的报文头标志发送至系统时钟域。
  3. 根据权利要求2所述的方法，所述在线路时钟下，确定1588报文的报文头标志对应的上升沿与线路时钟当前周期的上升沿的时间差的步骤包括：
    在线路时钟下，检测所述报文头标志对应的上升沿和所述线路时钟的当前周期的上升沿；
    根据检测到的所述报文头标志对应的上升沿和所述线路时钟的当前周期的上升沿，确定所述报文头标志对应的上升沿和所述线路时钟的当前周期的上升沿的时间差。
  4. 根据权利要求2或3所述的方法，所述在系统时钟下，生成与所述1588报文相关的时间戳的步骤包括：
    在系统时钟下，接收所述报文头标志，并通过对所收到的报文头标志进行时间戳采样，得到与所述1588报文相关的时间戳。
  5. 根据权利要求1所述的方法，所述利用所述相位差和所述时间差，对所生成的时间戳进行补偿，使之与线路时钟一致的步骤包括：
    比较所述相位差与所述时间差；
    若所述相位差大于所述时间差，则将所述时间戳与所述相位差相减，得到补偿后的时间戳；
    否则，将所述时间戳与所述相位差、系统时钟周期相减，得到补偿后的时间戳。
  6. 一种基于1588的时间同步装置，包括：
    相位差检测模块，设置为根据系统时钟和线路时钟，得到所述系统时钟和所述线路时钟之间的相位差。
    上升沿检测模块，在线路时钟下，确定1588报文的报文头标志对应的上升沿与线路时钟当前周期的上升沿的时间差；
    时间戳采样模块，设置为在系统时钟下，生成与所述1588报文相关的时间戳；
    时间戳补偿模块，设置为利用所述相位差和所述时间差，对所生成的时间戳进行补偿，使之与线路时钟一致。
  7. 根据权利要求6所述的装置，还包括：
    PMA/PCS模块，设置为在线路时钟下，生成所述1588报文的报文头标志，并将所生成的报文头标志发送至系统时钟域。
  8. 根据权利要求7所述的装置，所述上升沿检测模块在线路时钟下，检测所述报文头标志对应的上升沿和所述线路时钟的当前周期的上升沿，并根据检测到的所述报文头标志对应的上升沿和所述线路时钟的当前周期的上升沿，确定所述报文头标志对应的上升沿和所述线路时钟的当前周期的上升沿的时间差。
  9. 根据权利要求7或8所述的装置，所述时间戳采样模块设置为在系统时钟下，接收所述报文头标志，并通过对所收到的报文头标志进行时间戳采样，得到与所述1588报文相关的时间戳。
  10. 根据权利要求9所述的装置，所述时间戳补偿模块比较所述相位差与所述时间差，若所述相位差大于所述时间差，则将所述时间戳与所述相位差相减，得到补偿后的时间戳，否则将所述时间戳与所述相位差、系统时钟周期相减，得到补偿后的时间戳。
  11. 一种存储介质，设置为存储程序代码，所述程序代码用于执行权利要求1至5中任一项所述的基于1588的时间同步方法。
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