WO2022052588A1 - 电容结构的制备方法及电容器 - Google Patents

电容结构的制备方法及电容器 Download PDF

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Publication number
WO2022052588A1
WO2022052588A1 PCT/CN2021/103546 CN2021103546W WO2022052588A1 WO 2022052588 A1 WO2022052588 A1 WO 2022052588A1 CN 2021103546 W CN2021103546 W CN 2021103546W WO 2022052588 A1 WO2022052588 A1 WO 2022052588A1
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Prior art keywords
layer
semiconductor substrate
capacitor
mask layer
projection
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PCT/CN2021/103546
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English (en)
French (fr)
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盛超军
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长鑫存储技术有限公司
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Priority to US17/468,812 priority Critical patent/US11784216B2/en
Publication of WO2022052588A1 publication Critical patent/WO2022052588A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Definitions

  • the present disclosure relates to the technical field of semiconductor device preparation, and in particular, to a preparation method of a capacitor structure and a capacitor.
  • the capacitor hole structure is usually formed by a silicon nitride layer and two layers of silicon dioxide under the action of a hard mask.
  • Single cylindrical support structure For example, a support layer is directly formed on the bottom wire of the substrate as the bottom dielectric layer of the capacitor, and then two sacrificial layers are formed in sequence, and a hole structure is formed through an etching process, and the hole structure extends to the wire structure in the substrate, and then in the A lower electrode layer, a dielectric layer and an upper electrode layer are formed on the hole structure, thereby forming a single cylindrical support structure.
  • a main objective of the present disclosure is to provide a method for preparing a capacitor structure, which can effectively prevent the support structure from falling off while increasing the height of the capacitor structure.
  • Another object of the present disclosure is to provide a capacitor with a stable support structure, which can meet the demands of the continuous shrinking of semiconductor devices.
  • a method for preparing a capacitor structure including: providing a semiconductor substrate; forming a first mask layer on the semiconductor substrate, and on the first mask layer forming a plurality of uniformly distributed first circular hole patterns; based on the first circular hole patterns, etched uniformly distributed first openings on the semiconductor substrate, each of the first openings having on the semiconductor substrate a first circular projection; forming a second mask layer on a side of the first opening away from the semiconductor substrate, and forming a plurality of second patterns on the second mask layer; based on the second pattern, and uniformly distributed second openings are etched on the semiconductor substrate, while continuing to etch the first openings, so that the first openings and the second openings have the same depth, each of the second openings There is a second projection on the semiconductor substrate; wherein, the outline of the second projection intersects the outline of four adjacent first circular projections respectively; etching the first opening and the The second opening forms a capacitor hole; a lower electrode
  • a capacitor comprising: a semiconductor substrate; capacitor holes provided on the semiconductor substrate and arranged in an array; wherein each of the capacitor holes is composed of four circular first An opening and a second opening are formed; the projection of each of the first openings on the semiconductor substrate is a first circular projection, the projection of the second opening on the semiconductor substrate is a second projection, the The contour line of the second projection intersects the contour lines of the four adjacent first circular projections respectively; the continuous outer contours of the first circular projection and the second projection form the outer contour of the capacitor hole.
  • a projected profile on a semiconductor substrate and a lower electrode layer, a dielectric layer, and an upper electrode layer sequentially deposited in the capacitive hole.
  • the present disclosure has at least one of the following advantages and positive effects:
  • the capacitor holes formed by the etched first openings and the second openings are rhombus-shaped structures instead of a single cylindrical structure, which can provide Higher support stability, effectively avoid breakage and shedding of the support structure.
  • FIG. 1 is a schematic structural diagram of a semiconductor substrate provided in a method for fabricating a capacitor structure in an exemplary embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of forming a first line in a method for fabricating a capacitor structure according to an exemplary embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of forming a second line in a method for fabricating a capacitor structure according to an exemplary embodiment of the present disclosure
  • FIG. 4 is a schematic structural diagram of forming a first opening in a method for fabricating a capacitor structure according to an exemplary embodiment of the present disclosure
  • Fig. 5 is the top view of Fig. 4;
  • FIG. 6 is a schematic structural diagram of disposing a second mask layer in a method for fabricating a capacitor structure according to an exemplary embodiment of the present disclosure
  • Fig. 7 is the top view schematic diagram of Fig. 6;
  • FIG. 8 is a schematic structural diagram of a pattern of forming a capacitor hole in a method for fabricating a capacitor structure in an exemplary embodiment of the present disclosure
  • Fig. 9 is the top view of Fig. 8.
  • FIG. 10 is a schematic structural diagram of forming a capacitor hole in a method for preparing a double-sided capacitor with a triangular support structure disclosed in the present disclosure
  • Figure 11 is a schematic top view of Figure 10
  • FIG. 12 is a schematic structural diagram of forming a conductive layer in a capacitor hole in a method for fabricating a capacitor structure in an exemplary embodiment of the disclosure
  • Fig. 13 is the top view of Fig. 12;
  • FIG. 14 is a schematic structural diagram of forming a conductive layer in a method for fabricating a capacitor structure in an exemplary embodiment of the disclosure
  • Figure 15 is a schematic top view of 14
  • FIG. 16 is a schematic diagram after removing the sacrificial layer between the support layer and the lower electrode layer on the top of part of the side peripheral wall of the capacitor hole in the method for fabricating the capacitor structure according to an exemplary embodiment of the disclosure;
  • Figure 17 is a schematic top view of Figure 16
  • FIG. 18 is a schematic structural diagram of a capacitor formed in an exemplary embodiment of the disclosure.
  • FIG. 19 is a schematic cross-sectional view of one of the capacitor holes along A-A in FIG. 18;
  • FIG. 20 is a flow chart of a method for fabricating a capacitor structure of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments can be embodied in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.
  • FIG. 1 to FIG. 19 respectively show schematic diagrams of the manufacturing process of the capacitor structure in the present disclosure
  • FIG. 20 shows a flowchart of the manufacturing method of the capacitor structure in the present disclosure.
  • the preparation method of the capacitor structure of the present disclosure includes:
  • Step S200 providing a semiconductor substrate 1 .
  • Step S400 forming a first mask layer 2 on the semiconductor substrate 1 , and forming a plurality of uniformly distributed first circular hole patterns on the first mask layer 2 .
  • Step S600 Based on the first circular hole pattern, uniformly distributed first openings 25 are etched on the semiconductor substrate 1 , and each first opening 25 has a first circular projection on the semiconductor substrate 1 .
  • Step S800 forming a second mask layer 3 on the side of the first opening 25 away from the semiconductor substrate 1 , and forming a plurality of second patterns on the second mask layer 3 .
  • Step S1000 Based on the second pattern, uniformly distributed second openings 34 are etched on the semiconductor substrate 1, while continuing to etch the first openings 25 so that the first openings 25 and the second openings 34 have the same depth.
  • Each of the second openings 34 has a second projection on the semiconductor substrate 1 .
  • the contour lines of the second projection intersect with the contour lines of the four adjacent first circular projections respectively.
  • Step S1200 etching the first opening 25 and the second opening 34 to form the capacitor hole 4 .
  • Step S1400 depositing a lower electrode layer, a dielectric layer and an upper electrode layer in the capacitor hole 4 to form a capacitor structure.
  • the capacitor hole 4 formed by the etched first opening 25 and the second opening 34 has a substantially diamond-shaped cross-section. Instead of a single cylindrical structure, it can provide higher support stability and effectively avoid the cracking and falling off of the support structure of the capacitor.
  • the manufacturing method of the capacitor structure of the present disclosure will be described in detail below.
  • the capacitor structure of the embodiment of the present disclosure will be described by taking a double-sided capacitor structure as an example.
  • step S200 is performed: a semiconductor substrate 1 is provided.
  • the semiconductor substrate 1 includes a substrate 11 , a pad, a support layer and a sacrificial layer, and a base mask layer 17 , which are stacked in sequence.
  • the material of the substrate 11 may be silicon, silicon carbide, silicon nitride, silicon-on-insulator, silicon-on-insulator, silicon-germanium-on-insulator, silicon-germanium-on-insulator, germanium-on-insulator, or the like.
  • a plurality of pads, word lines and bit lines of the transistor are formed in the substrate 11, and the plurality of pads are electrically connected to the source electrode of the transistor (not shown in the figure), which is a semiconductor.
  • the device provides the circuit.
  • the support layers and the sacrificial layers are alternately arranged and cover the pads.
  • the sacrificial layer is arranged between the support layers.
  • the support layer and the sacrificial layer may be formed by an atomic deposition process (Atomic Layer Deposition) or a chemical vapor deposition process (Chemical Vapor Deposition).
  • the material of the support layer may include silicon nitride, silicon oxide or silicon oxynitride
  • the material of the sacrificial layer may include silicon nitride, silicon oxide or silicon oxynitride.
  • the materials used for the support layer and the sacrificial layer are different.
  • the material used for the support layer is SiN
  • the material for the sacrificial layer is SiO2. Therefore, in the same etching solution, the two are etched at different rates. In the same etching solution, the corrosion rate of the sacrificial layer is much greater than that of the supporting layer, so that when the sacrificial layer is completely removed, the supporting layer is almost completely retained.
  • the etching solution may be a concentrated hydrofluoric acid solution.
  • two alternating layers of support layers and sacrificial layers are provided, namely a first support layer 12 , a first sacrificial layer 13 , a second support layer 14 , a second sacrificial layer 15 and a third support layer 16 .
  • a first support layer 12 a first sacrificial layer 13
  • a second support layer 14 a second sacrificial layer 15
  • a third support layer 16 a third support layer 16 .
  • three, four, or five alternating layers of support layers and sacrificial layers can also be provided, and those skilled in the art can choose according to actual needs, which is not particularly limited here.
  • the basic mask layer 17 may be provided with one or more layers.
  • the basic mask layer 17 is provided with two layers, which are the first basic mask layer 171 and the second basic mask layer 172 respectively.
  • the pattern of the first opening 25 and the second opening 34 can be transferred to the base mask layer 17 to form a pattern of capacitor holes, and then the pattern of the capacitor holes can be transferred to the semiconductor substrate under the base mask layer 17 On, continue to etch, and finally form a capacitor hole.
  • the material of the base mask layer 17 is generally silicon oxide, silicon nitride, polysilicon or other materials and combinations thereof.
  • step S400 is performed: a first mask layer 2 is formed on the semiconductor substrate 1 , and a plurality of uniformly distributed first circular hole patterns are formed on the first mask layer 2 .
  • forming the first mask layer 2 includes: sequentially depositing and forming a first hard mask layer 21 and a second hard mask layer 23 on the semiconductor substrate 1 .
  • the first hard mask layer 21 is deposited on the semiconductor substrate 1 , specifically, deposited on the surface of the first base mask layer 171 located on the semiconductor substrate 1 .
  • the first organic material layer 22 may also be deposited on the semiconductor substrate, that is, on the first base mask layer 171 .
  • a plurality of parallel first lines are formed along the first direction on the first hard mask layer 21 . The first lines are arranged in parallel at intervals, and the distance between two adjacent first lines is the same, and the distance is the first distance.
  • a second hard mask layer 23 is deposited on the first hard mask layer 21 .
  • a second organic material layer 24 may be deposited on the first hard mask layer 21 , and then a second hard mask layer may be deposited on the second organic material layer 24 Layer 23.
  • a plurality of parallel and spaced second lines are formed on the second hard mask layer 23 along the second direction. The distance between two adjacent second lines is the same, and the distance is the second distance. Wherein, the above-mentioned first direction and the second direction intersect, that is, they are not parallel. Therefore, the first line and the second line have multiple intersections.
  • a first circular hole pattern is formed by etching at the intersection.
  • first distance and the second distance are the same, a square or a rhombus can be formed after the first line and the second line intersect.
  • first spacing can also be different from the second spacing, and after the two lines intersect, a plurality of rectangles or parallelograms can be formed, and the first circular hole pattern is distributed at four vertices.
  • the materials of the first hard mask layer 21 and the second hard mask layer 23 are generally silicon oxide, silicon nitride, polysilicon or other materials and combinations thereof, and the first circular hole pattern can be formed by plasma etching the hard mask layer.
  • step S600 is performed: based on the first circular hole pattern, uniformly distributed first openings 25 are etched on the semiconductor substrate 1 .
  • the depth of the first opening 25 is the thickness of the uppermost first basic mask layer 171 of the semiconductor substrate 1 , that is, the pattern of the first opening 25 is obtained by etching the first basic mask layer 171 .
  • the first opening 25 is a circular hole.
  • the cross-sectional profile of the first opening 25 is circular.
  • the projection of each first opening 25 on the semiconductor substrate 1 (in this case, the second base mask layer 172 ) is defined as a first circular projection.
  • step S800 is performed: a second mask layer 3 is formed on the side of the first opening 25 away from the semiconductor substrate 1 , and a plurality of mask layers 3 are formed on the second mask layer 3 Second pattern.
  • the second mask layer 3 is deposited on the side of the first opening 25 away from the semiconductor substrate 1 , that is, the second mask layer 3 is formed on the top of the first opening 25 .
  • the second mask layer 3 can be formed by atomic deposition or chemical vapor deposition, for example.
  • Deposition to form the second mask layer 3 may include: sequentially stacking and depositing a third organic material layer 31, a third hard mask layer 32 and a first photoresist layer 33, and then etching the photoresist through an exposure process and a development process
  • the adhesive layer is formed to form a photoresist pattern, and then the third hard mask layer 32 is etched by using the photoresist pattern as an etching mask to form a second pattern.
  • the second pattern can be a quadrilateral, such as a rhombus, a parallelogram, or an ellipse, and the outer contour of the ellipse intersects with four adjacent first circular projections.
  • the second pattern is a rhombus, which is located in the middle of the first circular projections of the four first openings 25 , and overlaps with the four first circular projections.
  • step S1000 is performed: based on the second pattern, second openings 34 distributed uniformly are etched on the semiconductor substrate 1 , and at the same time, the first openings 25 are continuously etched, so that The first opening 25 and the second opening 34 have the same depth.
  • the pattern of the second mask layer 3 is transferred to the second basic mask layer 172 of the semiconductor substrate 1 , and the second basic mask layer 172 is continuously etched, as shown in the diamond shape in FIG. 11 .
  • the second opening 34 is formed, that is, the second pattern is transferred to the second base mask layer 172 to form the pattern of the second opening 34 .
  • Each of the second openings 34 is defined to have a second projection on the semiconductor substrate 1 .
  • the first opening 25 has a first circular projection on the semiconductor substrate 1 .
  • the lines connecting the centers of the four first circular projections form a rhombus, and the contour lines of each second projection intersect with the contour lines of the four first circular projections respectively.
  • the first opening 25 and the second opening 34 are etched at the same time, and actually the first opening 25 and the second opening 34 are integrated into each other. Therefore, the first opening 25 and the second opening 34 can be formed.
  • the pattern of capacitor holes 4 As can be seen from FIG. 11 , since the pattern of each capacitor hole 4 includes four first openings 25 , the line connecting the centers of the four first openings 25 forms a rhombus. Therefore, the cross section of the capacitor hole 4 has a The outline shape is roughly diamond-shaped.
  • the first opening 25 and the second opening 34 already partially overlap. Therefore, when the second opening 34 is formed, the first opening 25 and the second opening 34 If it is through, the pattern of the capacitor hole 4 is formed, and the second opening 34 with a cross-section of a rhombus or an ellipse cannot be formed independently. Therefore, for ease of understanding, in the embodiment of the present disclosure, the first opening 25 and the second opening 34 are listed separately for description. In FIG. 11 , the portion of the second opening 34 overlapping with the first opening 25 is represented by a dotted line.
  • step S1200 is performed: the first opening 25 and the second opening 34 are etched to form the capacitor hole 4 .
  • the pattern of the capacitor holes 4 of the second base mask layer 172 is transferred to the third support layer 16 , and the etching is continued to the bottommost layer of the semiconductor substrate 1 .
  • the support layer forms the capacitor hole 4 .
  • the bottommost support layer is the first support layer 12, and the first support layer 12 is provided with a pad, so the capacitor hole 4 in this embodiment can be etched to the pad. It can be seen from this that the side peripheral walls forming the capacitor hole 4 are the first sacrificial layer 13, the second supporting layer 14, the second sacrificial layer 15 and the third supporting layer 16 in order from bottom to top.
  • step S1400 is performed: depositing a lower electrode layer, a dielectric layer and an upper electrode layer in the capacitor hole 4 to form a stable capacitor structure.
  • the lower electrode layer 6 is formed on the inner surface of the side peripheral wall of the capacitor hole 4 and the bottom surface of the capacitor hole 4 by a deposition method, that is, the lower electrode layer 6 is attached to the capacitor hole 4 .
  • the inner wall of the capacitor hole 4 and the first support layer 12 or pad forming the bottom surface of the capacitor hole 4 are not formed with the lower electrode layer 6 at the top of the side peripheral wall of the capacitor hole 4 .
  • a third mask layer 5 is formed on the top of the capacitor hole 4 , and a third circular hole pattern is formed on the third mask layer 5 .
  • the projection of the third circular hole pattern on the semiconductor substrate 1 is defined as the third circular projection, and the projection of the capacitive hole 4 on the semiconductor substrate 1 is the capacitive hole projection, then each third circular projection is respectively associated with the adjacent at least
  • the two capacitive hole projections have overlapping parts, for example, the contour line of each third projection intersects the contour line of the adjacent two or three capacitive hole projections, or the contour line of each third projection intersects the adjacent one.
  • Etching based on the third circular hole pattern of the third mask can remove the third support layer 16 on the top of the side peripheral wall of the capacitor hole 4 that overlaps with the third circular hole pattern, that is, the above-mentioned removal of part of the top of the side peripheral wall of the capacitor hole 4 support layer.
  • forming the third mask layer 5 includes: sequentially depositing a fourth organic material layer 51 , a fourth hard mask layer 52 and a second photoresist layer 53 , so that the three form a stacked layer structure.
  • the second photoresist layer 53 is etched through an exposure process and a development process to form a photoresist pattern, and then the fourth hard mask layer 52 is etched using the photoresist pattern as an etching mask to form a third circular hole pattern.
  • the side wall of the capacitor hole 4 (where the lower electrode layer 6 is attached at this time) is continuously etched to remove the first sacrificial layer 13 and the second sacrificial layer in the side wall of the capacitor hole 4 15.
  • Concentrated hydrofluoric acid solutions can be used as etching reagents.
  • the side wall of the capacitor hole 4 includes the lower electrode layer 6 , the second support layer 14 and the third support layer 16
  • the bottom wall of the capacitor hole 4 includes the lower electrode layer 6 and is deposited on the first support layer 12 .
  • a dielectric layer is formed, which covers the lower electrode layer 6 and the exposed semiconductor substrate 1 .
  • a dielectric layer 7 is deposited on the lower electrode layer 6 of the side peripheral wall, the top of the third support layer 16 on the top of the side peripheral wall, and the exposed first support layer 12.
  • the dielectric layer 7 is selected as a high-K medium to improve the Capacitance value per unit area
  • the material of the dielectric layer 7 may include: at least one of ZrOx, HfOx, ZrTiOx, RuOx, SbOx, AlOx, the dielectric layer 7 may also include multiple layers of different materials.
  • an upper electrode layer 8 is formed on the dielectric layer 7.
  • the material of the upper electrode layer 8 can be the same as the material of the lower electrode layer 6, and can include at least one of metal nitride and metal silicide species, such as titanium nitride, silicide Titanium, nickel silicide, etc.
  • the formation of the upper electrode layer 8 on the dielectric layer 7 can still use an atomic layer deposition process or a chemical vapor deposition process.
  • a conductor 9 is formed in the capacitor hole 4, and the conductor 9 includes a stack formed by at least one of tungsten, titanium, nickel, aluminum, platinum, titanium nitride, N-type polysilicon, and P-type polysilicon.
  • the above-mentioned lower electrode layer 6 , dielectric layer 7 and upper electrode layer 8 of the present disclosure can form the side peripheral wall of the capacitor hole 4 , and the side peripheral wall can form the supporting structure of the capacitor.
  • the shape of the cross section of the capacitor hole 4 is similar to a rhombus structure, that is, the connecting line of the center of each protruding part forms a rhombus, thus forming a rhombus supporting structure.
  • the capacitor hole 4 formed by the etched first opening 25 and the second opening 34 is a quadrilateral structure, specifically, a rhombus structure, rather than a single cylindrical structure, which can provide higher support stability and effectively avoid the fracture of the support structure. and fall off.
  • a capacitor manufactured by the manufacturing method in the above embodiment may be a double-sided capacitor.
  • the capacitor includes: a semiconductor substrate 1 , a capacitor hole 4 , and a lower electrode layer 6 , a dielectric layer 7 and an upper electrode layer 8 sequentially deposited in the capacitor hole.
  • the capacitor holes 4 are disposed on the semiconductor substrate 1 and arranged in an array.
  • Each capacitor hole 4 is formed by four adjacent circular first openings 25 and one second opening 34; the projection of each first opening 25 on the semiconductor substrate 1 is the first circular projection, and the second opening The projection of 34 on the semiconductor substrate 1 is the second projection, and the outline of the second projection and the outline of the four adjacent first circular projections respectively intersect; the continuous outer outline of the first circular projection and the second projection The projected outline of the capacitor hole 4 on the semiconductor substrate 1 is formed.
  • the lines connecting the centers of the four adjacent first circular projections form a quadrilateral.
  • the quadrilateral is a rhombus, and the four vertices of each second projection coincide with the centers of the four adjacent first circular projections, so that the capacitor hole 4 has a symmetrical structure, which is beneficial to improve its support stability sex.
  • the double-sided capacitor further includes a conductor 9 , and the conductor 9 is filled in the capacitor hole 4 .
  • the double-sided capacitor in the present disclosure can provide higher stability due to the triangular structure of the capacitance hole, effectively avoid the breaking and falling off of the support structure, and meet the demand for continuous miniaturization of semiconductor devices.

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Abstract

一种电容结构的制备方法及电容器。该方法包括：提供半导体基底；在半导体基底上形成具有多个均匀分布的第一圆孔图案的第一掩膜层；基于第一圆孔图案，在半导体基底上蚀刻第一开口，每个第一开口在半导体基底上具有第一圆形投影；在第一开口的远离半导体基底的一侧形成第二掩膜层，并在第二掩膜层上形成多个第二图案；基于第二图案，在半导体基底上蚀刻出第二开口，每个第二开口在半导体基底上具有第二投影；其中，第二投影的轮廓线与四个相邻的第一圆形投影的轮廓线分别相交；蚀刻第一开口和第二开口形成电容孔，在电容孔内沉积下电极层、电介质层和上电极层，形成电容结构。

Description

电容结构的制备方法及电容器
交叉引用
本公开要求于2020年9月10日提交的申请号为202010949024.7、名称为“电容结构的制备方法及电容器”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及半导体器件制备技术领域，尤其涉及一种电容结构的制备方法及电容器。
背景技术
在动态随机存储器(Dynamic Random Access Memory)形成电容孔工艺中，通常由氮化硅层和两层二氧化硅层在硬掩膜的作用下形成电容孔结构，目前通常形成的双面电容器大都采用单根圆柱支撑结构。例如，在基底的底部导线上直接形成支撑层，作为电容器的底部介质层，然后依序形成两层牺牲层，通过蚀刻工艺形成孔洞结构，该孔洞结构延伸至基底中的导线结构，之后在该孔洞结构上形成下电极层、电介质层和上电极层，由此形成单根圆柱支撑结构。
随着DRAM器件尺寸不断微缩，电容器的尺寸需要不断减小，而电容器的高度需要不断的增加，以提高电容值，但是这样势必会造成单根圆柱形的支撑结构不稳定，容易断裂、错位而脱落，影响电容器的稳定性。
发明内容
本公开的一个主要目在于提供一种电容结构的制备方法，能够在增加电容结构的高度的同时，有效避免支撑结构的脱落。
本公开的另一目的在于提供一种电容器，具有稳定的支撑结构，能够满足半导体器件不断微缩的需求。
为实现上述目的，根据本公开的一个方面，提供一种电容结构的制备方法，包括：提供半导体基底；在所述半导体基底上形成第一掩膜层，并在所述第一掩膜层上形成多个均匀分布的第一圆孔图案；基于所述第一圆孔图案，在所述半导体基底上蚀刻出均匀分布的第一开口，每个所述第一开口在所述半导体基底上具有第一圆形投影；在所述第一开口的 远离所述半导体基底的一侧形成第二掩膜层，并在所述第二掩膜层上形成多个第二图案；基于所述第二图案，在所述半导体基底上蚀刻出均匀分布的第二开口，同时继续蚀刻所述第一开口，使所述第一开口与所述第二开口具有相同的深度，每个所述第二开口在所述半导体基底上具有第二投影；其中，所述第二投影的轮廓线与四个相邻的所述第一圆形投影的轮廓线分别相交；刻蚀所述第一开口和所述第二开口形成电容孔；在所述电容孔内沉积下电极层、电介质层和上电极层，形成所述电容结构。
根据本公开的另一方面，提供一种电容器，包括：半导体基底；电容孔，设于所述半导体基底，且以阵列形式排列；其中，每个所述电容孔由四个圆形的第一开口和一个第二开口形成；每个所述第一开口在所述半导体基底上的投影为第一圆形投影，所述第二开口在所述半导体基底上的投影为第二投影，所述第二投影的轮廓线和四个相邻的所述第一圆形投影的轮廓线分别相交；所述第一圆形投影和所述第二投影的连续的外轮廓形成所述电容孔的在半导体基底上的投影轮廓；以及依序沉积于所述电容孔内的下电极层、电介质层和上电极层。
由上述技术方案可知，本公开具备以下优点和积极效果中的至少之一：
由于第二投影的轮廓线与四个第一圆形投影的轮廓线分别相交，因此，蚀刻后的第一开口和第二开口形成的电容孔为菱形结构，而并非单一的圆柱结构，能够提供更高的支撑稳定性，有效避免支撑结构的断裂及脱落。
附图说明
通过参照附图详细描述其示例实施方式，本公开的上述和其它特征及优点将变得更加明显。
图1为本公开一示例性实施例中的电容结构的制备方法中提供的半导体基底的结构示意图；
图2为本公开一示例性实施例中的电容结构的制备方法中形成第一线条的结构示意图；
图3为本公开一示例性实施例中的电容结构的制备方法中形成第二线条的结构示意图；
图4为本公开一示例性实施例中的电容结构的制备方法中形成第一开口的结构示意图；
图5为图4的俯视；
图6为本公开一示例性实施例中的电容结构的制备方法中设置第二掩膜层的结构示意图；
图7为图6的俯视示意图；
图8为本公开一示例性实施例中的电容结构的制备方法中形成电容孔的图案的结构示意图；
图9为图8的俯视图；
图10为本公开具有三角支撑结构的双面电容器的制备方法中形成电容孔的结构示意图；
图11为图10的俯视示意图；
图12为本公开一示例性实施例中的电容结构的制备方法中在电容孔内形成导电层的结构示意图；
图13为图12的俯视图；
图14为本公开一示例性实施例中的电容结构的制备方法中形成导电层的结构示意图；
图15为14俯视示意图；
图16为本公开一示例性实施例中的电容结构的制备方法中去除电容孔的部分侧周壁顶部的支撑层下电极层之间牺牲层后的示意图；
图17为图16的俯视示意图；
图18为本公开一示例性实施例中形成的电容器的结构示意图；
图19为图18中沿A-A的其中一个电容孔的剖面示意图；
图20为本公开的电容结构的制备方法的流程图。
附图标记说明：
1、半导体基底；11、衬底；12、第一支撑层；13、第一牺牲层；14、第二支撑层；15、第二牺牲层；16、第三支撑层；17、基础掩膜层；171、第一基础掩膜层；172、第二基础掩膜层；2、第一掩膜层；21、第一硬掩膜层；22、第一有机材料层；23、第二硬掩膜层；24、第二有机材料层；25、第一开口；3、第二掩膜层；31、第三有机材料层；32、第三硬掩膜层；33、第一光刻胶层；34、第二开口；4、电容孔；5、第三掩膜层；51、第四有机材料层；52、第四硬掩膜层；53、第二光刻胶层；6、下电极层；7、电介质层；8、上电极层；9、上电极。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
在对本公开的不同示例性实施方式的下面描述中，参照附图进行，附图形成本公开的一部分，并且其中以示例方式显示了可实现本公开的多个方面的不同示例性结构。应理解的是，可以使用部件、结构、示例性装置、系统和步骤的其他特定方案，并且可在不偏离本公开范围的情况下进行结构和功能性修改。而且，虽然本说明书中可使用术语“之上”、“之间”、“之内”等来描述本公开的不同示例性特征和元件，但是这些术语用于本文中仅出于方便，例如根据附图中的示例的方向。本说明书中的任何内容都不应理解为需要结构的特定三维方向才落入本公开的范围内。此外，权利要求书中的术语“第一”、“第二”等仅作为标记使用，不是对其对象的数字限制。
请参考图1至图19，其分别示出了本公开中的电容结构制备的过程示意图，图20示出了本公开中电容结构的制备方法的流程图。如图20所示，本公开的电容结构的制备方法包括：
步骤S200：提供半导体基底1。
步骤S400：在半导体基底1上形成第一掩膜层2，并在第一掩膜层2上形成多个均匀分布的第一圆孔图案。
步骤S600：基于第一圆孔图案，在半导体基底1上蚀刻出均匀分布的第一开口25，每个第一开口25在半导体基底1上具有第一圆形投影。
步骤S800：在第一开口25的远离半导体基底1的一侧形成第二掩膜层3，并在第二掩膜层3上形成多个第二图案。
步骤S1000：基于第二图案，在半导体基底1上蚀刻出均匀分布的第二开口34，同时继续蚀刻所述第一开口25，使第一开口25与第二开口34具有相同的深度。
每个第二开口34在半导体基底1上具有第二投影。其中，第二投影的轮廓线与四个相邻的第一圆形投影的轮廓线分别相交。
步骤S1200：蚀刻第一开口25和第二开口34形成电容孔4。
步骤S1400：在电容孔4内沉积下电极层、电介质层和上电极层，形成电容结构。
由于第二投影的轮廓线与四个相邻的第一圆形投影的轮廓线分别相交，因此，蚀刻后 的第一开口25和第二开口34形成的电容孔4为横截面为大致呈菱形的结构，而并非单一的圆柱结构，能够提供更高的支撑稳定性，有效避免电容器的支撑结构的断裂及脱落。
下面对本公开的电容结构的制备方法进行详细的说明，本公开实施例的电容结构以双面电容结构的为例进行说明。
如图1所示，进行步骤S200：提供半导体基底1。
半导体基底1包括依序堆叠设置的衬底11、焊盘、交替层叠设置的支撑层和牺牲层以及基础掩膜层17。其中，衬底11的材料可以为硅、碳化硅、氮化硅、绝缘体上硅、绝缘体上层叠硅、绝缘体上层叠锗化硅、绝缘体上层锗化硅或绝缘体上层锗等。
衬底11中形成有多个焊盘，晶体管的字符线(Word line)以及位线(Bit line)，该多个焊盘电性连接该晶体管的源极(图中未示出)，为半导体器件提供电路。
其中，支撑层和牺牲层交替设置，并且覆盖于焊盘上。其中，牺牲层设于支撑层之间。可以采用原子沉积工艺(Atomic Layer Deposition)或化学气相沉积工艺(Chemical Vapor Deposition)形成支撑层和牺牲层。支撑层的材料可以包括氮化硅、氧化硅或氮氧化硅，牺牲层的材料可以包括氮化硅、氧化硅或氮氧化硅。支撑层和牺牲层采用的材料不同，在本实施例中，支撑层采用的材料为SiN，牺牲层的材料为SiO2，因此，在同一腐蚀液中，二者被腐蚀的速率不同，具体为在同一腐蚀液中，牺牲层的腐蚀速率远远大于支撑层腐蚀速率，使得当牺牲层被完全去除时，支撑层几乎被完全保留。其中腐蚀液可以是浓氢氟酸溶液。
在本实施例中，设置了两层支撑层与牺牲层的交替层，即第一支撑层12、第一牺牲层13、第二支撑层14、第二牺牲层15和第三支撑层16。当然，也可以设置三层、四层或五层支撑层与牺牲层的交替层，本领域技术人员可以根据实际需求选择，此处不做特殊限定。
基础掩膜层17可以设置一层或多层，例如，在本实施例中，基础掩膜层17设置了两层，分别为第一基础掩膜层171和第二基础掩膜层172。当然，还可以设置三层、四层或五层，本领域技术人员可以根据实际需求进行选择，此处不做特殊限定。可以将第一开口25和第二开口34的图案转移至该基础掩膜层17上，以形成电容孔的图案，再将该电容孔的图案转移至位于该基础掩膜层17下方的半导体基底上，继续蚀刻，最终形成电容孔。另外，基础掩膜层17的材料一般为氧化硅、氮化硅、多晶硅或其他材料及其组合。
如图2至图3所示，进行步骤S400：在所述半导体基底1上形成第一掩膜层2，并在所述第一掩膜层2上形成多个均匀分布的第一圆孔图案。
具体地，如图2和图3所示，形成第一掩膜层2包括：在半导体基底1上依序沉积形成第一硬掩膜层21和第二硬掩膜层23。
其中，如图2所示，第一硬掩膜层21沉积在半导体基底1上，具体为沉积于位于半导体基底1的第一基础掩膜层171的表面。优选地，在沉积第一硬掩膜层21之前，还可以在半导体基底上，即在第一基础掩膜层171上沉积第一有机材料层22。在第一硬掩膜层21上沿第一方向形成多条平行的第一线条。该第一线条间隔平行设置，且相邻的两个第一线条之间的间距相同，该间距为第一间距。
如图3所示，沉积第二硬掩膜层23于第一硬掩膜层21上。优选的，在沉积第二硬掩膜层23之前，可以在第一硬掩膜层21上先沉积第二有机材料层24，之后，再在第二有机材料层24上沉积第二硬掩膜层23。在第二硬掩膜层23上沿第二方向形成多条平行间隔的第二线条。相邻的两个第二线条之间的间距相同，该间距为第二间距。其中，上述的第一方向和第二方向相交，即二者不平行。因此，第一线条和第二线条具有多个交点。在交点处蚀刻形成第一圆孔图案。
由于第一间距和第二间距相同，因此，第一线条和第二线条相交后可以形成正方形、菱形。当然，第一间距也可以和第二间距不相同，则两种线条相交后可以形成多个矩形或平行四边形，第一圆孔图案则分布在四个顶点。
第一硬掩膜层21和第二硬掩膜层23的材料一般为氧化硅、氮化硅、多晶硅或其他材料及其组合，可以通过等离子体蚀刻硬掩膜层形成第一圆孔图案。
之后，如图4和图5所示，进行步骤S600：基于所述第一圆孔图案，在所述半导体基底1上蚀刻出均匀分布的第一开口25。
如图4所示，该第一开口25的深度为半导体基底1的最上层的第一基础掩膜层171的厚度，即对第一基础掩膜层171蚀刻，得到第一开口25的图案。该第一开口25为圆形孔，如图5所示，该第一开口25的横截面轮廓为圆形。继续参考图5，定义每个第一开口25在半导体基底1(此时为第二基础掩膜层172)上的投影为第一圆形投影。
之后，如图6至图7所示，进行步骤S800：在第一开口25的远离半导体基底1的一侧形成第二掩膜层3，并在所述第二掩膜层3上形成多个第二图案。
具体地，如图6所示，在第一开口25的远离半导体基底1的一侧上沉积形成第二掩膜层3，即在第一开口25的顶端形成第二掩膜层3，该第二掩膜层3例如可以通过原子沉积或化学气相沉积形成。沉积形成第二掩膜层3可以包括：依序层叠沉积形成第三有机材料层31、第三硬掩膜层32和第一光刻胶层33，然后通过曝光工艺和显影工艺来蚀刻光刻 胶层以形成光刻胶图案，之后通过光刻胶图案作为蚀刻掩膜来蚀刻第三硬掩膜层32形成第二图案。
该第二图案可以为四边形，如菱形、平行四边形，也可以是椭圆形，该椭圆形的外轮廓与四个相邻的第一圆形投影均相交。如图7所示，第二图案为菱形，位于四个第一开口25的第一圆形投影的中间位置，并且与四个第一圆形投影均有重合的部分。
之后，如图8至图9所示，进行步骤S1000：基于所述第二图案，在所述半导体基底1上蚀刻出均匀分布的第二开口34，同时继续蚀刻所述第一开口25，使所述第一开口25与所述第二开口34具有相同的深度。
如图8和图9所示，将第二掩膜层3的图案转移至半导体基底1的第二基础掩膜层172，并对第二基础掩膜层172继续进行蚀刻，如图11的菱形的虚线所示，形成第二开口34，即将第二图案转移至第二基础掩膜层172，形成第二开口34的图案。定义每个第二开口34在半导体基底1上具有第二投影。在上一步骤中，已经定义了第一开口25在半导体基底1上具有第一圆形投影。如图5和图11所示，四个第一圆形投影的圆心的连线形成一菱形，每个第二投影的轮廓线与四个第一圆形投影的轮廓线分别相交。
由于在此蚀刻过程中，第一开口25和第二开口34是同时进行蚀刻的，实际第一开口25和第二开口34相互贯通为一体，因此，第一开口25和第二开口34可以形成电容孔4的图案。从图11中可以看出，由于每个电容孔4的图案包含了四个第一开口25，这四个第一开口25的圆心的连线形成一菱形，因此，电容孔4的横截面的轮廓形状大致呈菱形结构。
需说明的是，在形成第二开口34的同时，第一开口25和第二开口34就已经有部分重叠，因此，在形成第二开口34的同时，由于第一开口25与第二开口34是贯通的，就形成了电容孔4的图案，并不能单独地形成横截面为菱形或椭圆的第二开口34。因此，为了便于理解，在本公开的实施例中将第一开口25和第二开口34单独列出说明，在图11中，第二开口34的与第一开口25重叠的部分用虚线表示。
之后，如图10至图11所示，进行步骤S1200：蚀刻第一开口25和第二开口34形成电容孔4。
在本实施例中，如图8和图10所示，将第二基础掩膜层172的电容孔4的图案转移至第三支撑层16上，并继续进行蚀刻至半导体基底1的最底层的支撑层，形成电容孔4。该最底层的支撑层为第一支撑层12，第一支撑层12中设置有焊盘，因而，本实施例中的电容孔4可以被蚀刻至该焊盘。由此可知，形成电容孔4的侧周壁从下至上依次为第一牺 牲层13、第二支撑层14、第二牺牲层15和第三支撑层16。
之后，如图12至图17所示，进行步骤S1400：在所述电容孔4内沉积下电极层、电介质层和上电极层，形成稳定的电容结构。
具体地，如图12和图13所示，通过沉积的方法，在电容孔4的侧周壁的内表面及电容孔4的底面形成下电极层6，即该下电极层6附着于电容孔4的内壁以及形成电容孔4底面的第一支撑层12或焊盘，电容孔4侧周壁的顶端未形成下电极层6。
之后，如图14和图15所示，在电容孔4的顶部形成第三掩膜层5，在第三掩膜层5上形成第三圆孔图案。定义该第三圆孔图案在半导体基底1上的投影为第三圆形投影，电容孔4在半导体基底1上的投影为电容孔投影，则每个第三圆形投影分别与相邻的至少两个电容孔投影具有重合的部分，例如，每个第三投影的轮廓线与相邻的两个或三个电容孔投影的轮廓线相交，或者每个第三投影的轮廓线与相邻的四个电容孔的轮廓相交，且第三投影位于四个电容孔投影的中间位置，并且，每个电容孔投影的轮廓线均与一个第三投影的轮廓线相交。基于第三掩膜的第三圆孔图案进行蚀刻，能够去除电容孔4侧周壁顶部的与该第三圆孔图案重叠的第三支撑层16，即上述的去除电容孔4的部分侧周壁顶部的支撑层。
具体地，如图14所示，形成第三掩膜层5包括：依序沉积第四有机材料层51、第四硬掩膜层52和第二光刻胶层53，使三者形成层叠的结构。通过曝光工艺和显影工艺来蚀刻第二光刻胶层53以形成光刻胶图案，然后以光刻胶图案作为蚀刻掩膜来蚀刻第四硬掩膜层52形成第三圆孔图案。
之后，如图16和图17所示，对电容孔4的侧周壁(此时附着下电极层6)继续进行蚀刻，以去除电容孔4侧周壁中的第一牺牲层13和第二牺牲层15。可以利用浓的氢氟酸溶液作为蚀刻试剂。蚀刻完成后，电容孔4的侧周壁包括下电极层6、第二支撑层14和第三支撑层16，电容孔4底壁包括下电极层6，且沉积于第一支撑层12上。
之后，如图18和图19所示，形成电介质层，该电介质层覆盖下电极层6以及露出的半导体基底1。具体地，在该侧周壁的下电极层6、侧周壁顶部的第三支撑层16顶部以及露出的第一支撑层12上沉积形成电介质层7，该电介质层7选用为高K介质，以提高单位面积电容器电容值，该电介质层7的材料可以包括：ZrOx、HfOx、ZrTiOx、RuOx、SbOx、AlOx中的至少一种，该电介质层7也可以包括由不同材料层叠设置的多层。之后在该电介质层7上覆盖形成上电极层8，上电极层8的材料可以与下电极层6的材料相同，可以包括金属氮化物及金属硅化物种的至少一种，如氮化钛、硅化钛、硅化镍等。在电介质层 7上形成上电极层8仍然可以采用原子层沉积工艺或化学气相沉积工艺。
在电容孔4内形成导电体9，导电体9包括钨、钛、镍、铝、铂、氮化钛、N型多晶硅、P型多晶硅中的至少一种所形成的叠层。
因此，本公开的上述下电极层6、电介质层7和上电极层8能够形成电容孔4的侧周壁，侧周壁可以形成该电容器的支撑结构。从图19中可以看出，电容孔4的横截面的形状为类似于菱形结构，即每个凸出部分的圆心的连线形成一菱形，因此形成了菱形支撑结构。
综上所述，由于四个第一开口25的第一圆形投影的圆心的连线形成一四边形，且第二投影的轮廓线与四个第一圆形投影的轮廓线分别相交，因此，蚀刻后的第一开口25和第二开口34形成的电容孔4为四边形结构，具体地，为菱形结构，而并非单一的圆柱结构，能够提供更高的支撑稳定性，有效避免支撑结构的断裂及脱落。
根据本公开的另一方面，提供一种电容器，该电容器由上述实施例中的制备方法制得。该电容器可以为双面电容器。该电容器包括：半导体基底1、电容孔4和依序沉积于电容孔内的下电极层6、电介质层7和上电极层8。电容孔4设于半导体基底1，且以阵列形式排列。
其中每个电容孔4由四个相邻的圆形的第一开口25和一个第二开口34形成；每个第一开口25在半导体基底1上的投影为第一圆形投影，第二开口34在半导体基底1上的投影为第二投影，第二投影的轮廓线和四个相邻的第一圆形投影的轮廓线分别相交；第一圆形投影和第二投影的连续的外轮廓形成电容孔4的在半导体基底1上的投影轮廓。
四个相邻的第一圆形投影的圆心的连线形成一个四边形。在本实施例中，该四边形为菱形，每个第二投影的四个顶点与四个相邻的第一圆形投影的圆心重合，使电容孔4具有对称的结构，有利于提高其支撑稳定性。
另外，如图18和图19所示，双面电容器还包括导电体9，导电体9填充于电容孔4中。
关于该电容器的具体结构及材质，与制备方法的实施例中相同，此处不在赘述。
综上，本公开中的双面电容器由于其电容孔为三角结构，能够提供更高的稳定性，有效避免支撑结构的断裂及脱落，能够半导体器件不断微缩需求。
应可理解的是，本公开不将其应用限制到本说明书提出的部件的详细结构和布置方式。本公开能够具有其他实施方式，并且能够以多种方式实现并且执行。前述变形形式和修改形式落在本公开的范围内。应可理解的是，本说明书公开和限定的本公开延伸到文中 和/或附图中提到或明显的两个或两个以上单独特征的所有可替代组合。所有这些不同的组合构成本公开的多个可替代方面。本说明书所述的实施方式说明了已知用于实现本公开的最佳方式，并且将使本领域技术人员能够利用本公开。

Claims (20)

  1. 一种电容结构的制备方法，包括：
    提供半导体基底；
    在所述半导体基底上形成第一掩膜层，并在所述第一掩膜层上形成多个均匀分布的第一圆孔图案；
    基于所述第一圆孔图案，在所述半导体基底上蚀刻出均匀分布的第一开口，每个所述第一开口在所述半导体基底上具有第一圆形投影；
    在所述第一开口的远离所述半导体基底的一侧形成第二掩膜层，并在所述第二掩膜层上形成多个第二图案；
    基于所述第二图案，在所述半导体基底上蚀刻出均匀分布的第二开口，同时继续蚀刻所述第一开口，使所述第一开口与所述第二开口具有相同的深度，每个所述第二开口在所述半导体基底上具有第二投影；
    其中，所述第二投影的轮廓线与四个相邻的所述第一圆形投影的轮廓线分别相交；
    刻蚀所述第一开口和所述第二开口形成电容孔；
    在所述电容孔内沉积下电极层、电介质层和上电极层，形成所述电容结构。
  2. 根据权利要求1所述的制备方法，其中，所述第二投影为四边形，所述四边形的四个顶点分别位于四个相邻的所述第一圆形投影内。
  3. 根据权利要求1所述的制备方法，其中，所述半导体基底包括：
    衬底；
    焊盘，设于所述衬底上；
    多层交替层叠设置的支撑层和牺牲层，覆盖于所述焊盘，其中，所述牺牲层设于所述支撑层之间；
    基础掩膜层，设于距离所述衬底最远的所述支撑层上。
  4. 根据权利要求3所述的制备方法，其中，所述支撑层和所述牺牲层通过原子沉积工艺或化学气相沉积工艺形成。
  5. 根据权利要求3所述的制备方法，其中，支撑层采用的材料为SiN，牺牲层的材料为SiO2。
  6. 根据权利要求1所述的制备方法，其中，所述第一掩膜层包括：
    第一硬掩膜层，在所述第一硬掩膜层上沿第一方向形成多条平行的第一线条；
    第二硬掩膜层，设于所述第一硬掩膜层上，在所述第二硬掩膜层上沿第二方向形成多条平行的第二线条；
    其中，所述第一方向和所述第二方向相交，所述第一线条和所述第二线条具有多个交点，在所述交点处蚀刻形成所述第一圆孔图案。
  7. 根据权利要求6所述的制备方法，其中，相邻的所述第一线条之间间距相同，且为第一间距，相邻的所述第二线条之间间距相同，且为第二间距，所述第一间距等于所述第二间距。
  8. 根据权利要求6所述的制备方法，其中，所述第一硬掩膜层和所述第二硬掩膜层依序沉积在所述半导体基底上。
  9. 根据权利要求8所述的制备方法，其中，在沉积所述第一硬掩膜层之前，在所述半导体基底上沉积第一有机材料层。
  10. 根据权利要求9所述的制备方法，其中，在沉积所述第二硬掩膜层之前，在所述第一硬掩膜层上沉积第二有机材料层。
  11. 根据权利要求6所述的制备方法，其中，所述第一硬掩膜层和所述第二硬掩膜层的材料为氧化硅、氮化硅和多晶硅中的至少一种。
  12. 根据权利要求1所述的制备方法，其中，所述在所述第一开口的远离所述半导体基底的一侧形成第二掩膜层，并在所述第二掩膜层上形成多个第二图案包括：
    在所述第一开口的顶端依序层叠沉积形成第三有机材料层、第三硬掩膜层和第一光刻胶层；
    通过曝光工艺和显影工艺蚀刻所述光刻胶层，形成光刻胶图案；
    以所述光刻胶图案作为蚀刻掩膜来蚀刻所述第三硬掩膜层，形成所述第二图案。
  13. 根据权利要求12所述的制备方法，其中，所述第二图案为菱形，位于四个所述第一开口的所述第一圆形投影的中间位置，并且与四个所述第一圆形投影均有重合的部分。
  14. 根据权利要求3所述的制备方法，其中，在所述电容孔内沉积下电极层、电介质层和上电极层，形成电容结构包括：
    在所述电容孔的侧周壁的内表面及所述电容孔的底面形成所述下电极层，所述下电极层与所述焊盘连接；
    在所述电容孔的顶部形成第三掩膜层，并在所述第三掩膜层上形成第三圆孔图案；
    基于所述第三圆孔图案，去除所述电容孔的部分侧周壁顶部的支撑层；
    对所述电容孔进行蚀刻，去除所述下电极层之间的牺牲层。
  15. 根据权利要求14所述的制备方法，其中，在所述电容孔的顶部形成第三掩膜层，并在所述第三掩膜层上形成第三圆孔图案包括：
    依序沉积第四有机材料层、第四硬掩膜层和第二光刻胶层，使三者形成层叠的结构；
    通过曝光工艺和显影工艺来蚀刻所述第二光刻胶层以形成光刻胶图案；
    以光刻胶图案作为蚀刻掩膜来蚀刻所述第四硬掩膜层形成所述第三圆孔图案。
  16. 根据权利要求14所述的制备方法，其中，
    所述第三圆孔图案在所述半导体基底上的投影为第三圆形投影，所述电容孔在所述半导体基底上的投影为电容孔投影，其中，
    所述第三圆形投影与相邻的至少两个所述电容孔投影的轮廓均相交，基于所述第三圆孔图案进行蚀刻，去除所述电容孔的侧周壁顶部的与所述第三圆孔图案对应的支撑层。
  17. 根据权利要求14所述的制备方法，其中，所述半导体基底包括两层交替层叠设置的支撑层和牺牲层，利用氢氟酸溶液去除所述下电极层之间的牺牲层。
  18. 根据权利要求17所述的制备方法，其中，所述支撑层的材料为氮化硅，所述牺牲层的材料为氧化硅。
  19. 根据权利要求18所述的制备方法，其中，在所述电容孔内沉积下电极层、电介质层和上电极层，形成电容结构还包括：
    形成电介质层，所述电介质层覆盖所述下电极层以及露出的所述半导体基底；
    形成覆盖所述电介质层的上电极层；
    在所述电容孔内形成导电体。
  20. 一种电容器，包括：
    半导体基底；
    电容孔，设于所述半导体基底，且以阵列形式排列；
    其中，每个所述电容孔由四个圆形的第一开口和一个第二开口形成；每个所述第一开口在所述半导体基底上的投影为第一圆形投影，所述第二开口在所述半导体基底上的投影为第二投影，所述第二投影的轮廓线和四个相邻的所述第一圆形投影的轮廓线分别相交；所述第一圆形投影和所述第二投影的连续的外轮廓形成所述电容孔的在半导体基底上的投影轮廓；以及
    依序沉积于所述电容孔内的下电极层、电介质层和上电极层。
PCT/CN2021/103546 2020-09-10 2021-06-30 电容结构的制备方法及电容器 WO2022052588A1 (zh)

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