WO2022052531A1 - 芯片及存储器 - Google Patents

芯片及存储器 Download PDF

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Publication number
WO2022052531A1
WO2022052531A1 PCT/CN2021/098839 CN2021098839W WO2022052531A1 WO 2022052531 A1 WO2022052531 A1 WO 2022052531A1 CN 2021098839 W CN2021098839 W CN 2021098839W WO 2022052531 A1 WO2022052531 A1 WO 2022052531A1
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Prior art keywords
annular groove
substrate
spacer
chip
air gap
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PCT/CN2021/098839
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English (en)
French (fr)
Inventor
张志伟
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长鑫存储技术有限公司
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Priority to EP21769871.1A priority Critical patent/EP3996134A4/en
Priority to US17/386,655 priority patent/US20220077079A1/en
Publication of WO2022052531A1 publication Critical patent/WO2022052531A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H01L2225/06544—Design considerations for via connections, e.g. geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06589—Thermal management, e.g. cooling

Definitions

  • the present application relates to the field of semiconductor technology, and in particular, to a chip and a memory.
  • Stacked chip packaging technology also known as three-dimensional packaging technology, refers to a packaging technology in which two or more chips are stacked vertically in the same package.
  • DRAM Dynamic Random Access Memory
  • multiple chips are vertically stacked and connected to each other through three-dimensional packaging technology, so as to improve the storage capacity and bandwidth of DRAM.
  • TSV Through Silicon Via
  • the coefficient of thermal expansion (CTE) of copper is 17.8 ⁇ 10 -6 /K
  • the thermal expansion coefficient of silicon is 2.5 ⁇ 10 -6 /K, which makes the thermal expansion coefficient mismatch problem between the copper in the TSV structure and the silicon wafer.
  • the present application provides a chip and a memory, which are used to reduce the influence of the thermal expansion of the TSV structure on electrical components and improve the pass rate of the chip.
  • the present application provides a chip, including a base, wherein the base is provided with a through hole penetrating the base, the through hole is provided with a conductive column; the first surface of the base is provided with a first annular groove , the first annular groove is arranged around the conductive column; the first annular groove is provided with a first spacer, and a second spacer extending along the circumferential direction of the first annular groove is formed inside the first spacer. an air gap.
  • the base body is provided with through holes penetrating the substrate, the through holes are provided with conductive pillars, and the through holes filled with the conductive pillars form TSV holes for electrical signal connection between the chip and other components;
  • the first surface of the substrate A first annular groove is provided, and the first annular groove is arranged around the conductive column; a first spacer is arranged in the first annular groove, and a first air gap extending along the circumferential direction of the first annular groove is formed inside the first spacer.
  • the thermal stress When thermal stress is generated between the conductive column and the substrate, the thermal stress is released through the first air gap in the first spacer, thereby reducing or avoiding the deformation of the lattice in the substrate outside the first annular groove and relieving the local delamination of the chip.
  • the influence of thermal stress on the electrical components on the chip is reduced, the failure of the electrical components is reduced, and the pass rate of the chip is improved.
  • a plane perpendicular to the center line of the through hole is taken as a cross-section
  • the cross-sectional shape of the first annular groove is a regular polygon with a number of sides greater than or equal to eight.
  • the diameter of the inscribed circle of the regular polygon is 5-40 ⁇ m.
  • the depth of the first annular groove is 0.2-2 ⁇ m.
  • the center line of the first annular groove coincides with the center line of the through hole.
  • a plane perpendicular to the first surface of the substrate and including the center line of the through hole is taken as a cross section, and the cross-sectional shape of the first air gap is a triangle, a rectangle, a circle or an ellipse .
  • the first surface of the base is further provided with a second annular groove and a third annular groove; the second annular groove is sleeved outside the first annular groove, and the second annular groove is A second spacer is filled in the groove; the third annular groove is sleeved outside the second annular groove, and a third spacer is filled in the third annular groove.
  • a second air gap extending along the circumferential direction of the second annular groove is formed inside the second spacer; and/or a second air gap is formed inside the third spacer along the third spacer A circumferentially extending third air gap of the annular groove.
  • the width of the first annular groove is greater than the widths of the second annular groove and the third annular groove.
  • the present application further provides a memory, comprising at least two chips as described above arranged in a stack, and conductive pillars in adjacent chips are butted together.
  • FIG. 1 is a schematic structural diagram of a chip in an embodiment of the present application.
  • FIG. 2 is a cross-sectional view of a chip in an embodiment of the present application.
  • FIG. 3 is a partial schematic diagram of a structure of a chip in an embodiment of the present application.
  • FIG. 4 is a partial schematic diagram of another structure of the chip in the embodiment of the present application.
  • FIG. 5 is a schematic diagram of a mask in an embodiment of the present application.
  • FIG. 6 is a schematic diagram of etching in an embodiment of the present application.
  • FIG. 8 is a flow chart of the fabrication of the chip in the embodiment of the present application.
  • An embodiment of the present application provides a chip, the chip is provided with a TSV hole, a shallow trench is provided around the TSV hole for isolation, an isolation material is filled in the shallow trench, and an air gap extending along the circumferential direction of the shallow trench is formed in the isolation material, so that the isolation material While the components are isolated, the air gap plays a role in releasing the stress, reducing the influence of the thermal expansion of the TSV hole on the electrical components outside the shallow groove, thereby reducing the failure of the electrical components and improving the pass rate of the chip.
  • a dynamic random access memory can temporarily or permanently store data sets, among which, dynamic random access memory relies on capacitors to store charges to store information. It is a temporary data storage medium and is often used as memory.
  • a dynamic random access memory typically includes a substrate, at least two chips stacked on the substrate, and a TSV structure that electrically connects the chips.
  • each chip in the dynamic random access memory is provided with through holes, and conductive pillars are filled in the through holes to form TSV holes.
  • the TSV holes of the chips correspond to each other, so that the conductive pillars are in contact and conduct, forming a TSV structure, realizing the electrical connection between the chips, making the chips vertically connected, and shortening the signal transmission time. Reduce manufacturing costs.
  • each chip can make multiple TSV holes.
  • Chips close to the substrate can be connected to the substrate by solder balls, and TSV holes of two adjacent chips can also be connected by solder balls.
  • the chips close to the substrate and the substrate, and between the TSV holes of two adjacent chips can also be connected by conductive glue, conductive paste or alloy.
  • a chip usually refers to a semiconductor component carrying an integrated circuit, which is formed by steps such as wafer manufacturing, circuit design, packaging and testing. Specifically, a semiconductor is made into a wafer through processes such as crystal pulling and slicing, and the wafer is formed into a circuit through a semiconductor manufacturing process. structure, and then through cutting, packaging and other processes to form chips.
  • the memory in the embodiment of the present application includes at least two chips described in the following embodiments.
  • the two chips are stacked on the substrate, so that the memory has the advantages of chips.
  • the chip includes a substrate 10 .
  • the substrate 10 may be a silicon wafer
  • the substrate 10 is formed with through holes 14 penetrating the substrate
  • the through holes 14 are provided with conductive pillars 50
  • the through holes 14 filled with the conductive pillars 50 are TSV holes.
  • the TSV holes in two or more chips are in contact to form a TSV structure and realize vertical electrical connection between chips.
  • the through holes 14 can be formed by wet etching, laser processing, dry etching, and light-assisted electrochemical etching.
  • the required through holes 14 are formed by deep reactive ion etching (Deep Reactive Ion Etching, DRIE for short), and DRIE is used to form the through holes 14, the inner walls of the through holes 14 are smooth, and the mechanical and physical properties of the substrate 10 Damage is small.
  • DRIE Deep Reactive Ion Etching
  • the through holes 14 may be formed at different stages.
  • the through holes 14 may be formed after a back end of line process (BEOL for short) without changing the design process of the existing chip.
  • BEOL back end of line process
  • the first surface of the substrate 10 is the upper surface of the substrate 10
  • the cross-sectional shape of the through hole 14 is usually a circle, so as to facilitate the production of the through hole 14
  • the conductive pillars 50 are provided.
  • the through hole 14 may be a straight through hole or an oblique through hole, wherein the oblique through hole refers to a plane perpendicular to the first surface of the substrate 10 and including the center line of the through hole 14 as a cross section, and the cross sectional shape of the through hole 14 is an inverted trapezoid. .
  • the material of the conductive pillars 50 can be metal, for example, the material of the conductive pillars 50 is tungsten, copper, etc., so as to realize the interconnection of electrical signals between a plurality of stacked chips.
  • the material of the conductive pillars 50 is copper, for example, the copper pillars are formed in the through holes 14 by using a copper electroplating process.
  • an insulating layer and a barrier layer are further disposed between the through hole 14 and the conductive pillar 50 , wherein the insulating layer is close to the inner wall of the through hole 14 relative to the barrier layer.
  • the insulating layer is used to electrically isolate the conductive column 50 and the substrate 10 , and the insulating layer can be made of insulating materials such as silicon oxide or silicon nitride.
  • the barrier layer is used to prevent the metal from diffusing into the substrate 10 and improve the adhesion of the metal to improve the stability of the process.
  • the material of the barrier layer can be titanium, titanium nitride, tantalum, chromium, chromium nitride and the like.
  • the first surface of the substrate 10 is provided with a first annular groove 11 .
  • the upper surface of the substrate 10 is provided with a first annular groove 11 , and the first annular groove 11 is disposed around the conductive column 50 .
  • the first surface of the substrate 10 may also be provided with an electrical component 80, which is used to form an integrated circuit, and the electrical component 80 includes a metal-oxide-semiconductor (MOS) field effect transistor, a diode, a resistor, and capacitors, etc.
  • MOS metal-oxide-semiconductor
  • the first annular groove 11 forms a closed pattern around the conductive pillars 50, the conductive pillars 50 are located inside the closed pattern, and the electrical components are located outside the closed pattern, that is, the electrical components are located on the side of the first annular groove 11 away from its centerline.
  • a first spacer 20 is disposed in the first annular groove 11 , and the first spacer 20 is made of insulating material, such as silicon oxide, so as to electrically isolate the electrical element 80 from the conductive column 50 and ensure that the electrical element can work normally.
  • the depth of the first annular groove 11 is 0.2-2 ⁇ m, and the first annular groove 11 can be formed by a Shallow Trench Isolation (STI for short) process, mainly by groove carving Etching, oxide filling and oxide planarization steps are formed.
  • STI Shallow Trench Isolation
  • the cross-sectional shape of the first annular groove 11 is a regular polygon with a number of sides greater than or equal to eight.
  • the cross-sectional shape of the first annular groove 11 is a regular octagon.
  • This setting on the one hand, can alleviate the problem that the corners between the sides of the regular polygon are too sharp and the stress is concentrated. On the other hand, it can reduce the area of the Keep Out Zone (KOZ), in which electrical layout.
  • KZ Keep Out Zone
  • the diameter of the inscribed circle of the regular polygon is 5-40 ⁇ m.
  • the diameter of the inscribed circle of the side of the first annular groove 11 close to the conductive column is any value between 5 and 40 ⁇ m.
  • a plane perpendicular to the centerline of the through hole 14 is taken as the cross-section, and the cross-sectional shape of the first annular groove 11 is a circle to further reduce the area of the KOZ, so that the first annular groove 11 can be fully utilized. space on the surface.
  • the centerline of the first annular groove 11 may coincide with the centerline of the conductive column 50 , that is, the centerline of the first annular groove 11 and the centerline of the through hole 14 coincide.
  • the distances from each side of the first annular groove 11 to the center line of the conductive column 50 are approximately equal, so that the thermal stress on each side of the first annular groove 11 is approximately equal, thereby reducing the thermal stress at a certain place in the first annular groove 11. It is too large to cause the failure of the first annular groove 11 and the first spacer 20 located in the first annular groove 11 , thereby causing the failure of the electrical component 80 .
  • the first annular groove 11 is filled with the first spacer 20 , and the upper surface of the first spacer 20 may be flush with the upper surface of the substrate 10 .
  • a first air gap 21 extending along the circumferential direction of the first annular groove 11 is formed inside the first spacer 20 , that is, the first air gap 21 also surrounds the conductive column 50 .
  • the first air gap 21 can buffer thermal stress, so as to reduce the influence of thermal stress on the electrical components, so that the electrical components 80 can work normally.
  • the working principle of the first air gap 21 will be described in detail.
  • the thermal expansion coefficient of copper is greater than that of silicon
  • the conductive pillars 50 expand in volume, and thermal stress is generated between the conductive pillars 50 and the substrate 10 , resulting in the substrate 10 .
  • the silicon lattice in the region close to the conductive pillar 50 is squeezed and deformed.
  • the first air gap 21 in the first spacer 20 is used to release the thermal stress, so that the space outside the first annular groove 11 in the substrate 10 is released.
  • the silicon lattice in the region has little or no deformation, and the electrical components 80 on the region can work normally, that is, the influence of thermal stress on the region outside the first annular groove 11 can be alleviated or avoided through the first air gap 21 .
  • the cross-sectional shape of the first air gap 21 can be a triangle, a rectangle, a circle or an ellipse, and the first air gap 21 is not limited here.
  • the cross-sectional shape of an air gap 21 is not limited here.
  • the first spacer 20 may be deposited in the first annular groove 11 by chemical vapor deposition (Chemical Vapor Deposition, CVD for short) or physical vapor deposition (Physical Vapor Deposition, PVD for short), and by controlling the deposition rate, in the A first air gap 21 is formed in the first spacer 20 .
  • CVD Chemical Vapor Deposition
  • PVD Physical Vapor Deposition
  • the deposition rate is high, the first annular groove 11 is easy to seal, that is, the first air gap 21 is easy to be formed in the first spacer 20 .
  • the second annular groove 12 and/or the third annular groove 12 may also be provided on the first surface of the substrate 10, and the use of the multi-level isolation structure can further ensure the electrical isolation between the conductive pillars 50 and the electrical components, so as to avoid Make sure that the electrical components can work properly.
  • the depths of the first annular groove 11, the second annular groove 12 and the third annular groove 13 may be the same, so that the first annular groove 11, the second annular groove 12 and the third annular groove 13 It can be formed by one patterning process, which simplifies the fabrication steps of the chip.
  • the first surface of the substrate 10 is provided with a two-stage isolation structure, for example, the first surface of the substrate 10 is provided with a second annular groove 12 , and the second annular groove 12 is arranged around the first annular groove 11 .
  • the center line of the first annular groove 11, the center line of the second annular groove 12 and the center line of the conductive column 50 coincide, and take the plane parallel to the first surface of the substrate 10 as the cross section, the first annular groove 11 and the second annular groove
  • the cross-sectional shape of the annular groove 12 is matched.
  • the cross-sectional shapes of the first annular groove 11 and the second annular groove 12 are both regular octagons, and the corresponding sides of the first annular groove 11 and the second annular groove 12 are parallel to each other. Due to the large thermal stress in the area close to the conductive pillar 50 , the width of the first annular groove 11 is larger than the width of the second annular groove 12 along the radial direction of the through hole 14 .
  • a second spacer 30 is provided in the second annular groove 12 , and the material of the second spacer 30 may be the same as that of the first spacer 20 to further electrically isolate the conductive column 50 from the electrical components.
  • a second air gap 31 extending along the circumferential direction of the second annular groove 12 is formed inside the second spacer 30 to further relieve thermal stress while improving the effect of electrical isolation.
  • the second annular groove 12, the second spacer 30 and the second air gap 31 can be set with reference to the first annular groove 11, the first spacer 20 and the first air gap 21, which will not be repeated here.
  • the first surface of the base 10 is provided with a three-level isolation structure. As shown in FIGS. 1 and 2 , the first surface of the base 10 is further provided with a second annular groove 12 and a third annular groove 13.
  • the second annular groove 12 is sleeved outside the first annular groove 11
  • the second annular groove 12 is filled with a second spacer 30 .
  • the third annular groove 13 is sleeved outside the second annular groove 12
  • the third annular groove 13 is filled with a third spacer 40
  • the materials of the second spacer 30 and the third spacer 40 are both insulating materials.
  • the center line of the first annular groove 11 , the center line of the second annular groove 12 , the center line of the third annular groove 13 and the center line of the conductive column 50 coincide.
  • the cross-sectional shapes of the first annular groove 11, the second annular groove 12 and the third annular groove 13 are matched, for example, they are all regular octagons, and the Corresponding sides of the first annular groove 11, the second annular groove 12 and the third annular groove 13 are parallel to each other.
  • the width of the first annular groove 11 is greater than the widths of the second annular groove 12 and the third annular groove 13 , and the widths of the second annular groove 12 and the third annular groove 13 may be the same.
  • the first annular groove 11, the second annular groove 12 and the third annular groove 13 can be arranged at equal distances, and the distance between the first annular groove 11 and the second annular groove 12 can also be greater than the second annular groove 12 and the third annular groove 13 distances between.
  • the second air gap 31 extending along the circumferential direction of the second annular groove 12 may be formed only inside the second spacer 30 ; the third annular groove 13 may also be formed only inside the third spacer 40 .
  • a third air gap 41 extending in the circumferential direction; a second air gap 31 extending in the circumferential direction of the second annular groove 12 may also be formed inside the second spacer 30 , and a second air gap 31 extending in the circumferential direction of the second annular groove 12 may be formed inside the third spacer 40 .
  • the annular groove 13 is a third air gap 41 extending circumferentially.
  • a second air gap 31 is formed inside the second spacer 30
  • a third air gap 41 is formed inside the third spacer 40 .
  • the first spacer 20 , the second spacer 30 and the third spacer 40 can be formed at the same time, thereby reducing the number of processing steps.
  • the first air gap 21 , the second air gap 31 , and the second air gap 41 can play the role of stress relief step by step, and the thermal stress has less influence on the electrical component 80 .
  • the cross-sectional shapes of the first air gap 21, the second air gap 31 and the third air gap 41 can be all triangles, As shown in FIG. 3 , they may all be elliptical, as shown in FIG. 4 .
  • the second annular groove 12 , the second spacer 30 and the second air gap 31 , and the third annular groove 13 , the third spacer 40 and the third air gap 41 can all refer to the first annular groove 11 , the first spacer 20 and the first air gap 21, which will not be repeated here.
  • the chip having three annular grooves and three air gaps is taken as an example, and the manufacturing process and principle of the chip will be described in detail with reference to FIGS. 5 to 8 .
  • the material of the substrate 10 is silicon material, that is, the substrate 10 is a silicon substrate.
  • the substrate 10 includes an active area, and the active area is used for arranging the electrical components 80 .
  • the substrate 10 may be provided with through holes 14 , with a certain interval between the active region and the through holes 14 , and the through holes 14 are used for arranging conductive pillars 50 .
  • the through holes 14 may also not be provided in the substrate 10 , and the through holes 14 are provided after each annular groove and each air gap are formed in the substrate 10 .
  • each of the above-mentioned annular grooves may be formed by a patterning process. Specifically, a photoresist layer 60 is spin-coated on the upper surface of the substrate 10 . Then, the photoresist layer 60 is exposed and developed through a mask plate having the above-mentioned annular groove pattern, as shown in FIG. 5 , to obtain a patterned photoresist layer 60 . Then, the substrate 10 is etched by using the photoresist layer 60 as a mask, as shown in FIG. 6 , to form the above-mentioned annular groove. Finally, the remaining photoresist layer 60 is removed to obtain the first annular groove 11 , the second annular groove 12 and the third annular groove 13 .
  • the first annular groove 11 , the second annular groove 12 and the third annular groove 13 isolate the active area. , that is, the active area is located on the side of each annular groove away from the centerline thereof, so as to facilitate the subsequent electrical isolation of the electrical component 80 and the conductive column 50 .
  • the deposition may be chemical vapor deposition or physical vapor deposition, and the deposition may be performed at a lower temperature, for example, at 300-400° C., and each air gap is formed by controlling the deposition rate.
  • a deposition layer 70 on the upper surface of the substrate 10 is also formed, and the deposition layer 70 is used for subsequent polishing, as shown in FIG. 7 , that is, the first annular groove 11.
  • the second annular groove 12, the third annular groove 13 and the deposition layer 70 are integrated into one structure.
  • CMP Chemical Mechanical Polishing
  • the catalyst, surfactant, flow improver, stabilizer and other components in the polishing liquid are used to chemically react with the deposition layer 70 to soften the surface of the deposition layer 70, and then the softened layer is removed by physical and mechanical methods to expose the deposition layer. New surface for layer 70.
  • These two steps are carried out alternately, and finally the profiling is realized. That is to say, the deposition layer 70 on the substrate 10 is removed by mechanical cutting of abrasive grains and the etching action of chemical agents, so as to form a smooth upper surface of the substrate 10 .
  • the base body 10 is provided with a through hole 14 penetrating the substrate 10 , the through hole 14 is provided with a conductive column 50 , and the through hole 14 filled with the conductive column 50 forms a TSV hole for the chip and other parts to perform Electrical signal connection.
  • the first surface of the substrate 10 is provided with electrical components and a first annular groove 11 , the first annular groove 11 is arranged around the conductive pillars 50 , and the electrical components and the conductive pillars 50 are electrically isolated by the first annular grooves 11 .
  • a first spacer 20 is disposed in the first annular groove 11 , and a first air gap 21 extending along the circumferential direction of the first annular groove 11 is formed inside the first spacer 20 .
  • the thermal stress is released through the first air gap 21 in the first spacer 20, thereby reducing or avoiding the lattice deformation in the substrate 10 outside the first annular groove 11,
  • the local delamination of the chip is alleviated, the influence of thermal stress on the electrical components on the chip is reduced, the failure of the electrical components is reduced, and the pass rate of the chip is improved.
  • references to the terms “one embodiment,” “some embodiments,” “illustrative embodiments,” “examples,” “specific examples,” or “some examples” and the like are meant to incorporate embodiments A particular feature, structure, material, or characteristic described or exemplified is included in at least one embodiment or example of the present application.
  • schematic representations of the above terms do not necessarily refer to the same embodiment or example.
  • the particular features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

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Abstract

本申请提供一种芯片及存储器，涉及半导体技术领域，用于解决芯片的合格率低的技术问题。该芯片包括基底，基底中设有贯穿基底的通孔，通孔设有导电柱；基底的第一表面设有第一环形槽，第一环形槽环绕导电柱设置；第一环形槽中设有第一隔离件，第一隔离件内部形成有沿第一环形槽的周向延伸的第一空气隙，导电柱与基底之间产生热应力时，通过第一隔离件中的第一空气隙对热应力进行释放，从而减轻或者避免第一环形槽外的基底中晶格变形，缓解芯片局部分层，减轻热应力对芯片上的电气元件的影响，减少电气元件的失效，进而提高芯片的合格率。

Description

芯片及存储器
本申请要求于2020年09月09日提交中国专利局、申请号为202010950123.7、申请名称为“芯片及存储器”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体技术领域，尤其涉及一种芯片及存储器。
背景技术
随着半导体制造技术和立体封装技术的不断发展，电子产品趋向小型化、高度集成化，芯片的封装尺寸不断减小，叠层芯片封装技术应运而生。叠层芯片封装技术也称为三维封装技术，是指在同一个封装体内的垂直方向叠放两个以上芯片的封装技术。例如，动态随机存储器(Dynamic Random Access Memory，简称DRAM)中，通过三维封装技术将多个芯片垂直堆叠并相互连通，以提高DRAM的存储容量及带宽。
在三维封装技术中，硅通孔技术(Through Silicon Via，简称TSV)通过在各芯片的硅片上制作相对应的通孔，通孔中填充导电材料，以实现堆叠的芯片之间的垂直导通，缩短了互连距离，减少互连延时，同时可以提高芯片上的器件的运行效率，降低功耗，因此得到广泛应用。采用TSV技术形成的结构一般称为TSV结构，TSV结构中通常以铜作为填充在通孔中的导电材料，铜的热膨胀系数(Coefficient of Thermal Expansion，简称CTE)为17.8×10 -6/K，硅的热膨胀系数为2.5×10 -6/K，使得TSV结构中的铜与硅片之间存在热膨胀系数失配问题，当作为信号通道的TSV结构自发热或者当来自环境热源的热量增加时，TSV结构与硅片之间产生热应力，TSV结构附近的硅片的晶格变形，硅片的电子迁移率改变，导致芯片局部分层以及芯片上的电气元件易失效，影响芯片的合格率。
发明内容
鉴于上述问题，本申请提供一种芯片及存储器，用于降低TSV结构热膨胀对电气元件的影响，提高芯片的合格率。
为了实现上述目的，本申请提供如下技术方案：
第一方面，本申请提供一种芯片，包括基底，所述基底中设有贯穿所述基底的通孔，所述通孔设有导电柱；所述基底的第一表面设有第一环形槽，所述第一环形槽环绕所述导电柱设置；所述第一环形槽中设有第一隔离件，所述第一隔离件内部形成有沿所述第一环形槽的周向延伸的第一空气隙。
本申请提供的芯片具有如下优点：
本申请提供的芯片中，基体设有贯穿基底的通孔，通孔设有导电柱，填充有导电柱的通孔形成TSV孔，用于芯片与其他部件的电信号连接；基底的第一表面设有第一环形槽，第一环形槽环绕导电柱设置；第一环形槽中设有第一隔离件，第一隔离件内部形成有沿第一环形槽的周向延伸的第一空气隙，导电柱与基底之间产生热应力时，通过第一隔离件中的第一空气隙对热应力进行释放，从而减轻或者避免第一环形槽外的基底中晶格变形，缓解芯片局部分层，减轻热应力对芯片上的电气元件的影响，减少电气元件的失效，进而提高芯片的合格率。
如上所述的芯片中，以垂直于所述通孔的中心线的平面为截面，所述第一环形槽的截面形状为边数大于或等于八的正多边形。
如上所述的芯片中，所述正多边形的内切圆直径为5～40μm。
如上所述的芯片中，沿所述通孔的中心线的方向，所述第一环形槽的深度为0.2～2μm。
如上所述的芯片中，所述第一环形槽的中心线与所述通孔的中心线相重合。
如上所述的芯片中，以垂直于所述基底的第一表面且包含所述通孔的中心线的平面为截面，所述第一空气隙的截面形状为三角形、长方形、圆形或者椭圆形。
如上所述的芯片中，所述基底的第一表面还设有第二环形槽和第三环形槽；所述第二环形槽套设于所述第一环形槽外，且所述第二环形槽中填充有第二隔离件；所述第三环形槽套设于所述第二环形槽外，且所述第三环形槽中填充有第三隔离件。
如上所述的芯片中，所述第二隔离件内部形成有沿所述第二环形槽的周向延伸的第二空气隙；和/或所述第三隔离件内部形成有沿所述第三环形槽的周向延伸的第三空气隙。
如上所述的芯片中，沿所述通孔的径向，所述第一环形槽的宽度大于所述第二环形槽和所述第三环形槽的宽度。
第二方面，本申请还提供一种存储器，包括堆叠设置的至少两个如上所述的芯片，相邻的所述芯片中的导电柱对接。
本申请提供的存储器中，由于具有上述芯片，因为也具有合格率高的优点，具体效果参照上文所述，在此不再赘述。
附图说明
图1为本申请实施例中的芯片的结构示意图；
图2为本申请实施例中的芯片的剖视图；
图3为本申请实施例中的芯片的一种结构的局部示意图；
图4为本申请实施例中的芯片的另一种结构的局部示意图；
图5为本申请实施例中的掩膜示意图；
图6为本申请实施例中的刻蚀示意图；
图7为本申请实施例中的沉积示意图；
图8为本申请实施例中的芯片的制作流程图。
具体实施方式
本申请实施例提供一种芯片，芯片设置有TSV孔，环绕TSV孔设置浅槽隔离，浅槽中填充隔离材料，隔离材料内形成沿浅槽周向延伸的空气隙，使得隔离材料在对电气元件隔离的同时空气隙起到释放应力的作用，减TSV孔热膨胀对浅槽外的电气元件的影响，进而减少电气元件的失效，提高芯片的合格率。
为了使本申请实施例的上述目的、特征和优点能够更加明显易懂，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造 性劳动的前提下所获得的所有其它实施例，均属于本申请保护的范围。
存储器可以临时或者永久地存储数据组，其中，动态随机存储器依靠电容存储电荷来寄存信息，是一种临时性数据存储介质，常用作内存。动态随机存储器通常包括衬底、堆叠在衬底上的至少两个芯片，以及对各芯片进行电连接的TSV结构。
具体的，动态随机存储器中的每个芯片都设置有通孔，通孔中填充导电柱，形成TSV孔。当各芯片堆叠后，各芯片的TSV孔相对应，使得导电柱相接触而导通，形成TSV结构，实现各芯片之间的电连接，使得各芯片之间垂直连接，缩短了信号传递时间，降低制造成本。
其中，每个芯片可以制作多个TSV孔。靠近衬底的芯片与衬底之间可以通过焊球连接，相邻两个芯片的TSV孔之间也可以通过焊球连接。当然，靠近衬底的芯片与衬底之间，以及相邻两个芯片的TSV孔之间也可以通过导电胶、导电浆或者合金连接。
芯片通常是指载有集成电路的半导体元件，由晶圆制造、电路设计和封装测试等步骤形成，具体的，半导体经拉晶、切片等工序制成晶圆，晶圆通过半导体制造工艺形成电路结构，再经切割、封装等工序形成芯片。
由于晶圆的材质通常为硅，因此本实施例及以下各实施例均以硅晶圆为例进行详细描述，本申请实施例中的存储器中至少包括两个下文实施例中所述的芯片，这两个芯片在衬底上堆叠设置，使得存储器具有芯片所具有的优点。
参照图1和图2，芯片包括基底10。本申请实施例中，基底10可以为硅晶圆，基底10形成有贯穿基板的通孔14，通孔14中设有导电柱50，填充导电柱50后的通孔14为TSV孔。两个或者两个以上的芯片中的TSV孔相接触，形成TSV结构，实现芯片之间的垂直电连接。
通孔14可以通过湿法刻蚀、激光加工、干法刻蚀以及光辅助电化学刻蚀等方式形成。例如，本申请实施例中，通过深反应离子刻蚀(Deep Reactive Ion Etching，简称DRIE)形成所需通孔14，采用DRIE形成通孔14，通孔14的内壁平滑，基底10的机械及物理损伤较小。
通孔14的形成可以在不同的阶段，例如，在后道工序(Back End of Line， 简称BEOL)之后制作通孔14可以不改变现有芯片的设计流程。
以平行于基底10的第一表面的平面为截面，如图2所示，基底10的第一表面为基底10的上表面，通孔14的截面形状通常为圆形，以便于制作通孔14以及设置导电柱50。通孔14可以为直通孔或者斜通孔，其中，斜通孔是指以垂直于基底10的第一表面且包含通孔14的中心线的平面为截面，通孔14的截面形状呈倒梯形。
导电柱50的材质可以为金属，例如导电柱50的材质为钨、铜等，以实现多个堆叠的芯片之间的电信号互连。本申请实施例中，导电柱50的材质为铜，例如，采用电镀铜工艺在通孔14中形成铜柱。
可以理解的是，通孔14与导电柱50之间还设置有绝缘层和阻挡层，其中，绝缘层相对阻挡层靠近通孔14的内壁。绝缘层用于电气隔离导电柱50和基底10，绝缘层的材质可以为氧化硅或者氮化硅等绝缘材质。阻挡层用于防止金属扩散至基底10中，并提高金属的粘附性，以提高工艺的稳定性，阻挡层的材质可以为钛、氮化钛、钽、铬、氮化铬等。
继续参照图1和图2，基底10的第一表面设置有第一环形槽11。如图2所示，基底10的上表面设置有第一环形槽11，第一环形槽11环绕导电柱50设置。基底10的第一表面还可以设置有电气元件80，电气元件80用于形成集成电路，电气元件80包括金属-氧化物-半导体(Metal Oxide Semiconductor，简称MOS)场效应晶体管、二极管、电阻、以及电容等。
具体的，第一环形槽11环绕导电柱50形成封闭图形，导电柱50位于封闭图形的内部，电气元件位于封闭图形的外部，即电气元件位于第一环形槽11远离其中心线的一侧。第一环形槽11中设置有第一隔离件20，第一隔离件20为绝缘材质，例如氧化硅，使得电气元件80与导电柱50之间电气隔离，保证电气元件可以正常工作。
具体的，沿通孔14的中心线的方向，第一环形槽11的深度为0.2～2μm，第一环形槽11可以通过浅槽隔离工艺(Shallow Trench Isolation，简称STI)成型，主要通过槽刻蚀、氧化物填充及氧化物平坦化等步骤形成。
以垂直于通孔14的中心线的平面为截面，第一环形槽11的截面形状为边数大于或等于八的正多边形。例如，参照图1，第一环形槽11的截面形状 为正八边形。如此设置，一方面可以缓解正多边形各边之间拐角处过于尖锐，应力集中的问题，另一方面，可以减少排除区域(Keep Out Zone，简称KOZ)的面积，在该区域中不可以进行电气布局。
需要说明的是，第一环形槽11的截面形状为边数大于或等于八的正多边形时，正多边形的内切圆直径为5～40μm。本申请实施例中，第一环形槽11靠近导电柱的一侧的内切圆直径为5～40μm之间的任意一个数值。
在另一种可能的示例中，以垂直于通孔14的中心线的平面为截面，第一环形槽11的截面形状为圆形，进一步减少KOZ的面积，从而可以充分利用基底10的第一表面上的空间。
继续参照图1和图2，第一环形槽11的中心线可以与导电柱50的中心线相重合，即第一环形槽11的中心线与通孔14的中心线相重合。如此设置，第一环形槽11各边距离导电柱50的中心线的距离大致相等，使得第一环形槽11各边处的热应力大致相等，从而减少第一环形槽11中某处热应力过大而导致第一环形槽11及位于第一环形槽11中的第一隔离件20失效，进而导致电气元件80失效。
第一环形槽11中填充有第一隔离件20，第一隔离件20的上表面可以与基底10的上表面齐平。第一隔离件20的内部形成有沿第一环形槽11的周向延伸的第一空气隙21，即第一空气隙21也环绕导电柱50一周。第一空气隙21可以对热应力起到缓冲作用，以减少热应力对电气元件的影响，使得电气元件80可以正常工作。
以导电柱50的材质为铜，第一隔离件20的材质为二氧化硅，基底10的材质为硅为例，详述第一空气隙21的工作原理。
由于铜的热膨胀系数大于硅的热膨胀系数，当电流通过导电柱50使得导电柱50产生热量，或者环境热源的热量增加时，导电柱50体积膨胀，与基底10之间产生热应力，导致基底10中靠近导电柱50的区域硅晶格受到挤压发生变形。当热应力传递至第一隔离件20时，由于空气具有可压缩性，第一隔离件20中的第一空气隙21用于释放热应力，从而使得基底10中位于第一环形槽11外的区域硅晶格变形较小或者不发生变形，位于该区域上的电气元件80可以正常工作，即通过第一空气隙21可以减轻或者避免热应力对第一 环形槽11外的区域的影响。
需要说明的是，以垂直于基底10的表面且包含通孔14的中心线的平面为截面，第一空气隙21的截面形状可以为三角形、长方形、圆形或者椭圆形，在此不限定第一空气隙21的截面形状。
具体的，可以通过化学气相沉积(Chemical Vapor Deposition，简称CVD)或者物理气相沉积(Physical Vapor Deposition，简称PVD)在第一环形槽11中沉积形成第一隔离件20，并通过控制沉积速率，在第一隔离件20中形成第一空气隙21。例如，当沉积速率较快时，第一环形槽11易封口，即第一隔离件20中易形成第一空气隙21。
需要说明的是，基底10的第一表面还可以设置有第二环形槽12和/或第三环形槽12，采用多级隔离结构可以进一步保证导电柱50与电气元件之间的电气隔离，以保证电气元件可以正常工作。
沿通孔14的中心线方向，第一环形槽11、第二环形槽12和第三环形槽13的深度可以一致，以使第一环形槽11、第二环形槽12和第三环形槽13可以通过一次构图工艺形成，简化芯片的制作步骤。
在一种可能的示例中，基底10的第一表面设置有两级隔离结构，例如，基底10的第一表面设置有第二环形槽12，第二环形槽12环绕第一环形槽11设置。第一环形槽11的中心线、第二环形槽12的中心线和导电柱50的中心线相重合，且以平行于基底10的第一表面的平面为截面，第一环形槽11与第二环形槽12的截面形状相匹配。
例如，第一环形槽11与第二环形槽12的截面形状均为正八边形，且第一环形槽11和第二环形槽12中相对应的边相互平行。因靠近导电柱50的区域有较大的热应力，沿通孔14径向方向，第一环形槽11的宽度大于第二环形槽12的宽度。
需要说明的是，第二环形槽12中设置有第二隔离件30，第二隔离件30的材质可以与第一隔离件20的材质一致，进一步对导电柱50和电气元件进行电气隔离。第二隔离件30的内部形成有沿第二环形槽12的周向延伸的第二空气隙31，在提高电气隔离的效果的同时，进一步释放热应力。第二环形槽12、第二隔离件30和第二空气隙31可以参照第一环形槽11、第一隔离件 20和第一空气隙21设置，在此不再赘述。
在另一种可能的示例中，基底10的第一表面设置有三级隔离结构，如图1和图2所示，基体10的第一表面还设置有第二环形槽12和第三环形槽13，第二环形槽12套设于第一环形槽11外，第二环形槽12中填充有第二隔离件30。第三环形槽13套设于第二环形槽12外，第三环形槽13中填充有第三隔离件40，第二隔离件30和第三隔离件40的材质均为绝缘材质。
第一环形槽11的中心线、第二环形槽12的中心线、第三环形槽13的中心线和导电柱50的中心线相重合。参照图1，以平行于基底10的第一表面的平面为截面，第一环形槽11、第二环形槽12和第三环形槽13的截面形状相匹配，例如均为正八边形，且第一环形槽11、第二环形槽12和第三环形槽13中相对应的边相互平行。
沿通孔14径向方向，第一环形槽11的宽度大于第二环形槽12和第三环形槽13的宽度，第二环线槽12和第三环形槽13的宽度可以一致。第一环形槽11、第二环形槽12和第三环形槽13可以等距离设置，第一环形槽11和第二环形槽12之间的距离也可以大于第二环形槽12和第三环形槽13之间的距离。
需要说明的是，可以只在第二隔离件30内部形成有沿第二环形槽12周向延伸的第二空气隙31；也可以只在第三隔离件40内部形成有沿第三环形槽13周向延伸的第三空气隙41；也可以在第二隔离件30内部形成有沿第二环形槽12周向延伸的第二空气隙31，且在第三隔离件40内部形成有沿第三环形槽13周向延伸的第三空气隙41。
参照图2，本申请实施例中，第二隔离件30内部形成有第二空气隙31，第三隔离件40内部形成有第三空气隙41。如此设置，一方面第一隔离件20、第二隔离件30和第三隔离件40可以同时成型，减少加工步骤。另一方面，第一空气隙21、第二空气隙31和第二空气隙41可以逐级起到释放应力作用，热应力对电气元件80影响较小。
需要说明的是，以垂直于基底10的表面且包含通孔14的中心线的平面为截面，第一空气隙21、第二空气隙31和第三空气隙41的截面形状可以均为三角形，如图3所示，也可以均为椭圆形，如图4所示。
第二环形槽12、第二隔离件30和第二空气隙31，以及第三环形槽13、第三隔离件40和第三空气隙41均可以参照第一环形槽11、第一隔离件20和第一空气隙21设置，在此不再赘述。
以下以芯片具有三个环形槽和三个空气隙为例，并结合附图5至图8详述芯片的制作过程及原理。
S101、准备基底。
本申请实施例中，基底10的材质为硅材质，即基底10为硅基底。其中，基底10包括有源区域，有源区域用于设置电气元件80。
基底10可以设置有通孔14，有源区域和通孔14之间具有一定间隔，通孔14中用于设置导电柱50。基底10中也可以未设置通孔14，在基底10形成各环形槽和各空气隙后再设置通孔14。
S102、在基底上刻蚀形成第一环形槽、第二环形槽和第三环形槽。
本申请实施例中，上述各环形槽可以通过构图工艺形成，具体的，在基底10的上表面旋涂光刻胶层60。再通过具有上述环形槽图形的掩膜板对光刻胶层60进行曝光后显影，如图5所示，得到图案化的光刻胶层60。然后以光刻胶层60为掩膜对基底10进行刻蚀，如图6所示，形成上述环形槽。最后去除剩余的光刻胶层60，得到第一环形槽11、第二环形槽12和第三环形槽13，第一环形槽11、第二环形槽12和第三环形槽13隔离有源区域，即有源区域位于各环形槽远离其中心线的一侧，以便于后续对电气元件80和导电柱50进行电气隔离。
S103、分别在第一环形槽、第二环形槽和第三环形槽中进行沉积，形成第一隔离件、第二隔离件和第三隔离件和沉积层，第一隔离件、第二隔离件和第三隔离件内部分别形成周向延伸的第一空气隙、第二空气隙和第三空气隙。
本申请实施例中，沉积可以为化学气相沉积或者物理气相沉积，沉积可以在较低的温度下进行，例如在300～400℃下进行沉积，通过控制沉积速率以形成各空气隙。
需要说明的是，沉积过程中除了形成各隔离件和各空气隙外，还形成位于基底10上表面的沉积层70，沉积层70用于后续抛光，如图7所示，即第 一环形槽11、第二环形槽12、第三环形槽13和沉积层70为一体结构。
S104、对基底进行化学机械抛光。
化学机械抛光(Chemical Mechanical Polishing，简称CMP)用于对基底10进行平坦化处理。具体的，利用抛光液中的催化剂、表面活性剂、流动改进剂、稳定剂等成分与沉积层70进行化学反应，软化沉积层70表面，然后利用物理机械的方法去除该软化层，裸露出沉积层70的新表面。这两步循环交替进行，最终实现剖光。也就是说，借助磨粒的机械切削及化学试剂的腐蚀作用来去除基底10上的沉积层70的，形成光洁的基底10上表面。
需要说明的是，上述步骤为芯片制作的部分流程，用于形成各环形槽和各空气隙，其余制作过程可参照现有技术，在此不再赘述。
本申请实施例提供的芯片中，基体10设有贯穿基底10的通孔14，通孔14设有导电柱50，填充有导电柱50的通孔14形成TSV孔，用于芯片和其他部分进行电信号连接。基底10的第一表面设有电气元件和第一环形槽11，第一环形槽11环绕导电柱50设置，电气元件和导电柱50由第一环形槽11电气隔离。第一环形槽11中设有第一隔离件20，第一隔离件20内部形成有沿第一环形槽11的周向延伸的第一空气隙21。导电柱50与基底10之间产生热应力时，通过第一隔离件20中的第一空气隙21对热应力进行释放，从而减轻或者避免第一环形槽11外的基底10中晶格变形，缓解芯片局部分层，减轻热应力对芯片上的电气元件的影响，减少电气元件的失效，进而提高芯片的合格率。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
本领域技术人员应理解的是，在本申请的揭露中，术语“纵向”、“横向”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系是基于附图所示的方位或位置关系，其仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的系统或元件必须具有特定的方位、以特定的方位构造和操作，因此上述术语不能理解为对本申请的限制。
在本说明书的描述中，参考术“一个实施方式”、“一些实施方式”、“示意性实施方式”、“示例”、“具体示例”、或“一些示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本申请的至少一个实施方式或示例中。在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (10)

  1. 一种芯片，其特征在于，包括基底，所述基底中设有贯穿所述基底的通孔，所述通孔设有导电柱；
    所述基底的第一表面设有第一环形槽，所述第一环形槽环绕所述导电柱设置；
    所述第一环形槽中设有第一隔离件，所述第一隔离件内部形成有沿所述第一环形槽的周向延伸的第一空气隙。
  2. 根据权利要求1所述的芯片，其特征在于，以垂直于所述通孔的中心线的平面为截面，所述第一环形槽的截面形状为边数大于或等于八的正多边形。
  3. 根据权利要求2所述的芯片，其特征在于，所述正多边形的内切圆直径为5～40μm。
  4. 根据权利要求1所述的芯片，其特征在于，沿所述通孔的中心线的方向，所述第一环形槽的深度为0.2～2μm。
  5. 根据权利要求1所述的芯片，其特征在于，所述第一环形槽的中心线与所述通孔的中心线相重合。
  6. 根据权利要求1所述的芯片，其特征在于，以垂直于所述基底的第一表面且包含所述通孔的中心线的平面为截面，所述第一空气隙的截面形状为三角形、长方形、圆形或者椭圆形。
  7. 根据权利要求1所述的芯片，其特征在于，所述基底的第一表面还设有第二环形槽和第三环形槽；
    所述第二环形槽套设于所述第一环形槽外，且所述第二环形槽中填充有第二隔离件；
    所述第三环形槽套设于所述第二环形槽外，且所述第三环形槽中填充有第三隔离件。
  8. 根据权利要求7所述的芯片，其特征在于，所述第二隔离件内部形成有沿所述第二环形槽的周向延伸的第二空气隙；和/或
    所述第三隔离件内部形成有沿所述第三环形槽的周向延伸的第三空气隙。
  9. 根据权利要求7所述的芯片，其特征在于，沿所述通孔的径向，所 述第一环形槽的宽度大于所述第二环形槽和所述第三环形槽的宽度。
  10. 一种存储器，其特征在于，包括堆叠设置的至少两个如权利要求1所述的芯片，相邻的所述芯片中的导电柱对接。
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