WO2022047879A1 - 一种阵列基板及其制备方法、显示面板、拼接显示器 - Google Patents

一种阵列基板及其制备方法、显示面板、拼接显示器 Download PDF

Info

Publication number
WO2022047879A1
WO2022047879A1 PCT/CN2020/120100 CN2020120100W WO2022047879A1 WO 2022047879 A1 WO2022047879 A1 WO 2022047879A1 CN 2020120100 W CN2020120100 W CN 2020120100W WO 2022047879 A1 WO2022047879 A1 WO 2022047879A1
Authority
WO
WIPO (PCT)
Prior art keywords
patterned conductive
driving circuit
circuit layer
connection part
array substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2020/120100
Other languages
English (en)
French (fr)
Inventor
向昌明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
TCL China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by TCL China Star Optoelectronics Technology Co Ltd filed Critical TCL China Star Optoelectronics Technology Co Ltd
Priority to US17/053,754 priority Critical patent/US12506105B2/en
Publication of WO2022047879A1 publication Critical patent/WO2022047879A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/411—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by materials, geometry or structure of the substrates
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07331—Connecting techniques
    • H10W72/07337—Connecting techniques using a polymer adhesive, e.g. an adhesive based on silicone or epoxy
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/321—Structures or relative sizes of die-attach connectors
    • H10W72/325—Die-attach connectors having a filler embedded in a matrix
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/351—Materials of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/351—Materials of die-attach connectors
    • H10W72/353—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics
    • H10W72/354—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics comprising polymers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Definitions

  • the present application relates to the field of display technology, and in particular, to an array substrate and a preparation method thereof, a display panel, and a spliced display.
  • Display panels typically have narrow bezel or bezel-less designs.
  • a design with a narrow frame or no frame places higher requirements on the driver IC (chip) package.
  • the connection between the driver IC and the display panel is done through a bonding process.
  • the binding position of the driver IC is reserved.
  • COF chip on film
  • the line of the bent COF is not only prone to damage, which affects the conduction of the line, but also has a large gap between it and the side surface of the display panel.
  • the driver IC is arranged on the back of the display panel through the bonding structure, and then the printed circuit board and the driver IC are bonded to avoid the bending of the COF, due to technical limitations, the existing bonding structure is not compatible with the display panel. There are still gaps on the sides, and an outer frame of a certain width needs to be set to cover, and it is impossible to realize the narrow border or no border of the display, especially the splicing display.
  • the present application provides an array substrate and a preparation method thereof, a display panel, and a spliced display to avoid large gaps generated by the binding structure and the side of the display panel, which affects the realization of a narrow frame or a frameless design.
  • an array substrate including:
  • a driving circuit layer arranged on the substrate
  • a binding area is provided on the surface of the substrate away from the driving circuit layer for binding external circuits
  • the back binding structure includes a first connection part and a patterned conductive line, the first connection part is located in the binding area, and the The patterned conductive circuit is attached to the side surface of the substrate, the driving circuit layer and the first connection part, one end of the patterned conductive circuit is electrically connected to the driving circuit layer, and the other end is electrically connected to the Describe the first connection part.
  • the material of the patterned conductive traces includes a conductive polymer.
  • the conductive polymer is a composite material formed from a photocurable material and a conductive filler.
  • the back binding structure further includes a second connection part, the second connection part is disposed on a surface of the driving circuit layer away from the substrate, and the second connection part is connected to the driving circuit layer and the patterned conductive traces.
  • the first connection portion includes a first portion covered by the patterned conductive line and a second portion not covered by the patterned conductive line, and the external circuit connects the second portion.
  • the patterned conductive line completely covers the first connection portion, and the external circuit connects the area of the patterned conductive line that covers the first connection portion.
  • the present application also provides a method for preparing an array substrate, comprising the following steps:
  • a binding area is provided on the side of the substrate away from the driving circuit layer for binding external circuits
  • the back binding structure connects the binding region and the driving circuit layer
  • the step of forming the back bonding structure includes forming a first connection portion in the bonding area, and forming a patterned conductive circuit so that the patterned conductive circuit is attached to the substrate and the driving circuit. layer and the side surface of the first connection part, and one end of the patterned conductive circuit is electrically connected to the driving circuit layer, and the other end is electrically connected to the first connection part.
  • the step of forming the patterned conductive circuit includes: coating a conductive prepolymer film on the sides of the substrate, the driving circuit layer and the first connection part; The object film is exposed and developed to form the patterned conductive circuit.
  • the material of the patterned conductive traces includes a conductive polymer.
  • the conductive polymer is a composite material formed from a photocurable material and a conductive filler.
  • the step of forming the back bonding structure further includes: forming a second connection part on the surface of the driving circuit layer away from the substrate, the second connection part connecting the driving circuit layer and the The patterned conductive lines are described.
  • the patterned conductive line covers a part of the surface of the first connection part away from the substrate, and the surface not covered by the patterned conductive line is connected to the external circuit.
  • the patterned conductive line completely covers the first connection portion, and the external circuit is connected to the area of the patterned conductive line that covers the first connection portion.
  • the present application provides a display panel, including an array substrate, the array substrate includes:
  • a driving circuit layer disposed on the substrate
  • a binding area is provided on the surface of the substrate away from the driving circuit layer for binding external circuits
  • the back binding structure includes a first connection part and a patterned conductive line, the first connection part is located in the binding area, and the The patterned conductive circuit is attached to the side surface of the substrate, the driving circuit layer and the first connection part, one end of the patterned conductive circuit is electrically connected to the driving circuit layer, and the other end is electrically connected to the Describe the first connection part.
  • the material of the patterned conductive traces includes a conductive polymer.
  • the conductive polymer is a composite material formed from a photocurable material and a conductive filler.
  • the back binding structure further includes a second connection part, the second connection part is disposed on a surface of the driving circuit layer away from the substrate, and the second connection part is connected to the driving circuit layer and the patterned conductive traces.
  • the first connection portion includes a first portion covered by the patterned conductive line and a second portion not covered by the patterned conductive line, and the external circuit connects the second portion.
  • the patterned conductive line completely covers the first connection portion, and the external circuit connects the area of the patterned conductive line that covers the first connection portion.
  • the present application provides a spliced display, which is formed by splicing one or more display panels as described above.
  • the present application provides an array substrate, which includes a base, a driving circuit layer and a back bonding structure, and a surface of the base away from the driving circuit layer has a binding area for binding an external circuit
  • the back binding structure includes a first connection part and a patterned conductive circuit, the first connection part is located in the binding area, and the patterned conductive circuit is attached to the substrate, the driving circuit layer and the On the side surface of the first connection portion, the patterned conductive structure is closely attached to the side surface of the array substrate, one end is electrically connected to the driving circuit layer, and the other end is electrically connected to the first connection portion.
  • the patterned conductive structure avoids large gaps between the back-bonded structure and the side of the array substrate, and is beneficial to realizing ultra-narrow or frameless displays, especially spliced displays.
  • FIG. 1 is a schematic cross-sectional view of an array substrate according to an embodiment of the present application.
  • FIG. 2 is a schematic cross-sectional view of another array substrate according to an embodiment of the present application.
  • FIG. 3 is a schematic cross-sectional view of yet another array substrate according to an embodiment of the present application.
  • FIG. 4 is a schematic flowchart of a method for fabricating an array substrate according to an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of an array substrate after coating a conductive prepolymer film in an array substrate manufacturing process according to an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of an array substrate during exposure in an array substrate manufacturing process according to an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of an array substrate after development in an array substrate manufacturing process provided by an embodiment of the present application.
  • FIG. 1 is a schematic cross-sectional view of an array substrate according to an embodiment of the present application.
  • Embodiments of the present application provide an array substrate 100 , which includes a base 110 and a driving circuit layer 120 disposed on the base 110 .
  • the surface of the substrate 110 facing away from the driving circuit layer 120 has a bonding area 111 for bonding the external circuit 140 .
  • the external circuit 140 includes a driving IC and a printed circuit board connected to the driving IC.
  • the binding area 111 is used for binding the driver IC.
  • the driver IC may be COF or TCP (Tape Carrier Package), which is not particularly limited in this application.
  • the binding area 111 is located at the edge area of the substrate 110, as shown in FIG.
  • the array substrate 100 further includes a back bonding structure 130 .
  • the back bonding structure 130 is electrically connected to the driving circuit layer 120 and the bonding region 111 . Specifically, it is electrically connected to the thin film transistors in the driving circuit layer 120 .
  • the back bonding structure 130 includes a first connection part 131 and a patterned conductive line 132 , the first connection part 131 is located in the bonding area 111 , and the patterned conductive line 132 is attached to the substrate 110 , the driving circuit layer 120 and the first connection part 131 side.
  • One end of the patterned conductive line 132 is electrically connected to the driving circuit layer 120 , and specifically, is electrically connected to the thin film transistor in the driving circuit layer 120 . The other end is electrically connected to the first connection portion 131 .
  • the back bonding structure 130 further includes a second connection portion 133 , and the second connection portion 133 is located on a surface of the driving circuit layer 120 away from the substrate 110 .
  • the second connection parts 133 are respectively connected to the driving circuit layer 120 and the patterned conductive lines 132 .
  • the patterned conductive circuit 132 is electrically connected to the driving circuit layer 120 through the second connection portion 133 .
  • FIG. 2 is a schematic cross-sectional view of another array substrate 200 according to an embodiment of the present application.
  • the difference between the array substrate 200 and the array substrate 100 is the back bonding structure 230 , and other structures are the same.
  • the patterned conductive line 232 completely covers the first connection portion 231 in addition to the side surfaces of the substrate 210 and the driving circuit layer 220 .
  • the external circuit 240 is connected to the area of the patterned conductive line 232 covering the first connection portion 231 .
  • the driving IC is connected to the area of the patterned conductive line 232 covering the first connection portion 231 .
  • the patterned conductive line 232 may also completely or partially cover the second connection part 233 , and the second connection part 233 is connected to the thin film transistor in the driving circuit layer 220 .
  • FIG. 3 is a schematic cross-sectional view of yet another array substrate 300 according to an embodiment of the present application.
  • the difference between the array substrate 300 and the array substrate 100 is the back bonding structure 330 , and other structures are the same.
  • the patterned conductive line 332 covers the first portion 3311 of the first connection portion 331 except for the side surfaces of the substrate 310 and the driving circuit layer 320 .
  • the portion of the first connection portion that is not covered by the patterned conductive line 332 is the second portion 3312 .
  • the driver IC in the external circuit 340 is connected to the second part 3312 .
  • the patterned conductive line 332 may completely cover the second connection portion 332 , or may only cover a part of the second connection portion 333 , and the second connection portion 333 is connected to the thin film transistor in the driving circuit layer 320 .
  • the patterned conductive lines described above can be made of conductive polymers.
  • the conductive polymer can be a conductive composite material, and its resistivity is between 10 -7 -10 -5 ⁇ m.
  • the conductive composite material is usually formed by adding conductive fillers to a matrix such as resin.
  • the conductive polymer has good electrical conductivity, high corrosion resistance, bending resistance and strong designability. Due to the bending resistance or fatigue resistance of the conductive polymer, damage to the patterned conductive circuit during the bending process can be avoided, and the stability of the display panel can be improved. Due to its strong designability, it can be closely attached to the side of the array substrate by using special processes and special physical properties.
  • the material of the patterned conductive circuit of the present application is not limited to conductive polymers, and can also be other materials with bending resistance and high conductivity. There is no specific limitation here.
  • the matrix may be a photosensitive resin.
  • a photosensitive resin such as epoxy acrylate, urethane acrylate, unsaturated polyester, polyester acrylate, polyether acrylate, pure acrylic resin, epoxy resin, silicone oligomer, etc.
  • the epoxy acrylate can be bisphenol A type epoxy acrylate, novolac type epoxy acrylate and the like.
  • the organosilicon oligomer may be an acryloxy-bearing organosilicon acrylate oligomer.
  • the conductive filler can be metal or conductive carbon material or the like.
  • the metal may be nanoscale metal, such as nanosilver.
  • the conductive carbon material can be carbon black, carbon nanotubes, carbon fibers, graphene and other carbonaceous fillers.
  • the photocurable resin is a mixed ester composed of epoxy acrylate and urethane acrylate, and the ratio of the substances is 2:3.
  • the conductive filler is nano-silver, and the filling amount of the nano-silver is 60% (the filling amount refers to the percentage of the mass of the nano-silver to the total mass of the nano-silver and the photocurable resin).
  • the nano-silver can be one of silver nano-spherical particles or silver nano-sheets, or a mixture of the two.
  • the nano-silver used is a mixture of silver nano-spherical particles and silver nano-sheets, wherein the mass ratio of silver nano-spherical particles and silver nano-sheets is 3:7.
  • the patterned conductive lines in the back bonding structure are closely attached to the sides of the substrate and the driving circuit layer, and are bent to the back of the substrate, and the driver IC is bound on the back of the substrate to avoid gaps. It is beneficial to realize the narrow border or no border of the display, especially the spliced display.
  • the embodiment of the present application also provides a method for preparing an array substrate, please refer to FIG. 4 , which includes the following steps:
  • Step 101 Provide a substrate, and prepare a driving circuit layer on the substrate.
  • the driving circuit layer includes components such as thin film transistors. For details, reference may be made to the prior art, which will not be described in detail here.
  • Step 102 setting a binding area on the side of the substrate away from the driving circuit layer for binding external circuits.
  • the binding area is located at an edge position of the substrate on the side facing away from the driving circuit layer.
  • the external circuit includes a driving IC and a printed circuit board bound with the driving IC.
  • the binding area is used for binding the driver IC.
  • Step 103 forming a back bonding structure, the back bonding structure is connected to the bonding area and the driving circuit layer.
  • the step of forming the back bonding structure includes forming a first connection portion in the bonding area, and forming a patterned conductive circuit so that the patterned conductive circuit is closely attached to the substrate and the driving circuit layer. and the side surface of the first connection part, and one end of the patterned conductive circuit is electrically connected to the driving circuit layer, and the other end is electrically connected to the first connection part.
  • the step of forming the back bonding structure further includes: forming a second connection part on the surface of the driving circuit layer away from the substrate, the second connection part connecting the driving circuit layer and the The patterned conductive lines are described.
  • the step of forming the patterned conductive circuit includes: coating a conductive prepolymer film on the side surfaces of the substrate, the driving circuit layer and the first connection part, exposing the conductive prepolymer film, development.
  • the surface of the second connection portion 233 (not shown in FIG. 5 ) is coated with a conductive prepolymer film 2320 with a coating thickness of 20 ⁇ m-30 ⁇ m.
  • the coating method can be spray coating, spin coating or electroplating.
  • Conductive prepolymer is a mixture of photocurable resin, conductive filler and photoinitiator.
  • the photocurable resin may be epoxy acrylate, urethane acrylate, unsaturated polyester, polyester acrylate, polyether acrylate, pure acrylic resin, epoxy resin, organic Silicon oligomers, etc.
  • the epoxy acrylate can be bisphenol A type epoxy acrylate, novolac type epoxy acrylate and the like.
  • the organosilicon oligomer may be an acryloxy-bearing organosilicon acrylate oligomer.
  • the conductive filler can be metal or conductive carbon material or the like. The metal may be nanoscale metal, such as nanosilver.
  • the conductive carbon material can be carbon black, carbon nanotubes, carbon fibers, graphene and other carbonaceous fillers.
  • the photocurable resin is a mixed ester composed of epoxy acrylate and urethane acrylate, and the ratio of the substances is 2:3.
  • the conductive filler is nano-silver, and the filling amount of the nano-silver is 60% (the filling amount refers to the percentage of the mass of the nano-silver to the total mass of the nano-silver and the photocurable resin).
  • the nano silver can be silver nano spherical particles or silver nano flakes.
  • the nano-silver used is a mixture of silver nano-spherical particles and silver nano-sheets, wherein the mass ratio of silver nano-spherical particles and silver nano-sheets is 3:7.
  • a mask 2321 is used to block a portion of the conductive prepolymer film, and exposure is performed for curing.
  • the exposure light can be ultraviolet light, and the exposure curing time is 6 to 7 seconds.
  • the exposed conductive prepolymer film is partially immersed in a solvent, and the unexposed conductive prepolymer film is dissolved and removed by the solvent to form a patterned conductive circuit 232 .
  • the preparation method of the array substrate provided by the present application adopts the methods of coating, exposure and development, and the process is simple and easy to operate.
  • the prepared patterned conductive circuit is closely attached to the side surface of the array substrate, and there is no problem of large gap, so that the splicing display can easily realize ultra-narrow frame and no frame.
  • the present application also provides a display panel including the above-mentioned array substrate.
  • the display panel may be an LCD display panel, a Mini-LED display panel or a Micro-LED display panel.
  • the present application also provides a spliced display, wherein the spliced display is formed by splicing one or more display panels as described above.

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)

Abstract

本申请公开了一种阵列基板及其制备方法、显示面板、拼接显示器，阵列基板包括基底；驱动电路层；基底背离驱动电路层的表面上具有一绑定区；背绑定结构，电连接驱动电路层和绑定区；背绑定结构包括第一连接部和图案化导电线路，第一连接部位于绑定区，图案化导电线路贴合在基底、驱动电路层和第一连接部的侧面。

Description

一种阵列基板及其制备方法、显示面板、拼接显示器 技术领域
本申请涉及显示技术领域，尤其涉及一种阵列基板及其制备方法、显示面板、拼接显示器。
背景技术
随着显示技术的发展，全面屏已经成为市场追逐的热点。受限于目前的技术，全面屏的屏占比能够实现到90％以上。显示面板通常采用窄边框或无边框设计。但是采用窄边框或无边框的设计对驱动IC(芯片)封装提出了更高的要求。驱动IC和显示面板的连接是通过绑定(Bonding)工艺完成的。在显示面板的制备过程中，预留驱动IC的绑定位置。为了实现窄边框或无边框的设计，需要将驱动IC比如覆晶薄膜(Chip On Film，COF)弯折到显示面板的背面，将外部电路的绑定区设置在显示面板的背面。但是弯折的COF其线路不但容易出现损伤，影响线路导通，而且与显示面板的侧面之间存在的较大空隙。即使将驱动IC通过绑定结构设置在显示面板的背面，然后再将印刷电路板与驱动IC绑定以避免了COF的弯折，但由于技术的限制，现有的绑定结构与显示面板的侧面依然存在缝隙，需要设置一定宽度的外框遮挡，无法实现显示器特别是拼接显示器的窄边框化或无边框化。
技术问题
本申请提供一种阵列基板及其制备方法、显示面板、拼接显示器以避免绑定结构和显示面板侧面产生的较大空隙，影响窄边框或无边框设计的实现。
技术解决方案
本申请提供一种阵列基板，包括：
基底；
驱动电路层，设置在基底上；
所述基底背离所述驱动电路层的表面上具有一绑定区，用于绑定外部电路；
背绑定结构，电连接所述驱动电路层和所述绑定区；所述背绑定结构包括 第一连接部和图案化导电线路，所述第一连接部位于所述绑定区，所述图案化导电线路贴合在所述基底、所述驱动电路层和所述第一连接部的侧面，所述图案化导电线路的一端电性连接所述驱动电路层，另一端电性连接所述第一连接部。
在一些实施方式中，所述图案化导电线路的材料包括导电聚合物。
在一些实施方式中，所述导电聚合物由光固化材料和导电填料形成的复合材料。
在一些实施方式中，所述背绑定结构还包括第二连接部，所述第二连接部设置在所述驱动电路层远离所述基底的表面，所述第二连接部连接所述驱动电路层和所述图案化导电线路。
在一些实施方式中，第一连接部包括被所述图案化导电线路覆盖的第一部分和未被所述图案化导电线路覆盖的第二部分，所述外部电路连接所述第二部分。
在一些实施方式中，所述图案化导电线路完全覆盖所述第一连接部，所述外部电路连接所述图案化导电线路上覆盖所述第一连接部的区域。
本申请还提供一种阵列基板的制备方法，包括以下步骤：
提供一基底，在所述基底上制备驱动电路层；
在所述基底背离所述驱动电路层的一面设置一绑定区，用于绑定外部电路；
形成背绑定结构，所述背绑定结构连接所述绑定区和所述驱动电路层；
其中，所述形成背绑定结构的步骤包括在所述绑定区形成一第一连接部，形成一图案化导电线路以使所述图案化导电线路贴合在所述基底、所述驱动电路层和所述第一连接部的侧面，并使所述图案化导电线路的一端电性连接所述驱动电路层，另一端电性连接所述第一连接部。
在一些实施方式中，形成所述图案化导电线路的步骤包括：在所述基底、所述驱动电路层和所述第一连接部的侧面涂布导电预聚物膜；对所述导电预聚物膜进行曝光、显影形成所述图案化导电线路。
在一些实施方式中，所述图案化导电线路的材料包括导电聚合物。
在一些实施方式中，所述导电聚合物是由光固化材料和导电填料形成的复 合材料。
在一些实施方式中，所述形成背绑定结构的步骤还包括：在所述驱动电路层远离所述基底的表面形成第二连接部，所述第二连接部连接所述驱动电路层和所述图案化导电线路。
在一些实施方式中，将所述图案化导电线路覆盖所述第一连接部远离所述基底的部分表面，将未被所述图案化导电线路覆盖的表面连接所述外部电路。
在一些实施方式中，将所述图案化导电线路完全覆盖所述第一连接部，将所述外部电路连接所述图案化导电线路上覆盖所述第一连接部的区域。
本申请提供一种显示面板，包括阵列基板，所述阵列基板包括：
基底；
驱动电路层，设置于所述基底上；
所述基底背离所述驱动电路层的表面上具有一绑定区，用于绑定外部电路；
背绑定结构，电连接所述驱动电路层和所述绑定区；所述背绑定结构包括第一连接部和图案化导电线路，所述第一连接部位于所述绑定区，所述图案化导电线路贴合在所述基底、所述驱动电路层和所述第一连接部的侧面，所述图案化导电线路的一端电性连接所述驱动电路层，另一端电性连接所述第一连接部。
在一些实施方式中，所述图案化导电线路的材料包括导电聚合物。
在一些实施方式中，所述导电聚合物是由光固化材料和导电填料形成的复合材料。
在一些实施方式中，所述背绑定结构还包括第二连接部，所述第二连接部设置在所述驱动电路层远离所述基底的表面，所述第二连接部连接所述驱动电路层和所述图案化导电线路。
在一些实施方式中，所述第一连接部包括被所述图案化导电线路覆盖的第一部分和未被所述图案化导电线路覆盖的第二部分，所述外部电路连接所述第二部分。
在一些实施方式中，所述图案化导电线路完全覆盖所述第一连接部，所述外部电路连接所述图案化导电线路上覆盖所述第一连接部的区域。
本申请提供一种拼接显示器，由一个以上如上所述的显示面板拼接而成。
有益效果
相较于现有技术，本申请提供一种阵列基板，包括基底、驱动电路层和背绑定结构，所述基底远离所述驱动电路层的表面上具有用于绑定外部电路的绑定区，所述背绑定结构包括第一连接部和图案化导电线路，所述第一连接部位于所述绑定区，所述图案化导电线路贴合在所述基底、所述驱动电路层和所述第一连接部的侧面，所述图案化导电结构紧密贴合在阵列基板的侧面，一端电性连接所述驱动电路层，另一端电性连接所述第一连接部。该图案化导电结构避免了背绑定结构和阵列基板侧面产生较大的缝隙，有利于实现显示器特别是拼接显示器的超窄边框化或无边框化。
附图说明
下面结合附图，通过对本申请的具体实施方式详细描述，将使本申请的技术方案及其它有益效果清楚可见。
图1为本申请实施例提供的一种阵列基板的截面示意图。
图2为本申请实施例提供的另一种阵列基板的截面示意图。
图3为本申请实施例提供的又一种阵列基板的截面示意图。
图4为本申请实施例提供的阵列基板的制备方法流程示意图。
图5为本申请实施例提供的阵列基板制程中涂布导电预聚物薄膜后的阵列基板结构示意图。
图6为本申请实施例提供的阵列基板制程中曝光时的阵列基板结构示意图。
图7为本申请实施例提供的阵列基板制程中显影后的阵列基板结构示意图。
本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
为使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请 实施方式作进一步地详细描述。
请参考图1，图1为本申请实施例提供的一种阵列基板的截面示意图。本申请实施例提供一种阵列基板100，包括基底110与设置在基底110上的驱动电路层120。基底110背离驱动电路层120的表面上具有一绑定区111，用于绑定外部电路140。外部电路140包括驱动IC以及和驱动IC连接的印刷电路板。具体地，该绑定区111用于绑定所述驱动IC。在一个实施方式中，所述驱动IC可以为COF，也可以为TCP(Tape Carrier Package)，在此本申请不做特殊限制。绑定区111位于基底110的边缘区域，如图1中所示位置。所述阵列基板100还包括背绑定结构130。该背绑定结构130电性连接驱动电路层120和绑定区111。具体地，电性连接至驱动电路层120中的薄膜晶体管。背绑定结构130包括第一连接部131和图案化导电线路132，第一连接部131位于绑定区111，图案化导电线路132贴合在基底110、驱动电路层120和第一连接部131的侧面。该图案化导电线路132的一端电性连接驱动电路层120，具体电性连接至驱动电路层120中的薄膜晶体管。另一端电性连接至第一连接部131。
在一个实施方式中，背绑定结构130还包括第二连接部133，第二连接部133位于驱动电路层120远离基底110的表面。第二连接部133分别连接驱动电路层120和图案化导电线路132。图案化导电线路132通过第二连接部133电性连接至驱动电路层120。
参考图2，图2为本申请实施例提供的另一种阵列基板200的截面示意图。该阵列基板200和阵列基板100不同之处为背绑定结构230，其余结构相同。具体地，图案化导电线路232除设置基底210和驱动电路层220的侧面外，还完全覆盖第一连接部231。外部电路240连接图案化导电线路232覆盖第一连接部231的区域。具体地，驱动IC连接至图案化导电线路232覆盖第一连接部231的区域。在一些实施方式中，图案化导电线路232还可以完全覆盖或部分覆盖第二连接部233，第二连接部233连接至驱动电路层220中的薄膜晶体管。
参考图3，图3为本申请实施例提供的又一种阵列基板300的截面示意图。阵列基板300和阵列基板100的不同之处为背绑定结构330，其余结构相同。 具体地，图案化导电线路332除设置基底310和驱动电路层320的侧面外，覆盖第一连接部331的第一部分3311。第一连接部上未被图案化导电线路332覆盖的部分为第二部分3312。外部电路340中的驱动IC连接至第二部分3312。在一些实施方式中，图案化导电线路332可以完全覆盖第二连接部332，亦可以只覆盖第二连接部333的一部分，第二连接部333连接至驱动电路层320中的薄膜晶体管。
以上所述图案化导电线路可以由导电聚合物制作而成。所述导电聚合物可以为导电复合材料，其电阻率在10 -7-10 -5Ω·m之间。所述导电复合材料通常是在树脂等基体中加入导电填料复合而成。该导电聚合物在具有良好的导电性能的同时又具有高抗腐蚀、抗弯折性能和很强的可设计性。由于导电聚合物的抗弯折性或抗疲劳性，可以避免图案化导电线路在弯折的过程中的损伤，提高显示面板的稳定性。由于其很强的可设计性，可利用特殊制程和特殊物理性质将其紧密贴合在阵列基板的侧面。当然，本申请的图案化导电线路的材料不限于导电聚合物，也可以是其他具有抗弯折和高导电的材料。在此不作具体限制。
在一些实施方式中，所述基体可以为光敏树脂。比如环氧丙烯酸酯、聚氨酯丙烯酸酯、不饱和聚酯、聚酯丙烯酸酯、聚醚丙烯酯、纯丙烯酸树脂、环氧树脂、有机硅低聚物等。所述环氧丙烯酸酯可以为双酚A型环氧丙烯酸酯、酚醛型环氧丙烯酸酯等。所述有机硅低聚物可以为带有丙烯酰氧基的有机硅丙烯酸酯低聚物。所述导电填料可以为金属或导电碳材料等。所述金属可以为纳米级的金属，比如纳米银。导电碳材料可以为炭黑、碳纳米管、碳纤维、石墨烯等碳质填料。
在一个实施方式中，所述光固化树脂为环氧丙烯酸酯和聚氨酯丙烯酸酯二者组成的混合酯，物质的量比例为2：3。所述导电填料为纳米银，纳米银的填充量为60％(所述填充量是指纳米银的质量占纳米银和光固化树脂的总质量的百分比)。所述纳米银可以为银纳米球形颗粒或银纳米片的一种，也可以为两者的混合。在本实施方式中，所使用的的纳米银为银纳米球形颗粒和银纳米片的混合，其中银纳米球形颗粒和银纳米片的质量比为3:7。
本申请提供的阵列基板，其背绑定结构中的图案化导电线路紧密贴合在基底和驱动电路层的侧面，弯折到基底的背面，在基底背面进行驱动IC的绑定， 避免了空隙的产生，有利于实现显示器特别是拼接显示器的窄边框化或无边框化。
本申请实施例还提供了一种阵列基板的制备方法，请参考图4，包括以下步骤：
步骤101：提供一基底，在基底上制备驱动电路层。
所述驱动电路层包括薄膜晶体管等部件，具体可参照现有技术，在此不作详细介绍。
步骤102：在基底背离驱动电路层的一面设置一绑定区，用于绑定外部电路。
具体地，所述绑定区位于所述基底的背离所述驱动电路层一面的边缘位置。所述外部电路包括驱动IC和与驱动IC绑定的印刷电路板。所述绑定区用于绑定所述驱动IC。
步骤103：形成背绑定结构，所述背绑定结构连接至绑定区和驱动电路层。
其中，形成背绑定结构的步骤包括在所述绑定区形成一第一连接部，形成一图案化导电线路以使所述图案化导电线路紧密贴合在所述基底、所述驱动电路层和所述第一连接部的侧面，并使所述图案化导电线路的一端电性连接至所述驱动电路层，另一端电性连接至所述第一连接部。
在一些实施方式中，所述形成背绑定结构的步骤还包括：在所述驱动电路层远离所述基底的表面形成第二连接部，所述第二连接部连接所述驱动电路层和所述图案化导电线路。
其中，形成所述图案化导电线路步骤包括：在所述基底、所述驱动电路层和所述第一连接部的侧面涂布导电预聚物膜，对所述导电预聚物膜进行曝光、显影。
具体地，以阵列基板200的制程为例，请参考图5和图2，在基底210、驱动电路层220和第一连接231(图5未示出)的侧面，在第一连接部231和第二连接部233(图5未示出)的表面均涂布导电预聚物薄膜2320，涂布厚度为20μm-30μm。所述涂布的方式可以为喷涂、旋涂或电镀等。导电预聚物是由光固化树脂、导电填料和光引发剂等混合而成的混合物。
在一些实施方式中，所述光固化树脂(光敏树脂)可以为环氧丙烯酸酯、 聚氨酯丙烯酸酯、不饱和聚酯、聚酯丙烯酸酯、聚醚丙烯酯、纯丙烯酸树脂、环氧树脂、有机硅低聚物等。所述环氧丙烯酸酯可以为双酚A型环氧丙烯酸酯、酚醛型环氧丙烯酸酯等。所述有机硅低聚物可以为带有丙烯酰氧基的有机硅丙烯酸酯低聚物。所述导电填料可以为金属或导电碳材料等。所述金属可以为纳米级的金属，比如纳米银。导电碳材料可以为炭黑、碳纳米管、碳纤维、石墨烯等碳质填料。
在一个实施方式中，所述光固化树脂为环氧丙烯酸酯和聚氨酯丙烯酸酯二者组成的混合酯，物质的量比例为2：3。所述导电填料为纳米银，纳米银的填充量为60％(所述填充量是指纳米银的质量占纳米银和光固化树脂的总质量的百分比)。所述纳米银可以为银纳米球形颗粒也可以为银纳米片。在本实施方式中，所使用的纳米银为银纳米球形颗粒和银纳米片的混合，其中银纳米球形颗粒和银纳米片的质量比为3:7。
请参考图6，利用掩模板(Mask)2321遮挡部分所述导电预聚物膜，并进行曝光固化。所述曝光用的光可以为紫外光，曝光固化的时间为6至7秒。
请参考图7，将曝光后的导电预聚物膜部分浸入溶剂中，未被曝光的导电预聚物膜被溶剂溶解除去，形成图案化导电线路232。
本申请提供的阵列基板的制备方法，通过涂布、曝光和显影的方法，制程简单，易于操作。且制得的图案化导电线路紧密贴合在阵列基板的侧面，不存在空隙大的问题，使拼接显示器容易实现超窄边框化和无边框化。
本申请还提供了一种显示面板，所述显示面板包括如上所述的阵列基板。所述显示面板可以为LCD显示面板、Mini-LED显示面板或Micro-LED显示面板。
本申请还提供了一种拼接显示器，所述拼接显示器由一个以上如上所述的显示面板拼接而成。
以上对本申请实施方式所提供的一种阵列基板及其制备方法、显示面板、拼接显示器进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施方式的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施方式所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修 改或者替换，并不使相应技术方案的本质脱离本申请各实施方式的技术方案的范围。

Claims (20)

  1. 一种阵列基板，其中，包括
    基底；
    驱动电路层，设置在所述基底上；
    所述基底背离所述驱动电路层的表面上具有一绑定区，用于绑定外部电路；
    背绑定结构，电连接所述驱动电路层和所述绑定区；所述背绑定结构包括第一连接部和图案化导电线路，所述第一连接部位于所述绑定区，所述图案化导电线路贴合在所述基底、所述驱动电路层和所述第一连接部的侧面，所述图案化导电线路的一端电性连接所述驱动电路层，另一端电性连接所述第一连接部。
  2. 如权利要求1所述的阵列基板，其中，所述图案化导电线路的材料包括导电聚合物。
  3. 如权利要求2所述的阵列基板，其中，所述导电聚合物是由光固化材料和导电填料形成的复合材料。
  4. 如权利要求1所述的阵列基板，其中，所述背绑定结构还包括第二连接部，所述第二连接部设置在所述驱动电路层远离所述基底的表面，所述第二连接部连接所述驱动电路层和所述图案化导电线路。
  5. 如权利要求1所述的阵列基板，其中，所述第一连接部包括被所述图案化导电线路覆盖的第一部分和未被所述图案化导电线路覆盖的第二部分，所述外部电路连接所述第二部分。
  6. 如权利要求1所述的阵列基板，其中，所述图案化导电线路完全覆盖所述第一连接部，所述外部电路连接所述图案化导电线路上覆盖所述第一连接部的区域。
  7. 一种阵列基板的制备方法，其中，包括以下步骤：
    提供一基底，在所述基底上制备驱动电路层；
    在所述基底背离所述驱动电路层的一面设置一绑定区，用于绑定外部电路；
    形成背绑定结构，所述背绑定结构连接所述绑定区和所述驱动电路层；
    其中，所述形成背绑定结构的步骤包括在所述绑定区形成一第一连接部，形成一图案化导电线路以使所述图案化导电线路贴合在所述基底、所述驱动电路层和所述第一连接部的侧面，并使所述图案化导电线路的一端电性连接所述驱动电路层，另一端电性连接所述第一连接部。
  8. 如权利要求7所述的阵列基板的制备方法，其中，形成所述图案化导电线路的步骤包括：在所述基底、所述驱动电路层和所述第一连接部的侧面涂布导电预聚物膜；对所述导电预聚物膜进行曝光、显影形成所述图案化导电线路。
  9. 如权利要求7所述的阵列基板的制备方法，其中，所述图案化导电线路的材料包括导电聚合物。
  10. 如权利要求9所述的阵列基板的制备方法，其中，所述导电聚合物是由光固化材料和导电填料形成的复合材料。
  11. 如权利要求7所述的阵列基板的制备方法，其中，所述形成背绑定结构的步骤还包括：在所述驱动电路层远离所述基底的表面形成第二连接部，所述第二连接部连接所述驱动电路层和所述图案化导电线路。
  12. 如权利要求7所述的阵列基板的制备方法，其中，将所述图案化导电线路覆盖所述第一连接部远离所述基底的部分表面，将未被所述图案化导电线路覆盖的表面连接所述外部电路。
  13. 如权利要求7所述的阵列基板的制备方法，其中，将所述图案化导电线路完全覆盖所述第一连接部，将所述外部电路连接所述图案化导电线路上覆盖所述第一连接部的区域。
  14. 一种显示面板，其中，包括阵列基板，所述阵列基板包括：
    基底；
    驱动电路层，设置于所述基底上；
    所述基底背离所述驱动电路层的表面上具有一绑定区，用于绑定外部电路；
    背绑定结构，电连接所述驱动电路层和所述绑定区；所述背绑定结构包括第一连接部和图案化导电线路，所述第一连接部位于所述绑定区，所述图案化导电线路贴合在所述基底、所述驱动电路层和所述第一连接部的侧面，所述图 案化导电线路的一端电性连接所述驱动电路层，另一端电性连接所述第一连接部。
  15. 如权利要求14所述的显示面板，其中，所述图案化导电线路的材料包括导电聚合物。
  16. 如权利要求15所述的显示面板，其中，所述导电聚合物是由光固化材料和导电填料形成的复合材料。
  17. 如权利要求14所述的显示面板，其中，所述背绑定结构还包括第二连接部，所述第二连接部设置在所述驱动电路层远离所述基底的表面，所述第二连接部连接所述驱动电路层和所述图案化导电线路。
  18. 如权利要求14所述的显示面板，其中，所述第一连接部包括被所述图案化导电线路覆盖的第一部分和未被所述图案化导电线路覆盖的第二部分，所述外部电路连接所述第二部分。
  19. 如权利要求14所述的显示面板，其中，所述图案化导电线路完全覆盖所述第一连接部，所述外部电路连接所述图案化导电线路上覆盖所述第一连接部的区域。
  20. 一种拼接显示器，其中，由一个以上如权利要求14所述的显示面板拼接而成。
PCT/CN2020/120100 2020-09-03 2020-10-10 一种阵列基板及其制备方法、显示面板、拼接显示器 Ceased WO2022047879A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/053,754 US12506105B2 (en) 2020-09-03 2020-10-10 Array substrate, method of manufacturing same, display panel

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010914000.8 2020-09-03
CN202010914000.8A CN112014987A (zh) 2020-09-03 2020-09-03 一种阵列基板及其制备方法、显示面板、拼接显示器

Publications (1)

Publication Number Publication Date
WO2022047879A1 true WO2022047879A1 (zh) 2022-03-10

Family

ID=73516786

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/120100 Ceased WO2022047879A1 (zh) 2020-09-03 2020-10-10 一种阵列基板及其制备方法、显示面板、拼接显示器

Country Status (3)

Country Link
US (1) US12506105B2 (zh)
CN (1) CN112014987A (zh)
WO (1) WO2022047879A1 (zh)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113156722A (zh) * 2021-04-02 2021-07-23 Tcl华星光电技术有限公司 液晶显示面板及其制备方法
CN114038869B (zh) * 2021-05-14 2023-01-13 重庆康佳光电技术研究院有限公司 显示面板、显示背板及其制作方法
CN113380861B (zh) * 2021-05-24 2023-04-18 云谷（固安）科技有限公司 显示面板及其制备方法
CN113437025A (zh) * 2021-06-10 2021-09-24 深圳市华星光电半导体显示技术有限公司 阵列基板侧面走线制造方法及拼接显示面板
CN113386484A (zh) * 2021-06-11 2021-09-14 深圳市华仁三和科技有限公司 一种窄边框屏幕的制作工艺
CN113643613A (zh) * 2021-08-10 2021-11-12 深圳市华星光电半导体显示技术有限公司 显示面板、其制作方法及拼接显示装置
CN113690269B (zh) * 2021-08-13 2023-12-08 Tcl华星光电技术有限公司 阵列基板的制作方法与显示装置
CN113764564B (zh) * 2021-08-31 2024-01-23 Tcl华星光电技术有限公司 基板制备方法及膜片结构
CN115810310B (zh) * 2021-09-15 2025-07-25 成都辰显光电有限公司 显示模组、显示装置及其成型方法
CN113990209B (zh) 2021-10-22 2022-12-23 Tcl华星光电技术有限公司 一种显示模组及无缝拼接显示装置
CN114299828B (zh) * 2022-02-14 2023-04-07 惠州华星光电显示有限公司 显示单元、拼接屏以及显示装置
CN115207019B (zh) * 2022-05-24 2023-05-12 重庆惠科金渝光电科技有限公司 显示面板及其制作方法
CN114999338B (zh) * 2022-05-31 2023-11-28 Tcl华星光电技术有限公司 显示面板及制作方法、拼接显示装置
CN115064635B (zh) * 2022-06-07 2025-05-30 广州华星光电技术有限公司 基板的侧面走线的制作方法及显示面板
CN115207020B (zh) * 2022-06-08 2025-08-19 深圳市华星光电半导体显示技术有限公司 显示面板的制作方法及显示面板
CN115132813B (zh) * 2022-06-30 2025-04-29 武汉华星光电半导体显示技术有限公司 显示模组及其制备方法
CN116018011A (zh) * 2022-12-27 2023-04-25 义乌清越光电技术研究院有限公司 一种显示装置
CN116381996A (zh) * 2023-06-02 2023-07-04 惠科股份有限公司 显示面板及其制作方法、显示装置
CN119445975A (zh) * 2023-07-28 2025-02-14 京东方晶芯科技有限公司 显示模组及其制备方法、显示装置、拼接显示装置
CN117199215B (zh) * 2023-11-06 2024-02-02 Tcl华星光电技术有限公司 一种显示面板及其制备方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1124093A (ja) * 1997-07-08 1999-01-29 Alps Electric Co Ltd 液晶表示装置
CN108089382A (zh) * 2017-12-28 2018-05-29 惠州市华星光电技术有限公司 一种液晶面板及显示装置
CN108957812A (zh) * 2018-07-24 2018-12-07 武汉华星光电技术有限公司 液晶显示装置的制作方法及液晶显示装置
CN108957878A (zh) * 2018-07-19 2018-12-07 武汉天马微电子有限公司 显示模组及其制备方法和显示装置
CN109739057A (zh) * 2019-02-28 2019-05-10 京东方科技集团股份有限公司 显示装置及显示基板的绑定方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8994042B2 (en) * 2013-05-20 2015-03-31 Lg Electronics Inc. Display panel and display device
KR102304632B1 (ko) * 2015-07-17 2021-09-24 엘지디스플레이 주식회사 디스플레이 장치
KR102403671B1 (ko) * 2015-09-18 2022-05-27 엘지디스플레이 주식회사 디스플레이 장치
US10606135B2 (en) * 2017-12-29 2020-03-31 Huizhou China Star Optoelectronics Technology Co., Ltd. Liquid crystal panel, method for fabricating thereof and display apparatus
CN109962095B (zh) * 2018-04-18 2021-04-23 友达光电股份有限公司 无边框显示装置、无边框显示面板及其制造方法
CN110515481B (zh) * 2018-05-22 2023-05-26 鸿富锦精密工业（深圳）有限公司 电子装置及电子装置的制造方法
CN110596962B (zh) * 2019-09-03 2020-12-08 深圳市华星光电技术有限公司 显示模组及显示装置
KR102674350B1 (ko) * 2019-03-22 2024-06-12 삼성디스플레이 주식회사 표시 장치
CN110911393B (zh) * 2019-11-29 2022-05-20 京东方科技集团股份有限公司 一种显示驱动板及其制备方法和显示装置
CN111402754A (zh) * 2020-05-20 2020-07-10 上海天马有机发光显示技术有限公司 一种显示面板和显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1124093A (ja) * 1997-07-08 1999-01-29 Alps Electric Co Ltd 液晶表示装置
CN108089382A (zh) * 2017-12-28 2018-05-29 惠州市华星光电技术有限公司 一种液晶面板及显示装置
CN108957878A (zh) * 2018-07-19 2018-12-07 武汉天马微电子有限公司 显示模组及其制备方法和显示装置
CN108957812A (zh) * 2018-07-24 2018-12-07 武汉华星光电技术有限公司 液晶显示装置的制作方法及液晶显示装置
CN109739057A (zh) * 2019-02-28 2019-05-10 京东方科技集团股份有限公司 显示装置及显示基板的绑定方法

Also Published As

Publication number Publication date
US12506105B2 (en) 2025-12-23
US20220320030A1 (en) 2022-10-06
CN112014987A (zh) 2020-12-01

Similar Documents

Publication Publication Date Title
WO2022047879A1 (zh) 一种阵列基板及其制备方法、显示面板、拼接显示器
TWI387157B (zh) 導電粒子配置片材及其製造方法
TWI557208B (zh) An anisotropic conductive film, an anisotropic conductive film manufacturing method, a method for manufacturing a connecting body, and a connecting method
CN107079589B (zh) 连接体的制造方法、电子部件的连接方法、连接体
JPH0738502B2 (ja) 回路基板の接続方法
CN103563497B (zh) 连接方法、连接体的制造方法以及连接体
WO2013129437A1 (ja) 接続体の製造方法、及び異方性導電接着剤
WO2015137008A1 (ja) 異方性導電接着剤、接続体の製造方法及び電子部品の接続方法
JP2000242190A (ja) 表示パネルへのｔｃｐフィルムの実装方法
CN111882989B (zh) 显示面板及显示装置
CN104206032B (zh) 连接体的制造方法及电子部件的连接方法
JP6151412B2 (ja) 異方性導電フィルム、異方性導電フィルムの製造方法、接続体の製造方法、及び接続方法
JP2005122078A (ja) 液晶表示装置およびその製造方法
JP6291165B2 (ja) 接続体の製造方法、及び電子部品の接続方法
WO2025100136A1 (ja) 回路接続構造体の製造方法、回路接続用接着剤フィルム、及び回路接続構造体
JPH0732953U (ja) 液晶表示装置
HK1239724A1 (zh) 各向异性导电膜及其制法、连接体及其制法以及连接方法
HK1239724B (zh) 各向异性导电膜及其制法、连接体及其制法以及连接方法
HK1206772B (zh) 各向异性导电膜、各向异性导电膜的制造方法、连接体的制造方法及连接方法
JP2015138850A (ja) 接続体の製造方法、電子部品の接続方法
CN103472631A (zh) 一种封框胶固化方法及显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20952121

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20952121

Country of ref document: EP

Kind code of ref document: A1