WO2022041949A1 - 半导体结构 - Google Patents

半导体结构 Download PDF

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Publication number
WO2022041949A1
WO2022041949A1 PCT/CN2021/100218 CN2021100218W WO2022041949A1 WO 2022041949 A1 WO2022041949 A1 WO 2022041949A1 CN 2021100218 W CN2021100218 W CN 2021100218W WO 2022041949 A1 WO2022041949 A1 WO 2022041949A1
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WIPO (PCT)
Prior art keywords
groove
semiconductor
semiconductor structure
heat transfer
transfer layer
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PCT/CN2021/100218
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English (en)
French (fr)
Inventor
刘杰
张丽霞
应战
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长鑫存储技术有限公司
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Priority to US17/487,869 priority Critical patent/US20220068751A1/en
Publication of WO2022041949A1 publication Critical patent/WO2022041949A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3737—Organic materials with or without a thermoconductive filler

Definitions

  • the embodiments of the present application relate to the technical field of integrated circuit packaging, and in particular, to a semiconductor structure.
  • Thermal performance is particularly important in stacked package semiconductor structures. Since various heat dissipation technologies cannot effectively conduct or dissipate the heat of the pad, local temperature peaks in the semiconductor package structure are too high, and the reliability of the entire semiconductor package structure is negatively affected.
  • embodiments of the present application provide a semiconductor structure, which is used to solve the problems of poor heat dissipation capability of the semiconductor structure and high local temperature of the pads in the semiconductor structure.
  • an embodiment of the present application provides a semiconductor structure, comprising: a semiconductor substrate, the semiconductor substrate has a first surface and a second surface opposite to the first surface; a pad, the pad is located on the first surface a first side; a heat transfer layer, the heat transfer layer is located on the first side, and the heat transfer layer is in contact with the pad; a groove, the groove is located in the semiconductor substrate, and the A groove communicates with the heat transfer layer.
  • an embodiment of the present application further provides a semiconductor package structure, which is characterized in that it includes a plurality of the semiconductor structures described above that are stacked in sequence.
  • the semiconductor substrate includes a pad, a heat transfer layer and a groove, the pad is in contact with the heat transfer layer, and the groove and the heat transfer layer are connected, so the heat on the pad can be transferred to the groove through the heat transfer layer, which is beneficial to prevent soldering.
  • the local temperature peak value of the semiconductor structure caused by the heat accumulation in the disk is too high, thereby preventing the performance of the semiconductor structure system from being degraded or even completely failing, thereby solving the problems of poor heat dissipation capability of the semiconductor structure and high local temperature of the pads in the semiconductor structure.
  • FIG. 1 is a schematic top-view structural diagram of a semiconductor substrate of a semiconductor structure provided by an embodiment of the present application
  • Fig. 2 is a kind of sectional structure schematic diagram cut along PP1 direction in Fig. 1;
  • Fig. 3 is another schematic cross-sectional structure cut along the PP1 direction in Fig. 1;
  • Fig. 4 is another kind of cross-sectional structure schematic diagram cut along PP1 direction in Fig. 1;
  • Fig. 5 is another kind of cross-sectional structure schematic diagram cut along the PP1 direction in Fig. 1;
  • FIG. 6 is a schematic cross-sectional structure diagram of a semiconductor package structure provided by an embodiment of the present application.
  • a cold plate and a heat sink are often used to dissipate heat from a semiconductor package and are attached to the back of the package structure to transfer the heat to the system loop control or the air.
  • this heat dissipation structure does not directly contact the chip, and the package substrate and the shell are separated therebetween.
  • Due to the low thermal conductivity of the package substrate and the large interface thermal resistance between the film layers the heat cannot be transferred in a timely and efficient manner, which makes the overall heat dissipation effect of the package structure poor, resulting in poor reliability of the package structure.
  • dummy connectors are also arranged in the wafer in the prior art.
  • various heat dissipation technologies cannot effectively conduct or dissipate the heat of the pads, resulting in excessively high local temperature peaks in the semiconductor structure and affecting the entire semiconductor structure. The reliability of the structure is negatively affected.
  • the present application provides a semiconductor structure, which solves the problems of poor heat dissipation capability of the semiconductor structure and high local temperature of the pads in the semiconductor structure.
  • FIG. 1 is a schematic top view of a semiconductor substrate with a semiconductor structure provided by an embodiment of the application;
  • FIG. 2 is a schematic cross-sectional structure cut along the PP1 direction in FIG. 1 ;
  • FIG. 3 is another cut along the PP1 direction in FIG. 1 .
  • FIG. 4 is a schematic diagram of another cross-sectional structure cut along the PP1 direction in FIG. 1 ;
  • FIG. 5 is another schematic cross-sectional structure cut along the PP1 direction in FIG. 1 .
  • the semiconductor structure in the first embodiment of the present application includes: a semiconductor substrate 100, the semiconductor substrate 100 has a first surface 101 and a second surface 105 opposite to the first surface 101;
  • the disk 102 is located on the first side 101;
  • the heat transfer layer 103, the heat transfer layer 103 is located on the first side 101, and the heat transfer layer 103 is in contact with the pad 102;
  • the groove 104, the groove 104 is located in the semiconductor substrate 100, and the groove 104 communicates with the heat transfer layer 103 .
  • the semiconductor substrate 100 is a wafer or a chip.
  • the semiconductor substrate 100 includes a groove 104 on the first surface 101 , a heat transfer layer 103 and a pad 102 , the groove 104 communicates with the heat transfer layer 103 , and the heat transfer layer 103 Contact with pad 102 .
  • the semiconductor substrate further includes an insulating layer, the insulating layer covers the first side of the semiconductor substrate, and the heat transfer layer and the pad are located on the first side of the insulating layer.
  • the heat on the pad 102 can be transferred into the groove 104 through the heat transfer layer 103, preventing the local temperature peak of the semiconductor structure caused by the heat accumulation in the pad 102, thereby preventing the temperature in the space of the semiconductor structure from rising sharply, and preventing
  • the problems of signal interference, system performance degradation or even complete failure caused by a sharp rise in temperature solve the problems of poor heat dissipation capability of the semiconductor structure and excessive local temperature of the pads 102 in the semiconductor structure.
  • the grooves 104 are located in the semiconductor substrate 100 . Specifically, as shown in FIG. 2 , in the embodiment of the present application, the groove 104 penetrates the semiconductor substrate 100 in a direction perpendicular to the semiconductor substrate 100 .
  • the aspect ratio of the groove 104 may be 20:1 to 100:1, and specifically, the aspect ratio of the groove 104 may be 40:1, 60:1 or 80:1.
  • the width of the groove 104 may be 2-10 ⁇ m, and specifically, the width of the groove 104 may be 4 ⁇ m, 6 ⁇ m or 8 ⁇ m.
  • the groove 104 is a blind hole located in the semiconductor substrate 100 .
  • the semiconductor structure further includes a via hole 106 .
  • the via hole 106 In the semiconductor substrate 100 , the extending direction of the communication hole 106 is different from the extending direction of the groove 104 .
  • the groove 104 in the semiconductor substrate 100 may be a through hole penetrating the semiconductor substrate 100 or a blind hole in the semiconductor substrate 100.
  • the groove 104 communicates with the communication hole 106 whose one end is exposed outside the semiconductor substrate 100 .
  • each groove 104 in the semiconductor substrate 100 is in communication with the system loop control or air, the heat in the groove 104 can be quickly conducted out of the semiconductor structure, the reliability of the semiconductor structure is improved, and the problem of the semiconductor structure is solved.
  • the semiconductor structure further includes a heat-conducting layer 107 , the heat-conducting layer 107 is located in the groove 104 , and the volume of the heat-conducting layer 107 is smaller than that of the groove 104 .
  • the thermally conductive layer 107 can be made of a metal material.
  • thermal conductive layer 107 in the groove 104 with a volume smaller than that of the groove 104.
  • the thermal conductive layer 107 enhances the ability of the groove 104 to absorb heat, and can dissipate the heat on the pad 102 as soon as possible to prevent the signal from being disturbed. , improve the reliability of semiconductor structures.
  • the problems of poor heat dissipation capability of the semiconductor structure and excessive local temperature of the pads 102 in the semiconductor structure are solved.
  • the volume of the heat-conducting layer 107 is smaller than the volume of the groove 104 , which can prevent the heat-conducting layer 107 from expanding and contracting after being heated to squeeze the groove 104 .
  • one semiconductor substrate 100 may include a plurality of grooves 104 (refer to FIG. 4 ), such as a first groove 1041 and a second groove 1042 . It can be understood that the plurality of grooves 104 can improve the heat dissipation rate of the pad 102 and improve the reliability of the semiconductor structure.
  • the same heat transfer layer 103 communicates with one groove 104 .
  • the same heat transfer layer 103 communicates with a plurality of grooves (the first groove 1041 and the second groove 1042 ).
  • the plurality of grooves 104 can improve the heat dissipation rate of the heat transfer layer 103 and improve the reliability of the semiconductor structure.
  • the communication between the heat transfer layer 103 and the groove 104 is that the heat transfer layer 103 covers one end of the groove 104 .
  • the sidewall of the heat transfer layer 103 is flush with the sidewall of the groove 104
  • the heat transfer layer 103 covers one end of the groove 104 .
  • the heat transfer layer 103 may also cover only one end of the groove 104 or cover part of the end surface of the groove 104 . The larger the area where the heat transfer layer 103 communicates with the groove 104 is, the better the heat conduction effect is.
  • the heat transfer layer 103 is an insulating material, and the material of the heat transfer layer 103 includes: thermally conductive silica gel, thermally conductive insulating elastic glue or thermally conductive filling glue.
  • the thermally conductive filler has high thermal conductivity and electrical insulation, and can be vulcanized and solidified at room temperature, playing the role of sticking, sealing, and forming, and at the same time, it can quickly conduct the heat of the heating body to cool the heating body. Excellent thermal conductivity.
  • the thermally conductive insulating elastic adhesive is made of silicone rubber, and ceramic particles such as boron nitride and alumina are used as fillers. It has better thermal conductivity than thermally conductive silicone, and under the same conditions, its thermal impedance is lower than other thermally conductive materials.
  • Thermally conductive silicone including thermally conductive silicone grease, thermally conductive silicone tape, and thermally conductive silicone cloth, is the most widely used thermally conductive material.
  • the heat transfer layer 103 is in contact with the side surface of the pad 102 .
  • the heat transfer layer 103 is in contact with the bottom surface of the pad 102 facing the second side 105 .
  • the heat transfer layer 103 may be in contact with the side surface of the pad 102 and the bottom surface facing the second surface 105 at the same time. The larger the contact area between the heat transfer layer 103 and the pad 102, the better the thermal conductivity.
  • the heat on the pad 102 can be transferred to the groove 104 through the heat transfer layer 103, and the groove 104 then transfers the heat to the system loop control or the air, which solves the problem of current problems.
  • the heat dissipation requirement is high. Due to the low thermal conductivity of the substrate and the large interface thermal resistance of the multi-layer material, the heat cannot be transmitted in time and efficiently.
  • the second embodiment of the present application also provides a semiconductor structure, which is substantially the same as the previous embodiment, and the main differences include that the semiconductor substrate 100 includes a middle region 108 and an edge region 109 surrounding the middle region 108 , grooves 104 includes: a first groove 1041 in the middle region 108 and a second groove 1042 in the edge region 109 .
  • the semiconductor structure provided by the second embodiment of the present application will be described in detail below with reference to the accompanying drawings. For the same or corresponding parts as the previous embodiment, reference may be made to the description of the previous embodiment, which will not be repeated below.
  • the semiconductor substrate 100 includes a middle region 108 and an edge region 109 surrounding the middle region 108
  • the groove 104 includes: a first recess located in the middle region 108 .
  • the groove 1041 is located in the second groove 1042 of the edge region 109 , and the first groove 1041 penetrates through the semiconductor substrate 100 , and the second groove 1042 is a blind hole located in the semiconductor substrate 100 .
  • the groove 104 may penetrate the semiconductor substrate 100 or the groove 104 may be a blind hole in the semiconductor substrate 100 . If the groove 104 is a blind hole in the semiconductor substrate 100 , the groove 104 may The edge area 109 of the substrate 100, so that after the heat of the pad 102 is transferred into the groove 104 through the heat transfer layer 103, the different grooves 104 can be connected to the system loop or exposed to the air to transfer the heat of the pad 102. Transfer to system environment control or air.
  • each groove 104 in the semiconductor structure can be communicated with the system loop control or air. While not increasing the complexity of the semiconductor structure, it ensures that the heat of the groove 104 is quickly conducted out of the semiconductor structure, prevents the heat from accumulating in the semiconductor structure, improves the reliability of the semiconductor structure, and solves the problem of poor heat dissipation capability of the semiconductor structure and in the semiconductor structure. The problem that the local temperature of the pad 102 is too high.
  • FIG. 6 is a schematic cross-sectional structure diagram of a semiconductor package structure provided by an embodiment of the present application.
  • the third embodiment of the present application further provides a semiconductor package structure, the semiconductor package structure includes a plurality of the above-mentioned semiconductor structures stacked in sequence.
  • the semiconductor package structure includes a semiconductor substrate 100 , a second semiconductor substrate 200 and a third semiconductor substrate 300 , and a plurality of grooves 104 of the plurality of semiconductor structures are communicated with each other.
  • the plurality of grooves 104 of the plurality of semiconductor structures are connected to form one groove 104, which reduces the complexity of the semiconductor package structure and is more conducive to implementation.
  • a plurality of communicating grooves 104 may communicate to the outer surface of the semiconductor package structure.
  • the plurality of connected grooves 104 are connected to the outer surface of the semiconductor package structure to uniformly transmit the heat of the pads 102 in the semiconductor package structure to the system loop control or the air, so that the complexity of the semiconductor package structure is reduced. It can be understood that the grooves 104 of a plurality of semiconductor structures can also be separated from each other, and communicate with the system loop control or air independently.
  • the plurality of semiconductor structures in the semiconductor package structure include a first semiconductor structure and a second semiconductor structure; the second semiconductor structure further includes a pad 102 on the second surface 105 of the second semiconductor structure, and the first semiconductor structure is the first semiconductor structure.
  • the pads 102 of the side 101 are connected to the pads 102 of the second side 105 of the second semiconductor structure.
  • a semiconductor package structure provided by the third embodiment of the present application includes a plurality of semiconductor structures stacked in sequence, and the heat of the pads 102 of the plurality of semiconductor structures is transferred to the interconnected grooves 104 through the heat transfer layer 103 , and then The unified transmission to the system loop control or the air reduces the complexity of the semiconductor package structure and solves the problems of poor heat dissipation capability of the semiconductor package structure and excessive local temperature of the pads 102 in the semiconductor package structure.
  • the embodiments of the present application provide a semiconductor structure and a semiconductor packaging structure, in which the heat transfer layer 103 contacts the pad 102 and the groove 104, transfers the heat in the pad 102 to the groove 104, and transfers the heat in the groove 104 again
  • the pad 102 conducts a large current signal in the semiconductor structure and the semiconductor package structure, there is a lot of heat at the pad 102, the heat dissipation requirement is high, and the thermal conductivity of the substrate is low, and the interface of the multi-layer material is heated.

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Abstract

本申请实施例提供一种半导体结构，包括：半导体基底，所述半导体基底具有第一面和与所述第一面相对的第二面；焊盘，所述焊盘位于所述第一面；热传递层，所述热传递层位于所述第一面，且所述热传递层与所述焊盘接触；凹槽，所述凹槽位于所述半导体基底内，且所述凹槽与所述热传递层连通。本申请实施例提供的一种半导体结构，有利于解决半导体结构散热能力差和半导体结构中焊盘局部温度过高的问题。

Description

半导体结构
交叉引用
本申请引用于2020年08月28日递交的名称为“半导体结构”的第202010887595.2号中国专利申请，其通过引用被全部并入本申请。
技术领域
本申请实施例涉及集成电路封装技术领域，尤其涉及一种半导体结构。
背景技术
随着集成电路不断的改进、发展，体积不断的减小，在功能上则不断的提升，而在提升功能的同时，集成电路所需要的芯片数量越来越多、半导体封装的集成度和整合度逐步增强，对于半导体的散热管理便成为集成电路与半导体封装制程中十分重要的设计重点。由于芯片嵌入在散热能力不良的有机材料内部，热量无法快速散出可能会造成系统性能下降甚至完全失效。
在堆叠封装半导体结构中，散热性能尤为重要。由于目前各种散热技术都无法有效传导或消散焊盘的热量，导致半导体封装结构中局部温度峰值过高，且对整个半导体封装结构的可靠性产生负面影响。
发明内容
针对上述存在问题，本申请实施例提供一种半导体结构，用于解决半导体结构散热能力差和半导体结构中焊盘局部温度过高的问题。
第一方面，本申请实施例提供一种半导体结构，包括：半导体基底，所述半导体基底具有第一面和与所述第一面相对的第二面；焊盘，所述焊盘位于所述第一面；热传递层，所述热传递层位于所述第一面，且所述热传递层与所 述焊盘接触；凹槽，所述凹槽位于所述半导体基底内，且所述凹槽与所述热传递层连通。
第二方面，本申请实施例还提供一种半导体封装结构，其特征在于，包括多个依次堆叠设置的上述任一所述的半导体结构。
半导体基底包括焊盘、热传递层和凹槽，焊盘与热传递层接触，凹槽和热传递层连通，所以焊盘上的热量可以通过热传递层传递到凹槽中，有利于防止焊盘中热量积累引起的半导体结构局部温度峰值过高，从而防止半导体结构系统性能下降甚至完全失效，进而解决半导体结构散热能力差和半导体结构中焊盘局部温度过高的问题。
附图说明
图1为本申请实施例提供的一种半导体结构的半导体基底的俯视结构示意图；
图2为图1中沿PP1方向切割的一种剖面结构示意图；
图3为图1中沿PP1方向切割的另一种剖面结构示意图；
图4为图1中沿PP1方向切割的又一种剖面结构示意图；
图5为图1中沿PP1方向切割的再一种剖面结构示意图；
图6为本申请一实施例提供的一种半导体封装结构的一种剖面结构示意图。
具体实施方式
由背景技术可知，现有技术的半导体结构的散热性能有待提高。
现有技术中，半导体封装散热多采用冷板和热沉贴在封装结构背面，将热量传递到系统环控或空气中，但这种散热结构与芯片不直接接触，中间隔着 封装基板和外壳，由于封装基板热导率低，且膜层间界面热阻大，热量不能及时高效的传递出来，使得封装结构整体散热效果差，进而导致封装结构可靠性较差。此外，现有技术中还在晶圆中设置伪连接件，然而，目前各种散热技术中都无法有效传导或消散焊盘的热量，导致半导体结构中局部温度峰值过高，且会对整个半导体结构的可靠性产生负面影响。
为解决上问题，本申请实施提供一种半导体结构，解决半导体结构散热能力差和半导体结构中焊盘局部温度过高的问题。
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合附图对本申请的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。
图1为本申请实施例提供的一种半导体结构的半导体基底的俯视结构示意图；图2为图1中沿PP1方向切割的一种剖面结构示意图；图3为图1中沿PP1方向切割的另一种剖面结构示意图；图4为图1中沿PP1方向切割的又一种剖面结构示意图；图5为图1中沿PP1方向切割的再一种剖面结构示意图。
参考图1和图2，本申请第一实施例中的半导体结构，包括：半导体基底100，半导体基底100具有第一面101和与第一面101相对的第二面105；焊盘102，焊盘102位于第一面101；热传递层103，热传递层103位于第一面101，且热传递层103与焊盘102接触；凹槽104，凹槽104位于半导体基底100内，且凹槽104与热传递层103连通。
以下将结合附图对本申请第一实施例提供的半导体结构进行详细说明。
半导体基底100为晶圆或芯片。
如图2所示，在本申请实施例中，半导体基底100包括位于第一面101的凹槽104、热传递层103和焊盘102，凹槽104与热传递层103连通，热传递层103与焊盘102接触。在其他实施例中，半导体基底还包括绝缘层，绝缘层覆盖于半导体基底的第一面，且热传递层和焊盘位于绝缘层的第一面。
如此，焊盘102上的热量可以通过热传递层103传递到凹槽104中，防止了焊盘102中热量积累引起的半导体结构局部温度峰值，进而防止了半导体结构空间内温度急剧上升，以及防止温度急剧上升导致的信号干扰、系统性能下降甚至完全失效的问题，解决了半导体结构散热能力差和半导体结构中焊盘102局部温度过高的问题。
凹槽104位于半导体基底100内。具体地，如图2所示，在本申请实施例中，凹槽104沿垂直半导体基底100的方向贯穿半导体基底100。
凹槽104的深宽比可以为20：1至100：1，具体的，凹槽104的深宽比可以为40：1、60：1或80：1。
凹槽104的宽度可以为2～10μm，具体的，凹槽104的宽度可以为4μm、6μm或8μm。
在另一个例子中，如图3所示，凹槽104为位于半导体基底100内的盲孔，当凹槽104为位于半导体基底100的盲孔时，半导体结构还包括连通孔106，连通孔106位于半导体基底100内且连通孔106的延伸方向与凹槽104的延伸反向不同，半导体基底100暴露出连通孔106的一端，且连通孔106的另一端与凹槽104相连通。
可以理解的是，半导体基底100内的凹槽104可以为贯穿半导体基底100 的通孔，或者是半导体基底100内的盲孔，当凹槽104为半导体基底100内的盲孔时，该凹槽104会与一端暴露在半导体基底100外的连通孔106连通。
如此，保证了半导体基底100内的每一个凹槽104都与系统环控或空气连通，可以快速的将凹槽104中的热量传导出半导体结构，提高了半导体结构的可靠性，解决了半导体结构散热能力差和半导体结构中焊盘102局部温度过高的问题。
如图4所示，在另一个例子中，半导体结构还包括导热层107，导热层107位于凹槽104内，且导热层107的体积小于凹槽104的容积。可以理解的是，导热层107可以为金属材料。
本申请实施例中，凹槽104中有体积小于凹槽104容积的导热层107，导热层107增强了凹槽104吸收热量的能力，可以尽快散去焊盘102上的热量，防止信号受干扰，提高半导体结构的可靠性。解决了半导体结构散热能力差和半导体结构中焊盘102局部温度过高的问题。其中，导热层107体积小于凹槽104的容积，可以防止导热层107受热后热胀冷缩挤压凹槽104。
如图5所示，一个半导体基底100可包括多个凹槽104(参考图4)，例如第一凹槽1041和第二凹槽1042。可以理解的是，多个凹槽104可以提高焊盘102的散热速率，提高了半导体结构的可靠性。
在本申请实施例中，如图3所示，同一热传递层103与一个凹槽104连通。在另一个例子中，如图5所示，同一热传递层103与多个凹槽(第一凹槽1041和第二凹槽1042)连通。多个凹槽104可以提高热传递层103的散热速率，提高了半导体结构的可靠性。
在本申请实施例中，热传递层103与凹槽104的连通方式为热传递层103 覆盖凹槽104的一端。在另一个例子中，如图5所示，热传递层103的侧壁与凹槽104的侧壁齐平，以及热传递层103覆盖凹槽104的一端。可以理解的是，热传递层103还可以仅覆盖凹槽104的一端或者覆盖凹槽104的部分端面。热传递层103与凹槽104连通的面积越大，导热效果越好。
热传递层103为绝缘材料，热传递层103的材料包括：导热硅胶、导热绝缘弹性胶或导热填充胶。
其中，导热填充胶具有高导热性和电气绝缘性，能在室温下硫化凝固，起到粘、密封、成型的作用，同时能将发热体的热量迅速传导出来，起到冷却发热体的作用，导热效果极佳。
导热绝缘弹性胶采用硅橡胶基材，氮化硼、氧化铝等陶瓷颗粒为填充剂。比导热硅胶具有更优良的导热效果，同等条件下，热阻抗小于其他导热材料。
导热硅胶包括导热硅脂、导热硅胶带、导热矽胶布等，是应用最为广泛的导热材料。
在本申请实施例中，如图3所示，热传递层103与焊盘102的侧面相接触。在另一个例子中，热传递层103与焊盘102朝向第二面105的底面相接触。可以理解的是，如图4所示，热传递层103可以与焊盘102的侧面和朝向第二面105的底面同时相接触。热传递层103与焊盘102的接触面积越大，导热效果越好。
本申请第一实施例提供的一种半导体结构，焊盘102上的热量可以通过热传递层103传递到凹槽104中，凹槽104再把热量传递到系统环控或空气中，解决了现有的半导体结构中，当通过焊盘102传导大电流信号时，焊盘102处热量多，散热要求高，由于基板热导率低，多层材料界面热阻大，热量不能及 时高效的传递出来，造成半导体结构散热能力差的不良影响的问题，防止了焊盘102中热量积累引起的半导体结构局部温度峰值，进而防止了半导体封装结构空间内温度急剧上升，造成系统性能下降，甚至完全失效的问题，解决了半导体结构散热能力差和半导体结构中焊盘102局部温度过高的问题。
参见图5，本申请第二实施例还提供一种半导体结构，该半导体结构与前一实施例大致相同，主要区别包括半导体基底100包括中间区域108以及环绕中间区域108的边缘区域109，凹槽104包括：位于中间区域108的第一凹槽1041，位于边缘区域109的第二凹槽1042。以下将结合附图对本申请第二实施例提供的半导体结构进行详细说明，与前一实施例相同或者相应的部分，可参考前述实施例的说明，以下将不做赘述。
如图5所示，本申请第二实施例提供的一种半导体结构中，半导体基底100包括中间区域108以及环绕中间区域108的边缘区域109，凹槽104包括：位于中间区域108的第一凹槽1041，位于边缘区域109的第二凹槽1042，且第一凹槽1041贯穿半导体基底100，第二凹槽1042为位于半导体基底100内的盲孔。
综上，可以理解的是，凹槽104可以贯穿半导体基底100或者凹槽104为在半导体基底100内的盲孔，如果凹槽104是半导体基底100内的盲孔，则此凹槽104在半导体基底100的边缘区域109，这样焊盘102的热量通过热传递层103传递到凹槽104里之后，不同的凹槽104都可以连通到系统环控或暴露在空气中，将焊盘102的热量传递到系统环控或空气中。
对比本申请第一实施例，本实施例在半导体结构中不增加连通孔106(参考图3)的情况下，就可以使得半导体结构中每一个凹槽104都与系统环控或 空气连通，在不提高半导体结构复杂性的同时，保证了凹槽104热量快速导通出半导体结构，防止了热量积蓄在半导体结构中，提高了半导体结构的可靠性，解决了半导体结构散热能力差和半导体结构中焊盘102局部温度过高的问题。
图6为本申请一实施例提供的一种半导体封装结构的一种剖面结构示意图。
本申请第三实施例还提供一种半导体封装结构，半导体封装结构包括多个依次堆叠设置的上述的半导体结构。如图6所示，半导体封装结构包括半导体基底100，第二半导体基底200和第三半导体基底300，多个半导体结构的多个凹槽104相连通。多个半导体结构的多个凹槽104相连通，形成一个凹槽104，减小了半导体封装结构的复杂性，更利于实现。
如图6所示，多个连通的凹槽104可以连通到半导体封装结构的外表面。多个连通的凹槽104连通到半导体封装结构的外表面，将半导体封装结构中焊盘102的热量统一传输到系统环控或空气中，使得半导体封装结构复杂性降低。可以理解的是，多个半导体结构的凹槽104也可以相互分立，单独连通系统环控或空气。
在一个例子中，在半导体封装结构中多个半导体结构包括第一半导体结构和第二半导体结构；第二半导体结构还包括位于第二半导体结构第二面105的焊盘102，第一半导体结构第一面101的焊盘102和第二半导体结构第二面105的焊盘102相连接。
本申请第三实施例提供的一种半导体封装结构，包括多个依次堆叠设置的半导体结构，多个半导体结构的焊盘102的热量通过热传递层103传递到相互连通的凹槽104中，再统一传输到系统环控或空气中，在减小半导体封装结 构复杂性的同时，解决了半导体封装结构散热能力差和半导体封装结构中焊盘102局部温度过高的问题。
本申请实施例提供一种半导体结构及半导体封装结构，通过热传递层103接触焊盘102和凹槽104，将焊盘102中的热量传递到凹槽104中，凹槽104中的热量再传输到系统环控或空气中，防止了半导体结构及半导体封装结构中由于焊盘102传导大电流信号时，焊盘102处热量多，散热要求高，且基板热导率低，多层材料界面热阻大，热量不能及时高效的传递出来，造成半导体结构散热能力差的不良影响的问题，防止了焊盘102中热量积累引起的半导体结构局部温度峰值，进而防止了半导体封装结构空间内温度急剧上升，造成系统性能下降，甚至完全失效的问题，解决了半导体封装结构散热能力差和半导体结构中焊盘102局部温度过高的问题。
本领域的普通技术人员可以理解，上述各实施方式是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。任何本领域技术人员，在不脱离本申请的精神和范围内，均可作各自更动与修改，因此本申请的保护范围应当以权利要求限定的范围为准。

Claims (20)

  1. 一种半导体结构，其特征在于，包括：
    半导体基底，所述半导体基底具有第一面和与所述第一面相对的第二面；
    焊盘，所述焊盘位于所述第一面；
    热传递层，所述热传递层位于所述第一面，且所述热传递层与所述焊盘接触；
    凹槽，所述凹槽位于所述半导体基底内，且所述凹槽与所述热传递层连通。
  2. 根据权利要求1所述的半导体结构，其特征在于，所述凹槽沿垂直所述半导体基底的方向贯穿所述半导体基底；或者，所述凹槽为位于所述半导体基底内的盲孔。
  3. 根据权利要求2所述的半导体结构，其特征在于，所述凹槽为位于所述半导体基底内的盲孔，所述半导体结构还包括：连通孔，所述连通孔位于所述半导体基底内且所述连通孔的延伸方向与所述凹槽的延伸方向不同，所述半导体基底暴露出所述连通孔的一端，且所述连通孔的另一端与所述凹槽相连通。
  4. 根据权利要求1所述的半导体结构，其特征在于，所述凹槽的深宽比为20：1～100：1。
  5. 根据权利要求4所述的半导体结构，其特征在于，所述凹槽的宽度为2μm～10μm。
  6. 根据权利要求1所述的半导体结构，其特征在于，所述热传递层与所述焊盘的侧面相接触。
  7. 根据权利要求1所述的半导体结构，其特征在于，所述热传递层与所述焊盘朝向所述第二面的底面相接触。
  8. 根据权利要求1所述的半导体结构，所述热传递层与所述焊盘的侧面和朝向所述第二面的底面同时相接触。
  9. 根据权利要求1所述的半导体结构，其特征在于，所述热传递层的材料为绝缘材料。
  10. 根据权利要求9所述的半导体结构，其特征在于，所述热传递层的材料包括：导热硅胶、导热绝缘弹性橡胶或导热填充胶。
  11. 根据权利要求1所述的半导体结构，其特征在于，所述热传递层覆盖所述凹槽的一端。
  12. 根据权利要求1所述的半导体结构，其特征在于，所述热传递层覆盖所述凹槽的部分端面。
  13. 根据权利要求1所述的半导体结构，其特征在于，所述凹槽的数量为多个，且同一所述热传递层与多个所述凹槽连通。
  14. 根据权利要求1所述的半导体结构，其特征在于，还包括：导热层，所述导热层位于所述凹槽内，且所述导热层的体积小于所述凹槽的容积。
  15. 根据权利要求14所述的半导体结构，其特征在于，所述导热层为金属材料。
  16. 根据权利要求1所述的半导体结构，其特征在于，所述半导体基底还包括绝缘层，所述绝缘层覆盖于所述半导体基底的所述第一面，且所述热传递层和所述焊盘位于所述绝缘层的所述第一面。
  17. 根据权利要求1-16中任一项所述的半导体结构，其特征在于，所述半导体基底包括中间区域以及环绕所述中间区域的边缘区域，所述凹槽包括：位于所述中间区域的第一凹槽，位于所述边缘区域的第二凹槽，且所述第一凹槽贯穿所述半导体基底，所述第二凹槽为位于所述半导体基底内的盲孔。
  18. 一种半导体封装结构，其特征在于，包括多个依次堆叠设置的如权利要求1-17任一所述的半导体结构。
  19. 根据权利要求18所述的半导体封装结构，其特征在于，多个所述半导体结构的多个所述凹槽相连通。
  20. 根据权利要求18所述的半导体封装结构，其特征在于，多个所述半导体结构包括第一半导体结构和第二半导体结构；所述第二半导体结构还包括位于所述第二半导体结构第二面的焊盘；所述第一半导体结构第一面的所述焊盘和所述第二半导体结构第二面的所述焊盘相连接。
PCT/CN2021/100218 2020-08-28 2021-06-15 半导体结构 WO2022041949A1 (zh)

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