WO2022041496A1 - 一种阵列基板及显示装置 - Google Patents

一种阵列基板及显示装置 Download PDF

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Publication number
WO2022041496A1
WO2022041496A1 PCT/CN2020/128578 CN2020128578W WO2022041496A1 WO 2022041496 A1 WO2022041496 A1 WO 2022041496A1 CN 2020128578 W CN2020128578 W CN 2020128578W WO 2022041496 A1 WO2022041496 A1 WO 2022041496A1
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WIPO (PCT)
Prior art keywords
opening
layer
openings
array substrate
metal
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PCT/CN2020/128578
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English (en)
French (fr)
Inventor
陈建锋
张淑媛
Original Assignee
武汉华星光电半导体显示技术有限公司
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Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Priority to US17/265,859 priority Critical patent/US11837610B2/en
Publication of WO2022041496A1 publication Critical patent/WO2022041496A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/35—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being liquid crystals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement

Definitions

  • the present invention relates to the field of display technology, in particular to a display device, and in particular to an array substrate of a display device.
  • LCD Liquid Crystal Display
  • OLED Organic Light Emitting Diode
  • the LCD display device is composed of a thin film transistor array substrate (Thin Film Transistor Array Substrate, TFT Array Substrate) and a color filter (Color Filter, CF) substrates are bonded together, and the liquid crystal is poured between the TFT substrate and the CF substrate, and the liquid crystal molecules are controlled to change direction by whether the power is turned on or not, and the light from the backlight module is refracted to produce a picture.
  • a thin film transistor array substrate Thin Film Transistor Array Substrate, TFT Array Substrate
  • CF Color Filter
  • the OLED display device usually includes: a substrate, an anode arranged on the substrate, a hole injection layer arranged on the anode, a hole transport layer arranged on the hole injection layer, a light-emitting layer arranged on the hole transport layer, and a hole injection layer arranged on the hole injection layer.
  • the present invention provides an array substrate with a stable structure and a display device having the array substrate, which can meet the requirements of dynamic stretching and bending, and avoid cracks and affect the normal operation of thin film transistors.
  • an embodiment of the present application provides an array substrate including a bending area and a non-bending area, the array substrate including a base layer, a buffer layer, a functional layer, a filling layer and a metal layer that are stacked in sequence;
  • the functional layer includes a first part located in the non-bending region and a second part located in the bending region, the first part is provided with a plurality of driving thin film transistors, and the second part is provided with a plurality of first an opening;
  • the filling layer covers the upper surface of the functional layer and fills the first opening;
  • the filling layer is provided with a second opening at the first opening;
  • the metal layer includes a source and a drain A pattern and a plurality of metal traces connected to the source and drain patterns, the metal traces are bent toward the inside of the second opening in a region overlapping with the second opening.
  • the first openings extend into the base layer.
  • the first opening includes an upper opening and a lower opening
  • the lower opening is located below the upper opening
  • the lower opening has a smaller horizontal cross-sectional area than the upper opening The horizontal cross-sectional area of the opening.
  • the upper opening, the lower opening and the second opening are all trapezoidal cross-sections that are wide in the depth direction of the opening and narrow in the bottom.
  • the metal traces at least partially adhere to the bottom surface of the lower opening of the first opening.
  • a plurality of the second openings overlap with the metal traces and are arranged at equal distances along the extending direction of the metal traces.
  • the maximum opening length of the second opening along the extending direction of the metal trace is greater than the distance between two adjacent second openings along the extending direction of the metal trace, so The opening width of the second opening perpendicular to the extending direction of the metal trace is larger than the width of the metal trace.
  • the two rows of the second openings arranged along the extending direction of the adjacent metal traces are staggered.
  • a third opening is respectively set around each of the driving thin film transistors, the horizontal cross-section of each third opening is a rectangle of the same size, and the length of the third opening is The side faces the driving thin film transistor.
  • the third opening penetrates the functional layer and the buffer layer along the depth direction of the opening, and the filling layer fills the third opening.
  • an embodiment of the present application further provides a display device, the display device includes an array substrate, the array substrate includes a bending area and a non-bending area, and the array substrate includes a base layer, a buffer layer and a buffer layer arranged in sequence.
  • the functional layer includes a first part located in the non-bending region and a second part located in the bending region, the first part is provided with a plurality of driving thin film transistors, The second part is provided with a first opening;
  • the filling layer covers the upper surface of the functional layer and fills the first opening, and the filling layer is provided with a second opening at the first opening ;
  • the metal layer includes a source-drain pattern and a plurality of metal traces connected to the source-drain pattern, the metal traces extend to the inside of the second opening in a region overlapping with the second opening Bend.
  • the first opening extends into the base layer.
  • the first opening includes an upper opening and a lower opening
  • the lower opening is located below the upper opening
  • the lower opening has a smaller horizontal cross-sectional area than the upper opening The horizontal cross-sectional area of the opening.
  • the upper opening, the lower opening and the second opening are all trapezoidal cross-sections that are wide in the depth direction of the opening and narrow in the bottom.
  • the metal wiring at least partially adheres to the bottom surface of the lower opening of the first opening.
  • a plurality of the second openings overlap with the metal traces and are arranged at equal distances along the extending direction of the metal traces.
  • the maximum opening length of the second opening along the extending direction of the metal trace is greater than the distance between two adjacent second openings along the extending direction of the metal trace, so The opening width of the second opening perpendicular to the extending direction of the metal trace is larger than the width of the metal trace.
  • the two rows of the second openings arranged along the extending direction of the adjacent metal traces are staggered.
  • each of the driving thin film transistors is respectively provided with a third opening around the periphery, the horizontal cross-section of each third opening is a rectangle of the same size, and the length of the third opening is The side faces the driving thin film transistor.
  • the third opening penetrates the functional layer and the buffer layer along the depth direction of the opening; and the filling layer fills the third opening.
  • the technical solution of the present invention can effectively improve the structural stability of the array substrate during dynamic bending, avoid stress damage to the film structure and cause the threshold voltage drift of the driving thin film transistor to affect normal operation, and reduce bending.
  • the stress on the metal traces in the fold area can effectively improve the structural stability of the array substrate during dynamic bending, avoid stress damage to the film structure and cause the threshold voltage drift of the driving thin film transistor to affect normal operation, and reduce bending.
  • FIG. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of a location where a driving thin film transistor of an array substrate is provided according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of a bending region of an array substrate according to an embodiment of the present invention.
  • FIG. 4 is another schematic structural diagram of a bending region of an array substrate according to an embodiment of the present invention.
  • the present application provides a touch electrode layer and a touch display device.
  • a touch electrode layer and a touch display device.
  • the present application will be further described below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, but not to limit the present application.
  • an embodiment of the present invention provides an array substrate, which includes:
  • the array substrate includes a base layer 1, a buffer layer 2, a functional layer 3, a filling layer 4, a metal layer 5 and Flat layer 6,
  • the functional layer 3 includes an active layer 31, a first insulating layer 32, a gate electrode 33, a second insulating layer 34, a conductive layer 35 and a third insulating layer 36 stacked in sequence, the functional layer 3 according to The region can be divided into a first part located in the non-bending region 100 and a second part located in the bending region 200 , wherein a plurality of driving thin film transistors T1 are formed in the first part, and each of the driving thin film transistors T1 is formed in the first part.
  • a plurality of third openings 7 around the second part are provided with a plurality of first openings 8 .
  • the filling layer 4 covers the upper surface of the functional layer 3 and fills the third opening 7 and the first opening 8 .
  • the first insulating layer 32, the second insulating layer 34 and the third insulating layer 36 in the functional layer 3 are all inorganic insulating layers, and the filling layer 4 covering the upper surface of the functional layer 3 is an organic material, such as polyimide. Filling the third opening 7 and the first opening 8 with organic material can effectively improve the stability of the film layer structure of the array substrate under dynamic bending.
  • the filling layer 4 is etched at the position of the first opening 8 to form a second opening 9 , and the second opening 9 is smaller than the first opening 8 , that is, the second opening 9 is formed in the organic material filled in the filling layer 4 in the first opening 8 .
  • the metal layer 5 includes source and drain patterns 52 and a plurality of metal traces 51 connected to the source and drain patterns.
  • the source and drain patterns 52 are connected to the source regions and drains on the active layer 31 .
  • a plurality of metal traces 51 extend to the bending area 200, and the metal traces 51 are bent to the inside of the second opening 9 in the area overlapping with the second opening 9, and are in contact with the second opening 9. the inner surface of the second opening 9 .
  • the flat layer 6 covers the upper surface of the metal layer 5 , especially in the bending region 200 , the flat layer 6 is formed by filling the metal traces 51 and bending into the second opening 9 . the recessed part.
  • the material of the flat layer is preferably an organic material, especially the same material as the filling layer, so that the metal wiring 51 can be sandwiched between two layers of organic material, which can effectively relieve the bending stress on the metal wiring 51 when bending occurs.
  • the materials on both sides of the metal trace 51 are the same or similar, so as to avoid uneven stress due to the large difference in bending stress on both sides due to the different bending characteristics of the materials.
  • a plurality of the third openings 7 are rectangular with the same size along the horizontal section parallel to the film layer, and the long sides of the third openings 7 are facing the driving thin film transistor T1, and the third openings 7 It extends downward along the depth direction of the opening perpendicular to the surface of the film layer, and penetrates through the functional layer 3 and the buffer layer 2 . Setting a plurality of the third openings 7 as identical openings is beneficial to the implementation of the photolithography process, and can avoid uneven stress distribution during bending due to different openings.
  • the four third openings 7 are respectively located in four directions of the driving thin film transistor T1. Specifically: the front third opening 7A, the rear third opening 7B, the left third opening 7C, and the right third opening 7D, wherein the front third opening 7A and the rear The third openings 7B are located on the front and rear sides of the driving thin film transistor, and the left third opening 7C and the right third opening 7D are located on the left and right sides of the driving thin film transistor T1.
  • the front third opening is preferred.
  • the positions of 7A and the rear third opening 7B are symmetrical with respect to the driving thin film transistor T1
  • the positions of the left third opening 7C and the right third opening 7D are symmetrical with respect to the driving thin film transistor T1 .
  • the bending resistance and structural stability of the array substrate can be effectively improved.
  • the film layer of the functional layer structure of the array substrate is detached under the action of stress, thereby avoiding the threshold voltage (VTH) of the driving thin film transistor T1 from drifting due to excessive stress and causing uneven light emission.
  • VTH threshold voltage
  • the plurality of third openings 7 are symmetrically arranged on the driving thin film transistor. All around, the stress in all directions can be relieved more evenly.
  • the third openings 7 are all rectangular, and the long side L of the third openings 7 faces the driving thin film transistor T1 when arranged.
  • the functional layer and the buffer layer are penetrated at the depth of the opening to surround the driving thin film transistor as much as possible, so that the influence of stress on the driving thin film transistor can be alleviated to the greatest extent, and the stable operation of the driving thin film transistor can be ensured.
  • the third openings can also be arranged around other thin film transistors, so as to relieve the stress generated during bending and improve the stability of the device operation.
  • the second part of the functional layer 3 located in the bending area 200 is provided with a plurality of the first openings 8 , and the opening depth of the first openings 8 is larger than that of the third openings 7 .
  • the bending area may need to be kept in a bent state all the time, especially now that narrow bezels have become an important development trend of display panels, the bending area is smaller in size and has a larger bending range, which has a greater impact on the array substrate. Therefore, setting larger and deeper first openings 8 in the bending area 200 and filling the openings with organic materials can greatly relieve the effect of stress and avoid structural damage and cracks in the bending area.
  • the first opening 8 extends into the base layer 1 .
  • the first opening 8 can be divided into an upper opening 81 and a lower opening 82, wherein the upper opening 81 and the third opening 7
  • the same mask is used to etch and form, and then a mask is used to etch the lower opening 82 below the upper opening.
  • the opening depth of the upper opening 81 of the first opening is smaller than that of the third opening.
  • the opening depth of the opening 7 is because the opening size of the upper opening 81 of the first opening is usually larger than that of the third opening, and the same amount of light is used for etching. Depth will be different.
  • the horizontal cross-sectional area of the lower opening 82 is smaller than the horizontal cross-sectional area of the upper opening 81 .
  • the upper openings 81 and the lower openings 82 are trapezoidal cross-sections that are wide at the top and narrow at the bottom along the depth direction of the openings, and the upper openings 81 and the lower openings 82 are respectively formed with upper openings and the lower opening, wherein the cross-sectional area of the upper opening of the lower opening 82 is smaller than the cross-sectional area of the lower opening of the upper opening 81, and in particular, the second opening 9 is also set to be uniform along the depth direction of the opening.
  • the narrow trapezoidal structure enables the metal traces 51 to be closer to the neutral plane of the array substrate as a whole, reduces the applied stress after bending, and protects the metal traces 51 from damage.
  • the metal traces 51 at least partially adhere to the bottom surface of the lower opening 82 of the first opening 8, so that the metal traces can be located as close to the neutral plane as possible, Reduce stress when bending.
  • a plurality of the second openings 9 with the same size and depth are arranged in an array in the bending area 200 , wherein the plurality of second openings 9 in the same row are arranged along the The extending direction of the metal trace 51 is equidistantly arranged and overlaps with one of the metal traces 51.
  • the maximum opening length D of the second opening 9 along the extending direction of the metal trace 51 is greater than that of two adjacent ones along the direction of the metal trace. The distance d between each of the second openings. Further, preferably, the maximum opening length D of the second openings 9 along the extending direction of the metal trace 51 is equal to the length D of two adjacent second openings along the extending direction of the metal trace.
  • the distance d between the two openings 9 is 2 times.
  • the maximum opening length D of the second opening 9 along the extending direction of the metal trace 51 is 8um.
  • the distance d between the second openings 9 is 4um.
  • the opening width T of the second opening 9 along the extension direction perpendicular to the metal trace 51 is greater than the width t of the metal trace perpendicular to the extending direction thereof, preferably the second opening 9 is perpendicular to the metal trace
  • the opening width T of the extending direction of the metal trace 51 is 9.8um, and the width t of the metal trace 51 perpendicular to the extending direction thereof is 7.4um.
  • the adjacent two rows of the second openings 9 arranged along the extending direction of the metal traces 51 are arranged side by side.
  • the two adjacent rows of the second openings 9 arranged in the extending direction of the adjacent metal traces 51 are arranged in dislocation, which can make the overall force of the bending area more uniform, which is beneficial to the improvement of the bending resistance.
  • Embodiments of the present invention further include providing a display device including the array substrate.

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Abstract

一种阵列基板及显示装置，所述阵列基板的功能层（3）在弯折区（200）设有第一开孔（8），覆盖在所述功能层（3）上的填充层（4）填充所述第一开孔（8）并在所述第一开孔（8）的位置设第二开孔（9），所述阵列基板的金属层（5）包括多条金属走线（51），所述金属走线（51）在与所述第二开孔（9）重叠的区域向所述第二开孔（9）内部弯折。

Description

一种阵列基板及显示装置 技术领域
本发明涉及显示技术领域，尤其涉及显示装置，具体涉及一种显示装置的阵列基板。
 背景技术
在显示技术领域，液晶显示器件（Liquid Crystal Display，LCD）与有机发光二极管显示器件（Organic Light Emitting Diode，OLED）等平板显示器件已经逐步取代CRT显示器。
LCD显示器件是由一片薄膜晶体管阵列基板（Thin Film Transistor Array Substrate，TFT Array Substrate）与一片彩色滤光片（Color Filter，CF）基板贴合而成，且在TFT基板与CF基板之间灌入液晶，通过通电与否来控制液晶分子改变方向，将背光模组的光线折射出来产生画面。
OLED具有自发光、驱动电压低、发光效率高、响应时间短、清晰度与对比度高、近180°视角、使用温度范围宽，可实现柔性显示与大面积全色显示等诸多优点，被业界公认为是最有发展潜力的显示器件。OLED显示器件通常包括：基板、设于基板上的阳极、设于阳极上的空穴注入层、设于空穴注入层上的空穴传输层、设于空穴传输层上的发光层、设于发光层上的电子传输层、设于电子传输层上的电子注入层、及设于电子注入层上的阴极，发光原理为半导体材料和有机发光材料在电场驱动下，通过载流子注入和复合导致发光。以当前的市场趋势, 面板进入柔性时代，相关柔性面板开发，柔性可折叠成为小尺寸手机的主流方向，未来柔性OLED显示装置会是市场主流，其中动态折叠（Dynamic Foldable）产品将会成为中小显示行业的重中之重。弯折或折叠时，显示面板中的金属走线极易发生断裂，导致显示区的画面异常；而显示面板膜层之间附着力有限，弯折后容易发生膜层之间相互脱离，严重影响良率，甚至还会引起薄膜晶体管的阈值电压（VTH）漂移导致发光不均，因此需要显示面板有更稳定的结构来应对耐弯折的要求，需要柔性面板或材料的动态拉伸和弯折耐久性得到保证。
 技术问题
本发明提供一种具有稳定结构的阵列基板及具有该阵列基板的显示装置，能够满足动态拉伸和弯折的要求，避免出现裂纹及影响薄膜晶体管的正常工作。
 技术解决方案
第一方面，本申请实施例提供一种阵列基板，包括弯折区和非弯折区，所述阵列基板包括依次层叠设置的基底层、缓冲层、功能层、填充层和金属层；
所述功能层包括位于所述非弯折区的第一部分和位于所述弯折区的第二部分，所述第一部分设有多个驱动薄膜晶体管，所述第二部分设有多个第一开孔；所述填充层覆盖所述功能层上表面并填充所述第一开孔；所述填充层在所述第一开孔处设有第二开孔；所述金属层包括源漏极图案和与所述源漏极图案连接的多条金属走线，所述金属走线在与所述第二开孔重叠的区域向所述第二开孔内部弯折。
在所述阵列基板中，所述第一开孔延伸至所述基底层内。
在所述阵列基板中，所述第一开孔包括上部开孔和下部开孔，所述下部开孔位于所述上部开孔的下方，且所述下部开孔的水平截面面积小于所述上部开孔的水平截面面积。
在所述阵列基板中，所述上部开孔、所述下部开孔和所述第二开孔均为沿开孔深度方向上宽下窄的梯形截面。
在所述阵列基板中，所述金属走线至少部分贴合所述第一开孔的所述下部开孔的底面。
在所述阵列基板中，多个所述第二开孔与所述金属走线重叠，并沿所述金属走线延伸方向等距离设置。
在所述阵列基板中，所述第二开孔沿所述金属走线延伸方向的最大开口长度大于沿所述金属走线延伸方向相邻两个所述第二开孔之间的距离，所述第二开孔垂直于所述金属走线延伸方向的开口宽度大于所述金属走线的宽度。
在所述阵列基板中，沿相邻的所述金属走线延伸方向设置的两行所述第二开孔是交错布置。
在所述阵列基板中，每个所述驱动薄膜晶体管的四周分别各设一个第三开孔，每个所述第三开孔的水平截面为大小相同的长方形，所述第三开孔的长边正对所述驱动薄膜晶体管。
在所述阵列基板中，所述第三开孔沿开孔深度方向贯穿所述功能层和所述缓冲层，所述填充层填充所述第三开孔。
第二方面，本申请实施例还提供一种显示装置，所述显示装置包括阵列基板，所述阵列基板包括弯折区和非弯折区，所述阵列基板包括依次层叠设置的基底层、缓冲层、功能层、填充层和金属层；所述功能层包括位于所述非弯折区的第一部分和位于所述弯折区的第二部分，所述第一部分设有多个驱动薄膜晶体管，所述第二部分设有第一开孔；所述填充层覆盖所述功能层上表面并填充所述第一开孔，所述填充层在所述第一开孔处设有第二开孔；所述金属层包括源漏极图案和与所述源漏极图案连接的多条金属走线，所述金属走线在与所述第二开孔重叠的区域向所述第二开孔内部弯折。
在所述显示装置中，所述第一开孔延伸至所述基底层内。
在所述显示装置中，所述第一开孔包括上部开孔和下部开孔，所述下部开孔位于所述上部开孔的下方，且所述下部开孔的水平截面面积小于所述上部开孔的水平截面面积。
在所述显示装置中，所述上部开孔、所述下部开孔和所述第二开孔均为沿开孔深度方向上宽下窄的梯形截面。
在所述显示装置中，所述金属走线至少部分贴合所述第一开孔的所述下部开孔的底面。
在所述显示装置中，多个所述第二开孔与所述金属走线重叠，并沿所述金属走线延伸方向等距离设置。
在所述显示装置中，所述第二开孔沿所述金属走线延伸方向的最大开口长度大于沿所述金属走线延伸方向相邻两个所述第二开孔之间的距离，所述第二开孔垂直于所述金属走线延伸方向的开口宽度大于所述金属走线的宽度。
在所述显示装置中，沿相邻的所述金属走线延伸方向设置的两行所述第二开孔是交错布置。
在所述显示装置中，每个所述驱动薄膜晶体管的四周分别各设一个第三开孔，每个所述第三开孔的水平截面为大小相同的长方形，所述第三开孔的长边正对所述驱动薄膜晶体管。
在所述显示装置中，所述第三开孔沿开孔深度方向贯穿所述功能层和所述缓冲层；所述填充层填充所述第三开孔。
 有益效果
相较于现有技术，本发明的技术方案能有效提高阵列基板动态弯折时的结构稳定性，避免应力对膜层结构的破坏以及造成驱动薄膜晶体管的阈值电压漂移影响正常工作，减小弯折区金属走线受到的应力。
 附图说明
图1为本发明实施例提供的阵列基板的结构示意图。
图2为本发明实施例提供的阵列基板的驱动薄膜晶体管所在位置的结构示意图。
图3为本发明实施例提供的阵列基板的弯折区的结构示意图。
图4为本发明实施例提供的阵列基板的弯折区的另一结构示意图。
 本发明的实施方式
本申请提供一种触控电极层及触控显示装置，为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
如图1所示，本发明实施例提供一种阵列基板，其包括：
包括非弯折区100和围绕所述非弯折区100的弯折区200，所述阵列基板包括依次层叠设置的基底层1、缓冲层2、功能层3、填充层4、金属层5和平坦层6，所述功能层3包括依次层叠的有源层31、第一绝缘层32、栅极33、第二绝缘层34、导电层35和第三绝缘层36，所述功能层3根据所在区域可以划分为包括位于非弯折区100的第一部分和位于弯折区200的第二部分，所述第一部分中形成有多个驱动薄膜晶体管T1，及位于每个所述驱动薄膜晶体管T1周围的多个第三开孔7，所述第二部分设有多个第一开孔8。所述填充层4覆盖所述功能层3上表面并填充所述第三开孔7和所述第一开孔8。
所述功能层3中的所述第一绝缘层32、第二绝缘层34和第三绝缘层36均为无机绝缘层，覆盖所述功能层3上表面的所述填充层4为有机材料，如聚酰亚胺。将有机材料填充所述第三开孔7和所述第一开孔8，能够有效提升阵列基板在动态弯折下膜层结构的稳定性。
所述填充层4在所述第一开孔8的位置再经过一道刻蚀形成第二开孔9，所述第二开孔9小于所述第一开孔8，即所述第二开孔9形成于所述填充层4位于所述第一开孔8内填充的有机材料中。
所述金属层5包括源漏极图案52和与所述源漏极图案连接的多条金属走线51，所述源漏极图案52与所述有源层31上的源极区和漏极区连接，多条金属走线51延伸至弯折区200，所述金属走线51在与所述第二开孔9重叠的区域向所述第二开孔9内部弯折，并贴合所述第二开孔9的内表面。
所述平坦层6覆盖所述金属层5的上表面，特别是在所述弯折区200，所述平坦层6填充所述金属走线51向所述第二开孔9内弯折后形成的凹陷部位。平坦层材料优选有机材料，特别是选择与填充层相同的材料制作，这样能够使得金属走线51夹在两层有机材料层中间，在发生弯折时能有效缓解弯折应力对金属走线51的作用，并且金属走线51两侧材料相同或相近，避免因材料弯曲特性不同导致两侧弯曲应力差异较大而出现受力不均。
多个所述第三开孔7沿平行于膜层的水平截面为大小相同的长方形，并且所述第三开孔7的长边正对所述驱动薄膜晶体管T1，所述第三开孔7沿垂直于膜层表面的开孔深度方向向下延伸，贯穿所述功能层3和所述缓冲层2。将多个所述第三开孔7设为完全相同的开孔有利于光刻工艺的实施，而且能够避免因开孔不同导致弯折时应力分布不均。
每个所述驱动薄膜晶体管T1的周围设有四个所述第三开孔7，如图2所示，四个所述第三开孔7分别位于所述驱动薄膜晶体管T1的四个方向，具体为：前方的前第三开孔7A、后方的后第三开孔7B、左侧的左第三开孔7C、右侧的右第三开孔7D，其中前第三开孔7A与后第三开孔7B位于所述驱动薄膜晶体管的前后两侧，左第三开孔7C与右第三开孔7D位于所述驱动薄膜晶体管T1的左右两侧，本实施例优选前第三开孔7A与后第三开孔7B的位置关于所述驱动薄膜晶体管T1对称，左第三开孔7C与右第三开孔7D的位置关于所述驱动薄膜晶体管T1对称。
通过在驱动薄膜晶体管四周设第三开孔并以有机材料填充，能够有效提高阵列基板的耐弯折性能和结构稳定性，位于驱动薄膜晶体管四周两两相对设置的第三开孔能够有效的抑制弯折时阵列基板功能层膜层结构在应力作用下的膜层脱离，进而避免因为应力过大导致驱动薄膜晶体管T1的阈值电压（VTH）出现漂移进而引起发光不均。由于动态弯折时弯曲方向具有一定的不确定性，导致作用在阵列基板上的应力的方向可能来自多个方向，本实施例将多个所述第三开孔7对称布置在驱动薄膜晶体管的四周，能够更均匀缓解各方向的应力，另外，优选所述第三开孔7均为长方形，并且布置时将所述第三开孔7的长边L正对所述驱动薄膜晶体管T1，同时在开孔深度上贯穿所述功能层和缓冲层，以尽可能的包围所述驱动薄膜晶体管，这样可以最大程度缓解应力对驱动薄膜晶体管的影响，保证驱动薄膜晶体管的稳定工作。
进一步的，所述第三开孔还可以设置在其他薄膜晶体管的周围，以缓解弯折时产生的应力作用，提高器件工作的稳定性。
所述功能层3位于弯折区200的第二部分设有多个所述第一开孔8，所述第一开孔8的开孔深度比所述第三开孔7的开孔深度大，这是由于弯折区可能需要始终保持弯折的状态，特别是如今窄边框成为显示面板重要的发展趋势，弯折区由于尺寸较小，弯折幅度更大，对阵列基板产生更大的作用应力，因此，在弯折区200设置更大更深的第一开孔8并在开孔内填充有机材料能够极大的缓解应力的作用，避免弯折区域结构破坏，出现裂纹。本实施例优选所述第一开孔8延伸至所述基底层1内。
进一步的，考虑到所述第一开孔的深度较大，可以将所述第一开孔8分为上部开孔81和下部开孔82，其中上部开孔81与所述第三开孔7采用同一道掩模刻蚀成型，然后在所述上部开孔的下方再利用一道掩模刻蚀下部开孔82，所述第一开孔的上部开孔81的开孔深度小于所述第三开孔7的开孔深度，这是由于所述第一开孔的上部开孔81的开孔尺寸通常会比所述第三开孔的开孔尺寸大，采用相同的光照量进行刻蚀的深度就会不同。为简化工艺，优选所述下部开孔82的水平截面面积小于所述上部开孔81的水平截面面积。
本实施例中所述上部开孔81和所述下部开孔82沿开孔深度方向均为上宽下窄的梯形截面，所述上部开孔81和所述下部开孔82分别形成有上开口和下开口，其中所述下部开孔82的上开口的截面面积小于所述上部开孔81的下开口的截面面积，特别的，所述第二开孔9也设为沿开孔深度方向均为上宽下窄的梯形截面，这样所述金属走线51在向所述第二开孔9内弯折并贴合所述第二开孔9的内表面时也可以相应的形成上宽下窄的梯形结构，使得所述金属走线51整体上能更靠近阵列基板的中性面，减小弯折后的作用应力，保护所述金属走线51不发生破坏。
在另一些实施例中，所述金属走线51至少部分贴合所述第一开孔8的所述下部开孔82的底面，这样金属走线能够尽可能位于靠近中性面附近的位置，减小弯曲时所受到的应力。
请参阅图3所示，在一些实施例中，在弯折区200内阵列布置多个大小、深度完全相同的所述第二开孔9，其中处于同一行的多个第二开孔9沿金属走线51延伸的方向等距离设置，并与一条所述金属走线51重叠，所述第二开孔9沿金属走线51延伸方向的最大开口长度D大于沿金属走线方向相邻两个所述第二开孔之间的距离d，进一步的，优选所述第二开孔9沿金属走线51延伸方向的最大开口长度D是沿金属走线延伸方向相邻两个所述第二开孔9之间的距离d的2倍，优选所述第二开孔9沿金属走线51延伸方向的最大开口长度D为8um，沿所述金属走线延伸方向相邻两个所述第二开孔9之间的距离d为4um。所述第二开孔9沿垂直于金属走线51的延伸方向的开口宽度T大于所述金属走线沿垂直于其延伸方向的宽度t，优选所述第二开孔9垂直于金属走线51的延伸方向的开口宽度T为9.8um，所述金属走线51垂直于其延伸方向的宽度t为7.4um。
如图3所示，沿所述金属走线51延伸方向布置的相邻的两行所述第二开孔9为两两并列设置，在另一些实施例中，如图4所示，沿相邻的所述金属走线51延伸方向布置的相邻两行所述第二开孔9是错位布置，这样能够使弯折区的整体受力更均匀，有利于耐弯折性能的提升。
本发明实施例还包括提供一种显示装置，所述显示装置包括所述的阵列基板。
可以理解的是，对本领域普通技术人员来说，可以根据本申请的技术方案及其发明构思加以等同替换或改变，而所有这些改变或替换都应属于本申请所附的权利要求的保护范围。

Claims (20)

  1. 一种阵列基板，其中，包括弯折区和非弯折区，所述阵列基板包括依次层叠设置的基底层、缓冲层、功能层、填充层和金属层；
    所述功能层包括位于所述非弯折区的第一部分和位于所述弯折区的第二部分，所述第一部分设有多个驱动薄膜晶体管，所述第二部分设有第一开孔；
    所述填充层覆盖所述功能层上表面并填充所述第一开孔，所述填充层在所述第一开孔处设有第二开孔；
    所述金属层包括源漏极图案和与所述源漏极图案连接的多条金属走线，所述金属走线在与所述第二开孔重叠的区域向所述第二开孔内部弯折。
  2. 如权利要求1所述的阵列基板，其中，所述第一开孔延伸至所述基底层内。
  3. 如权利要求2所述的阵列基板，其中，所述第一开孔包括上部开孔和下部开孔，所述下部开孔位于所述上部开孔的下方，且所述下部开孔的水平截面面积小于所述上部开孔的水平截面面积。
  4. 如权利要求3所述的阵列基板，其中，所述上部开孔、所述下部开孔和所述第二开孔均为沿开孔深度方向上宽下窄的梯形截面。
  5. 如权利要求4所述的阵列基板，其中，所述金属走线至少部分贴合所述第一开孔的所述下部开孔的底面。
  6. 如权利要求1所述的阵列基板，其中，多个所述第二开孔与所述金属走线重叠，并沿所述金属走线延伸方向等距离设置。
  7. 如权利要求6所述的阵列基板，其中，所述第二开孔沿所述金属走线延伸方向的最大开口长度大于沿所述金属走线延伸方向相邻两个所述第二开孔之间的距离，所述第二开孔垂直于所述金属走线延伸方向的开口宽度大于所述金属走线的宽度。
  8. 如权利要求6所述的阵列基板，沿相邻的所述金属走线延伸方向设置的两行所述第二开孔是交错布置。
  9. 如权利要求1所述的阵列基板，其中，每个所述驱动薄膜晶体管的四周分别各设一个第三开孔，每个所述第三开孔的水平截面为大小相同的长方形，所述第三开孔的长边正对所述驱动薄膜晶体管。
  10. 如权利要求9所述的阵列基板，其中，所述第三开孔沿开孔深度方向贯穿所述功能层和所述缓冲层；所述填充层填充所述第三开孔。
  11. 一种显示装置，所述显示装置包括阵列基板，所述阵列基板包括弯折区和非弯折区，所述阵列基板包括依次层叠设置的基底层、缓冲层、功能层、填充层和金属层；
    所述功能层包括位于所述非弯折区的第一部分和位于所述弯折区的第二部分，所述第一部分设有多个驱动薄膜晶体管，所述第二部分设有第一开孔；
    所述填充层覆盖所述功能层上表面并填充所述第一开孔，所述填充层在所述第一开孔处设有第二开孔；
    所述金属层包括源漏极图案和与所述源漏极图案连接的多条金属走线，所述金属走线在与所述第二开孔重叠的区域向所述第二开孔内部弯折。
  12. 如权利要求11所述的显示装置，其中，所述第一开孔延伸至所述基底层内。
  13. 如权利要求12所述的显示装置，其中，所述第一开孔包括上部开孔和下部开孔，所述下部开孔位于所述上部开孔的下方，且所述下部开孔的水平截面面积小于所述上部开孔的水平截面面积。
  14. 如权利要求13所述的显示装置，其中，所述上部开孔、所述下部开孔和所述第二开孔均为沿开孔深度方向上宽下窄的梯形截面。
  15. 如权利要求14所述的显示装置，其中，所述金属走线至少部分贴合所述第一开孔的所述下部开孔的底面。
  16. 如权利要求11所述的显示装置，其中，多个所述第二开孔与所述金属走线重叠，并沿所述金属走线延伸方向等距离设置。
  17. 如权利要求16所述的显示装置，其中，所述第二开孔沿所述金属走线延伸方向的最大开口长度大于沿所述金属走线延伸方向相邻两个所述第二开孔之间的距离，所述第二开孔垂直于所述金属走线延伸方向的开口宽度大于所述金属走线的宽度。
  18. 如权利要求16所述的显示装置，沿相邻的所述金属走线延伸方向设置的两行所述第二开孔是交错布置。
  19. 如权利要求11所述的显示装置，其中，每个所述驱动薄膜晶体管的四周分别各设一个第三开孔，每个所述第三开孔的水平截面为大小相同的长方形，所述第三开孔的长边正对所述驱动薄膜晶体管。
  20. 如权利要求19所述的显示装置，其中，所述第三开孔沿开孔深度方向贯穿所述功能层和所述缓冲层；所述填充层填充所述第三开孔。
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