WO2022041370A1 - 栅极驱动电路及显示装置 - Google Patents

栅极驱动电路及显示装置 Download PDF

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Publication number
WO2022041370A1
WO2022041370A1 PCT/CN2020/117599 CN2020117599W WO2022041370A1 WO 2022041370 A1 WO2022041370 A1 WO 2022041370A1 CN 2020117599 W CN2020117599 W CN 2020117599W WO 2022041370 A1 WO2022041370 A1 WO 2022041370A1
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Prior art keywords
module
pull
output
electrically connected
signal input
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PCT/CN2020/117599
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English (en)
French (fr)
Inventor
曹海明
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to US17/056,795 priority Critical patent/US11615726B2/en
Publication of WO2022041370A1 publication Critical patent/WO2022041370A1/zh
Anticipated expiration legal-status Critical
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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present application relates to the field of display technology, and in particular, to a gate driving circuit and a display device.
  • GOA Gate Driver on Array
  • the application of the GOA technology is beneficial to realize the narrow frame design of the display device, and therefore, its application in the field of display technology is becoming more and more extensive.
  • the application types of GOA circuits are also diversified.
  • the dynamic frame rate display technology of low-temperature polysilicon oxide-based display devices in order to solve the problem of low-frequency display failure caused by the gate leakage of the driving transistor caused by the negative shift of the potential of the metal oxide transistor connected to the driving transistor during operation, the The number of metal oxide transistors directly connected to the gate of the driving transistor is increased to two sets, and they work alternately; at this time, the GOA circuit needs to provide two gate driving signals to act on the two sets of metal oxide transistors respectively, so as to realize its alternate work.
  • the present application provides a gate driving circuit, comprising a plurality of gate driving units, each of the gate driving units comprising:
  • the staging unit is used to output the staging signal
  • a first output unit for outputting a first driving signal
  • a second output unit for outputting a second driving signal
  • the first driving signal is a waveform signal
  • the second driving signal is a constant-high voltage signal
  • the first driving signal is a constant-high voltage signal
  • the second driving signal is a waveform signal
  • the first output unit includes a first bootstrap output module and a first pull-down maintaining module, and the first bootstrap output module is used to pull up the output of the first output unit. an output potential, the first pull-down maintaining module is used for pulling down and maintaining the output potential of the first output unit.
  • the first bootstrap output module is electrically connected to the first pull-down maintenance module, and the first pull-down maintenance module controls the first bootstrap output module to output a constant the first drive signal of high voltage.
  • the second output unit includes a second bootstrap output module and a second pull-down maintenance module, and the second bootstrap output module is used to pull up the output of the second output unit
  • the second pull-down maintaining module is used to pull down and maintain the output potential of the second output unit.
  • the second bootstrap output module is electrically connected to the second pull-down maintenance module, and the second pull-down maintenance module controls the second bootstrap output module to output a constant high voltage of the second drive signal.
  • each of the gate driving units further includes:
  • a first transfer module electrically connected between the stage transfer unit and the first bootstrap output module, and used for transferring an output control signal to the first bootstrap output module;
  • the second transfer module is electrically connected between the stage transfer unit and the second bootstrap output module, and is used for transferring an output control signal to the second bootstrap output module.
  • each of the gate driving units further includes:
  • the pull-up maintaining module is electrically connected to the first pull-down maintaining module and the second pull-down maintaining module, respectively, and is used for pulling up and maintaining the connection between the first pull-down maintaining module and the second pull-down maintaining module. control terminal potential;
  • the pull-down module is electrically connected to the first pull-down maintaining module and the second pull-down maintaining module respectively, and is used for pulling down the potentials of the control terminals of the first pull-down maintaining module and the second pull-down maintaining module.
  • the first pull-down maintaining module is electrically connected to the first control signal input terminal
  • the second pull-down maintaining module is electrically connected to the second control signal input terminal
  • the first control signal input terminal inputs a low voltage signal to the first pull-down maintaining module
  • the second control signal input terminal inputs a high voltage signal to the second pull-down maintaining module voltage signal
  • the first driving signal is a waveform signal
  • the second driving signal is a constant-high voltage signal
  • the first control signal input terminal inputs a high voltage signal to the first pull-down maintaining module
  • the second control signal input terminal inputs a low voltage signal to the second pull-down maintaining module voltage signal
  • the first driving signal is a constant-high voltage signal
  • the second driving signal is a waveform signal.
  • the first bootstrap output module and the second bootstrap output module are both electrically connected to the first high-voltage signal input terminal, and the pull-up maintaining module is electrically connected to the second high-voltage signal input terminal. signal input terminal;
  • the voltage input from the first high-voltage signal input terminal is greater than the voltage input from the second high-voltage signal input terminal.
  • the staging unit is electrically connected to the second high-voltage signal input terminal, the staging signal input terminal, the first clock signal input terminal, the second clock signal input terminal, and the low-voltage signal input terminal.
  • a terminal, a staging signal output terminal and a first node, the staging signal output terminal is used for outputting the staging signal;
  • the first transfer module is electrically connected to the first node, the first clock signal input end and the third node;
  • the second transfer module is electrically connected to the first node, the first clock signal input end and the fourth node;
  • the pull-up maintaining module is electrically connected to the second clock signal input end, the second high-voltage signal input end and the second node;
  • the pull-down module is electrically connected to the first node, the low-voltage signal input end and the second node;
  • the first bootstrap output module is electrically connected to the third node, the first high-voltage signal input terminal, the second high-voltage signal input terminal and the first driving signal output terminal, and the first driving signal output terminal for outputting the first drive signal;
  • the first pull-down maintaining module is electrically connected to the second node, the third node and the first control signal input end;
  • the second bootstrap output module is electrically connected to the fourth node, the first high-voltage signal input terminal, the second high-voltage signal input terminal and a second driving signal output terminal, and the second driving signal output terminal for outputting the second driving signal;
  • the second pull-down maintaining module is electrically connected to the second node, the fourth node and the second control signal input terminal.
  • the staging unit includes a first transistor, a second transistor, a third transistor and a fourth transistor, and the gate, source and drain of the first transistor are respectively electrically connected
  • the staging signal input terminal, the second high-voltage signal input terminal and the first node, the gate, source and drain of the second transistor are respectively electrically connected to the first node, the first node and the first node.
  • a clock signal input terminal and the staging signal output terminal, the gate, source and drain of the third transistor are respectively electrically connected to the second clock signal input terminal, the low-voltage signal input terminal and the a staging signal output terminal, the gate, source and drain of the fourth transistor are respectively electrically connected to the second clock signal input terminal, the low-voltage signal input terminal and the first node;
  • the first transfer module includes a fifth transistor and a first capacitor, and the gate, source and drain of the fifth transistor are respectively electrically connected to the first node, the first clock signal input end and the a third node, two poles of the first capacitor are respectively electrically connected to the first node and the third node;
  • the second transfer module includes a sixth transistor and a second capacitor, and the gate, source and drain of the sixth transistor are respectively electrically connected to the first node, the first clock signal input end and the a fourth node, two poles of the second capacitor are electrically connected to the first node and the fourth node respectively;
  • the pull-up maintaining module includes a seventh transistor and a third capacitor, and the gate, source and drain of the seventh transistor are respectively electrically connected to the second clock signal input end and the second high-voltage signal input end and the second node, two poles of the third capacitor are electrically connected to the second node and the low-voltage signal input terminal respectively;
  • the pull-down module includes an eighth transistor, and the gate, source and drain of the eighth transistor are electrically connected to the first node, the low-voltage signal input terminal and the second node, respectively;
  • the first bootstrap output module includes a ninth transistor, a tenth transistor and a fourth capacitor, and the gate, source and drain of the ninth transistor are respectively electrically connected to the second high-voltage signal input end, the The third node and the fifth node, the gate, source and drain of the tenth transistor are respectively electrically connected to the fifth node, the first high voltage signal input end and the first driving signal output end, Two poles of the fourth capacitor are respectively electrically connected to the fifth node and the first driving signal output terminal;
  • the first pull-down maintaining module includes an eleventh transistor and a twelfth transistor, and the gate, source and drain of the eleventh transistor are respectively electrically connected to the second node and the first control signal an input terminal and the third node, the gate, source and drain of the twelfth transistor are respectively electrically connected to the second node, the first control signal input terminal and the first drive signal output end;
  • the second bootstrap output module includes a thirteenth transistor, a fourteenth transistor and a fifth capacitor, and the gate, source and drain of the thirteenth transistor are respectively electrically connected to the second high-voltage signal input terminal , the fourth node and the sixth node, the gate, source and drain of the fourteenth transistor are respectively electrically connected to the sixth node, the first high voltage signal input terminal and the second drive a signal output end, where two poles of the fifth capacitor are respectively electrically connected to the sixth node and the second drive signal output end;
  • the second pull-down maintaining module includes a fifteenth transistor and a sixteenth transistor, and the gate, source and drain of the fifteenth transistor are respectively electrically connected to the second node and the second control signal input. terminal and the fourth node, the gate, source and drain of the sixteenth transistor are respectively electrically connected to the second node, the second control signal input terminal and the second drive signal output terminal .
  • a plurality of the gate driving units have the following cascade relationship: the cascade signal input terminal of the gate driving unit of this stage is electrically connected to the gate of the previous stage the output terminal of the staging signal of the driving unit.
  • the gate driving circuit provides clock signals through the first clock signal line, the second clock signal line and the third clock signal line, respectively,
  • the first clock signal input terminal and the second clock signal input terminal of the gate driving unit of the k+3i stage are respectively electrically connected to the first clock signal line and the second clock signal line;
  • the first clock signal input terminal and the second clock signal input terminal of the k+3i+1 th gate driving unit are respectively electrically connected to the second clock signal line and the third clock signal line ;
  • the first clock signal input terminal and the second clock signal input terminal of the gate driving unit of the k+3i+2 stage are electrically connected to the third clock signal line and the first clock signal line, respectively ;
  • k is an integer greater than or equal to 1
  • i is an integer greater than or equal to 0.
  • the present application further provides a display device, including a gate driving circuit, the gate driving circuit includes a plurality of gate driving units, and each of the gate driving units includes:
  • the staging unit is used to output the staging signal
  • a first output unit for outputting a first driving signal
  • a second output unit for outputting a second driving signal
  • the first driving signal is a waveform signal
  • the second driving signal is a constant-high voltage signal
  • the first driving signal is a constant-high voltage signal
  • the second driving signal is a waveform signal
  • the first output unit includes a first bootstrap output module and a first pull-down maintaining module, and the first bootstrap output module is used to pull up the output potential of the first output unit , the first pull-down maintaining module is used to pull down and maintain the output potential of the first output unit; the first bootstrap output module is electrically connected to the first pull-down maintaining module, and the first The pull-maintaining module controls the first bootstrap output module to output the first driving signal of a constant high voltage.
  • the second output unit includes a second bootstrap output module and a second pull-down maintaining module, the second bootstrap output module is used to pull up the output potential of the second output unit, The second pull-down maintaining module is used to pull down and maintain the output potential of the second output unit; the second bootstrap output module is electrically connected with the second pull-down maintaining module, and the second pull-down maintaining module controls The second bootstrap output module outputs the second driving signal with a constant high voltage.
  • each of the gate driving units further includes:
  • a first transfer module electrically connected between the stage transfer unit and the first bootstrap output module, and used for transferring an output control signal to the first bootstrap output module;
  • a second transfer module electrically connected between the stage transfer unit and the second bootstrap output module, and used for transferring an output control signal to the second bootstrap output module
  • the pull-up maintaining module is electrically connected to the first pull-down maintaining module and the second pull-down maintaining module, respectively, and is used for pulling up and maintaining the connection between the first pull-down maintaining module and the second pull-down maintaining module. control terminal potential;
  • a pull-down module which is electrically connected to the first pull-down maintaining module and the second pull-down maintaining module, respectively, for pulling down the potentials of the control terminals of the first pull-down maintaining module and the second pull-down maintaining module;
  • the first pull-down maintaining module is electrically connected to the first control signal input end, and the second pull-down maintaining module is electrically connected to the second control signal input end.
  • the first control signal input terminal inputs a low voltage signal to the first pull-down maintaining module
  • the second control signal input terminal inputs a high voltage signal to the second pull-down maintaining module
  • the first drive signal is a waveform signal
  • the second drive signal is a constant-high voltage signal
  • the first control signal input terminal inputs a high voltage signal to the first pull-down maintaining module
  • the second control signal input terminal inputs a low voltage signal to the second pull-down maintaining module
  • the first drive The signal is a constant high voltage signal
  • the second driving signal is a waveform signal.
  • Each stage of the gate drive unit of the gate drive circuit provided by the present application includes two drive signal output units, which can output constant-high voltage signals and waveform signals alternately, so as to realize the simultaneous output of two drive signals through one gate drive circuit Compared with the prior art design in which two sets of gate drive circuits are used to output two kinds of driving signals, the number of clock signal lines and the number of thin film transistors are reduced, and the application in the display device is beneficial to realize the narrow frame of the display device. .
  • FIG. 1 is a schematic diagram of a circuit structure of a gate driving unit in a gate driving circuit provided by an embodiment of the present application;
  • FIG. 2 is a schematic diagram of a cascade relationship of gate driving units provided by an embodiment of the present application
  • FIG 3 is an input/output timing diagram of the first output mode of the gate drive circuit provided by the embodiment of the present application.
  • FIG. 4 is an input/output timing diagram of the second output mode of the gate drive circuit provided by the embodiment of the present application.
  • An embodiment of the present application provides a gate drive circuit
  • the gate drive circuit includes a multi-stage gate drive unit
  • each stage of the gate drive unit includes two drive signal output units and one stage transmission signal output unit , wherein the two drive signal output units can alternately output the constant-high voltage signal and the waveform signal, so as to output two drive signals simultaneously through one gate drive circuit.
  • two sets of gate drive circuits are used to output two
  • the design of the driving signal reduces the number of clock signal lines and the number of thin film transistors used in the gate driving circuit, which is beneficial to realize the narrow frame of the display device.
  • FIG. 1 is a schematic diagram of a circuit structure of a gate driving unit in a gate driving circuit provided by an embodiment of the present application.
  • the gate driving circuit includes a plurality of gate driving units, and an electrical connection relationship exists between the gate driving units. Specifically, the plurality of gate driving units are cascaded in sequence to form a multi-level driving unit. It should be understood that the gate driving circuit is applied in a display device to provide a gate driving signal for the pixel circuit of each display unit of the display device, so as to ensure the normal function of each display unit.
  • the gate driving unit includes a staging unit 100 , a first output unit 200 and a second output unit 300 .
  • the staging unit 100 is used for outputting staging signals, and the staging signals are control signals or feedback signals transmitted between adjacent gate driving units; the first output unit 200 is used for outputting the first driving
  • the second output unit 300 is used for outputting a second driving signal, the first driving signal and the second driving signal act on the pixel circuit of each display unit of the display device, and regulate the function of the pixel circuit.
  • the first driving signal output by the first output unit 200 is a waveform signal
  • the second driving signal output by the second output unit 300 is a constant-high voltage signal
  • the first driving signal is a constant-high voltage signal
  • the second driving signal output by the second output unit 300 is a waveform signal.
  • the gate driving unit can output two kinds of gate driving signals through the first output unit 200 and the second output unit 300 at the same time, so as to satisfy the need for two kinds of gate driving signals in the display device at the same time
  • the requirement of gate driving signals reduces the number of clock signal lines and the number of thin film transistors used in the gate driving circuit, which is beneficial to realize the narrow frame of the display device
  • the first output unit 200 and the second output unit 300 can alternately output the two gate driving signals, which increases the application range of the gate driving circuit and avoids component fatigue and functional abnormality caused by a single output unit outputting the same signal for a long time.
  • the first output unit 200 includes a first bootstrap output module 201 and a first pull-down maintaining module 202 .
  • the first bootstrap output module 201 is used for pulling up the output potential of the first output unit 200 , that is, raising the potential of the first driving signal; Outputting the potential means lowering the potential of the first driving signal and maintaining the potential of the first driving signal at a low level. It should be understood that, under the joint action of the first bootstrap output unit 201 and the first pull-down maintaining unit 202, the first output unit 200 can output a waveform signal.
  • the second output unit 300 includes a second bootstrap output module 301 and a second pull-down maintenance module 302 .
  • the second bootstrap output module 301 is used for pulling up the output potential of the second output unit 300 , that is, raising the potential of the second driving signal;
  • the second pull-down maintaining module 302 is used for pulling down and maintaining the output of the second output unit 300 potential, that is, reducing the potential of the second driving signal and maintaining the potential of the second driving signal at a low level. It should be understood that, under the joint action of the second bootstrap output unit 301 and the second pull-down maintaining unit 302, the second output unit 300 can output a waveform signal.
  • the first bootstrap output module 201 is electrically connected with the first pull-down maintaining module 202, and the first pull-down maintaining module 202 can control the first bootstrap output module 201 to pull up the output of the first output unit 200 for a long time voltage to keep the first drive signal as a constant high voltage signal;
  • the second bootstrap output module 301 is electrically connected to the second pull-down maintaining module 302, and the second pull-down maintaining module 302 can control the second bootstrap output module 301 to compare Pulling up the output potential of the second output unit 300 for a long time keeps the second driving signal as a constant high voltage signal. It should be understood that, through the regulation of the first pull-down maintaining module 202 and the second pull-down maintaining module 302, the first output unit 200 and the second output unit 300 can alternately output a constant-high voltage signal.
  • each of the gate driving units further includes a first transfer module 400 , a second transfer module 500 , a pull-up maintaining module 600 and a pull-down module 700 .
  • the first transfer module 400 is electrically connected between the stage transfer unit 100 and the first output unit 200; specifically, the first transfer module 400 is electrically connected to the first bootstrap output module 201 of the first output unit 200; the first transfer The module 400 is configured to transmit an output control signal to the first bootstrap output module 201 under the control of the signal output by the staging unit 100 to control whether the first bootstrap output module 201 outputs a high voltage signal.
  • the second transfer module 500 is electrically connected between the stage transfer unit 100 and the second output unit 300; specifically, the second transfer module 500 is electrically connected to the second bootstrap output module 301 of the second output unit 300; the second transfer The module 500 is configured to transmit an output control signal to the second bootstrap output module 301 under the control of the signal output by the staging unit 100 to control whether the second bootstrap output module 301 outputs a high voltage signal.
  • the pull-up maintaining module 600 is electrically connected to the first pull-down maintaining module 202 and the second pull-down maintaining module 302, respectively, for pulling up and maintaining the control terminal potentials of the first pull-down maintaining module 202 and the second pull-down maintaining module 302, Then, the first pull-down maintaining module 202 and the second pull-down maintaining module 302 are controlled to be turned on.
  • the pull-down module 700 is electrically connected to the first pull-down maintaining module 202 and the second pull-down maintaining module 302, respectively, and is used to pull down the potentials of the control terminals of the first pull-down maintaining module 202 and the second pull-down maintaining module 302, thereby controlling the first pull-down maintaining module 202 and the second pull-down maintaining module 302.
  • the pull-down sustain module 202 and the second pull-down sustain module 302 are turned off.
  • the first pull-down maintaining module 202 is electrically connected to the first control signal input end LCA, the first control signal input end LCA inputs a control signal to the first pull-down maintaining module 202, and the first pull-down maintaining module 202 further connects the control signal to the first pull-down maintaining module 202.
  • the control signal is transmitted to the first bootstrap output module 201 to control whether the first bootstrap output module 201 outputs a high voltage signal.
  • the first driving signal is a waveform signal; the first control signal input terminal LCA inputs the first pull-down maintaining module 202 When a high voltage signal is input, the first driving signal is a constant high voltage signal.
  • the second pull-down holding module 302 is electrically connected to the second control signal input terminal LCB, the second control signal input terminal LCB inputs a control signal to the second pull-down holding module 302, and the second pull-down holding module 302 further transmits the control signal to the second pull-down holding module 302.
  • the bootstrap output module 301 further controls whether the second bootstrap output module 301 outputs a high voltage signal.
  • the second driving signal is a constant-high voltage signal; the second control signal input terminal LCB inputs the second pull-down maintaining module 302
  • the second driving signal is a waveform signal.
  • the first bootstrap output module 201 and the second bootstrap output module 301 are both electrically connected to the first high voltage signal input terminal VGHH, and the pull-up maintaining module 600 is electrically connected to the second high voltage signal input terminal VGH.
  • the high voltage signal input by the first high voltage signal input terminal VGHH is output by the first bootstrap output module 201 to form the high voltage part of the first driving signal; the high voltage signal input by the first high voltage signal input terminal VGHH is output by the second self-driving signal.
  • the output of the output module 301 is lifted to form the high voltage part of the second driving signal.
  • the high-voltage signal input from the second high-voltage signal input terminal VGH is output by the pull-up maintaining module 600 to pull up the potentials of the control terminals of the first pull-down maintaining module 202 and the second pull-down maintaining module 302 .
  • the voltage input by the first high voltage signal input terminal VGHH is greater than the voltage input by the second high voltage signal input terminal VGH.
  • the embodiment of the present application adopts two kinds of high-voltage signal input terminals. On the one hand, it can ensure that the first bootstrap output module 201 and the second bootstrap output module 301 output a drive signal with a higher potential, which is beneficial to the display device.
  • the potential of the control terminals of the first pull-down maintaining module 202 and the second pull-down maintaining module 302 can be kept at a relatively low high voltage level, reducing the voltage stress of the internal nodes, which is beneficial to enhance the stability of the circuit sex.
  • the staging unit 100 is electrically connected to the second high-voltage signal input terminal VGH, the staging signal input terminal STI, the first clock signal input terminal CLK1, the second clock signal input terminal CLK2, the low-voltage signal input terminal VGL, and the staging signal input terminal VGL.
  • the output terminal STO and the first node Q1, the staging signal output terminal STO is used for outputting the staging signal
  • the staging signal input terminal STI is used for inputting the staging signal output by the gate driving unit of the previous stage
  • the first clock signal The input terminal CLK1 and the second clock signal input terminal are respectively used for inputting two kinds of clock signals
  • the low voltage signal input terminal VGL is used for inputting the low voltage signal.
  • the first transfer module 400 is electrically connected to the first node Q1, the first clock signal input terminal CLK1 and the third node Q3.
  • the third node Q3 corresponds to the control terminal of the first bootstrap output module 201 .
  • the first transfer module 400 is configured to transfer the signal input from the first clock signal input terminal CLK1 to the third node Q3 under the potential control of the first node Q1 , so as to regulate the function of the first bootstrap output module 201 .
  • the second transfer module 500 is electrically connected to the first node Q1, the first clock signal input terminal CLK1 and the fourth node Q4.
  • the fourth node Q4 corresponds to the control terminal of the second bootstrap output module 301 .
  • the second transfer module 500 is used for transferring the signal input from the first clock signal input terminal CLK1 to the fourth node Q4 under the potential control of the first node Q1 , so as to regulate the function of the second bootstrap output module 301 .
  • the pull-up maintaining module 600 is electrically connected to the second clock signal input terminal CLK2, the second high voltage signal input terminal VGH and the second node Q2.
  • the second node Q2 corresponds to the control terminals of the first pull-down maintaining module 202 and the second pull-down maintaining module 302 .
  • the pull-up maintaining module 600 is configured to transmit the signal input from the second high voltage signal input terminal VGH to the second node Q2 under the control of the signal input from the second clock signal input terminal CLK2.
  • the pull-down module 700 is electrically connected to the first node Q1, the low-voltage signal input terminal VGL and the second node Q2, and is used for transmitting the voltage signal input from the low-voltage signal input terminal VGL to the second node Q2 under the potential control of the first node Q1. , thereby reducing the potential of the second node Q2.
  • the first bootstrap output module 201 is electrically connected to the third node Q3, the first high voltage signal input terminal VGHH, the second high voltage signal input terminal VGH and the first driving signal output terminal G1, and the first driving signal output terminal G1 is used for outputting all the the first drive signal. Under the potential control of the third node Q3, the voltage signal input by the first high voltage signal input terminal VGHH can be output through the first driving signal output terminal G1.
  • the first pull-down maintaining module 202 is electrically connected to the second node Q2, the third node Q3 and the first control signal input terminal LCA.
  • the first pull-down maintaining module 202 is configured to transmit the signal input from the first control signal input terminal LCA to the third node Q3 under the potential control of the second node Q2.
  • the second bootstrap output module 301 is electrically connected to the fourth node Q4, the first high voltage signal input terminal VGHH, the second high voltage signal input terminal VGH and the second driving signal output terminal G2, and the second driving signal output terminal G2 is used for outputting all the the second driving signal. Under the potential control of the fourth node Q4, the voltage signal input by the first high voltage signal input terminal VGHH can be output through the second driving signal output terminal G2.
  • the second pull-down maintaining module 302 is electrically connected to the second node Q2, the fourth node Q4 and the second control signal input terminal LCB.
  • the second pull-down maintaining module 302 is configured to transmit the signal input from the second control signal input terminal LCB to the fourth node Q4 under the potential control of the second node Q2.
  • the staging unit 100 includes a first transistor T1, a second transistor T2, a third transistor T3 and a fourth transistor T4, and the gate, source and drain of the first transistor T1 are respectively electrically connected to the staging signal.
  • the input end STI, the second high voltage signal input end VGH and the first node Q1, the gate, source and drain of the second transistor T2 are respectively electrically connected to the first node Q1, the first clock signal input end CLK1 and the staging signal
  • the output terminal STO, the gate, source and drain of the third transistor T3 are respectively electrically connected to the second clock signal input terminal CLK2, the low voltage signal input terminal VGL and the staging signal output terminal STO, the gate of the fourth transistor T4,
  • the source electrode and the drain electrode are respectively electrically connected to the second clock signal input terminal CLK2, the low voltage signal input terminal VGL and the first node Q1.
  • the first transfer module 400 includes a fifth transistor T5 and a first capacitor C1, and the gate, source and drain of the fifth transistor T5 are electrically connected to the first node Q1, the first clock signal input terminal CLK1 and the third respectively.
  • the two poles of the first capacitor C1 are electrically connected to the first node Q1 and the third node Q3 respectively.
  • the second transfer module 500 includes a sixth transistor T6 and a second capacitor C2.
  • the gate, source and drain of the sixth transistor T6 are electrically connected to the first node Q1, the first clock signal input terminal CLK1 and the fourth node Q4, respectively.
  • the two poles of the second capacitor C2 are electrically connected to the first node Q1 and the fourth node Q4 respectively.
  • the pull-up maintaining module 600 includes a seventh transistor T7 and a third capacitor C3.
  • the gate, source and drain of the seventh transistor T7 are respectively electrically connected to the second clock signal input terminal CLK2, the second high voltage signal input terminal VGH and the third Two nodes Q2, two poles of the third capacitor C3 are respectively electrically connected to the second node Q2 and the low voltage signal input terminal VGL.
  • the pull-down module 700 includes an eighth transistor T8, and the gate, source and drain of the eighth transistor T8 are electrically connected to the first node Q1, the low-voltage signal input terminal VGL and the second node Q2, respectively.
  • the first bootstrap output module 201 includes a ninth transistor T9, a tenth transistor T10 and a fourth capacitor C4.
  • the gate, source and drain of the ninth transistor T9 are respectively electrically connected to the second high-voltage signal input terminal VGH, the third The node Q3 and the fifth node Q5, the gate, source and drain of the tenth transistor T10 are respectively electrically connected to the fifth node Q5, the first high voltage signal input terminal VGHH and the first driving signal output terminal G1, and the fourth capacitor C4
  • the two poles of the terminal are electrically connected to the fifth node Q5 and the first driving signal output terminal G1 respectively.
  • the first pull-down maintaining module 202 includes an eleventh transistor T11 and a twelfth transistor T12.
  • the gate, source and drain of the eleventh transistor T11 are electrically connected to the second node Q2 and the first control signal input terminal LCA, respectively.
  • the third node Q3, the gate, source and drain of the twelfth transistor T12 are respectively electrically connected to the second node Q2, the first control signal input end LCA and the first drive signal output end G1.
  • the second bootstrap output module 301 includes a thirteenth transistor T13, a fourteenth transistor T14 and a fifth capacitor C5.
  • the gate, source and drain of the thirteenth transistor T13 are respectively electrically connected to the second high voltage signal input terminal VGH
  • the gate, source and drain of the fourteenth transistor T14 are respectively electrically connected to the sixth node Q6, the first high voltage signal input terminal VGHH and the second driving signal output terminal G2
  • Two poles of the fifth capacitor C5 are electrically connected to the sixth node Q6 and the second driving signal output terminal G2 respectively.
  • the second pull-down maintaining module 302 includes a fifteenth transistor T15 and a sixteenth transistor T16.
  • the gate, source and drain of the fifteenth transistor T15 are respectively electrically connected to the second node Q2, the second control signal input terminal LCB and At the fourth node Q4, the gate, source and drain of the sixteenth transistor T16 are respectively electrically connected to the second node Q2, the second control signal input end LCB and the second driving signal output end G2.
  • the gate driving circuit provided by the embodiments of the present application includes a plurality of the gate driving units, and a cascade relationship exists between the plurality of gate driving units.
  • FIG. 2 is a schematic diagram of a cascade relationship of gate driving units provided by an embodiment of the present application. The following description will be given by taking any three adjacent gate driving units U(n-1), U(n) and U(n+1) as an example, where n is an integer greater than or equal to 2.
  • the staging signal input terminal STI of the nth stage gate driving unit U(n) is electrically connected to the staging signal output terminal STO of the n-1st stage gate driving unit U(n-1), and the nth stage gate driving unit U(n-1) is electrically connected to the staging signal output terminal STO.
  • the staging signal output terminal STO of the unit U(n) is electrically connected to the staging signal input terminal STI of the n+1 th gate driving unit U(n+1).
  • the n-1th stage gate driving unit U(n-1) transmits the stage transmission signal ST(n-1) to the nth stage gate driving unit U(n), and the nth stage gate driving unit U(n) sends
  • the gate driving unit U(n+1) of the n+1st stage transmits the stage transfer signal ST(n).
  • the first driving signal output terminal G1 and the second driving signal output terminal G2 of the n-1 stage gate driving unit U(n-1) output the first driving signal G1(n-1) and the second driving signal G2( n-1);
  • the first driving signal output terminal G1 and the second driving signal output terminal G2 of the n-th gate driving unit U(n) output the first driving signal G1(n) and the second driving signal G2(n) respectively );
  • the first drive signal output end G1 and the second drive signal output end G2 of the n+1 stage gate drive unit U(n+1) output the first drive signal G1(n+1) and the second drive signal respectively G2(n+1).
  • the gate driving circuit provides clock signals through the first clock signal line CK1, the second clock signal line CK2 and the third clock signal line CK3 respectively, and the k+3ith stage of the gate driving unit
  • a clock signal input terminal CLK1 and a second clock signal input terminal CLK2 are respectively electrically connected to the first clock signal line CK1 and the second clock signal line CK2;
  • the input terminal CLK1 and the second clock signal input terminal CLK2 are respectively electrically connected to the second clock signal line CK2 and the third clock signal line CK3;
  • the first clock signal input terminal CLK1 of the gate driving unit of the k+3i+2 stage and the second clock signal input terminal CLK2 are respectively electrically connected to the third clock signal line CK3 and the first clock signal line CK1, wherein k is an integer greater than or equal to 1, and i is an integer greater than or equal to 0.
  • connection feature between the gate driving unit and the clock signal line is that the adjacent three gate driving units form a cycle.
  • the first clock signal input terminal CLK1 and the second clock signal input terminal CLK2 of the n-1 stage gate driving unit U(n-1) are electrically connected to the first clock signal line CK1 and the second clock signal line CK1 and the second clock signal line CK1 respectively.
  • a clock signal line CK2; the first clock signal input terminal CLK1 and the second clock signal input terminal CLK2 of the nth stage gate driving unit U(n) are electrically connected to the second clock signal line CK2 and the third clock signal line CK3 respectively;
  • the first clock signal input terminal CLK1 and the second clock signal input terminal CLK2 of the n+1 stage gate driving unit U(n+1) are electrically connected to the third clock signal line CK3 and the first clock signal line CK1 respectively.
  • the gate driving circuit can also provide clock signals through six clock signal lines, which can be freely selected according to actual needs without limitation.
  • the gate driving circuit provided by the embodiment of the present application can have two driving signal output modes, the first is that the outputted first driving signal is a waveform signal, and the outputted second driving signal is a constant-high voltage signal; The second type is that the outputted first driving signal is a constant-high voltage signal, while the outputted second driving signal is a waveform signal.
  • the input/output timing sequence of the gate driving circuit provided by the embodiments of the present application is analyzed below with reference to FIG. 1 to FIG. 4 .
  • transistors used in the gate driving circuit are described below by taking n-type transistors as an example, but it does not exclude the use of other types of transistors in this application; A transistor turns on when its gate is at a high voltage and turns off when its gate is at a low voltage.
  • FIG. 3 is an input/output timing diagram of the first output mode of the gate drive circuit provided by the embodiment of the present application.
  • the n-th gate driving unit U(n) is taken as an example for description.
  • both the first control signal input terminal LCA and the low voltage signal input terminal VGL input the low voltage signal V0
  • the second control signal input terminal LCB and the second high voltage signal input terminal VGH both input the first high voltage signal V1, the first high voltage signal input terminal VGHH inputs the second high voltage signal V2, and V2 is greater than V1.
  • the second node Q2 Before the time period t1, the second node Q2 is kept at a high level under the action of the pull-up maintaining module 600, the second control signal input terminal LCB charges the second capacitor C2 and the fifth capacitor C5 through the second pull-down maintaining module 302, and The potential of the sixth node Q6 is raised, the fourteenth transistor T14 is turned on, and the second high voltage signal V2 input from the first high voltage signal input terminal VGHH is output through the second driving signal output terminal G2(n); and at t1 and t2 During the time period, the second capacitor C2 continues to maintain the high potential state of the sixth node Q6, so that the second driving signal output terminal G2(n) outputs a constant high voltage signal.
  • the first control signal input terminal always inputs the low voltage signal V0, so no matter how the potential of the second node Q2 changes, the first pull-down maintaining module 202 will not affect the first bootstrap output module 201 The output state is affected.
  • ST(n-1) is at a high potential
  • the first transistor T1 is turned on, the potential of the first node Q1 is raised, the fifth transistor T5 is turned on, and the second clock signal line CK2 is at a low potential, so
  • the third node Q3 and the fifth node Q5 are at low potential
  • the tenth transistor T10 is turned off, the first driving signal output terminal G1(n) outputs a low voltage; the second transistor T2 is turned on, and the staging signal output terminal STO outputs a low voltage
  • the first capacitor C1 keeps the fifth transistor T5 turned on, the second clock signal line CK2 is at a high potential, and the potentials of the third node Q3 and the fifth node Q5 are raised; under the action of the first capacitor C1 , the potential of the first node Q1 is further raised; the tenth transistor T10 is turned on, the first driving signal output terminal G1(n) outputs the second high voltage V2; the second transistor T2 is turned on, and the staging signal output terminal STO outputs a high voltage The voltage level transfer signal ST(n).
  • FIG. 4 is an input/output timing diagram of the second output mode of the gate drive circuit provided by the embodiment of the present application.
  • the n-th gate driving unit U(n) is taken as an example for description.
  • both the second control signal input terminal LCB and the low voltage signal input terminal VGL input the low voltage signal V0
  • the first control signal input terminal LCA and the second high voltage signal input terminal VGH both input the first high voltage signal V1
  • the first high voltage signal input terminal VGHH inputs the second high voltage signal V2, and V2 is greater than V1.
  • the second node Q2 Before the time period t1, the second node Q2 maintains a high potential under the action of the pull-up maintaining module 600, and the first control signal input terminal LCA charges the first capacitor C1 and the fourth capacitor C4 through the first pull-down maintaining module 202, and raise the potential of the fifth node Q5, the tenth transistor T10 is turned on, and the second high voltage signal V2 input from the first high voltage signal input terminal VGHH is output through the first driving signal output terminal G1(n); and at t1 and t2 During the time period, the first capacitor C1 continues to maintain the high potential state of the fifth node Q5, so that the first driving signal output terminal G1(n) outputs a constant high voltage signal.
  • the second control signal input terminal always inputs the low voltage signal V0, so no matter how the potential of the second node Q2 changes, the second pull-down maintaining module 302 will not affect the output of the second bootstrap output module 301.
  • the output state has an effect.
  • ST(n-1) is at a high potential
  • the first transistor T1 is turned on, the potential of the first node Q1 is raised, the fifth transistor T5 is turned on, and the second clock signal line CK2 is at a low potential, so
  • the fourth node Q4 and the sixth node Q6 are at low potential
  • the fourteenth transistor T14 is turned off, the second driving signal output terminal G2(n) outputs a low voltage; the second transistor T2 is turned on, and the staging signal output terminal STO outputs a low voltage
  • the second capacitor C2 keeps the sixth transistor T6 turned on, the second clock signal line CK2 is at a high potential, and the potentials of the fourth node Q4 and the sixth node Q6 are raised; under the action of the second capacitor C2 , the potential of the first node Q1 is further raised; the fourteenth transistor T14 is turned on, the second driving signal output terminal G2(n) outputs the second high voltage V2; the second transistor T2 is turned on, and the staging signal output terminal STO outputs High voltage stage transfer signal ST(n).
  • the gate drive circuit provided by the embodiments of the present application includes multi-stage gate drive units, and each stage of the gate drive unit includes two drive signal output units and one stage transmission signal output unit, wherein two Each driving signal output unit can output constant-high voltage signal and waveform signal alternately, so as to output two driving signals simultaneously through one gate driving circuit, compared with the prior art, which output two driving signals through two sets of gate driving circuits
  • the design of the invention reduces the number of clock signal lines and the number of thin film transistors used in the gate driving circuit, which is beneficial to realize the narrow frame of the display device.
  • the embodiment of the present application further provides a display device, the display device includes the gate driving circuit provided by the embodiment of the present application, and the display device is easy to realize a narrow frame.

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Abstract

提供一种栅极驱动电路及显示装置，栅极驱动电路包括多级栅极驱动单元，每一级栅极驱动单元均包括两个驱动信号输出单元和一个级传信号输出单元，其中两个驱动信号输出单元可交替输出恒高电压信号和波形信号，从而实现通过一个栅极驱动电路同时输出两种驱动信号，应用于显示装置中，有利于实现显示装置的窄边框化。

Description

栅极驱动电路及显示装置
本申请要求于2020年08月31日提交中国专利局、申请号为202010897065.6、发明名称为“栅极驱动电路及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，尤其涉及一种栅极驱动电路及显示装置。
 背景技术
目前，显示装置作为电子设备的显示部件已经广泛应用于各种电子产品中，而GOA电路则是显示装置中的一个重要组成部分。GOA (Gate Driver on Array)技术，即阵列基板行扫描驱动技术，是将栅极行扫描驱动电路直接制作在阵列基板上，实现栅极逐行扫描的驱动方式的技术。GOA技术的应用有利于实现显示装置的窄边框设计，因此，其在显示技术领域的应用越来越广泛。
随着显示技术的发展，GOA电路的应用类型也出现多样化。在低温多晶硅氧化物基的显示装置动态帧频显示技术中，为了解决与驱动晶体管相连的金属氧化物晶体管在工作中电位负向漂移引起驱动晶体管栅极漏电而导致低频显示失效的问题，会将与驱动晶体管栅极直接相连的金属氧化物晶体管增设为两套，并使其交替工作；此时就需要GOA电路同时提供两种栅极驱动信号分别作用到这两套金属氧化物晶体管上，以实现其交替工作。现有技术采用两组GOA电路完成上述功能，这种设计会导致该GOA电路中的时钟线数量和薄膜晶体管数量均成倍增加，不利于实现显示装置的窄边框化；并且时钟线数量的增多也容易出现驱动芯片支持性差的问题。
 技术问题
现有技术为实现栅极驱动电路可同时输出两种驱动信号，会设计两组GOA电路，但这种设计会导致栅极驱动电路中的时钟线数量和薄膜晶体管数量均成倍增加，不利于实现显示装置的窄边框化；并且时钟线数量的增多也容易出现驱动芯片支持性差的问题。
 技术解决方案
为了解决上述技术问题，本申请提供的解决方案如下：
本申请提供一种栅极驱动电路，包括多个栅极驱动单元，每个所述栅极驱动单元包括：
级传单元，用于输出级传信号；
第一输出单元，用于输出第一驱动信号；以及
第二输出单元，用于输出第二驱动信号；
其中，所述第一驱动信号为波形信号，所述第二驱动信号为恒高电压信号；或者，所述第一驱动信号为恒高电压信号，所述第二驱动信号为波形信号。
在本申请的栅极驱动电路中，所述第一输出单元包括第一自举输出模块和第一下拉维持模块，所述第一自举输出模块用于上拉所述第一输出单元的输出电位，所述第一下拉维持模块用于下拉并维持所述第一输出单元的输出电位。
在本申请的栅极驱动电路中，所述第一自举输出模块与所述第一下拉维持模块电性连接，所述第一下拉维持模块控制所述第一自举输出模块输出恒高电压的所述第一驱动信号。
在本申请的栅极驱动电路中，所述第二输出单元包括第二自举输出模块和第二下拉维持模块，所述第二自举输出模块用于上拉所述第二输出单元的输出电位，所述第二下拉维持模块用于下拉并维持所述第二输出单元的输出电位。
在本申请的栅极驱动电路中，所述第二自举输出模块与所述第二下拉维持模块电性连接，所述第二下拉维持模块控制所述第二自举输出模块输出恒高电压的所述第二驱动信号。
在本申请的栅极驱动电路中，每个所述栅极驱动单元还包括：
第一传递模块，电性连接于所述级传单元与所述第一自举输出模块之间，用于向所述第一自举输出模块传递输出控制信号；
第二传递模块，电性连接于所述级传单元与所述第二自举输出模块之间，用于向所述第二自举输出模块传递输出控制信号。
根据本申请一实施例，每个所述栅极驱动单元还包括：
上拉维持模块，分别与所述第一下拉维持模块和所述第二下拉维持模块电性连接，用于上拉并维持所述第一下拉维持模块和所述第二下拉维持模块的控制端电位；
下拉模块，分别与所述第一下拉维持模块和所述第二下拉维持模块电性连接，用于下拉所述第一下拉维持模块和所述第二下拉维持模块的控制端电位。
在本申请的栅极驱动电路中，所述第一下拉维持模块电性连接第一控制信号输入端，所述第二下拉维持模块电性连接第二控制信号输入端。
在本申请的栅极驱动电路中，所述第一控制信号输入端向所述第一下拉维持模块输入低电压信号，所述第二控制信号输入端向所述第二下拉维持模块输入高电压信号，所述第一驱动信号为波形信号，所述第二驱动信号为恒高电压信号。
在本申请的栅极驱动电路中，所述第一控制信号输入端向所述第一下拉维持模块输入高电压信号，所述第二控制信号输入端向所述第二下拉维持模块输入低电压信号，所述第一驱动信号为恒高电压信号，所述第二驱动信号为波形信号。
在本申请的栅极驱动电路中，所述第一自举输出模块和所述第二自举输出模块均电性连接第一高压信号输入端，所述上拉维持模块电性连接第二高压信号输入端；
所述第一高压信号输入端输入的电压大于所述第二高压信号输入端输入的电压。
在本申请的栅极驱动电路中，所述级传单元电性连接所述第二高压信号输入端、级传信号输入端、第一时钟信号输入端、第二时钟信号输入端、低压信号输入端、级传信号输出端和第一节点，所述级传信号输出端用于输出所述级传信号；
所述第一传递模块电性连接所述第一节点、所述第一时钟信号输入端和第三节点；
所述第二传递模块电性连接所述第一节点、所述第一时钟信号输入端和第四节点；
所述上拉维持模块电性连接所述第二时钟信号输入端、所述第二高压信号输入端和第二节点；
所述下拉模块电性连接所述第一节点、所述低压信号输入端和所述第二节点；
所述第一自举输出模块电性连接所述第三节点、所述第一高压信号输入端、所述第二高压信号输入端和第一驱动信号输出端，所述第一驱动信号输出端用于输出所述第一驱动信号；
所述第一下拉维持模块电性连接所述第二节点、所述第三节点和所述第一控制信号输入端；
所述第二自举输出模块电性连接所述第四节点、所述第一高压信号输入端、所述第二高压信号输入端和第二驱动信号输出端，所述第二驱动信号输出端用于输出所述第二驱动信号；
所述第二下拉维持模块电性连接所述第二节点、所述第四节点和所述第二控制信号输入端。
在本申请的栅极驱动电路中，所述级传单元包括第一晶体管、第二晶体管、第三晶体管和第四晶体管，所述第一晶体管的栅极、源极和漏极分别电性连接所述级传信号输入端、所述第二高压信号输入端和所述第一节点，所述第二晶体管的栅极、源极和漏极分别电性连接所述第一节点、所述第一时钟信号输入端和所述级传信号输出端，所述第三晶体管的栅极、源极和漏极分别电性连接所述第二时钟信号输入端、所述低压信号输入端和所述级传信号输出端，所述第四晶体管的栅极、源极和漏极分别电性连接所述第二时钟信号输入端、所述低压信号输入端和所述第一节点；
所述第一传递模块包括第五晶体管和第一电容，所述第五晶体管的栅极、源极和漏极分别电性连接所述第一节点、所述第一时钟信号输入端和所述第三节点，所述第一电容的两极分别电性连接所述第一节点和所述第三节点；
所述第二传递模块包括第六晶体管和第二电容，所述第六晶体管的栅极、源极和漏极分别电性连接所述第一节点、所述第一时钟信号输入端和所述第四节点，所述第二电容的两极分别电性连接所述第一节点和所述第四节点；
所述上拉维持模块包括第七晶体管和第三电容，所述第七晶体管的栅极、源极和漏极分别电性连接所述第二时钟信号输入端、所述第二高压信号输入端和所述第二节点，所述第三电容的两极分别电性连接所述第二节点和所述低压信号输入端；
所述下拉模块包括第八晶体管，所述第八晶体管的栅极、源极和漏极分别电性连接所述第一节点、所述低压信号输入端和所述第二节点；
所述第一自举输出模块包括第九晶体管、第十晶体管和第四电容，所述第九晶体管的栅极、源极和漏极分别电性连接所述第二高压信号输入端、所述第三节点和第五节点，所述第十晶体管的栅极、源极和漏极分别电性连接所述第五节点、所述第一高压信号输入端和所述第一驱动信号输出端，所述第四电容的两极分别电性连接所述第五节点和所述第一驱动信号输出端；
所述第一下拉维持模块包括第十一晶体管和第十二晶体管，所述第十一晶体管的栅极、源极和漏极分别电性连接所述第二节点、所述第一控制信号输入端和所述第三节点，所述第十二晶体管的栅极、源极和漏极分别电性连接所述第二节点、所述第一控制信号输入端和所述第一驱动信号输出端；
所述第二自举输出模块包括第十三晶体管、第十四晶体管和第五电容，所述第十三晶体管的栅极、源极和漏极分别电性连接所述第二高压信号输入端、所述第四节点和第六节点，所述第十四晶体管的栅极、源极和漏极分别电性连接所述第六节点、所述第一高压信号输入端和所述第二驱动信号输出端，所述第五电容的两极分别电性连接所述第六节点和所述第二驱动信号输出端；
所述第二下拉维持模块包括第十五晶体管和第十六晶体管，所述第十五晶体管的栅极、源极和漏极分别电性连接所述第二节点、所述第二控制信号输入端和所述第四节点，所述第十六晶体管的栅极、源极和漏极分别电性连接所述第二节点、所述第二控制信号输入端和所述第二驱动信号输出端。
在本申请的栅极驱动电路中，多个所述栅极驱动单元存在以下级联关系：本级所述栅极驱动单元的所述级传信号输入端电性连接上一级所述栅极驱动单元的所述级传信号输出端。
在本申请的栅极驱动电路中，所述栅极驱动电路分别通过第一时钟信号线、第二时钟信号线和第三时钟信号线提供时钟信号，
第k+3i级所述栅极驱动单元的所述第一时钟信号输入端和所述第二时钟信号输入端分别电性连接所述第一时钟信号线和所述第二时钟信号线；
第k+3i+1级所述栅极驱动单元的所述第一时钟信号输入端和所述第二时钟信号输入端分别电性连接所述第二时钟信号线和所述第三时钟信号线；
第k+3i+2级所述栅极驱动单元的所述第一时钟信号输入端和所述第二时钟信号输入端分别电性连接所述第三时钟信号线和所述第一时钟信号线；
其中，k为大于或等于1的整数，i为大于或等于0的整数。
本申请还提供一种显示装置，包括栅极驱动电路，所述栅极驱动电路包括多个栅极驱动单元，每个所述栅极驱动单元包括：
级传单元，用于输出级传信号；
第一输出单元，用于输出第一驱动信号；以及
第二输出单元，用于输出第二驱动信号；
其中，所述第一驱动信号为波形信号，所述第二驱动信号为恒高电压信号；或者，所述第一驱动信号为恒高电压信号，所述第二驱动信号为波形信号。
在本申请的显示装置中，所述第一输出单元包括第一自举输出模块和第一下拉维持模块，所述第一自举输出模块用于上拉所述第一输出单元的输出电位，所述第一下拉维持模块用于下拉并维持所述第一输出单元的输出电位；所述第一自举输出模块与所述第一下拉维持模块电性连接，所述第一下拉维持模块控制所述第一自举输出模块输出恒高电压的所述第一驱动信号。
在本申请的显示装置中，所述第二输出单元包括第二自举输出模块和第二下拉维持模块，所述第二自举输出模块用于上拉所述第二输出单元的输出电位，所述第二下拉维持模块用于下拉并维持所述第二输出单元的输出电位；所述第二自举输出模块与所述第二下拉维持模块电性连接，所述第二下拉维持模块控制所述第二自举输出模块输出恒高电压的所述第二驱动信号。
在本申请的显示装置中，每个所述栅极驱动单元还包括：
第一传递模块，电性连接于所述级传单元与所述第一自举输出模块之间，用于向所述第一自举输出模块传递输出控制信号；
第二传递模块，电性连接于所述级传单元与所述第二自举输出模块之间，用于向所述第二自举输出模块传递输出控制信号；
上拉维持模块，分别与所述第一下拉维持模块和所述第二下拉维持模块电性连接，用于上拉并维持所述第一下拉维持模块和所述第二下拉维持模块的控制端电位；
下拉模块，分别与所述第一下拉维持模块和所述第二下拉维持模块电性连接，用于下拉所述第一下拉维持模块和所述第二下拉维持模块的控制端电位；
其中，所述第一下拉维持模块电性连接第一控制信号输入端，所述第二下拉维持模块电性连接第二控制信号输入端。
在本申请的显示装置中，所述第一控制信号输入端向所述第一下拉维持模块输入低电压信号，所述第二控制信号输入端向所述第二下拉维持模块输入高电压信号，所述第一驱动信号为波形信号，所述第二驱动信号为恒高电压信号；
或者，所述第一控制信号输入端向所述第一下拉维持模块输入高电压信号，所述第二控制信号输入端向所述第二下拉维持模块输入低电压信号，所述第一驱动信号为恒高电压信号，所述第二驱动信号为波形信号。
 有益效果
本申请提供的栅极驱动电路的每一级栅极驱动单元均包括两个驱动信号输出单元，可交替输出恒高电压信号和波形信号，实现了通过一个栅极驱动电路同时输出两种驱动信号设计，相较于现有技术通过两组栅极驱动电路来输出两种驱动信号的设计，减少了时钟信号线数量和薄膜晶体管数量，应用于显示装置中，有利于实现显示装置的窄边框化。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的栅极驱动电路中的栅极驱动单元的电路结构示意图；
图2是本申请实施例提供的栅极驱动单元的级联关系示意图；
图3是本申请实施例提供的栅极驱动电路的第一种输出方式的输入/输出时序图；
图4是本申请实施例提供的栅极驱动电路的第二种输出方式的输入/输出时序图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。
本申请实施例提供一种栅极驱动电路，所述栅极驱动电路包括多级栅极驱动单元，每一级所述栅极驱动单元均包括两个驱动信号输出单元和一个级传信号输出单元，其中两个驱动信号输出单元可交替输出恒高电压信号和波形信号，从而实现通过一个栅极驱动电路同时输出两种驱动信号，相较于现有技术通过两组栅极驱动电路来输出两种驱动信号的设计，减少了栅极驱动电路中使用的时钟信号线数量和薄膜晶体管数量，有利于实现显示装置的窄边框化。
图1是本申请实施例提供的栅极驱动电路中的栅极驱动单元的电路结构示意图。所述栅极驱动电路包括多个栅极驱动单元，所述栅极驱动单元之间存在电性连接关系，具体为多个所述栅极驱动单元之间依次级联，形成多级驱动单元。应当理解的是，所述栅极驱动电路应用于显示装置中，用于为显示装置的各显示单元的像素电路提供栅极驱动信号，保证各显示单元的正常功能。
所述栅极驱动单元包括级传单元100、第一输出单元200和第二输出单元300。其中，级传单元100用于输出级传信号，所述级传信号为在相邻所述栅极驱动单元之间的传递的控制信号或反馈信号；第一输出单元200用于输出第一驱动信号，第二输出单元300用于输出第二驱动信号，所述第一驱动信号和所述第二驱动信号作用于显示装置的各显示单元的像素电路中，并调控所述像素电路的功能。
可选地，第一输出单元200输出的所述第一驱动信号为波形信号，且第二输出单元300输出的所述第二驱动信号为恒高电压信号；或者，第一输出单元200输出的所述第一驱动信号为恒高电压信号，且第二输出单元300输出的所述第二驱动信号为波形信号。应当理解的是，在本申请实施例中，一方面所述栅极驱动单元可通过第一输出单元200和第二输出单元300同时输出两种栅极驱动信号，满足显示装置中同时需要两种栅极驱动信号的需求，相较于现有技术，减少了栅极驱动电路中使用的时钟信号线数量和薄膜晶体管数量，有利于实现显示装置的窄边框化；另一方面第一输出单元200和第二输出单元300可交替输出这两种栅极驱动信号，增大了所述栅极驱动电路的应用范围，避免单一输出单元长时间输出同种信号而导致的元件疲劳和功能异常。
可选地，第一输出单元200包括第一自举输出模块201和第一下拉维持模块202。第一自举输出模块201用于上拉第一输出单元200的输出电位，即抬高所述第一驱动信号的电位；第一下拉维持模块202用于下拉并维持第一输出单元200的输出电位，即降低所述第一驱动信号的电位，并将所述第一驱动信号的电位维持在较低水平。应当理解的是，在第一自举输出单元201和第一下拉维持单元202的共同作用下，第一输出单元200可输出波形信号。
可选地，第二输出单元300包括第二自举输出模块301和第二下拉维持模块302。第二自举输出模块301用于上拉第二输出单元300的输出电位，即抬高所述第二驱动信号的电位；第二下拉维持模块302用于下拉并维持第二输出单元300的输出电位，即降低所述第二驱动信号的电位，并将所述第二驱动信号的电位维持在较低水平。应当理解的是，在第二自举输出单元301和第二下拉维持单元302的共同作用下，第二输出单元300可输出波形信号。
进一步地，第一自举输出模块201与第一下拉维持模块202电性连接，第一下拉维持模块202可控制第一自举输出模块201较长时间上拉第一输出单元200的输出电位，使所述第一驱动信号保持为恒高电压信号；第二自举输出模块301与第二下拉维持模块302电性连接，第二下拉维持模块302可控制第二自举输出模块301较长时间上拉第二输出单元300的输出电位，使所述第二驱动信号保持为恒高电压信号。应当理解的是，通过第一下拉维持模块202和第二下拉维持模块302的调控，可实现第一输出单元200和第二输出单元300交替输出恒高电压信号。
可选地，每个所述栅极驱动单元还包括第一传递模块400、第二传递模块500、上拉维持模块600和下拉模块700。第一传递模块400电性连接于级传单元100与第一输出单元200之间；具体地，第一传递模块400电性连接第一输出单元200的第一自举输出模块201；第一传递模块400用于在级传单元100输出的信号控制下向第一自举输出模块201传递输出控制信号，以控制第一自举输出模块201是否输出高电压信号。第二传递模块500电性连接于级传单元100与第二输出单元300之间；具体地，第二传递模块500电性连接第二输出单元300的第二自举输出模块301；第二传递模块500用于在级传单元100输出的信号控制下向第二自举输出模块301传递输出控制信号，以控制第二自举输出模块301是否输出高电压信号。上拉维持模块600分别与第一下拉维持模块202和第二下拉维持模块302电性连接，用于上拉并维持第一下拉维持模块202和第二下拉维持模块302的控制端电位，进而控制第一下拉维持模块202和第二下拉维持模块302的开启。下拉模块700分别与第一下拉维持模块202和第二下拉维持模块302电性连接，用于下拉第一下拉维持模块202和第二下拉维持模块302的控制端电位，进而控制第一下拉维持模块202和第二下拉维持模块302的关闭。
进一步地，第一下拉维持模块202电性连接第一控制信号输入端LCA，第一控制信号输入端LCA向第一下拉维持模块202输入控制信号，第一下拉维持模块202进一步将该控制信号传递至第一自举输出模块201，进而控制第一自举输出模块201是否输出高电压信号。可选地，第一控制信号输入端LCA向第一下拉维持模块202输入低电压信号时，所述第一驱动信号为波形信号；第一控制信号输入端LCA向第一下拉维持模块202输入高电压信号时，所述第一驱动信号为恒高电压信号。
第二下拉维持模块302电性连接第二控制信号输入端LCB，第二控制信号输入端LCB向第二下拉维持模块302输入控制信号，第二下拉维持模块302进一步将该控制信号传递至第二自举输出模块301，进而控制第二自举输出模块301是否输出高电压信号。可选地，第二控制信号输入端LCB向第二下拉维持模块302输入高电压信号时，所述第二驱动信号为恒高电压信号；第二控制信号输入端LCB向第二下拉维持模块302输入低电压信号时，所述第二驱动信号为波形信号。
可选地，第一自举输出模块201和第二自举输出模块301均电性连接第一高压信号输入端VGHH，上拉维持模块600电性连接第二高压信号输入端VGH。第一高压信号输入端VGHH输入的高电压信号经第一自举输出模块201输出，形成所述第一驱动信号的高电压部分；第一高压信号输入端VGHH输入的高电压信号经第二自举输出模块301输出，形成所述第二驱动信号的高电压部分。第二高压信号输入端VGH输入的高电压信号经上拉维持模块600输出，以实现上拉第一下拉维持模块202和第二下拉维持模块302的控制端电位。其中，第一高压信号输入端VGHH输入的电压大于所述第二高压信号输入端VGH输入的电压。应当理解的是，本申请实施例采用两种高压信号输入端，一方面可以保证第一自举输出模块201和第二自举输出模块301输出较高电位的驱动信号，利于驱动信号在显示装置中的传导，另一方面可使第一下拉维持模块202和第二下拉维持模块302的控制端电位保持在相对较低的高电压水平，减小内部节点电压应力，有利于增强电路的稳定性。
进一步地，级传单元100电性连接第二高压信号输入端VGH、级传信号输入端STI、第一时钟信号输入端CLK1、第二时钟信号输入端CLK2、低压信号输入端VGL、级传信号输出端STO和第一节点Q1，级传信号输出端STO用于输出所述级传信号，级传信号输入端STI用于输入上一级栅极驱动单元输出的级传信号，第一时钟信号输入端CLK1和第二时钟信号输入端分别用于输入两种时钟信号，低压信号输入端VGL用于输入低电压信号。
第一传递模块400电性连接第一节点Q1、第一时钟信号输入端CLK1和第三节点Q3。第三节点Q3对应第一自举输出模块201的控制端。第一传递模块400用于在第一节点Q1的电位控制下，将第一时钟信号输入端CLK1输入的信号传递至第三节点Q3，进而调控第一自举输出模块201的功能。
第二传递模块500电性连接第一节点Q1、第一时钟信号输入端CLK1和第四节点Q4。第四节点Q4对应第二自举输出模块301的控制端。第二传递模块500用于在第一节点Q1的电位控制下，将第一时钟信号输入端CLK1输入的信号传递至第四节点Q4，进而调控第二自举输出模块301的功能。
上拉维持模块600电性连接第二时钟信号输入端CLK2、第二高压信号输入端VGH和第二节点Q2。第二节点Q2对应第一下拉维持模块202和第二下拉维持模块302的控制端。上拉维持模块600用于在第二时钟信号输入端CLK2输入的信号控制下，将第二高压信号输入端VGH输入的信号传递至第二节点Q2。
下拉模块700电性连接第一节点Q1、低压信号输入端VGL和第二节点Q2，用于在第一节点Q1的电位控制下，将低压信号输入端VGL输入的电压信号传递至第二节点Q2，从而使第二节点Q2的电位降低。
第一自举输出模块201电性连接第三节点Q3、第一高压信号输入端VGHH、第二高压信号输入端VGH和第一驱动信号输出端G1，第一驱动信号输出端G1用于输出所述第一驱动信号。在第三节点Q3的电位控制下，第一高压信号输入端VGHH输入的电压信号可通过第一驱动信号输出端G1输出。
第一下拉维持模块202电性连接第二节点  Q2、所述第三节点Q3和所述第一控制信号输入端LCA。第一下拉维持模块202用于在第二节点Q2的电位控制下，将第一控制信号输入端LCA输入的信号传递至第三节点Q3。
第二自举输出模块301电性连接第四节点Q4、第一高压信号输入端VGHH、第二高压信号输入端VGH和第二驱动信号输出端G2，第二驱动信号输出端G2用于输出所述第二驱动信号。在第四节点Q4的电位控制下，第一高压信号输入端VGHH输入的电压信号可通过第二驱动信号输出端G2输出。
第二下拉维持模块302电性连接第二节点  Q2、第四节点Q4和第二控制信号输入端LCB。第二下拉维持模块302用于在第二节点Q2的电位控制下，将第二控制信号输入端LCB输入的信号传递至第四节点Q4。
进一步可选地，级传单元100包括第一晶体管T1、第二晶体管T2、第三晶体管T3和第四晶体管T4，第一晶体管T1的栅极、源极和漏极分别电性连接级传信号输入端STI、第二高压信号输入端VGH和第一节点Q1，第二晶体管T2的栅极、源极和漏极分别电性连接第一节点Q1、第一时钟信号输入端CLK1和级传信号输出端STO，第三晶体管T3的栅极、源极和漏极分别电性连接第二时钟信号输入端CLK2、低压信号输入端VGL和级传信号输出端STO，第四晶体管T4的栅极、源极和漏极分别电性连接第二时钟信号输入端CLK2、低压信号输入端VGL和第一节点Q1。
第一传递模块400包括第五晶体管T5和第一电容C1，所述第五晶体管T5的栅极、源极和漏极分别电性连接第一节点Q1、第一时钟信号输入端CLK1和第三节点Q3，第一电容C1的两极分别电性连接第一节点Q1和第三节点Q3。
第二传递模块500包括第六晶体管T6和第二电容C2，第六晶体管T6的栅极、源极和漏极分别电性连接第一节点Q1、第一时钟信号输入端CLK1和第四节点Q4，第二电容C2的两极分别电性连接第一节点Q1和第四节点Q4。
上拉维持模块600包括第七晶体管T7和第三电容C3，第七晶体管T7的栅极、源极和漏极分别电性连接第二时钟信号输入端CLK2、第二高压信号输入端VGH和第二节点Q2，第三电容C3的两极分别电性连接第二节点Q2和低压信号输入端VGL。
下拉模块700包括第八晶体管T8，第八晶体管T8的栅极、源极和漏极分别电性连接第一节点Q1、低压信号输入端VGL和第二节点Q2。
第一自举输出模块201包括第九晶体管T9、第十晶体管T10和第四电容C4，第九晶体管T9的栅极、源极和漏极分别电性连接第二高压信号输入端VGH、第三节点Q3和第五节点Q5，第十晶体管T10的栅极、源极和漏极分别电性连接第五节点Q5、第一高压信号输入端VGHH和第一驱动信号输出端G1，第四电容C4的两极分别电性连接第五节点Q5和第一驱动信号输出端G1。
第一下拉维持模块202包括第十一晶体管T11和第十二晶体管T12，第十一晶体管T11的栅极、源极和漏极分别电性连接第二节点Q2、第一控制信号输入端LCA和第三节点Q3，第十二晶体管T12的栅极、源极和漏极分别电性连接第二节点Q2、第一控制信号输入端LCA和第一驱动信号输出端G1。
第二自举输出模块301包括第十三晶体管T13、第十四晶体管T14和第五电容C5，第十三晶体管T13的栅极、源极和漏极分别电性连接第二高压信号输入端VGH、第四节点Q4和第六节点Q6，第十四晶体管T14的栅极、源极和漏极分别电性连接第六节点Q6、第一高压信号输入端VGHH和第二驱动信号输出端G2，第五电容C5的两极分别电性连接第六节点Q6和第二驱动信号输出端G2。
第二下拉维持模块302包括第十五晶体管T15和第十六晶体管T16，第十五晶体管T15的栅极、源极和漏极分别电性连接第二节点Q2、第二控制信号输入端LCB和第四节点Q4，第十六晶体管T16的栅极、源极和漏极分别电性连接第二节点Q2、第二控制信号输入端LCB和第二驱动信号输出端G2。
本申请实施例提供的栅极驱动电路包括多个所述栅极驱动单元，所述多个栅极驱动单元之间存在级联关系。图2是本申请实施例提供的栅极驱动单元的级联关系示意图。下面以任意相邻三个所述栅极驱动单元U(n-1)、U(n)和U(n+1)为例进行说明，其中n为大于或等于2的整数。第n级栅极驱动单元U(n)的级传信号输入端STI电性连接第n-1级栅极驱动单元U(n-1)的级传信号输出端STO，第n级栅极驱动单元U(n)的级传信号输出端STO电性连接第n+1级栅极驱动单元U(n+1)的级传信号输入端STI。第n-1级栅极驱动单元U(n-1)向第n级栅极驱动单元U(n)传递级传信号ST(n-1)，第n级栅极驱动单元U(n)向第n+1级栅极驱动单元U(n+1)传递级传信号ST(n)。第n-1级栅极驱动单元U(n-1)的第一驱动信号输出端G1和第二驱动信号输出端G2分别输出第一驱动信号G1(n-1)和第二驱动信号G2(n-1)；第n级栅极驱动单元U(n)的第一驱动信号输出端G1和第二驱动信号输出端G2分别输出第一驱动信号G1(n)和第二驱动信号G2(n)；第n+1级栅极驱动单元U(n+1)的第一驱动信号输出端G1和第二驱动信号输出端G2分别输出第一驱动信号G1(n+1)和第二驱动信号G2(n+1)。
可选地，所述栅极驱动电路分别通过第一时钟信号线CK1、第二时钟信号线CK2和第三时钟信号线CK3提供时钟信号，并且第k+3i级所述栅极驱动单元的第一时钟信号输入端CLK1和第二时钟信号输入端CLK2分别电性连接第一时钟信号线CK1和第二时钟信号线CK2；第k+3i+1级所述栅极驱动单元的第一时钟信号输入端CLK1和第二时钟信号输入端CLK2分别电性连接第二时钟信号线CK2和第三时钟信号线CK3；第k+3i+2级所述栅极驱动单元的第一时钟信号输入端CLK1和第二时钟信号输入端CLK2分别电性连接第三时钟信号线CK3和第一时钟信号线CK1，其中，k为大于或等于1的整数，i为大于或等于0的整数。即：所述栅极驱动单元与时钟信号线之间的连接特征为相邻三个栅极驱动单元为一循环。以图2为例，第n-1级栅极驱动单元U(n-1)的第一时钟信号输入端CLK1和第二时钟信号输入端CLK2分别电性连接第一时钟信号线CK1和第二时钟信号线CK2；第n级栅极驱动单元U(n)的第一时钟信号输入端CLK1和第二时钟信号输入端CLK2分别电性连接第二时钟信号线CK2和第三时钟信号线CK3；第n+1级栅极驱动单元U(n+1)的第一时钟信号输入端CLK1和第二时钟信号输入端CLK2分别电性连接第三时钟信号线CK3和第一时钟信号线CK1。
可选地，所述栅极驱动电路还可以通过六条时钟信号线提供时钟信号，此处可以根据实际需求进行自由选择，不做限制。
本申请实施例提供的栅极驱动电路可存在两种驱动信号输出方式，第一种是输出的所述第一驱动信号为波形信号，同时输出的所述第二驱动信号为恒高电压信号；第二种是输出的所述第一驱动信号为恒高电压信号，同时输出的所述第二驱动信号为波形信号。下面结合图1至图4对本申请实施例提供的栅极驱动电路的输入/输出时序进行分析。
需要说明的是，为了便于理解，以下将所述栅极驱动电路中所使用的晶体管均以n型晶体管为例进行说明，但并不排除本申请中会使用其它类型的晶体管；其中，n型晶体管在其栅极为高电压时导通，在其栅极为低电压时断开。
图3是本申请实施例提供的栅极驱动电路的第一种输出方式的输入/输出时序图。参考图1至图3所示，并以第n级栅极驱动单元U(n)为例进行说明。在第一种输出方式下，第一控制信号输入端LCA和低压信号输入端VGL均输入低电压信号V0，第二控制信号输入端LCB和第二高压信号输入端VGH均输入第一高电压信号V1，第一高压信号输入端VGHH输入第二高电压信号V2，且V2大于V1。在t1时间段之前，第二节点Q2在上拉维持模块600的作用下保持高电位，第二控制信号输入端LCB通过第二下拉维持模块302对第二电容C2和第五电容C5充电，并升高第六节点Q6的电位，第十四晶体管T14导通，第一高压信号输入端VGHH输入的第二高电压信号V2通过第二驱动信号输出端G2(n)输出；且在t1和t2时间段内，第二电容C2继续维持第六节点Q6的高电位状态，从而使第二驱动信号输出端G2(n)输出恒高电压信号。
在第一种输出方式下，第一控制信号输入端始终输入低电压信号V0，因此无论第二节点Q2的电位如何变化，第一下拉维持模块202均不会对第一自举输出模块201的输出状态产生影响。
在t1时间段内，ST(n-1)为高电位，第一晶体管T1导通，第一节点Q1的电位被抬升，第五晶体管T5导通，第二时钟信号线CK2为低电位，因此第三节点Q3和第五节点Q5为低电位，第十晶体管T10断开，第一驱动信号输出端G1(n)输出低电压；第二晶体管T2导通，级传信号输出端STO输出低电压的级传信号ST(n)。
在t2时间段内，第一电容C1保持第五晶体管T5导通，第二时钟信号线CK2为高电位，第三节点Q3和第五节点Q5的电位被抬升；在第一电容C1的作用下，第一节点Q1的电位被进一步抬升；第十晶体管T10导通，第一驱动信号输出端G1(n)输出第二高电压V2；第二晶体管T2导通，级传信号输出端STO输出高电压的级传信号ST(n)。
图4是本申请实施例提供的栅极驱动电路的第二种输出方式的输入/输出时序图。参考图1图2和图4所示，并以第n级栅极驱动单元U(n)为例进行说明。在第二种输出方式下，第二控制信号输入端LCB和低压信号输入端VGL均输入低电压信号V0，第一控制信号输入端LCA和第二高压信号输入端VGH均输入第一高电压信号V1，第一高压信号输入端VGHH输入第二高电压信号V2，且V2大于V1。在t1时间段之前，第二节点Q2在上拉维持模块600的作用下保持高电位，第一控制信号输入端LCA通过第一下拉维持模块202对第一电容C1和第四电容C4充电，并升高第五节点Q5的电位，第十晶体管T10导通，第一高压信号输入端VGHH输入的第二高电压信号V2通过第一驱动信号输出端G1(n)输出；且在t1和t2时间段内，第一电容C1继续维持第五节点Q5的高电位状态，从而使第一驱动信号输出端G1(n)输出恒高电压信号。
在第二种输出方式下，第二控制信号输入端始终输入低电压信号V0，因此无论第二节点Q2的电位如何变化，第二下拉维持模块302均不会对第二自举输出模块301的输出状态产生影响。
在t1时间段内，ST(n-1)为高电位，第一晶体管T1导通，第一节点Q1的电位被抬升，第五晶体管T5导通，第二时钟信号线CK2为低电位，因此第四节点Q4和第六节点Q6为低电位，第十四晶体管T14断开，第二驱动信号输出端G2(n)输出低电压；第二晶体管T2导通，级传信号输出端STO输出低电压的级传信号ST(n)。
在t2时间段内，第二电容C2保持第六晶体管T6导通，第二时钟信号线CK2为高电位，第四节点Q4和第六节点Q6的电位被抬升；在第二电容C2的作用下，第一节点Q1的电位被进一步抬升；第十四晶体管T14导通，第二驱动信号输出端G2(n)输出第二高电压V2；第二晶体管T2导通，级传信号输出端STO输出高电压的级传信号ST(n)。
综上所述，本申请实施例提供的栅极驱动电路包括多级栅极驱动单元，每一级所述栅极驱动单元均包括两个驱动信号输出单元和一个级传信号输出单元，其中两个驱动信号输出单元可交替输出恒高电压信号和波形信号，从而实现通过一个栅极驱动电路同时输出两种驱动信号，相较于现有技术通过两组栅极驱动电路来输出两种驱动信号的设计，减少了栅极驱动电路中使用的时钟信号线数量和薄膜晶体管数量，有利于实现显示装置的窄边框化。
本申请实施例还提供一种显示装置，所述显示装置包含本申请实施例提供的栅极驱动电路，所述显示装置易于实现窄边框化。
需要说明的是，虽然本申请以具体实施例揭露如上，但上述实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种栅极驱动电路，其包括多个栅极驱动单元，每个所述栅极驱动单元包括：
    级传单元，用于输出级传信号；
    第一输出单元，用于输出第一驱动信号；以及
    第二输出单元，用于输出第二驱动信号；
    其中，所述第一驱动信号为波形信号，所述第二驱动信号为恒高电压信号；或者，所述第一驱动信号为恒高电压信号，所述第二驱动信号为波形信号。
  2. 根据权利要求1所述的栅极驱动电路，其中，所述第一输出单元包括第一自举输出模块和第一下拉维持模块，所述第一自举输出模块用于上拉所述第一输出单元的输出电位，所述第一下拉维持模块用于下拉并维持所述第一输出单元的输出电位。
  3. 根据权利要求1所述的栅极驱动电路，其中，所述第一自举输出模块与所述第一下拉维持模块电性连接，所述第一下拉维持模块控制所述第一自举输出模块输出恒高电压的所述第一驱动信号。
  4. 根据权利要求2所述的栅极驱动电路，其中，所述第二输出单元包括第二自举输出模块和第二下拉维持模块，所述第二自举输出模块用于上拉所述第二输出单元的输出电位，所述第二下拉维持模块用于下拉并维持所述第二输出单元的输出电位。
  5. 根据权利要求4所述的栅极驱动电路，其中，所述第二自举输出模块与所述第二下拉维持模块电性连接，所述第二下拉维持模块控制所述第二自举输出模块输出恒高电压的所述第二驱动信号。
  6. 根据权利要求4所述的栅极驱动电路，其中，每个所述栅极驱动单元还包括：
    第一传递模块，电性连接于所述级传单元与所述第一自举输出模块之间，用于向所述第一自举输出模块传递输出控制信号；
    第二传递模块，电性连接于所述级传单元与所述第二自举输出模块之间，用于向所述第二自举输出模块传递输出控制信号。
  7. 根据权利要求6所述的栅极驱动电路，其中，每个所述栅极驱动单元还包括：
    上拉维持模块，分别与所述第一下拉维持模块和所述第二下拉维持模块电性连接，用于上拉并维持所述第一下拉维持模块和所述第二下拉维持模块的控制端电位；
    下拉模块，分别与所述第一下拉维持模块和所述第二下拉维持模块电性连接，用于下拉所述第一下拉维持模块和所述第二下拉维持模块的控制端电位。
  8. 根据权利要求7所述的栅极驱动电路，其中，所述第一下拉维持模块电性连接第一控制信号输入端，所述第二下拉维持模块电性连接第二控制信号输入端。
  9. 根据权利要求8所述的栅极驱动电路，其中，所述第一控制信号输入端向所述第一下拉维持模块输入低电压信号，所述第二控制信号输入端向所述第二下拉维持模块输入高电压信号，所述第一驱动信号为波形信号，所述第二驱动信号为恒高电压信号。
  10. 根据权利要求8所述的栅极驱动电路，其中，所述第一控制信号输入端向所述第一下拉维持模块输入高电压信号，所述第二控制信号输入端向所述第二下拉维持模块输入低电压信号，所述第一驱动信号为恒高电压信号，所述第二驱动信号为波形信号。
  11. 根据权利要求8所述的栅极驱动电路，其中，所述第一自举输出模块和所述第二自举输出模块均电性连接第一高压信号输入端，所述上拉维持模块电性连接第二高压信号输入端；
    所述第一高压信号输入端输入的电压大于所述第二高压信号输入端输入的电压。
  12. 根据权利要求11所述的栅极驱动电路，其中，
    所述级传单元电性连接所述第二高压信号输入端、级传信号输入端、第一时钟信号输入端、第二时钟信号输入端、低压信号输入端、级传信号输出端和第一节点，所述级传信号输出端用于输出所述级传信号；
    所述第一传递模块电性连接所述第一节点、所述第一时钟信号输入端和第三节点；
    所述第二传递模块电性连接所述第一节点、所述第一时钟信号输入端和第四节点；
    所述上拉维持模块电性连接所述第二时钟信号输入端、所述第二高压信号输入端和第二节点；
    所述下拉模块电性连接所述第一节点、所述低压信号输入端和所述第二节点；
    所述第一自举输出模块电性连接所述第三节点、所述第一高压信号输入端、所述第二高压信号输入端和第一驱动信号输出端，所述第一驱动信号输出端用于输出所述第一驱动信号；
    所述第一下拉维持模块电性连接所述第二节点、所述第三节点和所述第一控制信号输入端；
    所述第二自举输出模块电性连接所述第四节点、所述第一高压信号输入端、所述第二高压信号输入端和第二驱动信号输出端，所述第二驱动信号输出端用于输出所述第二驱动信号；
    所述第二下拉维持模块电性连接所述第二节点、所述第四节点和所述第二控制信号输入端。
  13. 根据权利要求12所述的栅极驱动电路，其中，所述级传单元包括第一晶体管、第二晶体管、第三晶体管和第四晶体管，所述第一晶体管的栅极、源极和漏极分别电性连接所述级传信号输入端、所述第二高压信号输入端和所述第一节点，所述第二晶体管的栅极、源极和漏极分别电性连接所述第一节点、所述第一时钟信号输入端和所述级传信号输出端，所述第三晶体管的栅极、源极和漏极分别电性连接所述第二时钟信号输入端、所述低压信号输入端和所述级传信号输出端，所述第四晶体管的栅极、源极和漏极分别电性连接所述第二时钟信号输入端、所述低压信号输入端和所述第一节点；
    所述第一传递模块包括第五晶体管和第一电容，所述第五晶体管的栅极、源极和漏极分别电性连接所述第一节点、所述第一时钟信号输入端和所述第三节点，所述第一电容的两极分别电性连接所述第一节点和所述第三节点；
    所述第二传递模块包括第六晶体管和第二电容，所述第六晶体管的栅极、源极和漏极分别电性连接所述第一节点、所述第一时钟信号输入端和所述第四节点，所述第二电容的两极分别电性连接所述第一节点和所述第四节点；
    所述上拉维持模块包括第七晶体管和第三电容，所述第七晶体管的栅极、源极和漏极分别电性连接所述第二时钟信号输入端、所述第二高压信号输入端和所述第二节点，所述第三电容的两极分别电性连接所述第二节点和所述低压信号输入端；
    所述下拉模块包括第八晶体管，所述第八晶体管的栅极、源极和漏极分别电性连接所述第一节点、所述低压信号输入端和所述第二节点；
    所述第一自举输出模块包括第九晶体管、第十晶体管和第四电容，所述第九晶体管的栅极、源极和漏极分别电性连接所述第二高压信号输入端、所述第三节点和第五节点，所述第十晶体管的栅极、源极和漏极分别电性连接所述第五节点、所述第一高压信号输入端和所述第一驱动信号输出端，所述第四电容的两极分别电性连接所述第五节点和所述第一驱动信号输出端；
    所述第一下拉维持模块包括第十一晶体管和第十二晶体管，所述第十一晶体管的栅极、源极和漏极分别电性连接所述第二节点、所述第一控制信号输入端和所述第三节点，所述第十二晶体管的栅极、源极和漏极分别电性连接所述第二节点、所述第一控制信号输入端和所述第一驱动信号输出端；
    所述第二自举输出模块包括第十三晶体管、第十四晶体管和第五电容，所述第十三晶体管的栅极、源极和漏极分别电性连接所述第二高压信号输入端、所述第四节点和第六节点，所述第十四晶体管的栅极、源极和漏极分别电性连接所述第六节点、所述第一高压信号输入端和所述第二驱动信号输出端，所述第五电容的两极分别电性连接所述第六节点和所述第二驱动信号输出端；
    所述第二下拉维持模块包括第十五晶体管和第十六晶体管，所述第十五晶体管的栅极、源极和漏极分别电性连接所述第二节点、所述第二控制信号输入端和所述第四节点，所述第十六晶体管的栅极、源极和漏极分别电性连接所述第二节点、所述第二控制信号输入端和所述第二驱动信号输出端。
  14. 根据权利要求12所述的栅极驱动电路，其中，多个所述栅极驱动单元存在以下级联关系：本级所述栅极驱动单元的所述级传信号输入端电性连接上一级所述栅极驱动单元的所述级传信号输出端。
  15. 根据权利要求12所述的栅极驱动电路，其中，所述栅极驱动电路分别通过第一时钟信号线、第二时钟信号线和第三时钟信号线提供时钟信号，
    第k+3i级所述栅极驱动单元的所述第一时钟信号输入端和所述第二时钟信号输入端分别电性连接所述第一时钟信号线和所述第二时钟信号线；
    第k+3i+1级所述栅极驱动单元的所述第一时钟信号输入端和所述第二时钟信号输入端分别电性连接所述第二时钟信号线和所述第三时钟信号线；
    第k+3i+2级所述栅极驱动单元的所述第一时钟信号输入端和所述第二时钟信号输入端分别电性连接所述第三时钟信号线和所述第一时钟信号线；
    其中，k为大于或等于1的整数，i为大于或等于0的整数。
  16. 一种显示装置，其包括栅极驱动电路，所述栅极驱动电路包括多个栅极驱动单元，每个所述栅极驱动单元包括：
    级传单元，用于输出级传信号；
    第一输出单元，用于输出第一驱动信号；以及
    第二输出单元，用于输出第二驱动信号；
    其中，所述第一驱动信号为波形信号，所述第二驱动信号为恒高电压信号；或者，所述第一驱动信号为恒高电压信号，所述第二驱动信号为波形信号。
  17. 根据权利要求16所述的显示装置，其中，所述第一输出单元包括第一自举输出模块和第一下拉维持模块，所述第一自举输出模块用于上拉所述第一输出单元的输出电位，所述第一下拉维持模块用于下拉并维持所述第一输出单元的输出电位；所述第一自举输出模块与所述第一下拉维持模块电性连接，所述第一下拉维持模块控制所述第一自举输出模块输出恒高电压的所述第一驱动信号。
  18. 根据权利要求17所述的显示装置，其中，所述第二输出单元包括第二自举输出模块和第二下拉维持模块，所述第二自举输出模块用于上拉所述第二输出单元的输出电位，所述第二下拉维持模块用于下拉并维持所述第二输出单元的输出电位；所述第二自举输出模块与所述第二下拉维持模块电性连接，所述第二下拉维持模块控制所述第二自举输出模块输出恒高电压的所述第二驱动信号。
  19. 根据权利要求18所述的显示装置，其中，每个所述栅极驱动单元还包括：
    第一传递模块，电性连接于所述级传单元与所述第一自举输出模块之间，用于向所述第一自举输出模块传递输出控制信号；
    第二传递模块，电性连接于所述级传单元与所述第二自举输出模块之间，用于向所述第二自举输出模块传递输出控制信号；
    上拉维持模块，分别与所述第一下拉维持模块和所述第二下拉维持模块电性连接，用于上拉并维持所述第一下拉维持模块和所述第二下拉维持模块的控制端电位；
    下拉模块，分别与所述第一下拉维持模块和所述第二下拉维持模块电性连接，用于下拉所述第一下拉维持模块和所述第二下拉维持模块的控制端电位；
    其中，所述第一下拉维持模块电性连接第一控制信号输入端，所述第二下拉维持模块电性连接第二控制信号输入端。
  20. 根据权利要求19所述的显示装置，其中，所述第一控制信号输入端向所述第一下拉维持模块输入低电压信号，所述第二控制信号输入端向所述第二下拉维持模块输入高电压信号，所述第一驱动信号为波形信号，所述第二驱动信号为恒高电压信号；
    或者，所述第一控制信号输入端向所述第一下拉维持模块输入高电压信号，所述第二控制信号输入端向所述第二下拉维持模块输入低电压信号，所述第一驱动信号为恒高电压信号，所述第二驱动信号为波形信号。
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