WO2022037289A1 - 钝化接触电池及制备方法和钝化接触结构制备方法及装置 - Google Patents

钝化接触电池及制备方法和钝化接触结构制备方法及装置 Download PDF

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WO2022037289A1
WO2022037289A1 PCT/CN2021/104649 CN2021104649W WO2022037289A1 WO 2022037289 A1 WO2022037289 A1 WO 2022037289A1 CN 2021104649 W CN2021104649 W CN 2021104649W WO 2022037289 A1 WO2022037289 A1 WO 2022037289A1
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gas
layer
process chamber
substrate
amorphous silicon
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French (fr)
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杜哲仁
陆俊宇
季根华
马丽敏
陈嘉
林建伟
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泰州中来光电科技有限公司
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Priority to EP21857385.5A priority Critical patent/EP4203080A1/en
Publication of WO2022037289A1 publication Critical patent/WO2022037289A1/zh

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Definitions

  • the invention relates to the technical field of solar cells, in particular to a passivation contact cell and a preparation method thereof, and a passivation contact structure preparation method and device.
  • the mainstream passivation technology is to deposit a silicon nitride passivation film on the front and back of the battery to improve the composite problem.
  • a more advanced technology is to use tunnel oxide passivation contact technology (TOPCon); passivation tunneling technology first deposits a tunnel layer on the surface of the substrate; and then covers a layer of doped polysilicon; thus forming The tunnel oxide layer passivates the contacts.
  • TOPCon tunnel oxide passivation contact technology
  • the tunneling oxide passivation technology can form a tunneling film between the electrode and the substrate, isolate the contact between the metal electrode and the substrate, and reduce the contact recombination loss, so the open circuit voltage of the battery can be very high, and the electron energy tunneling film will not affect current transfer.
  • the commonly used methods for preparing the tunneling passivation contact structure in industrial production are: 1. First, the oxide layer is grown by thermal oxidation, 2. Then the intrinsic amorphous silicon layer is deposited by CVD (chemical vapor deposition) method, 3. Finally, Then, a doped polysilicon layer is formed by means of ion implantation or diffusion.
  • CVD chemical vapor deposition
  • the machine is relatively expensive; if the phosphorus expansion method is used, a mask needs to be used to realize single-sided doping, and the process is more complicated;
  • the process temperature of thermal oxidation and CVD methods is above 550 °C. High temperature will cause large curvature of the wafer and affect the product yield. At the same time, the reacted gas will spread to the back of the substrate, react and deposit into a film, forming a wrapping plating. , it is necessary to increase the de-winding plating step and increase the cost.
  • the purpose of the present invention is to overcome the deficiencies of the prior art, and to provide a passivation contact cell and its preparation method, and a passivation contact structure preparation method and device.
  • a preparation method of a passivation contact structure of the present invention comprises the following steps:
  • the substrate is first placed in a PECVD process chamber to deposit a tunnel oxide layer, and then placed in a PVD process chamber to deposit a doped amorphous silicon layer; the PECVD process chamber is provided with a first gas, and the PVD process chamber is provided with a first gas.
  • a second gas and a target are arranged inside;
  • the target material includes at least one target material containing a dopant source, and the second gas does not contain a dopant source gas; or,
  • the target material includes at least one target material containing a dopant source, and the second gas includes a dopant source gas; or,
  • the target material does not contain a target material containing a dopant source, and the second gas contains a dopant source gas;
  • the doped amorphous silicon layer includes n-layer thin films, n ⁇ 2, and the n-layer thin films at least include one layer of doped layer and one layer of undoped layer;
  • step S1
  • the PVD process chamber includes m independent chambers, and m ⁇ 2;
  • At least one independent cavity is provided with a target material without a doping source, and a gas without a doping source is introduced, so that the silicon wafer forms an intrinsic amorphous in the cavity silicon layer;
  • At least one independent cavity is provided with a target material containing a doping source, and a gas without a doping source is introduced, so that the silicon wafer forms doped amorphous silicon in the cavity. or, at least one of the m independent cavities is provided with a target without a doping source, and a gas containing a doping source is passed in, so that the silicon wafers are doped in the cavity. an amorphous silicon layer; or, at least one of the m independent cavities is provided with a target containing a dopant source, and a gas containing a dopant source is passed in, so that the silicon wafer is contained in the cavity A doped amorphous silicon layer is formed.
  • step S1
  • the PVD process chamber includes an integral cavity, and p regions are arranged in the integral cavity according to the traveling direction of the substrate, and p ⁇ 2;
  • At least one of the p regions is provided with a target material without a doping source, and a gas without a doping source is introduced, so that the silicon wafer forms an intrinsic amorphous silicon layer in this region;
  • At least one of the p regions is provided with a target containing a doping source, and a gas that does not contain a doping source is supplied, so that the silicon wafer forms a doped amorphous silicon layer in this region.
  • the doped amorphous silicon layer includes n-layer thin films, n ⁇ 2, and the n-layer thin films include at least one doped layer and one undoped layer.
  • step S1 plasma enhanced chemical vapor deposition is used to deposit the tunnel oxide layer in the PECVD process chamber, and the first gas at least includes oxygen and/or nitrogen monoxide.
  • a magnetron sputtering method is used to deposit an intrinsic amorphous silicon layer in a PVD process chamber, and the second gas includes at least one of argon, hydrogen or oxygen, or a mixed gas composed of any of several gases.
  • step S1 before performing step S1, the method further includes:
  • step S1 the substrate is first placed in a PECVD process chamber to deposit the tunnel oxide layer, and then the substrate is preheated, and then placed in a PVD process chamber to deposit a doped amorphous silicon layer.
  • step S1 the temperature of the PVD process chamber is not greater than 350°C; the thickness of the doped amorphous silicon layer is 50-350nm.
  • the present invention also provides a passivation contact cell, and the passivation structure of the passivation contact cell is prepared according to the method described above.
  • the present invention also provides a preparation device for a passivation contact structure, which is used for preparing the passivation contact structure in the above-mentioned passivation contact cell, which includes a PECVD process chamber and a PVD process chamber; wherein,
  • the PVD process chamber includes at least a first independent chamber and a second independent chamber;
  • the PVD process chamber includes an integral cavity, and at least a first area and a second area are arranged in the integral cavity according to the traveling direction of the substrate.
  • the present invention also provides a preparation method of a passivation contact battery, which is characterized in that: it comprises the following steps:
  • the substrate is first placed in a PECVD process chamber to deposit a tunnel oxide layer, and then placed in a PVD process chamber to deposit a doped amorphous silicon layer; the PECVD process chamber is provided with a first gas, and the PVD process chamber is provided with a first gas.
  • a second gas and a target are arranged inside;
  • the target material includes at least one target material containing a dopant source, and the second gas does not contain a dopant source gas; or,
  • the target material includes at least one target material containing a dopant source, and the second gas includes a dopant source gas; or,
  • the target material does not contain a target material containing a dopant source, and the second gas contains a dopant source gas;
  • the doped amorphous silicon layer includes n-layer thin films, n ⁇ 2, and the n-layer thin films at least include one layer of doped layer and one layer of undoped layer;
  • the invention adopts continuous coating equipment to prepare the passivation contact structure, and continuously completes the preparation of the tunnel oxide layer and the doped polysilicon layer in the same equipment, which simplifies the preparation process, improves the productivity, and avoids the step-by-step preparation of the tunnel oxide layer.
  • the interface pollution caused by the layer and the amorphous silicon layer further improves the passivation effect and improves the electrical performance of the battery.
  • the present invention adopts the PVD method to prepare the amorphous silicon layer, realizes in-situ doping, reduces the subsequent separate phosphorus doping process, and avoids the problem of poor passivation performance caused by high temperature damage to the tunnel oxide layer.
  • the PVD method has a low process temperature, which can greatly reduce the defects caused by the bending of the substrate.
  • the preparation method of the present invention can adjust the required doping ratio according to the process requirements, so as to obtain better passivation effect.
  • the process of the preparation method of the present invention has a single-sided property, does not generate wrapping plating, and reduces post-cleaning steps.
  • FIG. 1 is a schematic cross-sectional view of the battery structure after step S0 in Example 3 and Example 4 of the present invention.
  • FIG. 2 is a schematic cross-sectional view of the battery structure after step S1 ′′ in Example 3 and Example 4 of the present invention.
  • Example 3 is a schematic cross-sectional view of the battery structure after step S2 in Example 3 of the present invention.
  • FIG. 4 is a schematic cross-sectional view of the battery structure after step S31 in Example 3 of the present invention.
  • FIG. 5 is a schematic cross-sectional view of the battery structure after step S32 in Example 3 of the present invention.
  • FIG. 6 is a schematic cross-sectional view of the battery structure after step S33 in Example 3 of the present invention.
  • FIG. 7 is a schematic cross-sectional view of the battery structure after step S34 in Example 3 of the present invention.
  • FIG. 8 is a schematic cross-sectional view of the battery structure after step S2 in Example 4 of the present invention.
  • FIG. 9 is a schematic cross-sectional view of the battery structure after step S31 in Example 4 of the present invention.
  • FIG. 10 is a schematic cross-sectional view of the battery structure after step S32 in Example 4 of the present invention.
  • FIG. 11 is a schematic cross-sectional view of the battery structure after step S33 in Example 4 of the present invention.
  • FIG. 12 is a schematic cross-sectional view of the battery structure after step S34 in Example 4 of the present invention.
  • Example 13 is a schematic diagram of the preparation apparatus in Example 3 and Example 4 of the present invention.
  • the invention provides a preparation method of a passivation contact structure, comprising the following steps:
  • the substrate is first placed in a PECVD process chamber to deposit a tunnel oxide layer, and then placed in a PVD process chamber to deposit a doped amorphous silicon layer; the PECVD process chamber is provided with a first gas, and the PVD process chamber is provided with a first gas.
  • a second gas and a target are arranged inside;
  • the target material includes at least one target material containing a dopant source, and the second gas does not contain a dopant source gas; or,
  • the target material includes at least one target material containing a dopant source, and the second gas includes a dopant source gas; or,
  • the target material does not contain a target material containing a dopant source, and the second gas contains a dopant source gas;
  • the doped amorphous silicon layer includes n-layer thin films, n ⁇ 2, and the n-layer thin films at least include one layer of doped layer and one layer of undoped layer;
  • This embodiment essentially includes three parallel technical solutions: (1) The target in the PVD process chamber is a pure silicon pillar target, and the second gas in the PVD process chamber contains a doping source gas. At this time, the PVD process The doping source of the substrate in the cavity is only the doping source gas. This doping method is easier for the doping source to react with the substrate to form a doped amorphous silicon layer. The hetero-square resistance is uniform, and the gas doping is easier to achieve the doping of the high-concentration amorphous silicon layer; (2) The target in the PVD process chamber is a target containing a dopant source, and the second in the PVD process chamber is the target material. The gas does not contain doping source gas.
  • the doping source of the substrate in the PVD process chamber is only the target material containing the doping source.
  • This doping method does not require the use of doping source gas, and has high safety performance.
  • the cost of solid doping is relatively low, saving costs, and it is easier to quantitatively control the doping dose by solid doping.
  • the doping dose of the substrate-doped amorphous silicon film is controlled by controlling the doping dose of the target containing the doping source.
  • the target material in the PVD process chamber is a target material containing a dopant source, and the gas in the PVD process chamber contains a dopant source gas.
  • the dopant source of the substrate in the PVD process chamber is a dopant source gas containing
  • the target material of the doping source and the doping source gas the combination of the doping method combines the advantages of gas doping and solid doping, the doping is uniform, the doping concentration can be higher, and the passivation is improved.
  • the passivation level of the contact structure, while the higher doping concentration can reduce the contact resistivity and metal recombination of the passivated contact structure.
  • the gas in this embodiment is an inert gas and/or hydrogen gas
  • the gas containing the doping source is a phosphorus-containing doping gas or a boron-containing doping gas
  • the target material without a doping source It is a pure pillar silicon target.
  • the preparation method of the invention is simple in technique, convenient in operation, safe and reliable, stable in quality and high in production efficiency, easy to realize large-scale industrial production, and easy to update and integrate existing production lines.
  • step S1 in step S1,
  • the PVD process chamber includes m independent chambers, and m ⁇ 2;
  • At least one independent cavity is provided with a target material without a doping source, and a gas without a doping source is passed in, so that the silicon wafer forms an intrinsic amorphous in the cavity silicon layer;
  • At least one independent cavity is provided with a target material containing a doping source, and a gas without a doping source is introduced, so that the silicon wafer forms doped amorphous silicon in the cavity. or, at least one of the m independent cavities is provided with a target without a doping source, and a gas containing a doping source is passed in, so that the silicon wafers are doped in the cavity. an amorphous silicon layer; or, at least one of the m independent cavities is provided with a target containing a dopant source, and a gas containing a dopant source is passed in, so that the silicon wafer is contained in the cavity A doped amorphous silicon layer is formed.
  • the superposition of m cavities can realize the deposition of the stacked doped amorphous silicon film, and the optimal concentration of the doped amorphous silicon layer is from the interface of the tunnel oxide layer to the doped amorphous silicon layer.
  • the doping concentration gradually increases, the low doping concentration near the interface of the tunnel oxide layer can make the passivation level of the passivation contact structure higher, and the high doping concentration near the interface of the doped amorphous silicon layer can make the metal contact recombination more Low contact resistivity, the superposition of such cavities makes it easier to realize such stacked graded doping concentration doped amorphous silicon thin films.
  • step S1 in step S1,
  • the PVD process chamber includes an integral cavity, and p regions are arranged in the integral cavity according to the traveling direction of the substrate, and p ⁇ 2;
  • At least one of the p regions is provided with a target material without a doping source, and a gas without a doping source is introduced, so that the silicon wafer forms an intrinsic amorphous silicon layer in this region;
  • At least one of the p regions is provided with a target containing a doping source, and a gas that does not contain a doping source is supplied, so that the silicon wafer forms a doped amorphous silicon layer in this region.
  • the doped amorphous silicon layer includes n-layer thin films, n ⁇ 2, and the n-layer thin films include at least one doped layer and one undoped layer.
  • the doped amorphous silicon layer is configured to include an n-layer thin film to form a multi-layer tunneling structure, thereby making it easier for metal contact recombination and contact resistivity to obtain the best effect.
  • the tunnel oxide layer is deposited in a PECVD process chamber by using a plasma enhanced chemical vapor deposition method, and the first gas at least includes oxygen and/or nitrogen monoxide.
  • a magnetron sputtering method is used to deposit an intrinsic amorphous silicon layer in the PVD process chamber, which includes at least one gas in argon, hydrogen or oxygen or a mixed gas composed of any several gases.
  • the method before performing step S1, the method further includes:
  • a mask is arranged on the substrate to improve the efficiency of the battery sheet.
  • step S1 after the substrate is placed in a PECVD process chamber to deposit the tunnel oxide layer, the substrate is first preheated, and then placed in a PVD process chamber to deposit doped amorphous silicon Floor.
  • the temperature of the PVD process chamber is not greater than 350°C; the thickness of the doped amorphous silicon layer is 50-350nm.
  • the present invention also provides a passivation contact cell, and the passivation structure of the passivation contact cell is prepared according to the method described above.
  • the present invention also provides a preparation device for a passivation contact structure, which is used for preparing the passivation contact structure in the above-mentioned passivation contact cell, which includes a PECVD process chamber and a PVD process chamber; wherein,
  • the PVD process chamber includes at least a first independent chamber and a second independent chamber;
  • the PVD process chamber includes an integral cavity, and at least a first area and a second area are arranged in the integral cavity according to the traveling direction of the substrate.
  • the present invention also provides a preparation method of the passivated contact battery, comprising the following steps:
  • the substrate is first placed in a PECVD process chamber to deposit a tunnel oxide layer, and then placed in a PVD process chamber to deposit a doped amorphous silicon layer; the PECVD process chamber is provided with a first gas, and the PVD process chamber is provided with a first gas.
  • a second gas and a target are arranged inside;
  • the target material includes at least one target material containing a dopant source, and the second gas does not contain a dopant source gas; or,
  • the target material includes at least one target material containing a dopant source, and the second gas includes a dopant source gas; or,
  • the target material does not contain a target material containing a dopant source, and the second gas contains a dopant source gas;
  • the doped amorphous silicon layer includes n-layer thin films, n ⁇ 2, and the n-layer thin films at least include one layer of doped layer and one layer of undoped layer;
  • the invention adopts continuous coating equipment to prepare the passivation contact structure, and continuously completes the preparation of the tunnel oxide layer and the doped polysilicon layer in the same equipment, which simplifies the preparation process, improves the productivity, and avoids the step-by-step preparation of the tunnel oxide layer.
  • the interface pollution caused by the layer and the amorphous silicon layer further improves the passivation effect and improves the electrical performance of the battery.
  • the present invention adopts the PVD method to prepare the amorphous silicon layer, realizes in-situ doping, reduces the subsequent separate phosphorus doping process, and avoids the problem of poor passivation performance caused by high temperature damage to the tunnel oxide layer.
  • the PVD method has a low process temperature, which can greatly reduce the defects caused by the bending of the substrate.
  • the preparation method of the present invention can adjust the required doping ratio according to the process requirements, so as to obtain better passivation effect.
  • the process of the preparation method of the present invention has a single-sided property, does not generate wrapping plating, and reduces post-cleaning steps.
  • Step S0 select an N-type substrate 1, and preprocess the substrate to form a textured structure on the surface of the substrate.
  • the resistivity of the n-type crystalline silicon substrate is 0.3-5 ⁇ cm, and the thickness is 80-200 ⁇ m.
  • Step S1 put the substrate 1 pretreated in step S0 into the loading chamber for loading, and enter the PECVD process chamber, and generate the tunnel oxide layer 2 by plasma excitation in the PECVD process chamber, and the gas introduced into the PECVD process chamber is: Oxygen; after the deposition of the tunnel oxide layer 2 is completed in the PECVD process chamber, the substrate enters the PVD process chamber.
  • the PVD process chamber includes two independent chambers, and argon gas is introduced into the process chamber.
  • the first chamber is provided with a pure A silicon pillar target
  • the second cavity is provided with a target containing a phosphorus doping source
  • an amorphous silicon film is deposited on the surface of the substrate by magnetron sputtering.
  • the amorphous silicon film is doped.
  • the amorphous silicon film includes two layers of amorphous silicon layers, and the thickness of each amorphous silicon layer is 25-300 nm.
  • the first layer is The non-doped amorphous silicon layer, and the second layer is a phosphorus-doped amorphous silicon layer.
  • Step S2 annealing the substrate to activate the doped amorphous silicon layer to form the doped polysilicon layer 3 to complete the preparation of the passivation contact structure.
  • Step S0 select a P-type substrate 1, and preprocess the substrate to form a textured structure on the surface of the substrate.
  • the resistivity of the n-type crystalline silicon substrate is 0.1-5 ⁇ cm and the thickness is 80-200 ⁇ m.
  • Step S1 put the substrate pretreated in step S0 into the loading chamber for loading, and enter the PECVD process chamber, and generate a tunnel oxide layer 2 through plasma excitation in the PECVD process chamber, the thickness of which is 0.5-3 nm, and the PECVD process chamber
  • the gas introduced into the chamber is oxygen; after the deposition of the tunnel oxide layer 2 is completed in the PECVD process chamber, the substrate enters the PVD process chamber.
  • the PVD process chamber includes two independent chambers, and argon gas is introduced into the process chamber.
  • a pure silicon column target is arranged in the cavity, and a target material containing a phosphorus doping source is arranged in the second cavity.
  • a layer of amorphous silicon film is deposited on the surface of the substrate by magnetron sputtering.
  • the amorphous silicon film is doped in the second cavity at the same time as the crystalline silicon film.
  • the amorphous silicon film includes two layers of amorphous silicon layers, and the thickness of each amorphous silicon layer is 25-300nm. , wherein the first layer is a non-doped amorphous silicon layer, and the second layer is a phosphorus-doped amorphous silicon layer.
  • Step S2 annealing the substrate to activate the doped amorphous silicon layer to form the doped polysilicon layer 3 to complete the preparation of the passivation contact structure.
  • Step S0 select an N-type substrate 1, and preprocess the substrate to form a textured structure on the surface of the substrate.
  • the resistivity of the n-type crystalline silicon substrate is 0.3-5 ⁇ cm, and the thickness is 80-200 ⁇ m.
  • the battery structure after this step is completed is shown in FIG. 1 .
  • step S1 the substrate 1 pretreated in step S1" is loaded into the loading chamber shown in Fig. 13, and then enters the PECVD process chamber, where a tunnel oxide layer 2 is generated by plasma excitation in the PECVD process chamber.
  • the gas introduced is oxygen; after the deposition of the tunnel oxide layer 2 is completed in the PECVD process chamber, the substrate enters the PVD process chamber.
  • the PVD process chamber includes two independent chambers, and argon gas is introduced into the process chamber.
  • the first chamber A pure silicon column target is set in the body, and a target containing a phosphorus doping source is set in the second cavity.
  • a layer of amorphous silicon film is deposited on the back surface of the substrate by magnetron sputtering.
  • the amorphous silicon film is doped in the second cavity at the same time as the crystalline silicon film.
  • the amorphous silicon film includes two layers of amorphous silicon layers, and the thickness of each amorphous silicon layer is 25-300nm. , wherein the first layer is a non-doped amorphous silicon layer, and the second layer is a phosphorus-doped amorphous silicon layer.
  • Step S2 annealing the substrate to activate the doped amorphous silicon layer, form the doped polysilicon layer 3, and complete the passivation contact structure.
  • the square resistance of the film after annealing is 20-100 ⁇ /square.
  • the battery structure after this step is completed is shown in FIG. 3 .
  • Step S3 post-processing the substrate, which includes:
  • Step S31 a silicon nitride anti-reflection layer 4 is prepared on the backside of the substrate.
  • the battery structure after this step is completed is shown in FIG. 4 .
  • Step S32 preparing a front surface aluminum oxide passivation layer 5 on the front surface of the substrate.
  • the battery structure after this step is completed is shown in FIG. 5 .
  • Step S33 a silicon nitride anti-reflection layer 6 is prepared on the front surface of the substrate.
  • the battery structure after this step is completed is shown in FIG. 6 .
  • Step S34 using screen printing metallization paste 7 on the front and back of the substrate, and sintering.
  • the battery structure after this step is completed is shown in FIG. 7 .
  • Step S0 select a P-type substrate 1, and preprocess the substrate to form a textured structure on the surface of the substrate.
  • the resistivity of the n-type crystalline silicon substrate is 0.1-5 ⁇ cm and the thickness is 80-200 ⁇ m.
  • the battery structure after this step is completed is shown in FIG. 1 .
  • Step S1 carry out boron diffusion on the substrate to form the emitter 8 and clean it.
  • the battery structure is shown in Figure 2.
  • step S1 the substrate pretreated in step S1" is loaded into the loading chamber shown in FIG. 13, and then enters the PECVD process chamber, where a tunnel oxide layer 2 is generated by plasma excitation in the PECVD process chamber, and its thickness is 0.5 ⁇ 3nm, the gas introduced into the PECVD process chamber is oxygen; after the deposition of the tunnel oxide layer 2 is completed in the PECVD process chamber, the substrate enters the PVD process chamber.
  • the PVD process chamber includes two independent chambers, and argon is passed into the process chamber. A pure silicon column target is set in the first cavity, and a target containing a phosphorus doping source is set in the second cavity, and an amorphous layer is deposited on the surface of the front substrate by magnetron sputtering.
  • the amorphous silicon thin film is doped in the second cavity while depositing the amorphous silicon thin film, the amorphous silicon thin film includes two layers of amorphous silicon layers, each layer of amorphous silicon The thicknesses are all 25-300 nm, wherein the first layer is a non-doped amorphous silicon layer, and the second layer is a phosphorus-doped amorphous silicon layer.
  • Step S2 annealing the substrate to activate the doped amorphous silicon layer, form the doped polysilicon layer 3, and complete the passivation contact structure.
  • the square resistance of the film after annealing is 20-100 ⁇ /square.
  • the battery structure after this step is completed is shown in FIG. 8 .
  • Step S3 post-processing the substrate, which includes:
  • Step S31 preparing a backside aluminum oxide passivation layer 9 on the backside of the substrate.
  • the battery structure after this step is completed is shown in FIG. 9 .
  • Step S32 preparing a stack passivation anti-reflection layer 10 on the front and back surfaces of the substrate.
  • the battery structure after this step is completed is shown in FIG. 10 .
  • Step S33 laser cutting the groove-like structure 11 on the backside of the substrate.
  • the battery structure after this step is completed is shown in FIG. 11 .
  • Step S34 using screen printing metallization paste 7 on the front and back of the substrate, and sintering.
  • the battery structure after this step is completed is shown in FIG. 12 .

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Abstract

本发明涉及一种钝化接触电池及制备方法和钝化接触结构制备方法及装置。该方法包括：S1、对基片预处理；S2、先将基片在PECVD工艺腔内沉积隧穿氧化层，再在PVD工艺腔内沉积掺杂非晶硅层；PECVD工艺腔内设第一气体，PVD工艺腔内设第二气体和靶材；靶材包含至少一个含掺杂源靶材，第二气体不包含掺杂源气体；或，靶材包含至少一个含掺杂源的靶材，第二气体包含掺杂源气体；或，靶材不包含含掺杂源的靶材，第二气体包含掺杂源气体；掺杂非晶硅层包括n层薄膜，n≥2，n层薄膜中至少包含一层掺杂层和一层非掺杂层；S3、对基片进行退火处理，形成掺杂多晶硅层，完成钝化接触结构制备。本发明在同一设备中连续完成隧穿氧化层及掺杂多晶硅层制备，简化了制备工艺。

Description

钝化接触电池及制备方法和钝化接触结构制备方法及装置 技术领域
本发明涉及太阳能电池技术领域，具体涉及一种钝化接触电池及制备方法和钝化接触结构制备方法及装置。
背景技术
由于晶体硅电池基片厚度的不断降低，且对于一定厚度的电池片而言，当少数载流子的扩散长度大于基片厚度时，表面的复合速率对太阳能电池的效率影响特别明显。因此，现行的技术多是对晶体硅表面进行钝化处理。目前比较主流的钝化技术是在电池正背面沉积氮化硅钝化膜，改善复合问题。一种较为先进的技术是采用隧穿氧化层钝化接触技术(TOPCon)；钝化隧穿技术在基片表面先沉积一层隧穿层；然后再覆盖一层掺杂的多晶硅层；从而形成隧穿氧化层钝化接触。隧穿氧化层钝化技术能在电极与基底之间形成隧穿薄膜，隔绝金属电极与基底接触，减少接触复合损失，因此电池的开路电压可以做到很高，并且电子能隧穿薄膜不会影响电流传递。
目前工业化生产中制备该隧穿钝化接触结构通常采用的方法为：1、先用热氧化生长氧化层，2、再通过CVD法(化学气相沉积)沉积本征非晶硅层，3、最后再通过离子注入或者扩散的方法，形成掺杂的多晶硅层。这种方式有如下缺点：
1、需要3台设备分别单独完成上述3道工序；虽然热氧化生长氧化层和CVD沉积非晶硅层可以在同一个管式炉里实现，但由于工艺温度不一致，需要花费更长的升温、降温等待时间，导致产能偏低；
2、第3步掺杂，如果采用离子注入的方法，机台比较昂贵；如果采用磷扩的方法需要使用掩模来实现单面掺杂，工序比较复杂；
3、热氧化跟CVD的方法工艺温度在550℃以上，高温会造成片子弯曲度大，影响产品良率，同时反应的气体会蔓延到衬底的背面，发生反应并沉积成膜，形成绕镀，需增加去绕镀步骤，增加成本。
发明内容
本发明的目的在于克服现有技术的不足，提供一种钝化接触电池及制备方法和钝化接触结构制备方法及装置。
本发明的一种钝化接触结构的制备方法，其包括以下步骤：
S1、先将基片置于PECVD工艺腔内沉积隧穿氧化层，然后置于PVD工艺腔内沉积掺杂非晶硅层；所述PECVD工艺腔内设置有第一气体，所述PVD工艺腔内设置有第二气体和靶材；
所述靶材中包含至少一个含掺杂源的靶材，第二气体中不包含掺杂源气体；或，
所述靶材中包含至少一个含掺杂源的靶材，第二气体中包含掺杂源气体；或，
所述靶材中不包含含掺杂源的靶材，第二气体中包含掺杂源气体；
所述掺杂非晶硅层包括n层薄膜，n≥2，所述n层薄膜中至少包含一层掺杂层和一层非掺杂层；
S2、对基片进行退火处理，以激活所述掺杂非晶硅层，形成掺杂多晶硅层，完成钝化接触结构的制备。
本发明提供的一种钝化接触结构的制备方法，还包括如下附属技术方案：
其中，在步骤S1中，
所述PVD工艺腔包括m个独立腔体，m≥2；
所述m个独立腔体中至少存在一个独立腔体中设置有不含掺杂源的靶材， 并通入不含掺杂源的气体，以使硅片在该腔体内形成本征非晶硅层；
所述m个独立腔体中至少存在一个独立腔体中设置有含掺杂源的靶材，并通入不含掺杂源的气体，以使硅片在该腔体内形成掺杂非晶硅层；或，所述m个独立腔体中至少存在一个独立腔体中设置不含掺杂源的靶材，并通入含掺杂源的气体，以使硅片在该腔体内形成掺杂非晶硅层；或，所述m个独立腔体中至少存在一个独立腔体中设置有含掺杂源的靶材，并通入含掺杂源的气体，以使硅片在该腔体内形成掺杂非晶硅层。
其中，在步骤S1中，
所述PVD工艺腔包括一个整体腔体，所述整体腔体内按基片的行进方向设置有p个区域，p≥2；
所述p个区域中至少存在一个区域中设置有不含掺杂源的靶材，并通入不含掺杂源的气体，以使硅片在该区域形成本征非晶硅层；
所述p个区域中至少存在一个区域中设置有含掺杂源的靶材，并通入不含掺杂源的气体，以使硅片在该区域形成掺杂非晶硅层。
其中，在步骤S1中，所述掺杂非晶硅层包括n层薄膜，n≥2，所述n层薄膜中至少包含一层掺杂层和一层非掺杂层。
其中，在步骤S1中，采用等离子体增强化学气相沉积法在PECVD工艺腔内沉积所述隧穿氧化层，所述第一气体至少包括氧气和/或一氧化氮。
其中，采用磁控溅射法在PVD工艺腔内沉积本征非晶硅层，所述第二气体至少包括氩气、氢气或氧气中的一种气体或任几种气体组成的混合气体。
其中，在进行步骤S1之前，所述方法还包括：
S1’、在基片上设置带有图形的掩膜，以局部沉积隧穿氧化层和掺杂多晶硅层。
其中，在步骤S1中，先将基片置于PECVD工艺腔内沉积完隧穿氧化层之后，先对基片进行预热处理，然后置于PVD工艺腔内沉积掺杂非晶硅层。
其中，在步骤S1中，PVD工艺腔的温度不大于350℃；掺杂非晶硅层的 厚度为50-350nm。
本发明还提供了一种钝化接触电池，所述钝化接触电池的钝化结构根据上述所述的方法制备。
本发明还提供了一种钝化接触结构的制备装置，所述装置用于制备上述所述的钝化接触电池中的钝化接触结构，其包括PECVD工艺腔和PVD工艺腔；其中，
所述PVD工艺腔至少包括第一独立腔体和第二独立腔体；或
所述PVD工艺腔包括一个整体腔体，所述整体腔体内按基片的行进方向设置有至少第一区域和第二区域。
本发明还提供了一种钝化接触电池的制备方法，其特征在于：包括以下步骤：
S0、对基片进行预处理，以在基片表面形成制绒结构；
S1、先将基片置于PECVD工艺腔内沉积隧穿氧化层，然后置于PVD工艺腔内沉积掺杂非晶硅层；所述PECVD工艺腔内设置有第一气体，所述PVD工艺腔内设置有第二气体和靶材；
所述靶材中包含至少一个含掺杂源的靶材，第二气体中不包含掺杂源气体；或，
所述靶材中包含至少一个含掺杂源的靶材，第二气体中包含掺杂源气体；或，
所述靶材中不包含含掺杂源的靶材，第二气体中包含掺杂源气体；
所述掺杂非晶硅层包括n层薄膜，n≥2，所述n层薄膜中至少包含一层掺杂层和一层非掺杂层；
S2、对基片进行退火处理，以激活所述掺杂非晶硅层，形成掺杂多晶硅层，完成钝化接触结构；
S3、对基片进行后处理。
本发明的实施包括以下技术效果：
本发明采用连续镀膜设备制备钝化接触结构，在同一个设备中连续完成隧穿氧化层及掺杂多晶硅层的制备，简化了制备工艺，提高了产能的同时也避免了分步制备隧穿氧化层和非晶硅层带来的界面污染，进而提高了钝化效果，提高了电池的电性能。同时，本发明采用PVD法制备非晶硅层，实现了原位掺杂，减少了后续单独的磷掺杂工序，同时避免了高温对隧穿氧化层的破坏而导致的钝化性能差的问题；再者，PVD方法工艺温度低，可大大减少由基片弯曲带来的不良。并且，本发明的制备方法可以根据工艺要求调试所需的掺杂配比，获得更好的钝化效果。最后，本发明的制备方法的工艺具有单面性，无绕镀产生，减少了后期清洗步骤。
附图说明
图1为本发明的实施例3和实施例4中的步骤S0后的电池结构截面示意图。
图2为本发明的实施例3和实施例4中的步骤S1”后的电池结构截面示意图。
图3为本发明的实施例3中的步骤S2后的电池结构截面示意图。
图4为本发明的实施例3中的步骤S31后的电池结构截面示意图。
图5为本发明的实施例3中的步骤S32后的电池结构截面示意图。
图6为本发明的实施例3中的步骤S33后的电池结构截面示意图。
图7为本发明的实施例3中的步骤S34后的电池结构截面示意图。
图8为本发明的实施例4中的步骤S2后的电池结构截面示意图。
图9为本发明的实施例4中的步骤S31后的电池结构截面示意图。
图10为本发明的实施例4中的步骤S32后的电池结构截面示意图。
图11为本发明的实施例4中的步骤S33后的电池结构截面示意图。
图12为本发明的实施例4中的步骤S34后的电池结构截面示意图。
图13为本发明的实施例3和实施例4中的制备装置的示意图。
图中，1-基片，2-隧穿氧化层，3-掺杂多晶硅层，4-氮化硅减反射层，5-正 面氧化铝钝化层，6-氮化硅减反射层，7-金属化浆料，8-发射极，9-背面氧化铝钝化层，10-叠层钝化减反射层，11-槽状结构。
具体实施方式
下面结合具体的实施例对本发明进行详细的说明。
具体实施例仅仅是对本发明的解释，并不是对本发明的限制，本领域技术人员在阅读完本说明书后可以根据需要对本实施例做出没有创造性贡献的修改，但只要在本发明的权利要求范围内都受到保护。
本发明提供一种钝化接触结构的制备方法，包括以下步骤：
S1、先将基片置于PECVD工艺腔内沉积隧穿氧化层，然后置于PVD工艺腔内沉积掺杂非晶硅层；所述PECVD工艺腔内设置有第一气体，所述PVD工艺腔内设置有第二气体和靶材；
所述靶材中包含至少一个含掺杂源的靶材，第二气体中不包含掺杂源气体；或，
所述靶材中包含至少一个含掺杂源的靶材，第二气体中包含掺杂源气体；或，
所述靶材中不包含含掺杂源的靶材，第二气体中包含掺杂源气体；
所述掺杂非晶硅层包括n层薄膜，n≥2，所述n层薄膜中至少包含一层掺杂层和一层非掺杂层；
S2、对基片进行退火处理，以激活所述掺杂非晶硅层，形成掺杂多晶硅层，完成钝化接触结构的制备。
本实施例实质上包含三种并列的技术方案：(1)、PVD工艺腔中的靶材为纯硅柱靶材，PVD工艺腔中的第二气体包含掺杂源气体，此时，PVD工艺腔中的基片的掺杂源仅为掺杂源气体，这种掺杂方法掺杂源更容易与基片反应形成掺杂非晶硅层，同时气体掺杂均匀性好，整面的掺杂方阻均匀，且气体掺杂更容易做到高浓度非晶硅层的掺杂；(2)、PVD工艺腔中的靶材为含掺杂源的靶 材，PVD工艺腔中的第二气体不包含掺杂源气体，此时，PVD工艺腔中的基片的掺杂源仅为含掺杂源的靶材，这种掺杂方式不需要使用到掺杂源气体，安全性能高，同时固体掺杂成本相对较低，节约成本，且固体掺杂更容易实现定量控制掺杂剂量，通过控制含掺杂源靶材的掺杂剂量来控制基片掺杂非晶硅薄膜的掺杂浓度；(3)、PVD工艺腔中的靶材为含掺杂源的靶材，PVD工艺腔中的气体包含掺杂源气体，此时，PVD工艺腔中的基片的掺杂源为含掺杂源的靶材和掺杂源气体，两者结合的这种掺杂方式，集合了气体掺杂和固体掺杂的优势，掺杂均匀，掺杂浓度可以做到更高，提升钝化接触结构的钝化水平，同时更高的掺杂浓度可以降低该钝化接触结构的接触电阻率和金属复合。
需要说明的是，本实施例中的气体为惰性气体和/或氢气，所述含掺杂源的气体为含磷掺杂气体或含硼掺杂气体，所述不含掺杂源的靶材为纯柱硅靶材。
本发明的制备方法艺简单、操作方便、安全可靠、质量稳定、生产效率高，易于实现大规模工业化生产，对于已存在的生产线易于更新、整合。
在一个实施例中，在步骤S1中，
所述PVD工艺腔包括m个独立腔体，m≥2；
所述m个独立腔体中至少存在一个独立腔体中设置有不含掺杂源的靶材，并通入不含掺杂源的气体，以使硅片在该腔体内形成本征非晶硅层；
所述m个独立腔体中至少存在一个独立腔体中设置有含掺杂源的靶材，并通入不含掺杂源的气体，以使硅片在该腔体内形成掺杂非晶硅层；或，所述m个独立腔体中至少存在一个独立腔体中设置不含掺杂源的靶材，并通入含掺杂源的气体，以使硅片在该腔体内形成掺杂非晶硅层；或，所述m个独立腔体中至少存在一个独立腔体中设置有含掺杂源的靶材，并通入含掺杂源的气体，以使硅片在该腔体内形成掺杂非晶硅层。
本实施例中，m个腔体的叠加，可以实现叠层掺杂非晶硅薄膜的沉积，最优化的掺杂非晶硅层的浓度为从隧穿氧化层界面向掺杂非晶硅层，掺杂浓度逐渐增加，靠近隧穿氧化层界面的低掺杂浓度可以使钝化接触结构的钝化水平更 高，靠近掺杂非晶硅层界面的高掺杂浓度可以使金属接触复合更低，接触电阻率更低，这种腔体的叠加使这种叠层渐变掺杂浓度的掺杂非晶硅薄膜更容易实现。
在一个实施例中，在步骤S1中，
所述PVD工艺腔包括一个整体腔体，所述整体腔体内按基片的行进方向设置有p个区域，p≥2；
所述p个区域中至少存在一个区域中设置有不含掺杂源的靶材，并通入不含掺杂源的气体，以使硅片在该区域形成本征非晶硅层；
所述p个区域中至少存在一个区域中设置有含掺杂源的靶材，并通入不含掺杂源的气体，以使硅片在该区域形成掺杂非晶硅层。
在一个实施例中，在步骤S1中，所述掺杂非晶硅层包括n层薄膜，n≥2，所述n层薄膜中至少包含一层掺杂层和一层非掺杂层。
本实施例通过将掺杂非晶硅层设置成包括n层薄膜，以形成多层隧穿结构，进而使金属接触复合与接触电阻率更容易获得最佳效果。
可选地，在步骤S1中，采用等离子体增强化学气相沉积法在PECVD工艺腔内沉积所述隧穿氧化层，所述第一气体至少包括氧气和/或一氧化氮。
可选地，在步骤S1中，采用磁控溅射法在PVD工艺腔内沉积本征非晶硅层，至少包括氩气、氢气或氧气中的一种气体或任几种气体组成的混合气体。可选地，在进行步骤S1之前，所述方法还包括：
S1’、在基片上设置带有图形的掩膜，以局部沉积隧穿氧化层和掺杂多晶硅层。
本实施例通过在基片上设置掩膜，以提高电池片的效率。
在一个实施例中，在步骤S1中，将基片置于PECVD工艺腔内沉积完隧穿氧化层之后，先对基片进行预热处理，然后置于PVD工艺腔内沉积掺杂非晶硅层。
优选地，在步骤S1中，PVD工艺腔的温度不大于350℃；掺杂非晶硅层 的厚度为50-350nm。
本发明还提供了一种钝化接触电池，所述钝化接触电池的钝化结构根据上述所述的方法制备。
本发明还提供了一种钝化接触结构的制备装置，所述装置用于制备上述所述的钝化接触电池中的钝化接触结构，其包括PECVD工艺腔和PVD工艺腔；其中，
所述PVD工艺腔至少包括第一独立腔体和第二独立腔体；或
所述PVD工艺腔包括一个整体腔体，所述整体腔体内按基片的行进方向设置有至少第一区域和第二区域。
本发明还提供了一种钝化接触电池的制备方法，包括以下步骤：
S0、对基片进行预处理，以在基片表面形成制绒结构；
S1、先将基片置于PECVD工艺腔内沉积隧穿氧化层，然后置于PVD工艺腔内沉积掺杂非晶硅层；所述PECVD工艺腔内设置有第一气体，所述PVD工艺腔内设置有第二气体和靶材；
所述靶材中包含至少一个含掺杂源的靶材，第二气体中不包含掺杂源气体；或，
所述靶材中包含至少一个含掺杂源的靶材，第二气体中包含掺杂源气体；或，
所述靶材中不包含含掺杂源的靶材，第二气体中包含掺杂源气体；
所述掺杂非晶硅层包括n层薄膜，n≥2，所述n层薄膜中至少包含一层掺杂层和一层非掺杂层；
S2、对基片进行退火处理，以激活所述掺杂非晶硅层，形成掺杂多晶硅层，完成钝化接触结构；
S3、对基片进行后处理。
本发明采用连续镀膜设备制备钝化接触结构，在同一个设备中连续完成隧穿氧化层及掺杂多晶硅层的制备，简化了制备工艺，提高了产能的同时也避免 了分步制备隧穿氧化层和非晶硅层带来的界面污染，进而提高了钝化效果，提高了电池的电性能。同时，本发明采用PVD法制备非晶硅层，实现了原位掺杂，减少了后续单独的磷掺杂工序，同时避免了高温对隧穿氧化层的破坏而导致的钝化性能差的问题；再者，PVD方法工艺温度低，可大大减少由基片弯曲带来的不良。并且，本发明的制备方法可以根据工艺要求调试所需的掺杂配比，获得更好的钝化效果。最后，本发明的制备方法的工艺具有单面性，无绕镀产生，减少了后期清洗步骤。
下面将以具体的实施例对本发明钝化接触结构的制备方法和钝化接触电池的制备方法进行详细地说明。
实施例1
本实施例对钝化接触结构的制备方法进行详细地说明。
步骤S0、选取N型基片1，对基片进行预处理，以在基片表面形成制绒结构，n型晶体硅基体的电阻率为0.3～5Ω·cm，厚度为80～200μm。
步骤S1、将步骤S0预处理后的基片1放入装载腔装载，并进入PECVD工艺腔，在PECVD工艺腔内通过等离子体激发生成隧穿氧化层2，PECVD工艺腔内通入的气体为氧气；在PECVD工艺腔完成隧穿氧化层2的沉积后，基片进入PVD工艺腔，PVD工艺腔包括两个独立腔体，工艺腔内通入氩气，第一个腔体内设置有一个纯硅柱靶材，第二个腔体设置有一个含磷掺杂源的靶材，通过磁控溅射的方法在基片表面沉积一层非晶硅薄膜，在沉积非晶硅薄膜的同时在第二个腔体中对非晶硅薄膜进行掺杂，该非晶硅薄膜包含2层结构的非晶硅层的，每层非晶硅层的厚度均为25～300nm，其中第一层为非掺杂非晶硅层，第二层为掺磷非晶硅层。
步骤S2、对基片进行退火处理，以激活所述掺杂非晶硅层，形成掺杂多晶硅层3，完成钝化接触结构的制备。
实施例2
本实施例对钝化接触结构的制备方法进行详细地说明。
步骤S0、选取P型基片1，对基片进行预处理，以在基片表面形成制绒结构，n型晶体硅基体的电阻率为0.1～5Ω·cm，厚度为80～200μm。
步骤S1、将步骤S0预处理后的基片放入装载腔装载，并进入PECVD工艺腔，在PECVD工艺腔内通过等离子体激发生成隧穿氧化层2，其厚度为0.5～3nm，PECVD工艺腔内通入的气体为氧气；在PECVD工艺腔完成隧穿氧化层2的沉积后，基片进入PVD工艺腔，PVD工艺腔包括两个独立腔体，工艺腔内通入氩气，第一个腔体内设置有一个纯硅柱靶材，第二个腔体设置有一个含磷掺杂源的靶材，通过磁控溅射的方法在基片表面沉积一层非晶硅薄膜，在沉积非晶硅薄膜的同时在第二个腔体中对非晶硅薄膜进行掺杂，该非晶硅薄膜包含2层结构的非晶硅层的，每层非晶硅层的厚度均为25～300nm，其中第一层为非掺杂非晶硅层，第二层为掺磷非晶硅层。
步骤S2、对基片进行退火处理，以激活所述掺杂非晶硅层，形成掺杂多晶硅层3，完成钝化接触结构的制备。
实施例3
本实施例对钝化接触电池的制备方法进行详细地说明。
步骤S0、选取N型基片1，对基片进行预处理，以在基片表面形成制绒结构，n型晶体硅基体的电阻率为0.3～5Ω·cm，厚度为80～200μm。完成本步骤之后的电池结构如图1所示。
S1”、对基片进行硼扩散，形成发射极8，并进行清洗。采用BBr 3气态源扩散，方阻80-200Ω/sq，表面浓度5e18cm -3～2e19cm -3。完成本步骤之后的电池结构如图2所示。
步骤S1、将步骤S1”预处理后的基片1放入图13中的装载腔装载，并进入PECVD工艺腔，在PECVD工艺腔内通过等离子体激发生成隧穿氧化层2，PECVD工艺腔内通入的气体为氧气；在PECVD工艺腔完成隧穿氧化层2的沉积后，基片进入PVD工艺腔，PVD工艺腔包括两个独立腔体，工艺腔内通入氩气，第一个腔体内设置有一个纯硅柱靶材，第二个腔体设置有一个含磷掺杂源 的靶材，通过磁控溅射的方法在基片背表面沉积一层非晶硅薄膜，在沉积非晶硅薄膜的同时在第二个腔体中对非晶硅薄膜进行掺杂，该非晶硅薄膜包含2层结构的非晶硅层的，每层非晶硅层的厚度均为25～300nm，其中第一层为非掺杂非晶硅层，第二层为掺磷非晶硅层。
步骤S2、对基片进行退火处理，以激活所述掺杂非晶硅层，形成掺杂多晶硅层3，完成钝化接触结构，退火温度860～950℃，退火时间为15～80min，该多晶硅薄膜退火后的方阻为20～100Ω/方块。完成本步骤之后的电池结构如图3所示。
步骤S3、对基片进行后处理，其包括：
步骤S31、在基片背面制备氮化硅减反射层4。完成本步骤之后的电池结构如图4所示。
步骤S32、在基片正面制备正面氧化铝钝化层5。完成本步骤之后的电池结构如图5所示。
步骤S33、在基片正面制备氮化硅减反射层6。完成本步骤之后的电池结构如图6所示。
步骤S34、在基片正面和背面采用丝网印刷金属化浆料7，烧结。完成本步骤之后的电池结构如图7所示。
实施例4
本实施例对钝化接触电池的制备方法进行详细地说明。
步骤S0、选取P型基片1，对基片进行预处理，以在基片表面形成制绒结构，n型晶体硅基体的电阻率为0.1～5Ω·cm，厚度为80～200μm。完成本步骤之后的电池结构如图1所示。
步骤S1”、对基片进行硼扩散，形成发射极8，并进行清洗。采用POCl 3气态源扩散，方阻40-200Ω/sq，表面浓度5e18cm -3～2e19cm -3。完成本步骤之后的电池结构如图2所示。
步骤S1、将步骤S1”预处理后的基片放入图13中的装载腔装载，并进 入PECVD工艺腔，在PECVD工艺腔内通过等离子体激发生成隧穿氧化层2，其厚度为0.5～3nm，PECVD工艺腔内通入的气体为氧气；在PECVD工艺腔完成隧穿氧化层2的沉积后，基片进入PVD工艺腔，PVD工艺腔包括两个独立腔体，工艺腔内通入氩气，第一个腔体内设置有一个纯硅柱靶材，第二个腔体设置有一个含磷掺杂源的靶材，通过磁控溅射的方法在正面基片表面沉积一层非晶硅薄膜，在沉积非晶硅薄膜的同时在第二个腔体中对非晶硅薄膜进行掺杂，该非晶硅薄膜包含2层结构的非晶硅层的，每层非晶硅层的厚度均为25～300nm，其中第一层为非掺杂非晶硅层，第二层为掺磷非晶硅层。
步骤S2、对基片进行退火处理，以激活所述掺杂非晶硅层，形成掺杂多晶硅层3，完成钝化接触结构，退火温度860～950℃，退火时间为15～80min，该多晶硅薄膜退火后的方阻为20～100Ω/方块。完成本步骤之后的电池结构如图8所示。
步骤S3、对基片进行后处理，其包括：
步骤S31、在基片背面制备背面氧化铝钝化层9。完成本步骤之后的电池结构如图9所示。
步骤S32、在基片正面和背面制备叠层钝化减反射层10。完成本步骤之后的电池结构如图10所示。
步骤S33、在基片背面激光开槽状结构11。完成本步骤之后的电池结构如图11所示。
步骤S34、在基片正面和背面采用丝网印刷金属化浆料7，烧结。完成本步骤之后的电池结构如图12所示。
最后应当说明的是，以上实施例仅用以说明本发明的技术方案，而非对本发明保护范围的限制，尽管参照较佳实施例对本发明作了详细地说明，本领域的普通技术人员应当理解，可以对本发明的技术方案进行修改或者等同替换，而不脱离本发明技术方案的实质和范围。

Claims (12)

  1. 一种钝化接触结构的制备方法，其特征在于：包括以下步骤：
    S1、先将基片置于PECVD工艺腔内沉积隧穿氧化层，然后置于PVD工艺腔内沉积掺杂非晶硅层；所述PECVD工艺腔内设置有第一气体，所述PVD工艺腔内设置有第二气体和靶材；
    所述掺杂非晶硅层包括n层薄膜，n≥2，所述n层薄膜中至少包含一层掺杂层和一层非掺杂层；所述靶材中包含至少一个含掺杂源的靶材，第二气体中不包含掺杂源气体；或，
    所述靶材中包含至少一个含掺杂源的靶材，第二气体中包含掺杂源气体；或，
    所述靶材中不包含含掺杂源的靶材，第二气体中包含掺杂源气体；
    S2、对基片进行退火处理，以激活所述掺杂非晶硅层，形成掺杂多晶硅层，完成钝化接触结构的制备。
  2. 根据权利要求1所述的制备方法，其特征在于，在步骤S1中，
    所述PVD工艺腔包括m个独立腔体，m≥2；
    所述m个独立腔体中至少存在一个独立腔体中设置有不含掺杂源的靶材，并通入不含掺杂源的气体，以使硅片在该腔体内形成本征非晶硅层；
    所述m个独立腔体中至少存在一个独立腔体中设置有含掺杂源的靶材，并通入不含掺杂源的气体，以使硅片在该腔体内形成掺杂非晶硅层；或，所述m个独立腔体中至少存在一个独立腔体中设置不含掺杂源的靶材，并通入含掺杂源的气体，以使硅片在该腔体内形成掺杂非晶硅层；或，所述m个独立腔体中至少存在一个独立腔体中设置有含掺杂源的靶材，并通入含掺杂源的气体，以使硅片在该腔体内形成掺杂非晶硅层。
  3. 根据权利要求1所述的制备方法，其特征在于，在步骤S1中，
    所述PVD工艺腔包括一个整体腔体，所述整体腔体内按基片的行进方向设 置有p个区域，p≥2；
    所述p个区域中至少存在一个区域中设置有不含掺杂源的靶材，并通入不含掺杂源的气体，以使硅片在该区域形成本征非晶硅层；
    所述p个区域中至少存在一个区域中设置有含掺杂源的靶材，并通入不含掺杂源的气体，以使硅片在该区域形成掺杂非晶硅层。
  4. 根据权利要求1-3任一项所述的制备方法，其特征在于，在步骤S1中，
    采用等离子体增强化学气相沉积法在PECVD工艺腔内沉积所述隧穿氧化层，所述第一气体至少包括氧气和/或一氧化氮。
  5. 根据权利要求1-3任一项所述的制备方法，其特征在于，在步骤S1中，
    采用磁控溅射法在PVD工艺腔内沉积本征非晶硅层，所述第二气体至少包括氩气、氢气或氧气中的一种气体或任几种气体组成的混合气体。
  6. 根据权利要求1-3任一项所述的制备方法，其特征在于，在进行步骤S1之前，所述方法还包括：
    S1’、在基片上设置带有图形的掩膜，以局部沉积隧穿氧化层和掺杂多晶硅层。
  7. 根据权利要求1或2所述的制备方法，其特征在于，在步骤S1中，
    先将基片置于PECVD工艺腔内沉积完隧穿氧化层之后，先对基片进行预热处理，然后置于PVD工艺腔内沉积掺杂非晶硅层。
  8. [根据细则26改正14.09.2021]　
    根据权利要求6所述的制备方法，其特征在于，将基片置于PECVD工艺腔内进行预热处理，或将基片转移至加热腔中进行预热处理。
  9. 根据权利要求1或2所述的制备方法，其特征在于，在步骤S1中，
    PVD工艺腔的温度不大于350℃；掺杂非晶硅层的厚度为50-350 nm。
  10. 一种钝化接触电池，其特征在于，所述钝化接触电池的钝化结构根据权利要求1-9任一项所述的方法制备。
  11. 一种钝化接触结构的制备装置，其特征在于，所述装置用于制备权利要求11所述的钝化接触电池中的钝化接触结构，其包括PECVD工艺腔和PVD 工艺腔；其中，
    所述PVD工艺腔至少包括第一独立腔体和第二独立腔体；或
    所述PVD工艺腔包括一个整体腔体，所述整体腔体内按基片的行进方向设置有至少第一区域和第二区域。
  12. 一种钝化接触电池的制备方法，其特征在于：包括以下步骤：
    S1、先将基片置于PECVD工艺腔内沉积隧穿氧化层，然后置于PVD工艺腔内沉积掺杂非晶硅层；所述PECVD工艺腔内设置有第一气体，所述PVD工艺腔内设置有第二气体和靶材；
    所述靶材中包含至少一个含掺杂源的靶材，第二气体中不包含掺杂源气体；或，
    所述靶材中包含至少一个含掺杂源的靶材，第二气体中包含掺杂源气体；或，
    所述靶材中不包含含掺杂源的靶材，第二气体中包含掺杂源气体；
    所述掺杂非晶硅层包括n层薄膜，n≥2，所述n层薄膜中至少包含一层掺杂层和一层非掺杂层；
    S2、对基片进行退火处理，以激活所述掺杂非晶硅层，形成掺杂多晶硅层，完成钝化接触结构；
    S3、对基片进行后处理。
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CN117525180B (zh) * 2024-01-05 2024-03-12 通威太阳能(眉山)有限公司 太阳电池及其制备方法、光伏组件
CN117525179B (zh) * 2024-01-05 2024-04-02 通威太阳能(眉山)有限公司 太阳电池及其制备方法、光伏组件

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