WO2015130334A1

WO2015130334A1 - Silicon solar cells with epitaxial emitters

Info

Publication number: WO2015130334A1
Application number: PCT/US2014/042333
Authority: WO
Inventors: James M. Gee; John Renshaw
Original assignee: Applied Materials, Inc.
Priority date: 2014-02-28
Filing date: 2014-06-13
Publication date: 2015-09-03

Abstract

Embodiments of the disclosure generally relate to forming solar cells having epitaxial emitters. The emitters of the solar cells, as well as the bases of the solar cells, are epitaxially grown in a process chamber using a template substrate to form an epitaxial substrate. During the formation process of the epitaxial substrate, dopants can be introduced into the process chamber to dope the emitters and the bases with desired dopant profiles and concentrations. In one example, the epitaxial material is silicon and the dopants are n-type and p-type dopants.

Description

SILICON SOLAR CELLS WITH EPITAXIAL EMITTERS

BACKGROUND OF THE DISCLOSURE

Field of the Disclosure

[0001] Embodiments of the disclosure generally relate to solar cells and methods of formation.

Description of the Related Art

[0002] Electric power can be generated by using solar cells to convert energy from the sun into a flow of electrons. The photovoltaic effect refers to photons of light exciting electrons into a higher state of energy, allowing them to act as charge carriers for an electric current. Solar cells produce direct current electricity from sun light which can be used to power equipment or to recharge a battery. Present solar cells, however, generally have inadequate efficiencies, e.g., inadequate amounts of solar energy are converted to electricity by the solar cells.

[0003] Therefore, there is a need for solar cells having greater efficiencies and methods of forming same.

SUMMARY OF THE DISCLOSURE

[0004] Embodiments of the disclosure generally relate to forming solar cells having epitaxial emitters. The emitters of the solar cells, as well as the bases of the solar cells, are epitaxially grown in a process chamber using a template substrate to form an epitaxial substrate. During the formation process of the epitaxial substrate, dopants can be introduced into the process chamber to dope the emitters and the bases with desired dopant profiles and concentrations. In one example, the epitaxial material is silicon and the dopants are n-type and p-type dopants.

[0005] In one embodiment, a method of forming a solar cell comprises epitaxially growing a first emitter including a p-type or n-type dopant, epitaxially growing a base on the first emitter, and epitaxially growing a second emitter including a p-type or n-type dopant. The second emitter is textured and a first passivation layer is applied to the first emitter. A second passivation layer is applied to the second emitter, a first metal contact is applied over the first emitter, and a second metal contact is applied over the second emitter.

[0006] In another embodiment, a solar cell comprises a monocrystalline silicon base, a first monocrystalline silicon emitter disposed on a first side of the monocrystalline silicon base, the first monocrystalline silicon emitter having a thickness within a range of about 5 microns to about 15 microns, and a second monocrystalline silicon emitter disposed on a second side of the monocrystalline silicon base. The second monocrystalline silicon emitter has a thickness within a range of about 5 microns to about 15 microns. The solar cell further comprises a first passivation layer disposed over the first monocrystalline silicon emitter, a first metal layer disposed over the first passivation layer, and a second metal layer disposed over the second passivation layer.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this disclosure and are therefore not to be considered limiting of its scope, for the disclosure may admit to other equally effective embodiments.

[0008] Figure 1 is a cross sectional perspective view of a processing chamber, according to one embodiment.

[0009] Figures 2A-2L illustrate a solar cell formation process, according to one embodiment.

[0010] Figures 3A-3B illustrate a flow diagram of a method of forming a solar cell, according to one embodiment.

[0011] Figures 4A-4G illustrate a solar cell formation process, according to another embodiment.

[0012] Figure 5 illustrates a flow diagram of a method of forming a solar cell, according to another embodiment.

[0013] Figures 6A-6F illustrate a solar cell formation process, according to another embodiment.

[0014] Figure 7 illustrates a flow diagram of a method of forming a solar cell, according to another embodiment.

[0015] Figures 8A-8D illustrate a solar cell formation process, according to another embodiment.

[0016] Figure 9 illustrates a flow diagram of a method of forming a solar cell, according to another embodiment.

[0017] Figures 10A-10G illustrate a solar cell formation process, according to another embodiment.

[0018] Figure 1 1 illustrates a flow diagram of a method of forming a solar cell, according to another embodiment.

[0019] Figure 12 illustrates a partial solar cell, according to another embodiment of the invention.

[0020] Figures 13A-13G illustrate a solar cell formation process, according to another embodiment.

[0021] Figure 14 illustrates a flow diagram of a method of forming a solar cell, according to another embodiment. [0022] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.

DETAILED DESCRIPTION

[0023] Embodiments of the disclosure generally relate to forming solar cells having epitaxial emitters. The emitters of the solar cells, as well as the base of the solar cells, are epitaxially grown in a process chamber using a template substrate to form an epitaxial substrate. During the formation process of the epitaxial substrate, dopants can be introduced into the process chamber to dope the emitters and the base with desired dopant profiles and concentrations. In one example, the epitaxial material is silicon and the dopants are n-type and p-type dopants. Solar cells formed according to embodiments described herein have greater conversion efficiencies than solar cells with solid-state-diffused emitters due at least partially to formation of emitters during epitaxial growth. Because the emitters are formed during an epitaxial growth process, the emitters can have greater thicknesses while having lower dopant concentrations.

[0024] Figure 1 is a cross sectional perspective view of a processing chamber 100 according to one embodiment. The processing chamber 100 has a chamber wall 102, a lid 104 and a bottom 106. The chamber wall 102 may be cylindrical and may be formed from clear quartz. The chamber wall

102, lid 104 and bottom 106 may define a processing region 108, and a cassette 1 10 may be disposed within the processing region 108. The cassette 1 10 may include a plurality of susceptors 1 12 in a stack-like configuration, and each susceptor 1 12 may support one or more substrates

1 14 on an upper surface thereof. The susceptors 1 12 may be configured to hold the substrates 1 14 for either single sided deposition or dual sided deposition. The cassette 1 10 may rotate continuously during the deposition process for improved deposition uniformity.

[0025] Above the lid 104 is a top cover 120 and a loading region 122 may be defined by the top cover 120. An opening 124 may be formed in the top cover 120 to facilitate ingress and egress of substrates 1 14 to and from the loading region 122. During loading/unloading of the substrates 1 14, the cassette 1 10 is vertically actuated into the loading region 122, and substrates 1 14 are loaded/unloaded through the opening 124.

[0026] A heating element 125 may be disposed adjacent to the chamber wall 102 for providing thermal energy to the processing region 108. The heating element 125 may be any suitable heating element. In one embodiment, the heating element 125 includes a plurality of infrared ("IR") lamps surrounding the cassette 1 10. In one embodiment, the IR lamps 125 surround the chamber wall 102. The arrangement of the lamps 125 may vary depending on the process. In one example, the IR lamps 125 may be circular. The IR lamps 125 may be stacked to provide axial multi-zone heating. In another embodiment, each lamp 125 is a linear lamp that is disposed perpendicular to a support surface of the susceptors 1 12. In such an embodiment, a plurality of the linear lamps 125 is arranged around the circumference of the chamber wall 102. Additionally or alternatively, the heating element 125 may include one or more inductive heaters. The inductive heater 125 may be a ferrite core coiled around the cassette 1 10, such as around the chamber wall 102. One or more wires may be wrapped around the ferrite core and each wire may be connected to a power source to form an electric circuit.

[0027] An optional reflector 127 surrounds the heating element 125 to more efficiently control heating of the processing region 108. The reflector 127 includes a plurality of curved annular rings and each ring circumscribes the outer circumference of each IR lamp 125. Thus, heat generated from the IR lamp 125 is directed toward the processing region 108. The reflector 127 may have cooling channels 128 disposed therein. Each cooling channel 128 may have an inlet 129 and an outlet 130 (one is shown) and the reflector 127 may be cooled with a coolant such as water flowing from the inlet 129 through the cooling channels 128 and out of the outlet 130. A chamber liner (not shown) may be disposed between the cassette 1 10 and the chamber wall 102. The chamber liner 202 may have the similar shape as the chamber wall 102, such as cylindrical and provides thermal uniformity and create an isothermal zone 131 within the processing region 108. The chamber liner may be made of silicon carbide coated graphite.

[0028] In addition to the heating element 125, a heating element 132 may be disposed above and/or below the cassette 1 10 to provide radial multi-zone heating. The heating element 132 may be any suitable heating element. In one embodiment, the heating element 132 is a resistive heating element that is made of solid silicon carbide or silicon carbide coated graphite. A thermal insulator 133 may be disposed between the heating element 132 and the lid 104/bottom 106.

[0029] A plurality of gas inlets 134 may be disposed through the heating element 125 on the chamber wall 102. In one embodiment, the gas inlets 134 are substantially perpendicular to the chamber wall 102. As illustrated in Figure 1 , the gas inlets 134 and the IR lamps 125 may be interleaved. In other words, each gas inlet 134 is disposed between two adjacent IR lamps 125. A plurality of purging gas lines (not shown) may be disposed between the chamber liner and the chamber wall 102. The purging gas lines may be substantially parallel to the chamber wall 102. During operation of the chamber 100, one or more process gases may be introduced into the chamber 100 to deposit a material, such as an epitaxial layer, on the substrates 1 14. During the deposition, the substrates 1 14 may be heated to a desired temperature. One or more substrates 1 14 may be processed simultaneously.

[0030] The edge of the cassette 1 10 may be coupled to a plurality of shafts 135 which are coupled to a rotor 136. The rotor 136 may be coupled to a stator 137. In one embodiment, the rotor 136 and the stator 137 are both permanent magnets, and the rotor 136 is magnetically coupled to the stator 137. The cassette 1 10 levitates and rotates continuously during operation. In another embodiment, the rotor 136 and the stator 137 are parts of a linear arc motor, and the linear arc motor rotates the cassette 1 10 continuously during operation.

[0031] Figures 2A-2L illustrate a solar cell formation process, according to one embodiment. Figures 3A-3B illustrates a flow diagram 350 of a method of forming a solar cell, according to one embodiment. To facilitate explanation of embodiments of the disclosure, Figures 2A-2L and 3A-3B will be explained in conjunction.

[0032] Figure 2A illustrates a substrate 1 14 positioned on a support, such as an electrode 212 within an electrolytic cell (not shown). In one example, the substrate may be a silicon substrate formed from monocrystalline silicon which may function as a template for epitaxial growth. While only a single substrate 1 14 is shown positioned on the electrode 212 for clarity, it is to be understood that multiple substrates 1 14 may be positioned on the electrode 212.

[0033] At operation 351 , the substrate 1 14 is exposed to an etchant solution, which may include hydrogen fluoride, isopropyl alcohol, and de- ionized water, to form a porous upper surface 240 on the substrate 1 14, as shown in Figure 2B. Ethanol, acetic acid, or other chemical agents may be used to adjust surface tension rather than, or in addition to, isopropyl alcohol. An electrical current is passed through the electrolytic solution and the substrate to anodically etch the surface. The same electrolytic solution could be used for the rear contact rather than an electrode 212. In one example, the porous upper surface 240 may be a "bi-porous" layer, e.g., may be a layer containing one or more degrees of porosity therein. For example, the porous upper layer 240 may have an upper portion with a lower porosity having a thickness of about 0.01 micrometers to about 2 micrometers, and a lower region with a higher porosity thereunder, having a thickness of about 0.1 micrometer to about 1 micrometers. The lower layer can function as a release layer in some processes to facilitate release of an epitaxial 214A (shown in Figure 2G) epitaxially grown on the substrate 1 14.

[0034] In operation 352, the substrate 1 14 having the porous upper layer 240 thereon is thermally treated, for example, annealed or crystallized, to form a smooth silicon surface on the porous upper layer 240, as shown in Figure 2C. The thermal treatment process may occur in a hydrogen environment and may be performed using various heating methods, including laser or lamp illumination. The smoothness of the upper layer 240 facilitates the formation of a high quality epitaxial material thereon.

[0035] In operation 353, a first epitaxial emitter 241 is epitaxially formed, such as grown, on an upper surface of the substrate 1 14, for example in the processing chamber 100. The first epitaxial emitter 241 may be formed in a vapor phase epitaxy process through the reaction of a silicon-containing precursor and a reducing agent, such as trichlorosilane and hydrogen, in the presence of a dopant, such as an n-type dopant or p-type dopant. However, it is contemplated that other silicon-containing precursors, such as dichlorosilane, silicon tetrachloride, silane, or disilane may be utilized. Suitable n-type dopant gases include phosphine (PH₃), phosphoryl trichloride (POCI₃) or other phosphorus, arsenic, or antimony containing compounds. Suitable p-type dopants include borane or diborane, or other boron, aluminum, or gallium containing compounds. The first epitaxial emitter 241 may have a dopant concentration within a range of about 1 x10¹⁷ to about 1 x10¹⁸ atoms/cm³, and a thickness within a range of about 1 micrometers to about 15 micrometers, such as about 5 micrometers to about 10 micrometers. The epitaxial formation process may occur at a temperature of about 1200 degrees Celsius or less, and a pressure of about 1 atmosphere or less.

[0036] In operation 355, after the formation of the first epitaxial emitter 241 , a base layer 242 is epitaxially formed on the on the first epitaxial emitter 241 as shown in Figure 2E. The base layer 242 is generally formed using the same silicon-containing precursor and reducing agent as the first epitaxial emitter 241 , for example, trichlorosilane and hydrogen. The base layer 242 may have a thickness within a range of about 1 to about 200 microns. In one example, the formation of the first epitaxial emitter 241 and the base layer 242 is a continuous process. In such a process, the flow of the dopant gas may be halted, reduced in concentration, or changed to a different dopant with reduced concentration while maintaining the flow of the silicon-containing precursor and reducing agent, after formation of the first epitaxial emitter 241 . The dopant concentration in the base may also be graded {e.g., changed in continuous manner with thickness) to provide an internal electrical field to aid collection of photogenerated carriers. While figure 2E illustrates the first epitaxial emitter 241 and the base 242 as two different layers, it is to be understood that the first epitaxial emitter 241 and the base 242 may be one continuous epitaxial material, while each of the first epitaxial emitter 241 and the base 242 has a different dopant concentration and/or profile.

[0037] In operation 356, a second epitaxial emitter 243 is formed on the base layer 242, as shown in Figure 2F. The second epitaxial emitter 243 is formed similar to the first epitaxial emitter 241 ; however, the second epitaxial emitter 243 includes a dopant of the opposite conductivity type. For example, if the first epitaxial emitter 241 is doped with a p-type dopant, the second epitaxial emitter 243 may be doped with an n-type dopant, or vice versa. The second epitaxial emitter 243 may be formed in a continuous manner from the base 242 using the same silicon-containing precursor and reducing agent as the base 242. The second epitaxial emitter 243 may have a dopant concentration within a range of about 5x10¹⁶ to about 1 x10¹⁸ atoms/cm³, and a thickness within a range of about 1 micrometers to about 15 micrometers. The dopant concentration of either emitter 241 and 243 may be changed in a continuous manner to form an internal electrical field to aid collection of photogenerated carriers. [0038] In operation 357, the first epitaxial emitter 241 , the base 242, and the second epitaxial emitter 243, collectively referred to as an epitaxial 214A, are removed from the underlying template substrate 1 14, as illustrated in Figure 2G. The epitaxial 214A may be mechanically, energetically, or chemically cleaved from the substrate 214. If any of the porous layer 240 remains on the epitaxial 214A, the porous layer 240 present on the epitaxial 214A may be removed by etching, lapping, or the like.

[0039] In operation 358, a first surface 244 of the epitaxial substrate (e.g., the light receiving surface of the final device) is textured, for example, by exposure to an etchant such as potassium hydroxide, to reduce the light- reflecting qualities of the final device. While Figure 2H illustrates the second epitaxial emitter 243 as being the light receiving surface, it is contemplated that the first epitaxial layer 241 may be on the light receiving surface. In such an embodiment, the texturing operation may also be used to remove any residual porous material adhering to the epitaxial 214A. Thus, a separate removal operation would be unnecessary.

[0040] In operation 359, a selective emitter process is performed on the first surface 244 of the epitaxial 214A, as illustrated in Figure 2I. The selective emitter process may be performed using masked ion implantation or a dopant paste. In one example, the dopant paste may be printed on the surface and exposed to a laser or other heat source to drive the dopant into the second epitaxial emitter 243. The dopants introduced by ion implantation may be activated by a high-temperature anneal that may be performed in oxygen ambient. The oxidation of the surface may be useful for passivation of defects on the surface. The selective emitter process creates regions of higher dopant concentration than the emitter 243, for example n++ or p++ contact regions 245, on the first surface 244 to facilitate ohmic contact with a metal contact or electrode subsequently disposed on the first surface 244. The contact regions 245 are formed in a pattern corresponding to the metal contact. In one example, the n++ or p++ concentration may be about 5x10¹⁹ atoms/cm³ or greater, such as about 1x10²⁰ atoms/cm³ or greater.

[0041] In operation 360, a passivation layer 246, for example, silicon dioxide, silicon nitride, or aluminum oxide, is deposited on the first surface 244, as shown in Figure 2J. The passivation layer 246 reduces recombination at the light receiving surface. The passivation layer may be deposited by chemical vapor deposition, atomic layer deposition, plasma-enhanced chemical vapor deposition, and the like, using appropriate precursor gas and reducing or oxidizing agent.

[0042] In operation 361 , a passivation layer 248 is deposited on a second surface {e.g., back surface or non-light-receiving surface) 249, as shown in Figure 2K. The passivation layer 248 is similar to the passivation layer 246, and may be formed in a similar manner. In one embodiment, the passivation layers 246 and 248 may be formed simultaneously, or in immediate succession within the same tool.

[0043] In operation 362, a metal contact 247 is formed on the first surface 244 of the epitaxial 214A, as shown in Figure 2K. The metal contact 247 may be applied by screen printing one or more conductive pastes on the first surface 244, and then thermally treated to remove solvents {e.g., "dry"). The conductive paste may include one or more metals such as silver or aluminum in a polymer matrix. In operation 363, one or more vias 270 may be formed, such as by laser scribing, in the second surface 249 of the epitaxial 214A through the passiviation layer 248. The vias 270 preferably only scribe the passivation layer 248 and expose the surface of the epitaxial layer 241 . It is contemplated that formation of the vias 270 may occur prior to operation 362, but subsequent to operation 361 .

[0044] In operation 364, a metal layer 271 is formed over the second surface 249 of the epitaxial 214A. The metal layer 271 is deposited on the passivation layer 248 and in the vias 270. The metal layer 271 may include one or more conductive materials, such as silver or aluminum, and may be formed using screen printed conductive pastes, chemical vapor deposition, atomic layer deposition, physical vapor deposition, or the like. In one example, the metal layer 271 includes aluminum, and after depositing the metal layer 271 , the metal layer 271 and the metal contact 247 are thermally treated or fired to a temperature above the eutectic point of silicon and aluminum, thus resulting in a silicon-aluminum alloy. The silicon-aluminum alloy forms a heavily doped p++ region, thereby facilitating ohmic contact between the aluminum and the silicon. The metal contact 247 may be simultaneously sintered through the front passivation layer 246 to make ohmic contact to the front emitter 243. The resulting structure shown in Figure 2L illustrates a solar cell 272 formed according to one embodiment described herein.

[0045] Figures 2A-2L and Figures 3A-3B illustrate one embodiment of forming a solar cell 272; however, additional embodiments are also contemplated. For example, it is contemplated that operations 363 and 364 may be performed before operation 362.

[0046] Figures 4A-4G illustrate a solar cell formation process, according to another embodiment. Figure 5 illustrates a flow diagram of a method of forming a solar cell, according to another embodiment. To facilitate explanation, Figures 4A-4G and 5 will be explained in conjunction. Figures 4A-4G and 5 illustrate an alternative embodiment for forming a solar cell, and may replace Figures 2G-2I, and operations 357-364.

[0047] In operation 581 , which may occur after operation 356 of Figure 3, a highly-doped emitter surface 490 is epitaxially formed on the second epitaxial emitter 243, as shown in Figure 4A. The highly-doped emitter surface 490 is of the same dopant type (e.g., p-type or n-type) as the second epitaxial emitter 243, but has a greater dopant concentration. For example, the highly- doped emitter surface 490 may be an n++ or p++ layer having a thickness of about 2 micrometers or less, such as about 0.1 to about 1 micrometer. The highly-doped emitter surface 490 facilitates ohmic contact with a metal contact or grid subsequently deposited thereon. Alternatively, it is contemplated that a highly doped emitter surface may be formed on the second epitaxial emitter 243 using gaseous diffusion, ion implantation, or a dopant paste.

[0048] In operation 582, an epitaxial substrate 414a is removed from the template substrate 1 14, as similarly described in operation 357. The epitaxial substrate 414a illustrated in Figure 4B is similar to the epitaxial substrate 1 14a; however, the epitaxial substrate 414a includes the highly-doped emitter surface 490. In operation 583, a mask 491 is disposed over the first surface 444 on the highly-doped emitter surface 490, as illustrated in Figure 4C. The mask 491 may be a wet etch or dry etch mask, may be applied by screen printing or ink-jet printing, and may include polymers.

[0049] In operation 584, the first surface 444 of the epitaxial substrate 414a is exposed to an etchant, such as a wet etchant or dry etchant, to texture the first surface 444, as shown in Figure 4D. Exposure to the etchant results in removal of exposed portions of the highly-doped emitter surface 490, resulting in texturing of the second epitaxial emitter 243. The remaining portions of the highly doped emitter surface 490 define contact regions upon which a metal contact is subsequently disposed. In operation 585, the mask 491 is removed, as shown in Figure 4E. Alternatively, it is contemplated that the mask may be partially or completely removed during the etching process of operation 584.

[0050] In operation 586, passivation layers 446 and 448 are deposited on the first surface 444 and a second surface 449, as shown in Figure 4F. The passivation layer 446 and 448 are similar to passivation layers 246 and 248, and may be formed in a similar manner. In operation 587, a metal contact 447 is deposited on the first surface 444 in contact with the remaining portions of the highly-doped emitter surface 490. In operation 588, vias 470 are formed in the second surface 449 of the epitaxial substrate 414a, as shown in Figure 4G and as similarly described with respect to operation 363. In operation 589, a metal layer 471 is deposited over the second surface 449 of the epitaxial substrate 414a in contact with the passivation layer 448 and within the vias 470, as shown in Figure 4G. Deposition of the metal layer 471 is similar to the deposition of the metal layer 271 described with respect to operation 364, and results in a solar cell 472.

[0051] Solar cells formed using embodiments described herein have higher efficiencies than solar cells having emitters formed using dopant pastes, implanted, diffused emitters {e.g., solid-state diffusion). Emitters which are formed during an epitaxial growth process, such as emitters described herein, can be formed having a greater depth or thickness of dopant material, with a lower dopant concentration, which is generally not attainable using dopant pastes or gaseously-diffused emitters. For example, emitters formed using solid state diffusion may have thickness or depth less than 1 micron, such as about 3000 angstroms, and relatively high surface dopant concentrations, such as 1 x10²⁰ to about 3x10²⁰ atoms/cm³. In contrast, emitters formed during epitaxial growth processes according to embodiments herein have relatively smaller dopant concentrations, and thus, avoid many of the negative qualities of more highly doped silicon, such as carrier recombination, bandgap narrowing, and crystallographic defects.

[0052] Table 1 illustrates a comparison between solar cells formed with epitaxial emitters and solid-state-diffused emitters. The epitaxial emitter solar cell includes n+ and p+ emitters having thickness of about 5 microns and dopant concentrations of about 1x10¹⁷ atoms/cm³. The solid-state-diffused emitter solar cell includes n+ and p+ emitters having a thickness of about 3000 angstroms, and dopant concentrations of about 3x10²⁰ atoms/cm³. As illustrate in Table 1 , solar cells formed according to embodiments described herein have more desirable short circuit current density, open circuit voltage, and efficiency. Additionally, solar cells of the present embodiments may have a desirable reduction in saturation current density. Solid-state-diffused emitter solar cells may have a saturation current density of about 100 fA cm² or more, while solar cells formed according to embodiments described herein have a saturation current density of about 1 to about 10 fA cm².

Table 1

[0053] Example 1 : A solar cell is formed by first growing an epitaxial n+ emitter on a template substrate. The epitaxial n+ emitter is formed by reaction of trichlorosilane and hydrogen in the presence of POCI3 at a temperature less than about 1200 degrees Celsius and a pressure of about 1 atmosphere. The n+ emitter was formed to a thickness of about 5 microns and had a dopant concentration of about 3x10¹⁷ atoms/cm³. The flow rate of the trichlorosilane and hydrogen were maintained while the flow rate of the n+ dopant was halted to epitaxially form an epitaxial base. The base was formed to a thickness of about 100 microns. Then, the flow of the p-type dopant was halted and flow of the n-type dopant, such as diborane, was commenced to form an epitaxial n-type emitter having a thickness of about 5 microns and a concentration of about 3x10¹⁷ atoms/cm³. The flow of the n-type dopant was then further increased to form a heavily doped (n++) surface on the n-type emitter, for example, having a concentration of about 1 x10²⁰ atoms/cm³ or more_. The epitaxial layers where then removed together from the template substrate.

[0054] The n-type emitter was then patterned and etched, a passivation layer was applied, and a silver contact layer was disposed thereon in contact with the n++ emitter surface. Similarly, a passivation layer was applied to the p+ emitter, vias were scribed, and an aluminum layer was applied over the p+ emitter on the back surface passivation layer and within the vias. The solar cell was fired to form a silicon-aluminum eutectic layer. It is to be noted that other examples and embodiments are also contemplated.

[0055] Figures 6A-6F illustrate a solar cell formation process, according to another embodiment. Figure 7 illustrates a flow diagram of a method of forming a solar cell, according to another embodiment. To facilitate explanation, Figures 6A-6D and 7 will be explained in conjunction. Figures 6A-6D and 7 illustrate an alternative embodiment for forming a solar cell, and may replace Figures 2H-2K, and operations 358-362.

[0056] In operation 766 of flow diagram 765, a polysilicon layer 692 is deposited on the upper or light receiving surface of the epitaxial 214A, resulting in an epitaxial substrate 614A. The polysilicon layer 692 may be deposited in the same process chamber as is used for the formation of first epitaxial emitter 241 , the base 242, and the second epitaxial emitter 243. It is contemplated that the process chamber may be adapted to perform both epitaxial and polysilicon formation through the adjustment of one or more process parameters, such deposition temperature, process gas flow rate, and process gas composition. In one example, silane may be utilized to form the polysilicon layer 692. The polysilicon layer 692 may be deposited to a thickness of about 0.1 microns or greater, such as about 0.3 microns or greater.

[0057] The inclusion of the polysilicon layer 692 facilitates the formation of a passivated contact, thus reducing recombination loss at an interface of a metal contact subsequently deposited in electrical contact with the epitaxial substrate 614A. The inclusion of the polysilicon layer 692 allows for band gap tailoring to selectively allow only a single carrier type to pass therethrough. In one example, the polysilicon layer 692 may be a heavily doped polysilicon layer, such as an n++ or p++ polysilicon layer. In such an embodiment, a dopant gas, such as a p-type or n-type dopant gas, may be included with the silicon source gas, such as silane or trichlorosilane, during the polysilicon formation process, to facilitate formation of a doped polysilicon layer having the desired dopant profile and concentration.

[0058] A thin oxide between the polysilicon and monocrystalline silicon surface may facilitate improvement of electrical performance. This interfacial oxide layer could be generated in the same tool after the epi emitter deposition and before the polysilicon deposition. Alternatively, the interfacial oxide growth (chemical or thermal oxidation) and polysilicon deposition could be performed after the epitaxial silicon deposition in a separate tool(s).

[0059] In operation 767, an etch resist mask 691 is applied to a surface of the polysilicon layer 692 to facilitate selective removal of portions of the polysilicon layer 692, as shown in Figure 6B. The etch resist mask 691 may be a wet etch or dry etch mask, may be applied by screen printing or ink-jet printing, and may include polymers. In operation 768, a texturing operation is performed. The texturing operation 768 is similar to operation 358, however, masked portions of the polysilicon layer 692 and the second epitaxial emitter 243 are not textured. In operation 768, the texturing agent and the degree of exposure may be selected to remove undesired portions of the polysilicon layer 692 and to adequately texture the surface of the second epitaxial emitter 243, as shown in Figure 6C. Optionally, the etch resist mask 691 may be removed during operation 358 via etching of the mask, or alternatively, the mask 691 may be removed in a separate removal process.

[0060] In operation 769, the etch resist mask 691 is removed (if not previously removed), as shown in Figure 6D. In operation 770, a passivation layer 646 is applied over the second epitaxial emitter 243 and the polysilicon layer 692, as shown in Figure 6E. In operation 771 , a metal contact 247 is deposited on a surface of the passivation layer 646 over the remaining portion of the polysilicon layer 692, as shown in Figure 6F. While only a single metal contact 247 is shown, it is to be understood that multiple metal contacts 247 may be formed, and may include, for example, gridlines and/or fingers. Subsequent to operation 771 , the back surface or non-light receiving surface 649 may be subjected to operations 363 and 364 shown in Figures 3A-3B. The metal contact 247 may then be cured, firing through the passivation layer 646.

[0061] Figures 8A-8D illustrate a solar cell formation process, according to another embodiment. Figure 9 illustrates a flow diagram of a method of forming a solar cell, according to another embodiment. To facilitate explanation, Figures 8A-8D and 9 will be explained in conjunction. Figures 8A-8D and 9 illustrate an alternative embodiment for forming a solar cell, and may replace Figures 2I-2K, and operations 358-362.

[0062] In operation 976 of flow diagram 975, an intrinsic-amorphous silicon layer 993 is deposited on an upper or light-receiving surface of an epitaxial 214A, thus resulting in epitaxial substrate 914A, as shown in Figure 8A. The intrinsic-amorphous silicon layer 993 may be formed suing plasma-enhanced chemical vapor deposition (PECVD), and may occur in a separate chamber than formation of the first epitaxial emitter 241 , the base 242, and the second epitaxial emitter 243. In one example, a silicon-containing source gas, such as silane, may facilitate the formation of the intrinsic-amorphous silicon layer 993. In operation 977, a doped amorphous silicon layer 994 is deposited on the intrinsic amorphous silicon layer 993, as shown in Figure 8B. The doped amorphous silicon layer 994 may be deposited using a silicon-containing source gas, such as silane, and a dopant-containing source gas, via PECVD. The doped amorphous silicon layer 994 may be p-type or n-type doped, such as a p+ or n+ layer having a dopant concentration within a range of about 1 x10¹⁸ atoms/cm³ to about 1 x10²⁰ atoms/cm³, such as about 1 x10¹⁹ atoms/cm³.

[0063] In operation 978, a conductive oxide layer 995 is deposited on the doped amorphous silicon layer 994, as shown in Figure 8C. The conductive oxide layer 995 may be formed in the same PECVD chamber as the intrinsic- amorphous silicon layer 993 and the doped amorphous silicon layer 994. The conductive oxide layer 995 may be, for example, aluminum zinc oxide (AlZnO), indium tin oxide (ITO), fluorine-doped tin oxide (FTO), and doped zinc oxide. Each of the intrinsic amorphous silicon layer 993, the doped amorphous silicon layer 994, and the conductive oxide layer 995 may have a thickness of about 3 to about 50 nanometers, such as about 5 to 15 nanometers, such as about 10 nanometers.

[0064] In operation 979, metal contacts 247 are deposited on the conductive oxide layer 995, as shown in Figure 8D. The metal contacts 247 may be optionally cured in operation 979, or may be cured in a later operation. Optionally, prior to operation 979, the back surface or non-light receiving surface 949 may be subjected to deposition of intrinsic and doped amorphous-silicon layers, transparent conducting oxide, and metal deposition. The doped amorphous-silicon layer would use the conductivity type as the epitaxial emitter on the back surface. The amorphous-silicon layers on front and rear could be deposited in the same tool. Similarly, the transparent conducting oxide layers could be deposited in the same tool. Metal layers and contacts may be cured after deposition thereof.

[0065] The inclusion of the intrinsic amorphous silicon layer 993, the doped amorphous silicon layer 994, and the conductive oxide layer 995 facilitates the formation of a passivated contact to reduce recombination at a location between the metal contact and the epitaxial substrate 814A. Thus, the intrinsic amorphous silicon layer 993, the doped amorphous silicon layer 994, and the conductive oxide layer 995 collectively function similar to the polysilicon layer 692 of Figure 6. Moreover, the lateral conductivity charge carriers attributable to the second epitaxial emitter 243 allows for formation of the intrinsic amorphous silicon layer 993, the doped amorphous silicon layer 994, and the conductive oxide layer 995 having relatively reduced thicknesses, such less than 50 nanometers, for example, about 10 nanometers. It is contemplated that substrates lacking an epitaxially-formed emitter adjacent the intrinsic amorphous silicon layer 993, the doped amorphous silicon layer 994, and the conductive oxide layer 995 would otherwise require greater thicknesses and/or doping of the intrinsic amorphous silicon layer 993, the doped amorphous silicon layer 994, and the conductive oxide layer 995, which would then be responsible for a greater portion of carrier mobility. However, the reduced thicknesses and/or reduced doping of the intrinsic amorphous silicon layer 993, the doped amorphous silicon layer 994, and the conductive oxide layer 995 allows a greater amount of sunlight to penetrate the intrinsic amorphous silicon layer 993, the doped amorphous silicon layer 994, and the conductive oxide layer 995, thereby increasing the amount of energy generated by the finished device. Moreover, the presence of the intrinsic amorphous silicon layer 993 on the final device may facilitate increased passivation of the light-receiving surface.

[0066] Figures 10A-10G illustrate a solar cell formation process, according to another embodiment. Figure 1 1 illustrates a flow diagram of a method of forming a solar cell, according to another embodiment. To facilitate explanation, Figures 10A-10G and 1 1 will be explained in conjunction. Figures 10A-10G and 1 1 illustrate an alternative embodiment for forming a solar cell, and may replace Figures 2H-2K, and operations 358-362. The embodiment of Figure 1 1 is similar to the embodiment of Figure 9, however, the intrinsic amorphous silicon layer 993, the doped amorphous silicon layer 994, and the conductive oxide layer 995 are etched to remove portions thereof from between metal contacts.

[0067] Flow diagram 1 101 begins at operation 1 102, in which the intrinsic amorphous silicon layer 993 is deposited on an epitaxial 214A, as shown in Figure 10A and as similarly described with respect to operation 976 of Figure 9. In operation 1 103, the doped amorphous silicon layer 994 is deposited on the intrinsic amorphous silicon layer 993, as shown in Figure 10B and as similarly described in operation 977 of Figure 9. In operation 1 104, the conductive oxide layer 995 is deposited on the doped amorphous silicon layer 994, as shown in Figure 10C and as similarly described in operation 978 of Figure 9.

[0068] In operation 1 105, the intrinsic amorphous silicon 993, doped amorphous silicon layer 994, and the conductive oxide layer 995 are patterned using a laser (not shown) to selectively remove portions of the amorphous silicon layers 993 and 994 and the conductive oxide layer 995, as shown in Figure 10D. The laser may be configured to remove selective portions of the doped amorphous silicon layer 994 and the conductive oxide layer 995 while not removing the intrinsic amorphous silicon layer 993. In another embodiment, it is contemplated that an etchant and one or more masks, rather than a laser, may be utilized to remove selective portions of the doped amorphous silicon layer 994 and the conductive oxide layer 995.

[0069] In operation 1 106, a texturing operation is performed to texture the epitaxial emitter layer 243, as shown in Figure 10E. The texturing operation 1 106 is similar to the texturing operation 768. Although not shown, a mask may be disposed over the remaining portions of the doped amorphous silicon layer 994 and the conductive oxide layer 995 to prevent or reduce texturing of the doped amorphous silicon layer 994 and the conductive oxide layer 995. In operation 1 107, metal contacts 247 are deposited on the conductive oxide layer 995, as shown in Figure 10F. The metal contacts 247 may be optionally cured in operation 1 107, or may be cured in a later operation. In operation 1 108, a passivation layer 246 is selectively deposited over the textured intrinsic amorphous silicon layer 993, as shown in Figure 10G.

[0070] Subsequent to operation 1 108, the back surface or non-light receiving surface 949 may be subjected to operations 363 and 364 shown in Figures 3A-3B. Additionally, it is contemplated that the epitaxial substrate 814A may include a passivation layer, similar to passivation layer 248 shown in Figure 2K, on a second or back surface thereof {e.g., as formed in operation 361 ), which may occur prior to operation 363. Metal layers and contacts may be cured after deposition thereof. [0071] Figure 12 illustrates an epitaxial substrate, according to another embodiment of the invention. The epitaxial substrate 1214A of Figure 12 is similar to the epitaxial substrate illustrated in Figure 10G; however, the intrinsic amorphous silicon layer 993 of the epitaxial substrate 1214A is patterned concurrently with the doped amorphous silicon layer 994 and the conductive oxide layer 995 in operation 1 105. Thus, the passivation layer 246 is deposited on the second epitaxial emitter 243. Patterning of the intrinsic amorphous silicon layer 993 may allow a greater amount of solar radiation to reach the first epitaxial emitter 241 , the base 242, and/or the second epitaxial emitter 243, thus increasing the amount of power generated by the finished device.

[0072] Figures 13A-13G illustrate a solar cell formation process, according to another embodiment. Figure 14 illustrates a flow diagram of a method of forming a solar cell, according to another embodiment. To facilitate explanation, Figures 13A-13G and 14 will be explained in conjunction. Figures 13A-13G and 14 illustrate an alternative embodiment for forming a solar cell, and may replace Figures 2H-2K, and operations 358-362.

[0073] Flow diagram 1420 begins at operation 1421 in which an oxide layer 1396, such as a silicon oxide layer, is deposited an epitaxial 214A, as shown in Figure 13A. In one example, oxide layer 1396 may be a tunnel oxide having a thickness less than about 10 nanometers, such as less than about 3 nanometers. The oxide layer 1396 may be deposited on an upper surface of the epitaxial emitter 243 by atomic layer deposition, or other suitable formation methods, such as thermal oxidation at temperatures below about 500 degrees Celsius. In operation 1422, a doped polysilicon layer 692 is deposited on the oxide layer 1396, as shown in Figure 13B. The doped polysilicon layer 692 is similar to the doped polysilicon layer 692 described with respect to Figure 6, and may be formed in a similar manner.

[0074] In operation 1423, a mask, such as an etch resist mask 691 , is deposited on the doped polysilicon layer 692, as shown in Figure 13C. The doped polysilicon layer 692 facilitates selective patterning of the oxide layer 1396 and the doped polysilicon layer 692. In operation 1424, the oxide layer 1396 and the doped polysilicon layer 692 are patterned, as shown in Figure 13D. The oxide layer 1396 and the doped polysilicon layer 692 may be patterned, for example, by exposure to an etchant solution, dry etching, or by laser, in order to remove regions of the oxide layer 1396 and the doped polysilicon layer 692. In operation 1425, a texturing etching is performed to texture the second epitaxial emitter 243 and to optionally remove the mask 691 , as shown in Figure 13E. It is contemplated that the mask 691 may be removed in a separate operation, rather than concurrently with the texturing of the second epitaxial emitter 243.

[0075] In operation 1426, a passivation layer 246 is deposited on the second epitaxial emitter 243, as shown in Figure 13F. Subsequently, in operation 1427, metal contacts 247 are formed on the polysilicon layer 692 to facilitate an electrical connection with the finished device. Subsequent to operation 1427, the back surface or non-light receiving surface 1449 may be subjected to operations 363 and 364 shown in Figures 3A-3B. Additionally, it is contemplated that a passivation layer, such as the passivation layer 248 shown in Figure 2K, may be applied to the non-light receiving surface 1449 prior to operation 363. Metal layers and contacts may be cured after deposition.

[0076] In one example, the utilization of polysilicon to form passivated contacts, rather than amorphous silicon, may facilitate reduced processing costs. In one example, polysilicon may be subjected to temperatures of 800 degrees Celsius, 900 degrees Celsius, or more, during a metal contact curing process without converting the polysilicon to crystalline silicon. Thus, cheaper metal pastes may be utilized to form the metal contacts, rather than more expensive low-temperature alternatives.

[0077] Benefits of solar cells described herein generally include increased efficiency compared to previously-known solar cells. [0078] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims

What is claimed is:

1 . A method of forming a solar cell, comprising:

epitaxially growing a first emitter including a p-type or n-type dopant;

epitaxially growing a base on the first emitter;

epitaxially growing a second emitter including a p-type or n-type dopant;

texturing the second emitter;

applying a first passivation layer to the first emitter;

applying a second passivation layer to the second emitter;

applying a first metal contact over the first emitter; and

applying a second metal contact over the second emitter.

2. The method of claim 1 , further comprising forming a heavily doped emitter surface having a dopant concentration of about 1 x10²⁰ atoms/cm³ or more on the second emitter before texturing the second emitter.

3. The method of claim 2, further comprising epitaxially growing a heavily doped emitter surface on the second emitter before texturing the second emitter.

4. The method of claim 2, further comprising forming the heavily doped emitter surface on the second emitter before texturing the second emitter by gaseous diffusion, ion implantation, or deposited dopant source and diffusion.

5. The method of claim 1 , further comprising exposing the second emitter to a dopant paste or ion implant to selectively form a heavily doped emitter surface.

6. The method of claim 1 , wherein the solar cell comprises epitaxial silicon.

7. The method of claim 1 , wherein the first emitter is either n-type doped or p- type doped, and the second emitter is the other of n-type doped or p-type doped different than the first emitter.

8. A solar cell, comprising:

a monocrystalline silicon base;

a first monocrystalline silicon emitter disposed on a first side of the monocrystalline silicon base, the first monocrystalline silicon emitter having a thickness within a range of about 5 microns to about 15 microns;

a second monocrystalline silicon emitter disposed on a second side of the monocrystalline silicon base, the second monocrystalline silicon emitter having a thickness within a range of about 5 microns to about 15 microns;

a first passivation layer disposed over the first monocrystalline silicon emitter; a first metal layer disposed over the first passivation layer; and

a second metal layer disposed over the second passivation layer.

9. The solar cell of claim 8, wherein the first monocrystalline silicon emitter and the second monocrystalline silicon emitter include dopants having a concentration within a range of about 1 x10¹⁷ to about 1 x10¹⁸ atoms/cm³.

10. The solar cell of claim 8, further comprising a second passivation layer disposed over the second monocrystalline silicon emitter.

1 1 . The solar cell of claim 8, further comprising a doped polysilicon layer disposed on the second microcrystalline silicon emitter.

12. The solar cell of claim 8, further comprising:

an intrinsic-amorphous silicon layer deposited on the second microcrystalline silicon emitter;

a doped amorphous silicon layer deposited on the intrinsic-amorphous silicon layer; and

a conductive oxide layer deposited on the doped amorphous silicon layer.

13. The solar cell of claim 12, wherein the conductive oxide layer and the doped amorphous silicon layer are patterned.

14. The solar cell of claim 8, further comprising a tunneling oxide layer deposited on the second microcrystalline silicon emitter.

15. The solar cell of claim 14, further comprising a doped polysilicon layer deposited on the tunneling oxide layer.