Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
  • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
  • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
  • H10P14/6326—Deposition processes
  • H10P14/6328—Deposition from the gas or vapour phase
  • H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
  • H10P14/6339—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D1/00—Resistors, capacitors or inductors
  • H10D1/60—Capacitors
  • H10D1/68—Capacitors having no potential barriers
  • H10D1/682—Capacitors having no potential barriers having dielectrics comprising perovskite structures
  • H10D1/684—Capacitors having no potential barriers having dielectrics comprising perovskite structures the dielectrics comprising multiple layers, e.g. comprising buffer layers, seed layers or gradient layers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
  • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
  • H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
  • H10P14/6516—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials
  • H10P14/6544—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials to change the morphology of the insulating materials, e.g. transformation of an amorphous layer into a crystalline layer
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
  • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
  • H10P14/66—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials
  • H10P14/662—Laminate layers, e.g. stacks of alternating high-k metal oxides
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
  • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
  • H10P14/69—Inorganic materials
  • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
  • H10P14/6938—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides
  • H10P14/6939—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides characterised by the metal
  • H10P14/69392—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides characterised by the metal the material containing hafnium, e.g. HfO2
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
  • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
  • H10P14/69—Inorganic materials
  • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
  • H10P14/6938—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides
  • H10P14/6939—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides characterised by the metal
  • H10P14/69395—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides characterised by the metal the material containing zirconium, e.g. ZrO2
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
  • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
  • H10P14/69—Inorganic materials
  • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
  • H10P14/6938—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides
  • H10P14/6939—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides characterised by the metal
  • H10P14/69397—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides characterised by the metal the material containing two or more metal elements

Definitions

• the present invention relates to semiconductor processing and semiconductor devices, and more particularly, to substrate processing methods for forming dielectric materials with selected polarization by thin film vapor phase deposition.
• Dielectric materials are used for CMOS-related applications, including field-effect transistor (FET) devices and dynamic random-access memory (DRAM) devices. New methods are needed for forming dielectric materials with selected polarization by thin film vapor phase deposition.
• FET field-effect transistor
• DRAM dynamic random-access memory
• Embodiments of the invention include methods for forming structures of dielectric films on a substrate, including high-k films that may be used as capacitors and memory cells in semiconductor devices and other devices.
• the method includes forming a first film of a first dielectric material on a substrate by performing a first plurality of cycles of atomic layer deposition and, thereafter, heat-treating the first film, where a thickness of the first film is below a threshold thickness needed for spontaneous polarization in the first dielectric material.
• the method further includes forming a second film of a second dielectric material on the substrate by performing a second plurality of cycles of atomic layer deposition and, thereafter, heat-treating the second film, where a thickness of the second film is greater than the thickness of the first film, and the second film is ferroelectric or antiferroelectric.
• a semiconductor device includes a first film of a first dielectric material on a substrate, where a thickness of the first film is below a threshold thickness needed for spontaneous polarization in the first dielectric material, and a second film of a second dielectric material on the substrate, where a thickness of the second film is greater than the thickness of the first film, and the second film is ferroelectric or antiferroelectric.
• FIG. l is a flowchart of an example method of manufacturing a dielectric film structure according to an embodiment of the invention.
• FIGS. 2 A - 2E show cross-sectional views of an example dielectric film structure according to an embodiment of the invention
• FIG. 3 shows a cross-sectional view of an example dielectric film structure according to an embodiment of the invention
• FIG. 4 shows a cross-sectional view of an example dielectric film structure according to an embodiment of the invention
• FIG. 5 shows a cross-sectional view of an example dielectric film structure according to an embodiment of the invention.
• FIGS. 6 A and 6B schematically show cross-sectional views of example film structures for semiconductor devices according to embodiments of the invention.
• a method in flowchart 1 includes, in 100, providing a substrate 200 in a process chamber.
• the process chamber may be configured to perform atomic layer deposition (ALD) of a dielectric material on the substrate 200.
• the substrate 200 may, for example, include a semiconductor material, including silicon, germanium, silicon germanium, silicon germanium carbide, gallium arsenic phosphide, gallium indium phosphide, silicon carbide, gallium arsenic, indium arsenide, or indium phosphide.
• the substrate 200 may have an epitaxial layer overlying a bulk semiconductor.
• the substrate 200 may include a semiconductor-on-insulator (SOI) structure.
• the substrate 200 may include a metal layer.
• the substrate 200 may also include various p-type doped regions and/or n-type doped regions, implemented by a process such as ion implantation and/or diffusion. Those doped regions can include n-well, p-well, light-doped region (LDD) and various channel doping profiles configured to form various integrated circuit (IC) devices, such as a complimentary metal-oxide-semiconductor field-effect transistor (CMOSFET), an imaging sensor, and/or a light emitting diode (LED).
• CMOSFET complimentary metal-oxide-semiconductor field-effect transistor
• LED light emitting diode
• the substrate 200 may also include various isolation regions.
• the isolation regions separate various device regions in the substrate 200.
• the isolation regions include different structures formed by using different processing technologies.
• the isolation regions may include shallow trench isolation (STI) regions.
• the formation of an STI region may include etching a trench in the substrate 200 and filling in the trench with insulator materials such as silicon oxide, silicon nitride, and/or silicon oxynitride.
• the filled trench may have a multi-layer structure such as a thermal oxide liner layer with silicon nitride filling the trench.
• a chemical mechanical polishing (CMP) may be performed to polish back excessive insulator materials and planarize the top surface of the isolation features.
• CMP chemical mechanical polishing
• the method further includes, in 110, forming a first film 220 of a first dielectric material on the substrate 200 by performing a first plurality of cycles of atomic layer deposition (ALD).
• ALD atomic layer deposition
• the first film 220 includes a high dielectric constant (high-k) material with a dielectric constant greater than that of SiCh (k ⁇ 4).
• the ALD can include cycles of alternating saturating gaseous exposures of a metal-containing precursor and an oxidizer, where each cycle includes one exposure of the metal -containing precursor, followed by one exposure of the oxidizer.
• the first film 220 can contain zirconium oxide (ZrCb), hafnium oxide (HfCb), or laminates or mixtures thereof.
• the HfCb may be doped with aluminum (Al), gadolinium (Gd), lanthanium (La), silicon (Si), strontium (Sr), or yttrium (Y) dopants.
• a first film 220 containing ZrCb may be deposited by ALD using cycles of alternating gaseous exposures of a zirconium-containing precursor and an oxidizer.
• a first film 220 containing a mixture of ZrCb and HfCh may be deposited by ALD using cycles of alternating gaseous exposures of a zirconium-containing precursor, and oxidizer, a hafnium-containing precursor, and an oxidizer.
• a first film 220 containing doped HfCb may be deposited by ALD using cycles of alternating gaseous exposures of a hafnium-containing precursor, a dopant gas, and an oxidizer.
• the dopant concentration can, for example, be between about 0.1 atomic % and about 20 atomic %, between about 0.1 atomic % and about 10 atomic %, or between about 0.1 atomic % and about 1 atomic %.
• Embodiments of the invention may utilize a wide variety of zirconium (Zr) and hafnium (Hf) precursors for the vapor phase deposition.
• Zr zirconium
• Hf hafnium
• representative examples include: Zr(O*Bu)4 (zirconium tert-butoxide, ZTB), Zr(NEt2)4 (tetrakis(diethylamido)zirconium, TDEAZ), Zr(NMeEt)4 (tetrakis(ethylmethylamido)zirconium, TEMAZ), Zr(NMe2)4 (tetrakis(dimethylamido)zirconium, TDMAZ), Hf(O t Bu)4 (hafnium tert-butoxide, HTB), Hf(NEt2)4 (tetrakis(diethylamido)hafnium, TDEAH), Hf(NEtMe)4 (tetrakis(eth
• tris(dimethylaminocyclopentadienylhafnium (HfCp(NMe2)3) available from Air Liquide as HyALDTM may be used as a hafnium precursor and tris(dimethylaminocyclopentadienylzirconinum (ZrCp(NMe2)3) available from Air Liquide as ZyALDTM may be used as a zirconium precursor.
• the oxidizer may include an oxygencontaining gas, including plasma-excited O2, water (H2O), or ozone (O3).
• the Al, Gd, La, Si, Sr, and Y dopants may be provided using any dopant gases that have sufficient reactivity, thermal stability, and volatility.
• Al precursors include AhMee, AhEte, [Al(O(sBu))3]4, A1(CH 3 COCHCOCH3)3, AIBn, AIL, Al(O(iPr)) 3 , [Al(NMe 2 )3] 2 , Al(iBu) 2 Cl, Al(iBu) 3 , Al(iBu) 2 H, AlEt 2 Cl, Et3Al 2 (O(sBu))3, and A1(THD) 3 .
• Gd precursors include Gd(N(SiMe3)2)3, ((iPr)Cp)3Gd, CpsGd, Gd(THD) 3 , Gd[OOCCH(C2H 5 )C 4 H9]3, Gd(O(iPr)) 3 , and Gd(acac) 3 .
• La precursors include La(N(SiMe3)2)3, La(N(iPr)2)3, La(N(tBu)SiMe3)3, La(TMPD) 3 , ((iPr)Cp) 3 La, Cp 3 La, Cp3La(NCCH 3 )2, La(Me 2 NC2H 4 Cp)3, La(THD) 3 , La[OOCCH(C2H 5 )C 4 H9]3, La(CnHi9O 2 )3 CH3(OCH 2 CH 2 )3OCH3, La(CnHi9O 2 )3 CH3(OCH 2 CH 2 ) 4 OCH3, La(O(iPr)) 3 , La(OEt) 3 , La(acac) 3 , La(((tBu)2N) 2 CMe)3, La(((iPr) 2 N) 2 CMe)3, La(((tBu) 2 N)2C(tBu)) 3 , La(((((((t
• silicon precursors examples include silane (SiH 4 ), disilane (Si2He), monochlorosilane (SiClEE), dichlorosilane (SiEECh), trichlorosilane (SiHCh), hexachlorodisilane (Si2Cle), diethylsilane (Et2SiH2), and alkylaminosilane compounds.
• alkylaminosilane compounds include, but are not limited to, diisopropylaminosilane (EESi NPn)), bis(/c/7-butylarnino)silane ((C 4 H9(H)N)2SiH2), tetrakis(dimethylamino)silane (Si(NMe2) 4 ), tetrakis(ethylmethylamino)silane (Si(NEtMe) 4 ), tetrakis(diethylamino)silane (Si(NEt2) 4 ), tris(dimethylamino)silane (HSi(NMe2)3), tris(ethylmethylamino)silane (HSi(NEtMe)3), tris(diethylamino)silane (HSi(NEt2)3), and tris(dimethylhydrazino)silane (HSi(N(H)NMe2)3), bis(
• Sr precursors include Bis(tert-butylacetamidinato)strontium (TBAASr), Sr-C, Sr-D, Sr(N(SiMe3)2)2, Sr(THD)2, Sr(THD)2(tetraglyme), Sr(iPr 4 Cp)2, Sr(iPnCp)2, and Sr(MesCp)2.
• Examples of Y precursors include Y(N(SiMe3)2)3, Y(N(iPr)2)3, ((iPr)Cp)3Y, CpsY, Y(THD) 3 , Y[OOCCH(C 2 H 5 )C 4 H9]3, Y(O(iPr))3, Y(acac) 3 , (C 5 Me 5 ) 2 Y, Y(hfac) 3 , and Y(FOD) 3 .
• Si silicon; Me: methyl; Et: ethyl; iPr: isopropyl; nPr: n-propyl; Bu: butyl; nBu: n-butyl; sBu: sec-butyl; iBu: iso-butyl; tBu: tert-butyl; Cp: cyclopentadienyl; THD: 2,2,6,6-tetramethyl-3,5-heptanedionate; TMPD: 2, 2,6,6- tetramethylpiperidide; acac: acetylacetonate; hfac: hexafluoroacetylacetonate; and FOD: 6,6,7,7,8,8,8-heptafluoro-2,2-dimethyl-3,5-octanedionate.
• a heat-treating process is performed on the first film 220 using a predetermined substrate temperature and time period to form a heat-treated first film 221. This is schematically shown in FIG. 2C.
• the heat-treating organizes the atomic elements in the first film 220, reduces the film stress, and locks in the crystallographic orientation of the first dielectric material.
• the heat-treating for the first film 220 may be performed at a substrate temperature of about 500°C or lower, between about 200°C and about 500°C, between about 200°C and about 300°C, between about 300°C and about 400°C, or between about 400°C and about 500°C.
• the heat-treating may be performed in the same process chamber as the deposition of the first film 220. In another example, the heat-treating may be formed in a different process chamber than the deposition of the first film 220.
• the heat-treating may be performed under vacuum conditions in the presence of an inert gas, for example argon(Ar) or nitrogen (N2).
• a thickness of the heat-treated first film 221 can be about 1.5nm, or less. In the case of a first dielectric material containing a metal oxide, this thickness corresponds to only a few atomic monolayers of the metal oxide, and this thickness is below a threshold thickness needed for spontaneous polarization in the metal oxide. This results in a linearly polarizable metal oxide film in the presence of an external electric field.
• the heat-treated first film 221 contains textured tetragonal ZrCh with (111) crystallographic orientation.
• additional heat-treated films of dielectric materials may be formed on the heat-treated first film 221 by repeating the depositing and heat-treating steps at least once. This is schematically shown in FIG. 3, where additional heat-treated films 223, 225 are formed on the heat-treated first film 221 substrate 200 by repeating the depositing and heat-treating steps twice. In general, any number of additional heat-treated films may be formed. Collectively, the heat-treated first film 221 and the additional heat- treated films 223, 225 form a linearly polarizable dielectric material 230.
• the method further includes, in 120, forming a second film 240 of a second dielectric material on the substrate 200 by performing a second plurality of cycles of ALD.
• a thickness of the second film 240 is greater than a thickness of the first heat- treated first film 221.
• the second film 240 can include a high-k material.
• the second film 240 can contain ZrCh, HfCh, or laminates or mixtures thereof.
• the HfCb may be doped with Al, Gd, La, Si, Sr, or Y dopants.
• the heat- treated first film 220 and the second film 240 can contain the same metal oxide.
• a heat-treating process is performed using a predetermined substrate temperature and time period to form a heat-treated second film 241. This is schematically shown in FIG. 2E.
• the heat-treating organizes the atomic elements in the second film 240, reduces the film stress, and locks in the crystallographic orientation of the second dielectric material.
• the heat-treated second 241 and the heat-treated first film 221 can have different crystallographic orientations.
• the heat-treating of the second film 240 may be performed at a substrate temperature of about 500°C or lower, between about 200°C and about 500°C, between about 200°C and about 300°C, between about 300°C and about 400°C, or between about 400°C and about 500°C.
• a cap layer (not shown) may be deposited on the second film 240 prior to the heat-treating.
• the cap layer can include titanium nitride (TiN).
• the heat-treating of the second film 240 may be performed in the same process chamber as the deposition of the second film 240. In another example, the heat-treating may be formed in a different process chamber than the deposition of the second film 240.
• the heat-treating may be performed under vacuum conditions in the presence of an inert gas, for example Ar or N2.
• a thickness of the heat-treated second film 241 is greater than a thickness of the heat-treated first film 221, and the heat-treated second film 241 is ferroelectric or antiferroelectric. In some examples, a thickness of the heat-treated second film 241 is about 5nm, or greater.
• the heat-treated second film 241 is formed on the substrate 200 and, thereafter, the heat-treated first film 221 is formed on the heat-treated second film 241. This is schematically shown in FIG. 4.
• additional heat-treated dielectric material may the formed on the heat-treated first film 221 by repeating at least once the depositing and heat- treating steps. This is schematically shown in FIG. 5, where additional heat-treated films 223, 225 are formed on the heat-treated first film 221. Generally, any number of additional heat-treated film may be formed. Collectively, the heat-treated first film 221 and the additional heat-treated films 223, 225 form a linearly polarizable dielectric material 231.
• Embodiments described herein provide methods for forming dielectric materials on a substrate that may be utilized for CMOS-related applications, for example for forming negative capacitance (NC) gate stacks for field-effect transistor (FET) devices or dynamic random-access memory (DRAM) devices.
• the dielectric materials may, for example, be formed with selected and modulated polarization for use in metal-oxide-semiconductor fieldeffect transistors (MOSFETs) with very short channel length for ultra-low power computing.
• MOSFETs metal-oxide-semiconductor fieldeffect transistors
• the first and second conductive layers 600, 606 may include metal-containing materials, for example aluminum (Al), copper (Cu), tungsten (W), nickel (Ni), platinum (Pt), alloys thereof, or metal compounds such as titanium nitride (TiN) or tantalum nitride (TaN).
• the first and second conductive layers 600, 606 may also include a metal silicide or doped silicon.
• the first and second conductive layers 600, 606 may be selected to be compatible for n-type and p-type FETs.
• the first film 602 may be formed as described above for heat- treated first film 221.
• the first film 602 can have a thickness below a threshold thickness needed for spontaneous polarization in the first dielectric material.
• the first film 602 may be linearly polarizable in the presence of an external electric field.
• the second film 604 may be formed as described above for heat-treated second film 241.
• the second film 604 can have a thickness that is greater than the thickness of the first film 602, and the second dielectric material has spontaneous polarization.
• the spontaneous polarization can be ferroelectric or antiferroelectric.
• a capacitance C of the semiconductor structure 60 is composed of the capacitance of the films and layers shown in FIG. 6A.
• the first film 602 can contain ZrCh, HfCh, or laminates or mixtures thereof.
• the HfCb may be doped with Al, Gd, La, Si, Sr, or Y dopants. Exemplary methods for forming of the first film 602 and the second film 604 are described in FIGS. 1-5.
• the film structure 61 in FIG. 6B is similar to the film structure 60 and contains a first conductive layer 600, a second film 604 containing a second dielectric material, a first film 602 containing a first dielectric material, and a second conductive layer 606 over the first film 602.
• the film structures 60, 61 may undergo further CMOS or MOS technology processing to form various features and regions known in the art. For example, subsequent processing may form a multilayer interconnection that includes vertical interconnects, such as conventional vias or contacts, and horizontal interconnects, such as metal lines.
• the various interconnection features may implement various conductive materials including copper, tungsten, and/or silicide to provide electrical routings to couple various devices in the substrate to the input/output power and signals.
• a plurality of embodiments for forming dielectric materials with selected polarization by thin film vapor phase deposition have been described. The foregoing description of the embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed.

Landscapes

• Formation Of Insulating Films (AREA)
• Semiconductor Memories (AREA)
• Chemical Vapour Deposition (AREA)
• Insulated Gate Type Field-Effect Transistor (AREA)
• Chemical & Material Sciences (AREA)
• Crystallography & Structural Chemistry (AREA)

Priority Applications (2)

Applications Claiming Priority (2)

Publications (1)

Family

ID=80115248

Family Applications (1)

Country Status (5)

Families Citing this family (1)

Citations (5)

Family Cites Families (18)

• 2021
  • 2021-07-30 JP JP2023509574A patent/JP7743144B2/ja active Active
  • 2021-07-30 WO PCT/US2021/043952 patent/WO2022035618A1/en not_active Ceased
  • 2021-07-30 KR KR1020237002323A patent/KR102941906B1/ko active Active
  • 2021-07-30 US US17/390,399 patent/US12588434B2/en active Active
  • 2021-08-09 TW TW110129234A patent/TWI907477B/zh active

Patent Citations (5)

Also Published As

Similar Documents

Legal Events