WO2022033221A1 - 半导体结构 - Google Patents

半导体结构 Download PDF

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Publication number
WO2022033221A1
WO2022033221A1 PCT/CN2021/103522 CN2021103522W WO2022033221A1 WO 2022033221 A1 WO2022033221 A1 WO 2022033221A1 CN 2021103522 W CN2021103522 W CN 2021103522W WO 2022033221 A1 WO2022033221 A1 WO 2022033221A1
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Prior art keywords
pattern
patterns
photoresist
rectangular
semiconductor structure
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PCT/CN2021/103522
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English (en)
French (fr)
Inventor
夏云升
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长鑫存储技术有限公司
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Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to EP21855274.3A priority Critical patent/EP4131351A4/en
Priority to JP2023501539A priority patent/JP2023533566A/ja
Priority to KR1020227041692A priority patent/KR20230005316A/ko
Priority to US17/575,867 priority patent/US20220139842A1/en
Publication of WO2022033221A1 publication Critical patent/WO2022033221A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7073—Alignment marks and their environment
    • G03F9/7076—Mark details, e.g. phase grating mark, temporary mark
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20—Exposure; Apparatus therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment

Definitions

  • the embodiments of the present application relate to the technical field of semiconductors, and in particular, to a semiconductor structure.
  • the ion implantation of some layers in the fabrication of semiconductor devices is deep, and high-energy exposure is required during exposure, which may easily lead to deformation or ghosting of the marking pattern, resulting in poor appearance of the marking pattern, which seriously affects the accuracy of measurement. , resulting in a decrease in the yield of semiconductor devices.
  • the present application provides a semiconductor structure comprising:
  • the first pattern has a first arrangement length in the first direction
  • the second pattern has a second arrangement length in the second direction
  • each of the first patterns and each of the second patterns has a first arrangement length.
  • the sum of the areas is less than 1/2 of the product of the first array length and the second array length.
  • FIG. 1 is a schematic top view of a semiconductor structure provided in the first embodiment
  • FIG. 2 is a schematic top view of a semiconductor structure provided in the second embodiment
  • FIG. 3 is a schematic top view of a semiconductor structure provided in a third embodiment
  • FIG. 4 is a schematic top view of a semiconductor structure provided in a fourth embodiment
  • FIG. 5 is a schematic top view of a semiconductor structure provided in a fifth embodiment
  • FIG. 6 is a schematic top view of a semiconductor structure provided in a sixth embodiment
  • Fig. 7a is the Qmerit measurement result of the traditional mark pattern
  • Fig. 7b is the Qmerit measurement result of the marking pattern provided by the second embodiment
  • FIG. 7c is the Qmerit measurement result of the mark pattern provided in the fourth embodiment.
  • a semiconductor structure provided in an embodiment of the present application includes a plurality of first patterns 10 arranged in a first direction Ox in a photoresist layer 100 with a thickness greater than 1.2um and a plurality of first patterns 10 arranged along a Several second patterns 20 arranged in two directions Oy, the first direction Ox and the second direction Oy have an included angle a, 0 degree ⁇ a ⁇ 180 degrees; the first pattern 10 has a first arrangement length L1 in the first direction Ox , the second pattern 20 has a second arrangement length L2 in the second direction Oy, denote the total area of each first pattern 10 as S1, and denote the area of each second pattern 20 as S2, then S1+S2 ⁇ 0.5L1*L2 .
  • the photoresist layer 100 by setting a plurality of first patterns 10 arranged along the first direction Ox and a plurality of second patterns 20 arranged along the second direction Oy on the photoresist layer 100 with a thickness greater than 1.2um , wherein the first direction Ox and the second direction Oy have an included angle a, 0° ⁇ a ⁇ 180°, the first pattern 10 has a first arrangement length L1 in the first direction Ox, and the second pattern 20 is in the second direction Oy has a second arrangement length L2, which facilitates accurate measurement between different layers in the semiconductor structure through the first pattern 10 and the second pattern 20; since the first pattern 10 and the second pattern 20 are both formed with a thickness greater than 1.2um On the photoresist layer 100, the photoresist provides a good support for the first pattern 10 and the second pattern 20, so as to avoid deformation or ghosting of some marking patterns during high-energy exposure, which reduces the measurement efficiency and accuracy By setting the sum of the areas of the first patterns 10 and the second patterns 20 to be less than 1/2
  • the first pattern and the second pattern are both void patterns.
  • the first pattern is set as the first rectangular through holes 11 , a plurality of first rectangular through holes 11 arranged at intervals are arranged along the first direction Ox, and each first rectangular through hole 11 has a first arrangement length in the first direction Ox L1; set the second pattern as second rectangular through holes 21, a plurality of second rectangular through holes 21 arranged at intervals are arranged along the second direction Oy, and each second rectangular through hole 21 has a second rectangular through hole 21 in the second direction Oy Arrange length L2.
  • the sum of the area of the orthographic projection of each first rectangular through hole 11 on the surface of the photoresist layer 100 and the area of the orthographic projection of each second rectangular through hole 21 on the surface of the photoresist layer 100 is less than the first arrangement length 1/2 of the product of L1 and the second arrangement length L2.
  • first rectangular through-holes 11 and a plurality of second rectangular through-holes 21 are provided as marking patterns, accurate measurement can be achieved through the marking patterns; since the photoresist layer 100 provides good support for the marking patterns, To avoid the situation of reducing the measurement efficiency and accuracy due to the deformation or ghosting of part of the marking pattern during high-energy exposure; by setting the sum of the areas of the first pattern 10 and the second pattern 20 to be smaller than the first arrangement length L1 and the first pattern 1/2 of the product of the two arrangement lengths L2 is convenient to set a plurality of first patterns and a plurality of second patterns, so as to further improve the accuracy of measurement, thereby improving the yield of semiconductor devices.
  • the first pattern is set as a first rectangular through hole 11 , and a plurality of first rectangular through holes 11 are arranged at intervals along the first direction Ox.
  • the width w1 is 0.5um-1.5um, or/and the spacing d1 of the adjacent first rectangular through holes 11 is 0.5um-1.5um.
  • the photoresist at the position of a rectangular through hole 11 can be exposed and developed; at the same time, the spacing of the first rectangular through holes 11 is set to ensure that the photoresist between the first rectangular through holes 11 is not damaged during high-energy exposure. will be destroyed.
  • the formed mark pattern has an excellent appearance, which is beneficial to the accurate measurement of the mark pattern. As shown in Fig. 7a and Fig.
  • the Qmerit value in the measurement result obtained by using the marking pattern in this embodiment is smaller and more convergent, indicating that the quality of the marking pattern in this implementation is better, and the obtained The measurement results are more reliable and the accuracy is better.
  • the voids in the first pattern may be one or more of a circle, an ellipse, a triangle or a polygon.
  • the second pattern is set as a second rectangular photoresist pattern 22 , and a plurality of second rectangular photoresist patterns 22 are arranged at intervals along the second direction Oy, and each The two rectangular photoresist patterns 22 have a second arrangement length L2 in the second direction Oy;
  • the first pattern is set as the first rectangular through holes 11 , and a plurality of first rectangular through holes 11 are arranged at intervals along the first direction Ox, and each The first rectangular through holes 11 have a first arrangement length L1 in the first direction Ox; the sum of the areas of the first rectangular through holes 11 and the second rectangular photoresist patterns 22 is smaller than the first arrangement length L1 and the second arrangement 1/2 of the product of length L2.
  • each second rectangular photoresist pattern 22 is 1.5um-3.5um, and the spacing d2 of the adjacent second rectangular photoresist patterns 22 is 0.5um-1.5um.
  • the width of the second rectangular photoresist pattern 22 is greater than the distance between the adjacent second rectangular photoresist patterns 22, which prevents the photoresist layer from being too thick when the photoresist layer is too thick.
  • the collapse of the second rectangular photoresist pattern 22 is conducive to the accurate measurement of the marking pattern. Meanwhile, by using the first pattern of the void pattern and the second pattern of the photoresist pattern, the detection of different types of patterns can be simultaneously realized in the marking pattern in the same layer or the same marking pattern in the same layer.
  • the distance between the first pattern and the second pattern is greater than the sum of the distance between the first patterns and the distance between the second patterns.
  • the first pattern is a first rectangular through hole 11
  • the distance d1 between the adjacent first rectangular through holes 11 is 0.5um-1.5um
  • the second pattern is a second rectangular photoresist pattern 22 .
  • the spacing d2 of the adjacent second rectangular photoresist patterns 22 is 0.5um-1.5um.
  • the distance between the first rectangular through hole 11 and the second rectangular photoresist pattern 22 is greater than the sum of the distance d1 of the adjacent first rectangular through hole 11 and the distance d2 of the adjacent second rectangular photoresist pattern 22, This ensures that the boundary between the first rectangular through hole 11 and the second rectangular photoresist pattern 22 is clear and prevents the measurement result from being affected.
  • the first pattern is set as the first rectangular photoresist pattern 12
  • the second pattern is set as the second rectangular photoresist pattern 22 .
  • a plurality of first rectangular photoresist patterns 12 are arranged at intervals along the first direction Ox, the width w12 of each first rectangular photoresist pattern 12 is 2um-3um, and the spacing d12 of each first rectangular photoresist pattern 12 is 1um -1.5um;
  • a plurality of second rectangular photoresist patterns 22 are arranged at intervals along the second direction Oy, the width w2 of each second rectangular photoresist pattern 22 is 2um-3um, and the width of each second rectangular photoresist pattern 22 is The spacing d2 is 1um-1.5um.
  • the width of the first rectangular photoresist patterns 12 is greater than the spacing between the adjacent first rectangular photoresist patterns 12;
  • the width of the rectangular photoresist pattern 22 is greater than the spacing between the adjacent second rectangular photoresist patterns 22, preventing the first rectangular photoresist pattern 12 or the second rectangular photoresist pattern when the photoresist layer is too thick 22 collapse occurs, especially when the thickness of the photoresist is greater than 1.2um, the width and spacing of the photoresist pattern are more conducive to ensuring the quality of the marking pattern and enabling accurate measurement of the marking pattern.
  • the Qmerit value in the measurement result obtained by using the marking pattern in this embodiment is smaller and more convergent, indicating that the quality of the marking pattern in this implementation is better, and the obtained The measurement results are more reliable and the accuracy is better.
  • the photoresist patterns in the first pattern 10 and the second pattern 20 may be one or more of a circle, an ellipse, a triangle or a polygon.
  • the first rectangular photoresist patterns 12 are arranged at equal intervals along the first direction Ox, and the second rectangular photoresist patterns 22 are arranged at equal intervals along the second direction Oy, so as to ensure the measurement accuracy of the marking pattern. reduce the complexity of marking pattern preparation without the need for
  • the included angle between the first direction Ox and the second direction Oy is 90°, which can easily realize the detection results of the X direction and the Y direction in the Cartesian coordinate system.
  • the photoresist layer 100 is further formed with a first pattern 30 and a second pattern 40 , the arrangement direction of the first pattern 30 and the arrangement of the first pattern 10
  • the arrangement direction is parallel
  • the arrangement direction of the second pattern 40 is parallel to the arrangement direction of the second pattern 20
  • the first pattern 30 and the second pattern 40 are used to define the position and shape of the semiconductor device structure in the chip area.
  • the arrangement direction of the first pattern 30 is parallel to the arrangement direction of the first pattern 10
  • the arrangement direction of the second pattern 40 is parallel to the arrangement direction of the second pattern 20, which can reduce the influence of lithography conditions on the measurement results.
  • the measurement result of the mark pattern can better reflect the real situation of the first pattern 30 and the second pattern 40 in the chip removal area.
  • the first pattern 30 is a gap pattern
  • the second pattern 40 is a photoresist pattern
  • the first pattern 30 is a gap pattern, which is consistent with the type of the first pattern 10 , that is, the first pattern 10 is also a gap pattern
  • the second pattern 40 is a photoresist pattern
  • the type of the second pattern 20 is the same, that is, the second pattern 20 is also a photoresist pattern; for example, please continue to refer to FIG.
  • the width w3 of the first pattern 30 is 0.5um-1.5um; the width w4 of the second pattern 40 is 1.5um-3.5um, so as to ensure that the first pattern 30 and the The quality of the second pattern 40 makes it possible to accurately define the position and shape of the semiconductor device structure in the chip area.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

一种半导体结构，包括：位于厚度大于1.2um的光刻胶层中沿第一方向排列的若干个第一图案和沿第二方向排列的若干个第二图案，所述第一方向与所述第二方向具有夹角；所述第一图案在所述第一方向上具有第一排列长度，所述第二图案在所述第二方向上具有第二排列长度，所述第一图案和所述第二图案的面积之和小于所述第一排列长度与所述第二排列长度乘积的1/2。

Description

半导体结构
相关申请的交叉引用
本申请要求于2020年8月12日提交中国专利局、申请号为2020108046386、发明名称为“半导体结构”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及半导体技术领域，特别是涉及一种半导体结构。
背景技术
随着半导体技术的快速发展，半导体器件的尺寸越来越小，对制作工艺中不同层的对准量测精度提出了更高的要求。
然而，制作半导体器件中的有些层的离子植入较深，曝光时需要采用高能量曝光，容易导致标记图形出现变形或叠影，使得标记图形产生较差的形貌，严重影响量测的精确度，导致半导体器件的良品率降低。
发明内容
根据一些实施例，本申请提供一种半导体结构，包括：
位于厚度大于1.2um的光刻胶层中沿第一方向排列的若干个第一图案和沿第二方向排列的若干个第二图案，所述第一方向与所述第二方向具有夹角；
所述第一图案在所述第一方向上具有第一排列长度，所述第二图案在所述第二方向上具有第二排列长度，各所述第一图案和各所述第二图案的面积 之和小于所述第一排列长度与所述第二排列长度乘积的1/2。
附图说明
为了更清楚地说明本申请实施例或传统技术中的技术方案，下面将对实施例或传统技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为第一实施例中提供的一种半导体结构的俯视图示意图；
图2为第二实施例中提供的一种半导体结构的俯视图示意图；
图3为第三实施例中提供的一种半导体结构的俯视图示意图；
图4为第四实施例中提供的一种半导体结构的俯视图示意图；
图5为第五实施例中提供的一种半导体结构的俯视图示意图；
图6为第六实施例中提供的一种半导体结构的俯视图示意图；
图7a为传统标记图形的Qmerit量测结果；
图7b为实施例二提供的标记图形的Qmerit量测结果；
图7c为实施例四提供的标记图形的Qmerit量测结果。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请实施例进行更全面的描述。附图中给出了本申请的一些实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本申请的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技 术领域的技术人员通常理解的含义相同。本文中在本申请实施例的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请实施例。另外，贯穿说明书和跟随的权利要求中所使用的某些术语指代特定元件。本领域的技术人员会理解为，制造商可以用不同的名字指代元件。本文件不想要区分名字不同但是功能相同的元件。在以下的描述和实施例中，术语“包含”和“包括”都是开放式使用的，因此应该解读为“包含，但不限于……”。同样，术语“连接”想要表达间接或直接的电气连接。相应地，如果一个设备被连接到另一个设备上，连接可以通过直接的电气连接完成，或者通过其他设备和连接件的间接电气连接完成。
应当理解，尽管本文可以使用术语“第一”、“第二”等来描述各种元件，但是这些元件不应受这些术语的限制。这些术语仅用于将一个元件和另一个元件区分开。例如，在不脱离本申请的范围的情况下，第一元件可以被称为第二元件，并且类似地，第二元件可以被称为第一元件。
本申请实施例中的“若干个”指一个或多个。
请参考图1，在本申请的一个实施例中提供的一种半导体结构中，包括位于厚度大于1.2um的光刻胶层100中沿第一方向Ox排列的若干个第一图案10和沿第二方向Oy排列的若干个第二图案20，第一方向Ox与第二方向Oy具有夹角a，0度<a<180度；第一图案10在第一方向Ox上具有第一排列长度L1，第二图案20在第二方向Oy上具有第二排列长度L2，记各第一图案10的总面积为S1，记各第二图案20的面积为S2，则S1+S2<0.5L1*L2。
示例的，请继续参考图1，通过在厚度大于1.2um的光刻胶层100上设置沿第一方向Ox排列的若干个第一图案10和沿第二方向Oy排列的若干个第二图案20，其中，第一方向Ox与第二方向Oy具有夹角a，0度<a<180度， 第一图案10在第一方向Ox上具有第一排列长度L1，第二图案20在第二方向Oy上具有第二排列长度L2，便于通过第一图案10及第二图案20实现半导体结构中不同层之间的精确量测；由于第一图案10及第二图案20均形成于厚度大于1.2um的光刻胶层100上，光刻胶为第一图案10及第二图案20提供了良好的支撑，避免在高能量曝光时导致部分标记图形出现变形或叠影而产生降低量测效率及精确度的情况；通过设置各第一图案10和各第二图案20的面积之和小于第一排列长度L1与第二排列长度L2乘积的1/2，便于设置多个第一图案和多个第二图案，以进一步提高量测的精确度，从而提高制成半导体器件的良品率。
请参考图2，在本申请的一个实施例中，所述第一图案和所述第二图案均为空隙图案。设置第一图案为第一矩形通孔11，多个间隔排布的第一矩形通孔11沿第一方向Ox排布，各第一矩形通孔11在第一方向Ox上具有第一排列长度L1；设置第二图案为第二矩形通孔21，多个间隔排布的第二矩形通孔21沿第二方向Oy排布，各第二矩形通孔21在第二方向Oy上具有第二排列长度L2。各第一矩形通孔11在光刻胶层100的表面的正投影的面积，与各第二矩形通孔21在光刻胶层100的表面的正投影的面积之和，小于第一排列长度L1与第二排列长度L2乘积的1/2。由于设置了多个第一矩形通孔11和多个第二矩形通孔21作为标记图形，以经由该标记图形实现精确量测；由于光刻胶层100为该标记图形提供了良好的支撑，避免在高能量曝光时导致部分标记图形出现变形或叠影而产生降低量测效率及精确度的情况；通过设置第一图案10和第二图案20的面积之和小于第一排列长度L1与第二排列长度L2乘积的1/2，便于设置多个第一图案和多个第二图案，以进一步提高量测的精确度，从而提高制成半导体器件的良品率。
在本申请的一个实施例中，请参考图3，设置第一图案为第一矩形通孔11，多个第一矩形通孔11沿第一方向Ox间隔排布，第一矩形通孔11的宽度w1为0.5um-1.5um，或/和相邻的第一矩形通孔11的间距d1为0.5um-1.5um，所述第一矩形通孔11尺寸的设置保证在高能量曝光时，第一矩形通孔11位置的光刻胶可以被曝光和显影掉；同时，所述第一矩形通孔11的间距的设置保证在高能量曝光时第一矩形通孔11之间的光刻胶不会被破坏。使得形成的标记图形具有优良的形貌，有利于标记图形实现精确量测。如图7a和图7b所示，相较传统标记图形，采用本实施例中的标记图形获得的量测结果中Qmerit值较小且更加收敛，说明本实施中的标记图形质量更佳，获得的量测结果更可靠，精度更好。
在本申请的其他实施例中，第一图案中的空隙可以为圆形、椭圆形、三角形或多边形中的一种或多种。
在本申请的一个实施例中，请继续参考图3，设置第二图案为第二矩形光刻胶图形22，多个第二矩形光刻胶图形22沿第二方向Oy间隔排布，各第二矩形光刻胶图形22在第二方向Oy上具有第二排列长度L2；设置第一图案为第一矩形通孔11，多个第一矩形通孔11沿第一方向Ox间隔排布，各第一矩形通孔11在第一方向Ox上具有第一排列长度L1；各第一矩形通孔11和各第二矩形光刻胶图形22的面积之和小于第一排列长度L1与第二排列长度L2乘积的1/2。各第二矩形光刻胶图形22的宽度w2为1.5um-3.5um，相邻的第二矩形光刻胶图形22的间距d2为0.5um-1.5um。在第二图案为光刻胶图案时，具体的，第二矩形光刻胶图形22的宽度大于相邻的第二矩形光刻胶图形22之间的间距，防止在光刻胶层过厚时第二矩形光刻胶图形22发生倒塌，有利于标记图形实现精确量测。同时，利用空隙图案的第一图案以及光刻胶 图案的第二图案可以在同一层中的标记图形或同一层中的同一标记图形中同时实现对不同类型图案的检测。
在本申请的一个实施例中，第一图案和第二图案之间的距离大于第一图案之间的间距和第二图案之间的间距之和。请继续参考图3，第一图案为第一矩形通孔11，相邻的第一矩形通孔11的间距d1为0.5um-1.5um，第二图案为第二矩形光刻胶图形22，相邻的第二矩形光刻胶图形22的间距d2为0.5um-1.5um。第一矩形通孔11和第二矩形光刻胶图形22之间的距离大于相邻的第一矩形通孔11的间距d1和相邻的第二矩形光刻胶图形22的间距d2之和，以保证第一矩形通孔11和第二矩形光刻胶图形22之间的边界清晰，防止影响量测结果。
在本申请的一个实施例中，请参考图4，设置第一图案为第一矩形光刻胶图形12，设置第二图案为第二矩形光刻胶图形22。多个第一矩形光刻胶图形12沿第一方向Ox间隔排布，各第一矩形光刻胶图形12的宽度w12为2um-3um，各第一矩形光刻胶图形12的间距d12为1um-1.5um；多个第二矩形光刻胶图形22沿第二方向Oy间隔排布，各第二矩形光刻胶图形22的宽度w2为2um-3um，各第二矩形光刻胶图案22的间距d2为1um-1.5um。本实施例的第一图案和第二图案为光刻胶图案时，具体的，第一矩形光刻胶图形12的宽度大于相邻的第一矩形光刻胶图形12之间的间距；第二矩形光刻胶图形22的宽度大于相邻的第二矩形光刻胶图形22之间的间距，防止在光刻胶层过厚时第一矩形光刻胶图形12或第二矩形光刻胶图形22发生倒塌，特别是在光刻胶厚度大于1.2um时，前述光刻胶图形的宽度和间距更有利于保证标记图形的质量，有利于标记图形实现精确量测。如图7a和图7c所示，相较传统标记图形，采用本实施例中的标记图形获得的量测结果中Qmerit值 较小且更加收敛，说明本实施中的标记图形质量更佳，获得的量测结果更可靠，精度更好。在本申请其他实施例中，第一图案10和第二图案20中的光刻胶图案可以为圆形、椭圆形、三角形或多边形中的一种或多种。
请继续参考图4，各第一矩形光刻胶图形12沿第一方向Ox等间距排列，各第二矩形光刻胶图形22沿第二方向Oy等间距排列，在保证标记图形量测精确度的情况下降低标记图形制备的复杂度。
在本申请的一个实施例中，请参考图5，第一方向Ox与第二方向Oy的夹角为90°，可以方便实现直角坐标系中X方向和Y方向的检测结果。
在本申请的一个实施例中，请参考图6，所述光刻胶层100中还形成有第一图形30和第二图形40，第一图形30的排布方向和第一图案10的排布方向平行，第二图形40的排布方向与第二图案20的排布方向平行，第一图形30和第二图形40用于定义芯片区的半导体器件结构的位置及形状。第一图形30的排布方向和第一图案10的排布方向平行，第二图形40的排布方向与第二图案20的排布方向平行，可以减弱光刻条件对量测结果的影响，使得标记图形的量测结果更能反映芯片去区的第一图形30和第二图形40的真实情况。
请继续参考图6，第一图形30为间隙图形，第二图形40为光刻胶图形，第一图形30为间隙图形，与第一图案10的类型一致，即第一图案10也为间隙图形；第二图形40为光刻胶图形，第二图案20的类型一致，即第二图案20也为光刻胶图形；示例的，请继续参考图6，设置第一图形30为第三矩形通孔，多个第三矩形通孔的排布方向与第一图案10的排布方向平行；设置第二图形40为第四矩形光刻胶图形，多个第四矩形光刻胶图形的排布方向与第二图案的排布方向平行。保证芯片区的图形和标记图形的图形类型一致，使 得标记图形的量测结果更能反映芯片区的图形的真实情况。
在本申请的一个实施例中，请继续参考图6，第一图形30的宽度w3为0.5um-1.5um；第二图形40的宽度w4为1.5um-3.5um，以保证第一图形30和第二图形40的质量，使得能够准确定义出芯片区的半导体器件结构的位置及形状。
请注意，上述实施例仅出于说明性目的而不意味对本发明的限制。
本说明书中的各个实施例均采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似的部分互相参见即可。
上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (11)

  1. 一种半导体结构，包括：
    位于厚度大于1.2um的光刻胶层中沿第一方向排列的若干个第一图案和沿第二方向排列的若干个第二图案，所述第一方向与所述第二方向具有夹角；
    所述第一图案在所述第一方向上具有第一排列长度，所述第二图案在所述第二方向上具有第二排列长度，各所述第一图案和各所述第二图案的面积之和小于所述第一排列长度与所述第二排列长度乘积的1/2。
  2. 根据权利要求1所述的半导体结构，其中所述第一图案和所述第二图案均为空隙图案。
  3. 根据权利要求1所述的半导体结构，其中所述第一图案为空隙图案，所述空隙图案的宽度为0.5um-1.5um，或/和相邻的两个所述空隙图案的间距为0.5um-1.5um。
  4. 根据权利要求3所述的半导体结构，其中所述第二图案为光刻胶图案，所述光刻胶图案的宽度为1.5um-3.5um，相邻的两个所述光刻胶图案的间距为0.5um-1.5um。
  5. 根据权利要求1所述的半导体结构，其中所述第一图案和所述第二图案均为光刻胶图案，所述光刻胶图案的宽度为2um-3um，相邻的两个所述第一图案的间距为1um-1.5um，相邻的两个所述第二图案的间距为1um-1.5um。
  6. 根据权利要求1所述的半导体结构，其特征在于，所述第一图案沿第一方向等间距排列，所述第二图案沿所述第二方向等间距排列。
  7. 根据权利要求1所述的半导体结构，其中所述第一方向与所述第二方向夹角为90°。
  8. 根据权利要求4所述的半导体结构，其中所述光刻胶层中还形成有若 干个第一图形和若干个第二图形，所述第一图形的排布方向与所述第一方向平行，所述第二图形的排布方向与所述第二方向平行。
  9. 根据权利要求8所述的半导体结构，其中所述第一图形为间隙图形，所述第二图形为光刻胶图形。
  10. 根据权利要求9所述的半导体结构，其中所述第一图形的宽度为0.5um-1.5um；所述第二图形的宽度为1.5um-3.5um。
  11. 根据权利要求4所述的半导体结构，其中所述第一图案和所述第二图案之间的距离大于所述第一图案之间的间距和所述第二图案之间的间距之和。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101398630A (zh) * 2007-09-25 2009-04-01 南亚科技股份有限公司 对准及叠对的标记、及其掩模结构与使用方法
US20190067204A1 (en) * 2017-08-28 2019-02-28 United Microelectronics Corp. Alignment mark and measurement method thereof
CN109870876A (zh) * 2017-12-05 2019-06-11 长鑫存储技术有限公司 一种对准图案制作方法
CN110824847A (zh) * 2018-08-08 2020-02-21 长鑫存储技术有限公司 提高套刻精度的刻蚀方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09162102A (ja) * 1995-12-07 1997-06-20 Mitsubishi Electric Corp アライメントマーク検出方法
JP5497605B2 (ja) * 2010-09-30 2014-05-21 Ｈｏｙａ株式会社 転写マスク、転写マスクの製造方法、転写マスク収容体、及び転写マスク収容体の製造方法
US9395629B2 (en) * 2014-02-19 2016-07-19 Macronix International Co., Ltd. Special layout design printed rectangular pattern and improved pattern critical dimension uniformity
JP2017021263A (ja) * 2015-07-14 2017-01-26 セイコーエプソン株式会社 レチクル、及び、半導体装置の製造方法
NL2017466A (en) * 2015-09-30 2017-04-05 Asml Netherlands Bv Metrology method, target and substrate
CN207352356U (zh) * 2017-11-02 2018-05-11 睿力集成电路有限公司 具有孔洞图形的半导体结构
KR20200090488A (ko) * 2019-01-21 2020-07-29 삼성전자주식회사 반도체 소자 제조 방법

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101398630A (zh) * 2007-09-25 2009-04-01 南亚科技股份有限公司 对准及叠对的标记、及其掩模结构与使用方法
US20190067204A1 (en) * 2017-08-28 2019-02-28 United Microelectronics Corp. Alignment mark and measurement method thereof
CN109870876A (zh) * 2017-12-05 2019-06-11 长鑫存储技术有限公司 一种对准图案制作方法
CN110824847A (zh) * 2018-08-08 2020-02-21 长鑫存储技术有限公司 提高套刻精度的刻蚀方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4131351A4

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