WO2022032463A1 - 一种透射电镜高分辨原位流体冷冻芯片及其制备方法 - Google Patents
一种透射电镜高分辨原位流体冷冻芯片及其制备方法 Download PDFInfo
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- WO2022032463A1 WO2022032463A1 PCT/CN2020/108322 CN2020108322W WO2022032463A1 WO 2022032463 A1 WO2022032463 A1 WO 2022032463A1 CN 2020108322 W CN2020108322 W CN 2020108322W WO 2022032463 A1 WO2022032463 A1 WO 2022032463A1
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- 238000007710 freezing Methods 0.000 title claims abstract description 88
- 238000011065 in-situ storage Methods 0.000 title claims abstract description 86
- 230000008014 freezing Effects 0.000 title claims abstract description 82
- 239000012530 fluid Substances 0.000 title claims abstract description 78
- 238000002360 preparation method Methods 0.000 title claims abstract description 27
- 230000005540 biological transmission Effects 0.000 title claims abstract description 16
- 229910052751 metal Inorganic materials 0.000 claims abstract description 109
- 239000002184 metal Substances 0.000 claims abstract description 109
- 239000004065 semiconductor Substances 0.000 claims abstract description 91
- 239000010409 thin film Substances 0.000 claims abstract description 47
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 14
- 239000010703 silicon Substances 0.000 claims abstract description 14
- 235000012431 wafers Nutrition 0.000 claims description 248
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 claims description 120
- 238000000034 method Methods 0.000 claims description 101
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- 229910052581 Si3N4 Inorganic materials 0.000 claims description 68
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 68
- 238000004627 transmission electron microscopy Methods 0.000 claims description 67
- 239000008367 deionised water Substances 0.000 claims description 60
- 229910021641 deionized water Inorganic materials 0.000 claims description 60
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 60
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 54
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 54
- 229920002120 photoresistant polymer Polymers 0.000 claims description 45
- 238000012546 transfer Methods 0.000 claims description 32
- 238000001459 lithography Methods 0.000 claims description 24
- 238000001020 plasma etching Methods 0.000 claims description 20
- XSOKHXFFCGXDJZ-UHFFFAOYSA-N telluride(2-) Chemical compound [Te-2] XSOKHXFFCGXDJZ-UHFFFAOYSA-N 0.000 claims description 20
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 19
- 229910052797 bismuth Inorganic materials 0.000 claims description 19
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 claims description 19
- 238000011161 development Methods 0.000 claims description 18
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 17
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 13
- MRPWWVMHWSDJEH-UHFFFAOYSA-N antimony telluride Chemical compound [SbH3+3].[SbH3+3].[TeH2-2].[TeH2-2].[TeH2-2] MRPWWVMHWSDJEH-UHFFFAOYSA-N 0.000 claims description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 12
- 229920005591 polysilicon Polymers 0.000 claims description 12
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 10
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 9
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 9
- 229910052802 copper Inorganic materials 0.000 claims description 9
- 239000010949 copper Substances 0.000 claims description 9
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 9
- 229910052737 gold Inorganic materials 0.000 claims description 9
- 239000010931 gold Substances 0.000 claims description 9
- 239000000463 material Substances 0.000 claims description 9
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- 238000000233 ultraviolet lithography Methods 0.000 claims description 9
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- 229910052782 aluminium Inorganic materials 0.000 claims description 7
- FBGGJHZVZAAUKJ-UHFFFAOYSA-N bismuth selenide Chemical compound [Se-2].[Se-2].[Se-2].[Bi+3].[Bi+3] FBGGJHZVZAAUKJ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052738 indium Inorganic materials 0.000 claims description 7
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- OCGWQDWYSQAFTO-UHFFFAOYSA-N tellanylidenelead Chemical compound [Pb]=[Te] OCGWQDWYSQAFTO-UHFFFAOYSA-N 0.000 claims description 6
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- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 5
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- AXCZMVOFGPJBDE-UHFFFAOYSA-L calcium dihydroxide Chemical class [OH-].[OH-].[Ca+2] AXCZMVOFGPJBDE-UHFFFAOYSA-L 0.000 description 2
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/26—Electron or ion microscopes; Electron or ion diffraction tubes
- H01J37/261—Details
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N23/00—Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00
- G01N23/02—Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00 by transmitting the radiation through the material
- G01N23/04—Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00 by transmitting the radiation through the material and forming images of the material
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N23/00—Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00
- G01N23/20—Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00 by using diffraction of the radiation by the materials, e.g. for investigating crystal structure; by using scattering of the radiation by the materials, e.g. for investigating non-crystalline materials; by using reflection of the radiation by the materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/02—Details
- H01J37/20—Means for supporting or positioning the objects or the material; Means for adjusting diaphragms or lenses associated with the support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/26—Electron or ion microscopes; Electron or ion diffraction tubes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/38—Cooling arrangements using the Peltier effect
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N10/00—Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects
- H10N10/80—Constructional details
- H10N10/82—Connection of interconnections
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N10/00—Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects
- H10N10/80—Constructional details
- H10N10/85—Thermoelectric active materials
- H10N10/851—Thermoelectric active materials comprising inorganic compositions
- H10N10/852—Thermoelectric active materials comprising inorganic compositions comprising tellurium, selenium or sulfur
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N10/00—Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects
- H10N10/80—Constructional details
- H10N10/85—Thermoelectric active materials
- H10N10/851—Thermoelectric active materials comprising inorganic compositions
- H10N10/8556—Thermoelectric active materials comprising inorganic compositions comprising compounds containing germanium or silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
- H01J2237/20—Positioning, supporting, modifying or maintaining the physical state of objects being observed or treated
- H01J2237/2001—Maintaining constant desired temperature
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
- H01J2237/20—Positioning, supporting, modifying or maintaining the physical state of objects being observed or treated
- H01J2237/2002—Controlling environment of sample
- H01J2237/2003—Environmental cells
Definitions
- the invention relates to the field of chips, in particular to a transmission electron microscope high-resolution in-situ fluid freezing chip and a preparation method thereof.
- the current in situ TEM technology provides a full dynamic gas-fluid environment, which helps technicians to capture more dynamic structural change information. Capture some important instantaneous information, such as the change of element valence and molecular structure during chemical reaction, the distribution of ions in the electrochemical solid-liquid interface and the electric double layer, and the three-dimensional structure of biomolecules (such as antigen/antibody) when interacting.
- the instantaneous chemical state and spatial distribution information in these process information are very necessary for technicians to interpret the reaction principle from the molecular and atomic scales, and the characterization of these information requires an invariant state for a long time. These are The current cryogenic cryo-EM and in-situ fluid transmission electron microscopy cannot be achieved. To obtain these information, technicians must realize micro-regional rapid freezing during in-situ testing, combined with high-resolution STEM/EDS/EELES characterization. .
- the purpose of the present invention is to provide a transmission electron microscope high-resolution in-situ fluid freezing chip capable of micro-region quick freezing during in-situ testing. At the same time, the chip also has the advantages of rapid freezing of micro-regions, high resolution and low sample drift rate.
- the present invention provides a transmission electron microscope high-resolution in-situ fluid freezing chip, the structure of which is that the upper sheet and the lower sheet are combined by a metal bonding layer, wherein the upper sheet and the lower sheet are divided into front and back.
- the front side of the lower sheet is directly bonded to the front side of the lower sheet through a metal bonding layer, and an ultra-thin chamber is formed by self-closing;
- the upper sheet and the lower sheet are made of silicon substrates with silicon nitride or silicon oxide on both sides,
- the upper sheet is provided with two sample injection ports and a central window 1, and is characterized in that the lower sheet is provided with a support layer, a freezing layer, an insulating layer, a hole and a central window 2; the freezing layer is provided with three contact electrodes, six pairs of Semiconductor film and conductive metal film; there is a circle of conductive metal film on the periphery of the central window 2, the center of which is the central window 2; three contact electrodes are placed on the edge of the chip; one end of the six pairs of semiconductor films is placed on the conductive metal film, and the other end is placed on the conductive metal film.
- the electrode On the electrode; with the central window 2 as the center, and in the outer edge area larger than the conductive metal film, there are holes left after the silicon is etched away, and the support layer covers the holes; the conductive metal film is placed on the support layer on the holes, The freezing layer is covered with an insulating layer except for the contact electrode area;
- the area of the upper sheet is slightly smaller than that of the lower sheet, the central window 1 of the upper sheet is aligned with the central window 2 of the lower sheet, and both the central window 1 and the central window 2 have a plurality of small holes.
- the outer dimension of the lower piece is 2mm*2mm-10mm*10mm; preferably, the outer dimension of the lower piece is 4mm*8mm;
- the thickness of the metal bonding layer is 50nm-2000nm; the material of the metal bonding layer is a low melting point metal; preferably, the material of the metal bonding layer is In, Sn or Al;
- the thickness of the silicon nitride or silicon oxide is 5-200nm;
- the thickness of the silicon substrate is 50-500 ⁇ m
- the central viewing window 1 of the upper sheet is located at the center of the upper sheet, and the two injection ports are symmetrically arranged with respect to the central viewing window 1 .
- the support layer is silicon nitride or silicon oxide, and the thickness is 0.5-5 ⁇ m.
- two electrodes in the three contact electrodes are used as the input current of the positive electrode; one electrode is used as the output current of the negative electrode;
- the contact electrode is made of gold, silver or copper with a thickness of 50nm-300nm, the length of the positive electrode is 1-1.5mm and the width is 0.5-1.2mm; the length of the negative electrode is 1-1.5mm and the width is 0.4- 0.8mm;
- the six pairs of semiconductor thin films are six n-type semiconductor thin films and six p-type semiconductor thin films; the six n-type semiconductor thin films are in the shape of L-shaped strips and are placed on the outside of the chip in parallel and symmetrical; six p-type semiconductor thin films are The shape of the semiconductor thin film is a regular rectangle, and is placed in parallel on the inside of the chip; preferably, the n-type semiconductor in the n-type semiconductor thin film is n-type bismuth telluride, n-type silicon germanium, n-type lead telluride, n-type zinc telluride or n-type bismuth selenide; the p-type semiconductor in the p-type semiconductor film is polysilicon, p-type bismuth telluride, p-type silicon germanium or p-type antimony telluride;
- the length of the semiconductor thin film is 4-6 mm, the width is 0.4-0.8 mm, and the thickness is 50-500 nm.
- the conductive metal film is a back-shaped conductive metal film formed of conductive metal, and the center of the conductive metal film is the central window 2; preferably, the conductive metal is gold, silver or copper, with a thickness of 50nm-300nm ;
- the outer square size of the conductive metal film is 100 ⁇ m*100 ⁇ m-500 ⁇ m*500 ⁇ m, and the inner square size is 5 ⁇ m*5 ⁇ m-100 ⁇ m*100 ⁇ m;
- the insulating layer is a layer of silicon nitride or silicon oxide with a thickness of 30-150 nm.
- the hole is circular or square; preferably, the diameter of the circular hole is 200 ⁇ m-600 ⁇ m; the size of the square hole is 200 ⁇ m*200 ⁇ m-800 ⁇ m*800 ⁇ m;
- the central window 1 and the central window 2 are both square central windows; preferably, the size of the square central window is 5 ⁇ m*5 ⁇ m-100 ⁇ m*100 ⁇ m; more preferably, the size of the square central window is 20 ⁇ m*50 ⁇ m;
- the size of the pores is 0.5 ⁇ m-5 ⁇ m.
- the preparation method of the top sheet is,
- the photolithography process is exposure in the hard contact mode of an ultraviolet photolithography machine; the thickness of the silicon nitride or silicon oxide layer is 5-200nm; the development time is 50s;
- the exposure time is 15s
- the development time is 50s;
- the thickness of silicon nitride at the small holes on the back of wafer A-3 is etched to 10nm-15nm, and then the front side of wafer A-3 is placed in acetone and soaked in acetone. , and finally rinsed with acetone to remove the photoresist to obtain wafer A-4;
- the size of the small hole is 0.5 ⁇ m-5 ⁇ m;
- the mass percentage concentration of the potassium hydroxide solution is 20%; the etching temperature is 80°C, and the time is 1.5-4h;
- the time of etching is 2h;
- the lithography process is exposure in the hard contact mode of the UV lithography machine; the development time is 50s;
- the exposure time is 15s
- the wafer A-6 is evaporated with a metal bonding material to form a metal bonding layer, and the wafer A-7 is obtained;
- the metal is a low melting point metal; the thickness of the metal bonding layer is 50-2000 nm;
- the metal is In, Sn or Al;
- the lithography process is exposure in the hard contact mode of an ultraviolet lithography machine; the photoresist used in the lithography process is AZ5214E; the development time is 65s;
- the exposure time is 20s;
- the silicon nitride or silicon oxide of the conductive metal is etched on the silicon nitride layer on the back of the wafer B-1, and then the back of the wafer is put into acetone successively. Soak in acetone, and finally rinse with acetone to remove the photoresist to obtain wafer B-2;
- the size of the outer square of the conductive metal film is 100 ⁇ m*100 ⁇ m-500 ⁇ m*500 ⁇ m, and the size of the inner square is 5 ⁇ m*5 ⁇ m-100 ⁇ m*100 ⁇ m;
- silicon oxide or silicon nitride is grown on the front side of the etched silicon wafer of wafer B-2 to obtain wafer B-3;
- the thickness of silicon oxide or silicon nitride is 0.5-5 ⁇ m;
- the metal thin film is gold, silver or copper, with a thickness of 50nm-300nm;
- the n-type semiconductor pattern is transferred from the photolithography mask to the front side of the wafer B-5, and then developed in a positive-gel developer, and then rinsed with deionized water to clean the surface to obtain wafer B -6;
- the n-type semiconductor in the n-type semiconductor thin film is n-type bismuth telluride, n-type silicon germanium, n-type lead telluride, n-type zinc telluride or n-type bismuth selenide;
- the p-type semiconductor adopts polysilicon, p-type bismuth telluride, p-type silicon germanium or p-type antimony telluride;
- the p-type semiconductor in the p-type semiconductor thin film is polysilicon, p-type bismuth telluride, p-type silicon germanium or p-type antimony telluride.
- the thickness of the insulating layer is 30-150 nm;
- the pinhole pattern of the central window is transferred from the lithography mask to the front side of the wafer B-10, and then developed in a positive gel developer, and then rinsed with deionized water. surface to obtain wafer B-11;
- the photoresist used in the UV laser direct writing process is AZ5214E; the output power is 260W/us;
- the size of the small hole is 0.5 ⁇ m-5 ⁇ m;
- the wafer B-12 is laser diced and divided into independent chips, which are the next wafers.
- the present invention also protects a method for preparing the transmission electron microscope high-resolution in-situ fluid freezing chip, which is characterized in that:
- the preparation method of the top sheet is,
- the photolithography process is exposure in the hard contact mode of an ultraviolet photolithography machine; the thickness of the silicon nitride or silicon oxide layer is 5-200nm; the development time is 50s;
- the exposure time is 15s
- the development time is 50s;
- the thickness of silicon nitride at the small holes on the back of wafer A-3 is etched to 10nm-15nm, and then the front side of wafer A-3 is placed in acetone and soaked in acetone. , and finally rinsed with acetone to remove the photoresist to obtain wafer A-4;
- the size of the small hole is 0.5 ⁇ m-5 ⁇ m;
- the mass percentage concentration of the potassium hydroxide solution is 20%; the etching temperature is 80°C, and the time is 1.5-4h;
- the time of etching is 2h;
- the lithography process is exposure in the hard contact mode of the UV lithography machine; the development time is 50s;
- the exposure time is 15s
- the wafer A-6 is evaporated with a metal bonding material to form a metal bonding layer, and the wafer A-7 is obtained;
- the metal is a low melting point metal; the thickness of the metal bonding layer is 50-2000 nm;
- the metal is In, Sn or Al;
- the preparation method of the lower tablet is,
- the lithography process is exposure in the hard contact mode of an ultraviolet lithography machine; the photoresist used in the lithography process is AZ5214E; the development time is 65s;
- the exposure time is 20s;
- the silicon nitride or silicon oxide of the conductive metal is etched on the silicon nitride layer on the back of the wafer B-1, and then the back of the wafer is put into acetone successively. Soak in acetone, and finally rinse with acetone to remove the photoresist to obtain wafer B-2;
- the size of the outer square of the conductive metal film is 100 ⁇ m*100 ⁇ m-500 ⁇ m*500 ⁇ m, and the size of the inner square is 5 ⁇ m*5 ⁇ m-100 ⁇ m*100 ⁇ m;
- silicon oxide or silicon nitride is grown on the front side of the etched silicon wafer of wafer B-2 to obtain wafer B-3;
- the thickness of silicon oxide or silicon nitride is 0.5-5 ⁇ m;
- the metal thin film is gold, silver or copper, with a thickness of 50nm-300nm;
- the n-type semiconductor pattern is transferred from the photolithography mask to the front side of the wafer B-5, and then developed in a positive gel developer, and then rinsed with deionized water to clean the surface to obtain wafer B -6;
- the n-type semiconductor in the n-type semiconductor thin film is n-type bismuth telluride, n-type silicon germanium, n-type lead telluride, n-type zinc telluride or n-type bismuth selenide;
- the p-type semiconductor adopts polysilicon, p-type bismuth telluride, p-type silicon germanium or p-type antimony telluride;
- the p-type semiconductor in the p-type semiconductor film is polysilicon, p-type bismuth telluride, p-type silicon germanium or p-type antimony telluride;
- the thickness of the insulating layer is 30-150 nm;
- the pinhole pattern of the central window is transferred from the lithography mask to the front side of the wafer B-10, and then developed in a positive gel developer, and then rinsed with deionized water. surface to obtain wafer B-11;
- the photoresist used in the UV laser direct writing process is AZ5214E; the output power is 260W/us;
- the size of the small hole is 0.5 ⁇ m-5 ⁇ m;
- Assembly Assemble the obtained upper and lower films under a microscope, and align the central windows of the upper and lower films.
- the temperature control area of the chip of the invention is small (100 ⁇ m*100 ⁇ m-500 ⁇ m*500 ⁇ m area), and the heat insulation treatment is designed, so that the heat transfer is small, so the micro-area rapid temperature control can be realized.
- Fig. 1 is the frozen layer structure schematic diagram of the lower sheet of the chip of the present invention
- Fig. 2 is the structural schematic diagram after corroding holes in the preparation process of the chip of the present invention
- FIG. 3 is a schematic structural diagram after the holes are etched and the conductive metal film and the contact electrodes are plated during the preparation process of the chip of the present invention
- Fig. 4 is the structure schematic diagram of plating the n-type semiconductor thin film on the basis of Fig. 3;
- Fig. 5 is the structural representation of plating p-type semiconductor thin film on the basis of Fig. 4;
- FIG. 6 is a schematic diagram of the lower chip structure of the chip of the present invention.
- FIG. 7 is a schematic structural diagram of the chip of the present invention before the upper and lower sheets are combined;
- FIG. 8 is a schematic structural diagram of the chip of the present invention after the upper and lower sheets are combined;
- FIG. 9 is an enlarged view of 51 center windows 1 and 52 center windows 2;
- Figure 10 is an enlarged view of 52 center windows 1 and 52 center windows 2;
- Fig. 11 is the electron microscope image of the sample observed using the chip of the present invention.
- Figure 12 is a temperature standard curve obtained using the chip of the present invention.
- 1 is the high-resolution in-situ fluid cryochip for transmission electron microscopy
- 2 is the upper film
- 3 is the lower film
- 4 is the metal bonding layer
- 5 is the central window
- 51 is the central window of the upper film
- 7 is the injection port
- 8 is the support layer
- 9 is the freezing layer
- 10 is the insulating layer
- 11 is the three contact electrodes
- 12 is the silicon substrate
- 13 and 14 are both silicon nitride or silicon oxide layers 15 is a hole
- 161 is an n-type semiconductor film
- 162 is a p-type semiconductor film
- 17 is a conductive metal film.
- Example 1 Preparation of high-resolution in situ fluid cryochip for transmission electron microscopy
- the preparation method of the top sheet is,
- the photolithography process is exposure in the hard contact mode of an ultraviolet photolithography machine; the thickness of the silicon nitride or silicon oxide layer is 5-200nm; the development time is 50s;
- the exposure time is 15s
- the development time is 50s;
- the thickness of silicon nitride at the small holes on the back of wafer A-3 is etched to 10nm-15nm, and then the front side of wafer A-3 is placed in acetone and soaked in acetone. , and finally rinsed with acetone to remove the photoresist to obtain wafer A-4;
- the size of the small hole is 0.5 ⁇ m-5 ⁇ m;
- the mass percentage concentration of the potassium hydroxide solution is 20%; the etching temperature is 80°C, and the time is 1.5-4h;
- the time of etching is 2h;
- the lithography process is exposure in the hard contact mode of the UV lithography machine; the development time is 50s;
- the exposure time is 15s
- the wafer A-6 is evaporated with a metal bonding material to form a metal bonding layer, and the wafer A-7 is obtained;
- the metal is a low melting point metal; the thickness of the metal bonding layer is 50-2000 nm;
- the metal is In, Sn or Al;
- the preparation method of the lower tablet is,
- the lithography process is exposure in the hard contact mode of an ultraviolet lithography machine; the photoresist used in the lithography process is AZ5214E; the development time is 65s;
- the exposure time is 20s;
- the silicon nitride or silicon oxide of the conductive metal is etched on the silicon nitride layer on the back of the wafer B-1, and then the back of the wafer is put into acetone successively. Soak in acetone, and finally rinse with acetone to remove the photoresist to obtain wafer B-2;
- the size of the outer square of the conductive metal film is 100 ⁇ m*100 ⁇ m-500 ⁇ m*500 ⁇ m, and the size of the inner square is 5 ⁇ m*5 ⁇ m-100 ⁇ m*100 ⁇ m;
- silicon oxide or silicon nitride is grown on the front side of the etched silicon wafer of wafer B-2 to obtain wafer B-3;
- the thickness of silicon oxide or silicon nitride is 0.5-5 ⁇ m;
- the metal thin film is gold, silver or copper, with a thickness of 50nm-300nm;
- the n-type semiconductor pattern is transferred from the photolithography mask to the front side of the wafer B-5, and then developed in a positive-gel developer, and then rinsed with deionized water to clean the surface to obtain wafer B -6;
- the n-type semiconductor in the n-type semiconductor thin film is n-type bismuth telluride, n-type silicon germanium, n-type lead telluride, n-type zinc telluride or n-type bismuth selenide;
- the p-type semiconductor adopts polysilicon, p-type bismuth telluride, p-type silicon germanium or p-type antimony telluride;
- the p-type semiconductor in the p-type semiconductor film is polysilicon, p-type bismuth telluride, p-type silicon germanium or p-type antimony telluride;
- the thickness of the insulating layer is 30-150 nm;
- the pinhole pattern of the central window is transferred from the lithography mask to the front side of the wafer B-10, and then developed in a positive gel developer, and then rinsed with deionized water. surface to obtain wafer B-11;
- the photoresist used in the UV laser direct writing process is AZ5214E; the output power is 260W/us;
- the size of the small hole is 0.5 ⁇ m-5 ⁇ m;
- Assembly Assemble the obtained upper and lower films under a microscope, and align the central windows of the upper and lower films.
- the supersaturated calcium hydroxide aqueous solution (containing trace calcium hydroxide particles in the solution) was injected into the sample injection port of the transmission electron microscope high-resolution in-situ fluid freezing chip prepared in Example 1, and the temperature was controlled by external temperature control equipment.
- Software set the chip temperature to -30 °C, and obtain the electron microscope image of Figure 11. It is observed from A and B of Figure 11 that in the process of decreasing the temperature, due to the increase of solute solubility, the nanoparticles become smaller.
- the particle morphology and outline are clear, indicating that the imaging resolution of the chip in the electron microscope is high; at the same time, the position of the sample does not shift during the entire shooting process, indicating that the chip has good stability and low sample drift rate during the experiment.
- the transmission electron microscope high-resolution in-situ fluid freezing chip is used to measure the temperature reached by the chip under different output powers by using a thermometer to obtain a temperature standard curve, and then accurately control the temperature by accurately adjusting the output power of the power supply equipment.
- the results are shown in Figure 12. From the line graph in Figure 12, it can be seen that the temperature difference reaches 70 degrees within 5-6s, and the cooling rate is fast. And it can be stable at -50 degrees Celsius for a long time, which shows that the temperature control precision is high, and it also shows that the chip temperature control range of the present invention is large. Low temperature to high temperature can be.
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Abstract
Description
Claims (71)
- 一种透射电镜高分辨原位流体冷冻芯片,其结构为上片和下片通过金属键合层组合,其中上片和下片均分为正面和背面,上片的正面直接与下片的正面通过金属键合层粘结,自封闭形成一个超薄的腔室;所述上片和下片的材质均为两面有氮化硅或氧化硅的硅基片,上片设置有两个注样口和一个中心视窗1,其特征在于,下片设置有支撑层、冷冻层、绝缘层,孔洞以及中心视窗2;所述冷冻层设置有三个接触电极、六对半导体薄膜以及导电金属薄膜;中心视窗2的外围有一圈导电金属薄膜,其中心为中心视窗2;三个接触电极置于芯片边缘;六对半导体薄膜一端搭在导电金属薄膜上,另一端搭在电极上;以中心视窗2为中心,且在大于导电金属薄膜的外边缘区域内,硅腐蚀掉后留有孔洞,支撑层覆盖在孔洞的上方;导电金属薄膜置于孔洞上的支撑层上,冷冻层除接触电极区域的上方覆盖绝缘层;所述上片的面积略小于下片的面积,上片的中心视窗1与下片的中心视窗2对齐,中心视窗1和中心视窗2上均有多个小孔。
- 如权利要求1所述透射电镜高分辨原位流体冷冻芯片,其特征在于,所述下片的外形尺寸为2mm*2mm-10mm*10mm。
- 如权利要求1所述透射电镜高分辨原位流体冷冻芯片,其特征在于,所述下片的外形尺寸为4mm*8mm。
- 如权利要求1所述透射电镜高分辨原位流体冷冻芯片,其特征在于,所述金属键合层的厚度为50nm-2000nm;金属键合层的材料为低熔点金属。
- 如权利要求1所述透射电镜高分辨原位流体冷冻芯片,其特征在于,金属键合层的材料为In、Sn或Al。
- 如权利要求1所述透射电镜高分辨原位流体冷冻芯片,其特征在于,所述氮化硅或氧化硅的厚度为5-200nm。
- 如权利要求1所述透射电镜高分辨原位流体冷冻芯片,其特征在于,所述硅基片的厚度为50-500μm;
- 如权利要求1所述透射电镜高分辨原位流体冷冻芯片,其特征在于,所述上片的中心视窗1位于上片中心处,两个注样口关于中心视窗1对称布置。
- 如权利要求1所述透射电镜高分辨原位流体冷冻芯片,其特征在于,所述支撑层为氮化硅或氧化硅,厚度为0.5-5μm。
- 如权利要求1所述透射电镜高分辨原位流体冷冻芯片,其特征在于,所述冷冻层中,所述三个接触电极中的两个电极作为正极的输入电流;一个电极作为负极的输出电流。
- 如权利要求1所述透射电镜高分辨原位流体冷冻芯片,其特征在于,所述接触电极采用的是金、银或铜,厚度为50nm-300nm,正极的长为1-1.5mm,宽为0.5-1.2mm;负极的长1-1.5mm,宽0.4-0.8mm;
- 如权利要求1所述透射电镜高分辨原位流体冷冻芯片,其特征在于,所述六对半导体薄膜为六块n型半导体薄膜和六块P型半导体薄膜;六块n型半导体薄膜的形状为L型条状,平行对称置于芯片外侧;六块P型半导体薄膜的形状为规则矩形,平行并列置于芯片内侧。
- 如权利要求12所述透射电镜高分辨原位流体冷冻芯片,其特征在于,所述n型半导体薄膜中的n型半导体采用的是n型碲化铋、n型锗化硅、n型碲化铅、n型碲化锌或n型硒化铋;p型半导体薄膜中的p型半导体采用的是多晶硅、p型碲化铋、p型锗化硅或p型碲化锑。
- 如权利要求1所述透射电镜高分辨原位流体冷冻芯片,其特征在于,所述半导体薄膜的长为4-6mm,宽为0.4-0.8mm,厚度为50nm-500nm。
- 如权利要求1所述透射电镜高分辨原位流体冷冻芯片,其特征在于,所述导电金属薄膜为由导电金属形成的回字形导电金属薄膜,导电金属薄膜的中心为中心视窗2。
- 如权利要求15所述透射电镜高分辨原位流体冷冻芯片,其特征在于,所述导电金属采用的是金、银或铜,厚度为50nm-300nm。
- 如权利要求1所述透射电镜高分辨原位流体冷冻芯片,其特征在于所述导电金属薄膜的外方形尺寸为100μm*100μm-500μm*500μm,内方形尺寸为5μm*5μm-100μm*100μm。
- 如权利要求1所述透射电镜高分辨原位流体冷冻芯片,其特征在于,所述绝缘层为一层氮化硅或氧化硅,厚度为30-150nm。
- 如权利要求1所述透射电镜高分辨原位流体冷冻芯片,其特征在于,所述孔洞为圆形孔洞或方形孔洞。
- 如权利要求19所述透射电镜高分辨原位流体冷冻芯片,其特征在于,圆形孔洞的直径为200μm-600μm;方形孔洞的尺寸为200μm*200μm-800μm*800μm。
- 如权利要求1所述透射电镜高分辨原位流体冷冻芯片,其特征在于,所述中心视窗1和中心视窗2均为方形中心视窗。
- 如权利要求21所述透射电镜高分辨原位流体冷冻芯片,其特征在于,所述方形中心视窗的大小为5μm*5μm-100μm*100μm。
- 如权利要求21所述透射电镜高分辨原位流体冷冻芯片,其特征在于,所述方形中心视窗的大小为20μm*50μm;
- 如权利要求1所述透射电镜高分辨原位流体冷冻芯片,其特征在于,所述小孔的大小为0.5μm-5μm。
- 如权利要求1所述透射电镜高分辨原位流体冷冻芯片,其特征在于,所述上片的制备方法为,S1.利用光刻工艺,将中心视窗图案从光刻掩膜版转移到两面带有氮化硅或氧化硅层的Si(100)晶圆A,然后在正胶显影液中显影得到晶圆A-1;S2.利用反应离子刻蚀工艺,在所述晶圆A-1的正面的氮化硅层上刻蚀出中心视窗,然后将晶圆A-1的正面朝上放入丙酮浸泡,最后用大量去离子水冲洗,去除光刻胶,得到晶圆A-2;S3.利用紫外激光直写工艺,将中心视窗的小孔图案从光刻掩膜版转移到晶圆A-2的正面,然后在正胶显影液中显影,再用去离子水冲洗清洗表面,得到晶圆A-3;S4.利用反应离子刻蚀工艺,在晶圆A-3的背面的小孔处的氮化硅厚度刻蚀至10nm-15nm,然后将晶圆A-3的正面朝上先后放入丙酮中浸泡,最后用丙酮冲洗,去掉光刻胶,得到晶圆A-4;S5.将晶圆A-4的背面朝上放入氢氧化钾溶液中进行湿法刻蚀,刻蚀直至正面只留下薄膜窗口,取出晶圆A-4用大量去离子水冲洗,得到晶圆A-5;S6.利用光刻工艺,将键合层图案从光刻掩膜版转移到晶圆A-5的正面,然后在正胶显影液中显影,再用去离子水冲洗清洗表面,得到晶圆A-6;S7.利用热蒸发镀膜工艺,将晶圆A-6蒸镀金属键合材料形成金属键合层,得到晶圆A-7;S8.将晶圆A-7进行激光划片,分成独立芯片即为上片。
- 如权利要求25所述透射电镜高分辨原位流体冷冻芯片,其特征在于,所述S1步骤中,光刻工艺为在紫外光刻机的hard contact模式下曝光;所述氮化硅或氧化硅层的厚度5-200nm;显影的时间为50s。
- 如权利要求26所述透射电镜高分辨原位流体冷冻芯片,其特征在于,所述曝光的时间为15s。
- 如权利要求25所述透射电镜高分辨原位流体冷冻芯片,其特征在于,所述S3步骤中,所述显影的时间为50s。
- 如权利要求25所述透射电镜高分辨原位流体冷冻芯片,其特征在于,所述S4步骤中,所述小孔的大小为0.5μm-5μm。
- 如权利要求25所述透射电镜高分辨原位流体冷冻芯片,其特征在于,所述S5步骤中,优选的,所述氢氧化钾溶液的质量百分比浓度为20%;所述刻蚀的温度为80℃,时间为1.5-4h。
- 如权利要求30所述透射电镜高分辨原位流体冷冻芯片,其特征在于,所述刻蚀的时间为2h。
- 如权利要求25所述透射电镜高分辨原位流体冷冻芯片,其特征在于,所述S6步骤中,所述光刻工艺为在紫外光刻机的hard contact模式下曝光;所述显影的时间为50s。
- 如权利要求32所述透射电镜高分辨原位流体冷冻芯片,其特征在于,所述所述曝光时间为15s。
- 如权利要求25所述透射电镜高分辨原位流体冷冻芯片,其特征在于,所述S7步骤中,所述金属为低熔点金属;所述金属键合层的厚度为50-2000nm。
- 如权利要求34所述透射电镜高分辨原位流体冷冻芯片,其特征在于,所述金属为In、Sn或Al。
- 如权利要求1所述透射电镜高分辨原位流体冷冻芯片,其特征在于,所述下片的制备方法为,S1.准备两面带有氮化硅或氧化硅层的Si(100)晶圆B;S2.利用光刻工艺,将中心视窗外圈导电金属载膜图案从光刻掩膜版转移到上述晶圆的背面,然后在正胶显影液中显影,再用去离子水清洗表面得到晶圆B-1;S3.利用反应离子刻蚀工艺,在晶圆B-1的背面的氮化硅层上刻蚀出导电金属的氮化硅或氧化硅刻蚀掉,然后将晶圆背面朝上先后放入丙酮中浸泡,最后用丙酮冲洗,去掉光刻胶,得到晶圆B-2;S4.利用PECVD工艺,在晶圆B-2腐蚀后的硅片上正面生长氧化硅或氮化硅,得到晶圆B-3;S5.利用光刻工艺,将金属薄膜图案及接触电极图案从光刻掩膜版转移到晶圆B-3的正面,然后在正胶显影液中显影,再用去离子水冲洗清洗表面,得到晶圆B-4;S6.利用直流磁控溅射,在晶圆B-4的正面溅射一层金属薄膜,然后将晶圆B-4的正面朝上先后放入丙酮中浸泡剥离,最后用去离子水冲洗,去除光刻胶,留下金属薄膜,得到晶圆B-5;S7.利用光刻工艺,将n型半导体图案从光刻掩膜版转移到晶圆B-5的正面,然后在正胶显影液中显影,再用去离子水冲洗清洗表面,得到晶圆B-6;S8.用射频磁控溅射,在晶圆B-6的正面溅射一层n型半导体薄膜,然后将晶圆B-6的正面朝上先后放入丙酮中浸泡剥离,最后用去离子水冲洗,去除光刻胶,留下n型半导体薄膜,得到晶圆B-7;S9.利用光刻工艺,将p型半导体图案从光刻掩膜版转移到晶圆B-7的正面,然后在正胶显影液中显影,再用去离子水冲洗清洗表面,得到晶圆B-8;S10.利用射频磁控溅射,在晶圆B-8的正面溅射一层p型半导体薄膜,然后将晶圆11的正面朝上先后放入丙酮中浸泡剥离,最后用去离子水冲洗,去除光刻胶,留下p型半导体薄膜,得到晶圆B-9;S11.利用PECVD工艺,在晶圆B-9的半导体薄膜生长一层氮化硅或氧化硅或氧化铝作为绝缘层,得到晶圆B-10;S12.利用紫外激光直写光刻工艺,将中心视窗的小孔图案从光刻掩膜版转移到晶圆B-10的正面,然后在正胶显影液中显影,再用去离子水冲洗清洗表面,得到晶圆B-11;S13.利用反应离子刻蚀工艺,在晶圆B-11的背面的小孔处的氮化硅或氧化硅刻蚀,然后将晶圆B-11的正面朝上放入丙酮中浸泡,最后用丙酮冲洗,去掉光刻胶,得到晶圆B-12;S14.将晶圆B-12进行激光划片,分成独立芯片即为下片。
- 如权利要求36所述透射电镜高分辨原位流体冷冻芯片,其特征在于,所述S1步骤 中,氮化硅或氧化硅层的厚度5-200nm。
- 如权利要求36所述透射电镜高分辨原位流体冷冻芯片,其特征在于,所述S2步骤中,所述光刻工艺为在紫外光刻机的hard contact模式下曝光;光刻工艺中使用的光刻胶为AZ5214E;显影的时间为65s。
- 如权利要求38所述透射电镜高分辨原位流体冷冻芯片,其特征在于,所述曝光的时间为20s。
- 如权利要求36所述透射电镜高分辨原位流体冷冻芯片,其特征在于,所述S3步骤中,所述导电金属薄膜的外方形尺寸为100μm*100μm-500μm*500μm,内方形尺寸为5μm*5μm-100μm*100μm。
- 如权利要求36所述透射电镜高分辨原位流体冷冻芯片,其特征在于,所述S4步骤中,氧化硅或氮化硅的厚度为0.5-5μm。
- 如权利要求36所述透射电镜高分辨原位流体冷冻芯片,其特征在于,所述S6步骤中,所述金属薄膜采用的是金、银或铜,厚度为50nm-300nm。
- 如权利要求36所述透射电镜高分辨原位流体冷冻芯片,其特征在于,所述S8步骤中,所述n型半导体薄膜中的n型半导体采用的是n型碲化铋、n型锗化硅、n型碲化铅、n型碲化锌或n型硒化铋。
- 如权利要求36所述透射电镜高分辨原位流体冷冻芯片,其特征在于,所述S9步骤中,所述p型半导体采用的是多晶硅、p型碲化铋、p型锗化硅或p型碲化锑。
- 如权利要求36所述透射电镜高分辨原位流体冷冻芯片,其特征在于,所述S10步骤中,所述p型半导体薄膜中的p型半导体采用的是多晶硅、p型碲化铋、p型锗化硅或p型碲化锑。
- 如权利要求36所述透射电镜高分辨原位流体冷冻芯片,其特征在于,所述S11步骤中,所述绝缘层的厚度为30-150nm。
- 如权利要求36所述透射电镜高分辨原位流体冷冻芯片,其特征在于,所述S12步骤中,所述紫外激光直写工艺的所用光刻胶为AZ5214E;输出功率为260W/us。
- 如权利要求36所述透射电镜高分辨原位流体冷冻芯片,其特征在于,所述S13步骤中,优选的,所述小孔的大小为0.5μm-5μm。
- 一种权利要求1-48任一所述透射电镜高分辨原位流体冷冻芯片的制备方法,其特征在于,所述上片的制备方法为,S1.利用光刻工艺,将中心视窗图案从光刻掩膜版转移到两面带有氮化硅或氧化硅层的Si(100)晶圆A,然后在正胶显影液中显影得到晶圆A-1;S2.利用反应离子刻蚀工艺,在所述晶圆A-1的正面的氮化硅层上刻蚀出中心视窗,然后将晶圆A-1的正面朝上放入丙酮浸泡,最后用大量去离子水冲洗,去除光刻胶,得到晶圆A-2;S3.利用紫外激光直写工艺,将中心视窗的小孔图案从光刻掩膜版转移到晶圆A-2的正面,然后在正胶显影液中显影,再用去离子水冲洗清洗表面,得到晶圆A-3;S4.利用反应离子刻蚀工艺,在晶圆A-3的背面的小孔处的氮化硅厚度刻蚀至10nm-15nm,然后将晶圆A-3的正面朝上先后放入丙酮中浸泡,最后用丙酮冲洗,去掉光刻胶,得到晶圆A-4;S5.将晶圆A-4的背面朝上放入氢氧化钾溶液中进行湿法刻蚀,刻蚀直至正面只留下薄膜窗口,取出晶圆A-4用大量去离子水冲洗,得到晶圆A-5;S6.利用光刻工艺,将键合层图案从光刻掩膜版转移到晶圆A-5的正面,然后在正胶显影液中显影,再用去离子水冲洗清洗表面,得到晶圆A-6;S7.利用热蒸发镀膜工艺,将晶圆A-6蒸镀金属键合材料形成金属键合层,得到晶圆A-7;S8.将晶圆A-7进行激光划片,分成独立芯片即为上片;所述下片的制备方法为,S1.准备两面带有氮化硅或氧化硅层的Si(100)晶圆B;S2.利用光刻工艺,将中心视窗外圈导电金属载膜图案从光刻掩膜版转移到上述晶圆的背面,然后在正胶显影液中显影,再用去离子水清洗表面得到晶圆B-1;S3.利用反应离子刻蚀工艺,在晶圆B-1的背面的氮化硅层上刻蚀出导电金属的氮化硅或氧化硅刻蚀掉,然后将晶圆背面朝上先后放入丙酮中浸泡,最后用丙酮冲洗,去掉光刻胶,得到晶圆B-2;S4.利用PECVD工艺,在晶圆B-2腐蚀后的硅片上正面生长氧化硅或氮化硅,得到晶圆B-3;S5.利用光刻工艺,将金属薄膜图案及接触电极图案从光刻掩膜版转移到晶圆B-3的正面,然后在正胶显影液中显影,再用去离子水冲洗清洗表面,得到晶圆B-4;S6.利用直流磁控溅射,在晶圆B-4的正面溅射一层金属薄膜,然后将晶圆B-4的正面朝上先后放入丙酮中浸泡剥离,最后用去离子水冲洗,去除光刻胶,留下金属薄膜,得到晶圆B-5;S7.利用光刻工艺,将n型半导体图案从光刻掩膜版转移到晶圆B-5的正面,然后在正胶显影液中显影,再用去离子水冲洗清洗表面,得到晶圆B-6;S8.用射频磁控溅射,在晶圆B-6的正面溅射一层n型半导体薄膜,然后将晶圆B-6的正面朝上先后放入丙酮中浸泡剥离,最后用去离子水冲洗,去除光刻胶,留下n型半导体薄膜,得到晶圆B-7;S9.利用光刻工艺,将p型半导体图案从光刻掩膜版转移到晶圆B-7的正面,然后在正胶显影液中显影,再用去离子水冲洗清洗表面,得到晶圆B-8;S10.利用射频磁控溅射,在晶圆B-8的正面溅射一层p型半导体薄膜,然后将晶圆11的正面朝上先后放入丙酮中浸泡剥离,最后用去离子水冲洗,去除光刻胶,留下p型半导体薄膜,得到晶圆B-9;S11.利用PECVD工艺,在晶圆B-9的半导体薄膜生长一层氮化硅或氧化硅或氧化铝作为绝缘层,得到晶圆B-10;S12.利用紫外激光直写光刻工艺,将中心视窗的小孔图案从光刻掩膜版转移到晶圆B-10的正面,然后在正胶显影液中显影,再用去离子水冲洗清洗表面,得到晶圆B-11;S13.利用反应离子刻蚀工艺,在晶圆B-11的背面的小孔处的氮化硅或氧化硅刻蚀,然后将晶圆B-11的正面朝上放入丙酮中浸泡,最后用丙酮冲洗,去掉光刻胶,得到晶圆B-12;S14.将晶圆B-12进行激光划片,分成独立芯片即为下片;组装:将所得上片和下片在显微镜下进行组装,使上片和下片的中心视窗对齐即可。
- 如权利要求49所述透射电镜高分辨原位流体冷冻芯片,其特征在于,所述上片制备的S1步骤中,光刻工艺为在紫外光刻机的hard contact模式下曝光;所述氮化硅或氧化硅层的厚度5-200nm;显影的时间为50s。
- 如权利要求50所述透射电镜高分辨原位流体冷冻芯片,其特征在于,所述曝光的时间为15s。
- 如权利要求49所述透射电镜高分辨原位流体冷冻芯片,其特征在于,所述上片制备的S3步骤中,显影的时间为50s。
- 如权利要求49所述透射电镜高分辨原位流体冷冻芯片,其特征在于,所述上片制备的S4步骤中,小孔的大小为0.5μm-5μm。
- 如权利要求49所述透射电镜高分辨原位流体冷冻芯片,其特征在于,所述上片制备的S5步骤中,所述氢氧化钾溶液的质量百分比浓度为20%;所述刻蚀的温度为80℃,时间为1.5-4h。
- 如权利要求54所述透射电镜高分辨原位流体冷冻芯片,其特征在于,所述刻蚀的时间为2h。
- 如权利要求49所述透射电镜高分辨原位流体冷冻芯片,其特征在于,所述上片制备的S6步骤中,所述光刻工艺为在紫外光刻机的hard contact模式下曝光;所述显影的时间为50s。
- 如权利要求56所述透射电镜高分辨原位流体冷冻芯片,其特征在于,所述所述曝光时间为15s。
- 如权利要求49所述透射电镜高分辨原位流体冷冻芯片,其特征在于,所述上片制备的S7步骤中,金属为低熔点金属;所述金属键合层的厚度为50-2000nm。
- 如权利要求58所述透射电镜高分辨原位流体冷冻芯片,其特征在于,所述金属为In、Sn或Al。
- 如权利要求49所述透射电镜高分辨原位流体冷冻芯片,其特征在于,所述下片制备的S1步骤中,氮化硅或氧化硅层厚度5-200nm。
- 如权利要求49所述透射电镜高分辨原位流体冷冻芯片,其特征在于,所述下片制备的S2步骤中,优选的,所述光刻工艺为在紫外光刻机的hard contact模式下曝光;光刻工艺中使用的光刻胶为AZ5214E;显影的时间为65s。
- 如权利要求61所述透射电镜高分辨原位流体冷冻芯片,其特征在于,所述曝光的时间为20s。
- 如权利要求49所述透射电镜高分辨原位流体冷冻芯片,其特征在于,所述下片制备的S3步骤中,所述导电金属薄膜的外方形尺寸为100μm*100μm-500μm*500μm,内方形尺寸为5μm*5μm-100μm*100μm。
- 如权利要求49所述透射电镜高分辨原位流体冷冻芯片,其特征在于,所述下片制备的S4步骤中,氧化硅或氮化硅的厚度为0.5-5μm。
- 如权利要求49所述透射电镜高分辨原位流体冷冻芯片,其特征在于,所述下片制备的S6步骤中,金属薄膜采用的是金、银或铜,厚度为50nm-300nm。
- 如权利要求49所述透射电镜高分辨原位流体冷冻芯片,其特征在于,所述下片制备的S8步骤中,所述n型半导体薄膜中的n型半导体采用的是n型碲化铋、n型锗化硅、n型碲化铅、n型碲化锌或n型硒化铋。
- 如权利要求49所述透射电镜高分辨原位流体冷冻芯片,其特征在于,所述下片制备的S9步骤中,所述p型半导体采用的是多晶硅、p型碲化铋、p型锗化硅或p型碲化锑。
- 如权利要求49所述透射电镜高分辨原位流体冷冻芯片,其特征在于,所述下片制备的S10步骤中,所述p型半导体薄膜中的p型半导体采用的是多晶硅、p型碲化铋、p型锗化硅或p型碲化锑。
- 如权利要求49所述透射电镜高分辨原位流体冷冻芯片,其特征在于,所述下片制备的S11步骤中,所述绝缘层的厚度为30-150nm。
- 如权利要求49所述透射电镜高分辨原位流体冷冻芯片,其特征在于,所述下片制备的S12步骤中,所述紫外激光直写工艺的所用光刻胶为AZ5214E;输出功率为260W/us。
- 如权利要求49所述透射电镜高分辨原位流体冷冻芯片,其特征在于,所述下片制备的S13步骤中,所述小孔的大小为0.5μm-5μm。
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CN206535564U (zh) * | 2017-02-17 | 2017-10-03 | 深圳韦拓生物科技有限公司 | 一种用于细胞冷冻的微流控芯片及混合系统 |
CN111370280A (zh) * | 2020-03-12 | 2020-07-03 | 厦门超新芯科技有限公司 | 一种透射电镜高分辨原位气相加热芯片及其制备方法 |
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CN114563259A (zh) * | 2022-04-29 | 2022-05-31 | 北京大学 | 一种基于微流控芯片制备时间分辨冷冻电镜样品的方法及装置 |
CN114563259B (zh) * | 2022-04-29 | 2022-07-26 | 北京大学 | 一种基于微流控芯片制备时间分辨冷冻电镜样品的方法及装置 |
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