WO2022028028A1 - 半导体结构及半导体结构的制造方法 - Google Patents

半导体结构及半导体结构的制造方法 Download PDF

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Publication number
WO2022028028A1
WO2022028028A1 PCT/CN2021/093135 CN2021093135W WO2022028028A1 WO 2022028028 A1 WO2022028028 A1 WO 2022028028A1 CN 2021093135 W CN2021093135 W CN 2021093135W WO 2022028028 A1 WO2022028028 A1 WO 2022028028A1
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WIPO (PCT)
Prior art keywords
groove
isolation structure
semiconductor structure
word line
convex
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PCT/CN2021/093135
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English (en)
French (fr)
Inventor
何亚川
黄信斌
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长鑫存储技术有限公司
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Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to EP21852276.1A priority Critical patent/EP4084073A4/en
Priority to JP2022552276A priority patent/JP7450058B2/ja
Priority to KR1020227037887A priority patent/KR20220152339A/ko
Priority to US17/445,317 priority patent/US20220045071A1/en
Publication of WO2022028028A1 publication Critical patent/WO2022028028A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines

Definitions

  • the present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor structure and a method for manufacturing the semiconductor structure.
  • DRAM Dynamic Random Access Memory
  • the present disclosure provides a semiconductor structure and a method for fabricating the semiconductor structure to improve the performance of the semiconductor structure.
  • a semiconductor structure comprising:
  • the word line includes a first protruding portion and a second protruding portion, wherein the first protruding portion and the second protruding portion are located in the isolation structure, and the depth of the first protruding portion is greater than that of the second protruding portion.
  • the word line further includes: a main body part connected to the first convex part and the second convex part.
  • both the first convex portion and the second convex portion are plural, and the plurality of first convex portions and the plurality of second convex portions are arranged at intervals.
  • the isolation structure includes a first isolation structure and a second isolation structure; the first protrusion is located in the first isolation structure, the second protrusion is located in the second isolation structure, and the bottom of the first isolation structure lower than the bottom of the second isolation structure.
  • the depth ratio of the first convex portion and the second convex portion is greater than 1.05.
  • the depth of the first convex portion is greater than 30 nm.
  • the length of the first convex portion in the extending direction of the vertical word line is greater than the length of the second convex portion in the extending direction of the vertical word line.
  • the first protrusion includes:
  • the side wall of the convex lower part has a first slope
  • the side wall of the convex upper part has a second slope
  • the first slope is different from the second slope.
  • the sidewall of the second protrusion has a third slope, and the first slope is the same as the third slope.
  • the cross-section of the convex upper portion along the substrate surface direction is circular or elliptical, and the cross-section of the convex lower portion along the substrate surface direction is strip-shaped.
  • the bar shape includes two parallel line segments and two arc-shaped line segments connecting ends of the two line segments.
  • a plurality of active regions are arranged in the substrate, and an isolation structure is arranged between the plurality of active regions;
  • the main body part intersects with the active region.
  • the plurality of active regions are arranged in a plurality of rows
  • the first isolation structure is located between the end portions of the two active regions, and the second isolation structure is located between the side portions of the two adjacent active regions.
  • a method for fabricating a semiconductor structure comprising:
  • a substrate having an isolation structure and a plurality of active regions, the isolation structure being disposed between the plurality of active regions;
  • first grooves and second grooves on the isolation structure, and the depth of the first groove is greater than the depth of the second groove;
  • a word line is formed in the substrate.
  • the word line includes a main body portion, a first protruding portion and a second protruding portion.
  • the first protruding portion and the second protruding portion are respectively disposed in the first groove and the second groove.
  • forming the first groove and the second groove on the isolation structure includes:
  • a first groove and a second groove are formed on the isolation structure having the groove, and the first groove is formed at the position of the groove.
  • forming grooves on the isolation structure includes:
  • first photoresist layer with photoresist openings on the substrate, and the photoresist openings are located between the ends of two adjacent active regions;
  • the isolation structures are etched using photoresist openings to form grooves.
  • the method before forming the first photoresist layer on the substrate, the method further includes:
  • a first photoresist layer is formed on the word line mask layer.
  • the wordline mask openings have a first dimension perpendicular to the extending direction thereof, and the photoresist openings on the first photoresist layer have a second dimension perpendicular to the extending direction of the wordline mask openings size, the second size is larger than the first size.
  • forming the first groove and the second groove on the isolation structure includes:
  • the isolation structure is etched using the word line mask opening to form the first groove and the second groove.
  • the semiconductor structure of the present disclosure can enhance the control ability of the word line to the transistor channel and improve the leakage current by making the first protrusion of the word line have a longer depth.
  • FIG. 1 is a schematic structural diagram of a semiconductor structure according to an exemplary embodiment
  • Fig. 2 is the structural representation at A-A place in Fig. 1;
  • Fig. 3 is the structural representation at B-B place in Fig. 1;
  • FIG. 4 is a schematic structural diagram of a first protrusion of a semiconductor structure according to an exemplary embodiment
  • FIG. 5 is a schematic structural diagram of a first protrusion of a semiconductor structure according to another exemplary embodiment
  • FIG. 6 is a schematic structural diagram of a second convex portion of a semiconductor structure according to an exemplary embodiment
  • FIG. 7 is a schematic flowchart of a method for manufacturing a semiconductor structure according to an exemplary embodiment
  • FIG. 8 is a schematic view of the structure after forming a first photoresist layer according to a method for manufacturing a semiconductor structure according to an exemplary embodiment
  • FIG. 9 is a schematic structural diagram showing a method for manufacturing a semiconductor structure after forming grooves according to an exemplary embodiment
  • 10A-10C are schematic structural diagrams illustrating a method for manufacturing a semiconductor structure according to an exemplary embodiment
  • Fig. 11 is a schematic diagram showing a structure after forming a first groove and a second groove in a method for manufacturing a semiconductor structure according to an exemplary embodiment.
  • a second isolation structure 10, substrate; 11, active region; 20, first isolation structure; 30, word line; 31, main body part; 32, first convex part; 33, second convex part; 321, convex lower part; 322, convex upper part; 40, first photoresist layer; 41, groove; 43, photoresist opening; 44, word line mask layer; 231, first groove; 232, second groove; 45, word line mask Membrane opening; 50.
  • a second isolation structure A second isolation structure.
  • the semiconductor structure includes: a substrate 10 ; an isolation structure formed in the substrate 10 ; a word line 30 , and the word line 30 includes a first protrusion
  • the first convex portion 32 and the second convex portion 33 are located in the isolation structure, and the depth of the first convex portion 32 is greater than the depth of the second convex portion 33 .
  • the control ability of the word line 30 over the transistor channel can be enhanced, and the leakage current can be improved.
  • the depth of the first convex portion 32 can be understood as the vertical distance from the bottom of the first convex portion 32 to the main body portion 31 of the word line 30 .
  • the depth of the second convex portion 33 can be understood as the vertical distance from the bottom of the second convex portion 33 to the main body portion 31 of the word line 30 .
  • the word line 30 further includes a main body portion 31 , and the main body portion 31 is connected to the first convex portion 32 and the second convex portion 33 .
  • both the first protruding portion 32 and the second protruding portion 33 are multiple, and the multiple first protruding portions 32 and the multiple second protruding portions 33 are arranged at intervals.
  • a plurality of first protrusions 32 and a plurality of second protrusions 33 are provided in the isolation structure at intervals.
  • the isolation structure includes a first isolation structure 20 and a second isolation structure 50; the first protrusion 32 is located in the first isolation structure 20, the second protrusion 33 is located in the second isolation structure 50, and the first isolation The bottom of the structure 20 is lower than the bottom of the second isolation structure 50 .
  • a plurality of active regions 11 are disposed in the substrate 10 , and the isolation structure is disposed between the plurality of active regions 11 ; wherein, the main body portion 31 intersects the active regions 11 .
  • active regions 11 are formed in the substrate 10 , and isolation structures are filled between adjacent active regions 11 , and the depths of each isolation structure may be the same or different; it can be seen from FIG. 1 that the word lines 30 cross over The plurality of active regions 11 , that is, the main body portion 31 intersects the active regions 11 .
  • the plurality of active regions 11 are arranged in multiple rows; wherein, the first isolation structure 20 is located between the ends of two adjacent active regions 11 , and the second isolation structure 50 is located between two adjacent active regions 11 . between the sides of the active region 11 .
  • a plurality of active regions 11 are arranged in multiple rows, and each row is arranged in parallel, while the word lines 30 span across the multiple rows of active regions 11 , and two adjacent active regions in two adjacent rows The distance between the sides of 11 is relatively short, while the distance between the ends of two adjacent active regions 11 in a row is relatively far.
  • the depth ratio of the first convex portion 32 and the second convex portion 33 is greater than 1.05. It should be noted that, in the related art, in an ideal state, the depths of the protrusions of the word lines are all equal, that is, when etching grooves for accommodating protrusions, the depths of each groove should be the same, but the depth of each groove should be the same. Due to the limitations of the etching process, during specific etching, the depth of each groove will basically fluctuate on a small scale (but in terms of the fluctuation value, it can still be considered that the depth of each groove is equal), so that each convex part will also There are corresponding fluctuations.
  • the depth ratio between the first convex portion 32 and the second convex portion 33 is greater than 1.05, which is different from the height difference caused by fluctuation in the related art. performance of semiconductor structures.
  • the depth ratio of the first convex portion 32 and the second convex portion 33 may be greater than 1.1, 1.2, 1.3, 1.4, 1.5 or 1.6.
  • the substrate 10 may be a p-type silicon substrate, an n-type silicon substrate, a silicon germanium substrate, or the like.
  • the depth of the first protrusions 32 is greater than 30 nm.
  • the depth ratio of the first convex portion 32 and the second convex portion 33 is determined, and the depth of the second convex portion 33 is determined according to the depth value of the first convex portion 32 .
  • the depth of the second protrusions 33 is less than 25 nm.
  • the depth ratio of the first convex portion 32 and the second convex portion 33 is determined, and the depth of the first convex portion 32 is determined according to the depth value of the second convex portion 33 .
  • the length of the first protruding portion 32 on the word line 30 along the extending direction of the vertical word line 30 is greater than the length of the second protruding portion 33 along the extending direction of the vertical word line 30 .
  • the length of the first convex portion 32 on the same word line 30 perpendicular to the extending direction of the word line 30 can be understood as that the surface connecting the first convex portion 32 and the main body portion 31 has a first dimension along the extending direction of the main body portion 31 . and a second dimension perpendicular to the extending direction of the main body portion 31, correspondingly, the second convex portion 33 also has a third dimension along the extending direction of the main body portion 31 and a fourth dimension perpendicular to the extending direction of the main body portion 31, And the second size is larger than the fourth size.
  • the first protruding portion 32 includes: a protruding lower portion 321, the sidewall of which has a first slope; a protruding upper portion 322, whose sidewall has a second slope; wherein the first slope is different from second slope.
  • the side walls of the convex upper part 322 and the convex lower part 321 can be the side walls of the convex upper part 322 and the convex lower part 321 along the AA section;
  • the convex upper part 322 is formed, and the top end of the convex upper part 322 is connected to the main body part 31 .
  • the first slope is different from the second slope, that is, the inclination of the side wall of the convex lower part 321 with respect to the vertical direction is different from the inclination of the side wall of the convex upper part 322 with respect to the vertical direction, the side wall of the convex lower part 321 and the convex upper part
  • the side walls of 322 are neither parallel nor in the same plane.
  • the first slope is greater than the second slope, that is, the angle between the sidewall of the convex lower portion 321 and the vertical direction is smaller than the angle between the sidewall of the convex upper portion 322 and the vertical direction.
  • the included angle between the side wall of the convex portion 321 and the vertical direction is smaller than the included angle between the side wall of the convex portion 322 and the vertical direction, the process difficulty can be reduced and the process window can be increased.
  • the included angle of the convex upper portion 322 is relatively large, which is beneficial to the formation of the first convex portion of the word line.
  • the side wall of the second convex portion 33 has a third slope, and the first slope is the same as the third slope, that is, the side wall of the convex portion 321 is sandwiched with the vertical direction.
  • the angle is the same as the angle between the side wall of the second convex portion 33 and the vertical direction.
  • a one-step etching process can be used to simultaneously form the groove where the convex portion 321 and the second convex portion 33 are located, so that the slopes of the sidewalls of the convex portion 321 and the second convex portion 33 are filled in the groove.
  • the forming steps can be simplified.
  • the bottom dimension of the convex upper portion 322 is greater than or equal to the top dimension of the convex lower portion 321 .
  • the top dimension of the convex upper part 322 is larger than the bottom dimension of the convex upper part 322
  • the top dimension of the convex lower part 321 is larger than the bottom dimension of the convex lower part 321
  • the top dimension of the convex lower part 321 is the same as the bottom dimension of the convex upper part 322 , That is, the part where the convex upper part 322 and the convex lower part 321 are connected completely overlap.
  • the top dimension of the convex upper part 322 is larger than the bottom dimension of the convex upper part 322
  • the top dimension of the convex lower part 321 is larger than the bottom dimension of the convex lower part 321
  • the top dimension of the convex lower part 321 is smaller than the bottom dimension of the convex upper part 322 by the same size, That is, the parts where the convex upper part 322 and the convex lower part 321 are connected do not completely overlap. In this way, the process window is enlarged, and the risk of direct contact between the convex portion 321 and the active region is reduced.
  • the top dimension of the second convex portion 33 is larger than the bottom dimension of the second convex portion 33 , so that the side wall of the second convex portion 33 has a third slope.
  • the cross-section of the convex upper portion 322 in the direction of the substrate surface is circular or oval, and the cross-section of the convex lower portion 321 in the direction of the substrate surface is strip-shaped.
  • the specific shapes of the convex upper part 322 and the convex lower part 321 can be controlled by the first groove 231 and the second groove 232 , which are not limited here, and can be selected according to actual needs.
  • the bar shape includes two parallel line segments and two arc-shaped line segments connecting the ends of the two line segments.
  • the section of the convex lower part 321 is surrounded by two parallel line segments and two opposite arc line segments. Specifically, the line segment is parallel to the extending direction of the word line 30 .
  • the line segment edges of the convex lower portion 321 can reduce the risk of direct contact with adjacent active regions, and at the same time, the arc-shaped line segment edges can reduce the difficulty of forming the convex lower portion.
  • the arc-shaped line segment edge is conducive to the filling of the conductor material.
  • An embodiment of the present disclosure also provides a method for fabricating a semiconductor structure, as shown in FIGS. 7 to 11 , the method for fabricating the semiconductor structure includes:
  • S101 providing a substrate 10 having an isolation structure and a plurality of active regions 11, and the isolation structure is arranged between the plurality of active regions 11;
  • the word line 30 is formed in the substrate 10 .
  • the word line 30 includes a main body portion 31 , a first protruding portion 32 and a second protruding portion 33 .
  • the first protruding portion 32 and the second protruding portion 33 are respectively disposed in the first groove 231 and the second groove 232.
  • a method of fabricating a semiconductor structure according to an embodiment of the present disclosure includes forming a first groove 231 and a second groove 232 on a substrate 10 having an isolation structure and a plurality of active regions 11 , and forming word lines in the substrate 10 30, and the first convex portion 32 of the word line 30 has a longer depth, which can effectively improve the leakage current phenomenon of the semiconductor structure.
  • the provided substrate 10 is a substrate 10 having an isolation structure and multiple active regions 11 , that is, regardless of the specific molding method of the isolation structure and multiple active regions 11 , the The first groove 231 and the second groove 232 are formed on the substrate 10, and the word line 30 is formed. Before forming the first groove 231 and the second groove 232, dry etching or chemical mechanical polishing (Chemical Mechanical Polishing, CMP) may be used to planarize the substrate 10.
  • CMP chemical mechanical polishing
  • the word line 30 is a buried word line, and the material of the word line 30 includes one or any combination of conductive materials such as tungsten, titanium, nickel, aluminum, platinum, and titanium nitride. After the word lines 30 are formed, the word lines 30 may be planarized using dry etching or chemical mechanical polishing (CMP).
  • CMP chemical mechanical polishing
  • forming the first groove 231 and the second groove 232 on the isolation structure includes: forming a groove 41 on the isolation structure, and the groove 41 is located between the ends of two adjacent active regions 11 .
  • the first groove 231 and the second groove 232 are formed on the isolation structure having the groove 41, and the first groove 231 is formed at the position where the groove 41 is located.
  • a plurality of active regions 11 are arranged in parallel rows, and an isolation structure is located between the plurality of active regions 11 , and the isolation structure includes a first isolation structure 20 and a second isolation structure 50 .
  • the first isolation structure 20 is located between the end portions of two adjacent active regions 11
  • the second isolation structure 50 is located between the side portions of two adjacent active regions 11 .
  • a part of the first isolation structure 20 is etched to form a groove 41 , and then a first groove 231 and a second groove 232 are etched on the substrate 10 having the groove 41 , and the first groove 231 is formed by the groove 41
  • the position is etched downward, so as to realize the control of the formation depth of the first groove 231 and the second groove 232, and also ensure that the first groove 231 with a larger depth is etched.
  • forming the groove 41 on the isolation structure includes: forming a first photoresist layer 40 with photoresist openings 43 on the substrate 10, and the photoresist openings 43 are located at two adjacent active Between the ends of the regions 11 ; the isolation structure is etched using the photoresist openings 43 to form the grooves 41 . Specifically, the photoresist opening 43 is located above the first isolation structure 20 , and a part of the first isolation structure 20 is etched to form the groove 41 .
  • a word line mask layer 44 is formed on the substrate 10, the first photoresist layer 40 is located on the word line mask layer 44, and the word line mask layer 44 is first etched by using the photoresist opening 43 and then using the etched word line mask layer 44 to etch the first isolation structure 20 to form a groove 41 .
  • forming the first groove 231 and the second groove 232 on the isolation structure with the groove 41 includes: forming a patterned second photoresist layer on the substrate 10; using the patterned second photoresist layer; The second photoresist layer etches the isolation structure, and the first groove 231 and the second groove 232 are formed on the isolation structure.
  • a gate dielectric layer is formed in the first groove 231 and the second groove 232 .
  • the word line 30 is formed by filling the substrate 10 having the first groove 231 and the second groove 232 with one or any combination of conductive materials such as tungsten, titanium, nickel, aluminum, platinum, titanium nitride, etc. .
  • the word lines 30 may be formed by chemical vapor deposition, physical vapor deposition or other deposition methods.
  • the gate dielectric layer can be selected as a film layer based on silicon materials, such as silicon oxide (SiOx), silicon nitride (Si3Nx), and silicon oxynitride (SiON), etc., or can be selected as a film layer based on high-K materials, such as including Hafnium (Hf), Zirconium (Zr), Alumina (AlOx), etc. According to actual process requirements, at least one or a combination of the materials listed in this embodiment may be selected, and other materials may also be selected, which is not limited here.
  • silicon materials such as silicon oxide (SiOx), silicon nitride (Si3Nx), and silicon oxynitride (SiON), etc.
  • high-K materials such as including Hafnium (Hf), Zirconium (Zr), Alumina (AlOx), etc. According to actual process requirements, at least one or a combination of the materials listed in this embodiment may be selected, and other materials may also be selected, which is not
  • the gate dielectric layer can be obtained by a chemical vapor deposition CVD process. Or first, a thin layer of silicon dioxide is grown by the ISSG (In Situ Water Vapor Generation) method, and then another thin layer of silicon dioxide is grown by the ALD (atomic layer deposition) method to form a gate dielectric layer.
  • ISSG In Situ Water Vapor Generation
  • ALD atomic layer deposition
  • the method before forming the first photoresist layer 40 on the substrate 10 , the method further includes: forming a word line mask having word line mask openings 45 on the substrate 10 layer 44 ; forming a first photoresist layer 40 on the word line mask layer 44 .
  • the first photoresist layer 40 has photoresist openings 43 . Specifically, the plurality of photoresist openings 43 are distributed in an array dislocation, and the photoresist openings 43 are located above the first isolation structure 20 .
  • the wordline mask openings 45 have a first dimension perpendicular to the direction in which they extend, and the photoresist openings 43 have a second dimension perpendicular to the direction in which the wordline mask openings 45 extend, the second dimension being greater than the first dimension size.
  • the use of the word line mask layer 44 can ensure that the portion of the photoresist opening 43 that falls in the word line mask opening 45 will etch the isolation structure downward, so that the size of the first groove 231 formed in the isolation structure will not be too large Defects that are large and in direct contact with adjacent active regions.
  • forming the first groove 231 and the second groove 232 on the isolation structure includes: etching the isolation by using the photoresist opening 43 on the first photoresist layer 40 and the word line mask layer 44 The structure forms grooves 41 ; the isolation structures are etched using word line mask openings 45 to form first grooves 231 and second grooves 232 .
  • a substrate is provided having isolation structures and a plurality of active regions 11 disposed between the plurality of active regions 11; in FIG. 10B, a word having word line mask openings 45 is formed Line mask layer 44; as shown in FIG. 10C to FIG. 11, a first photoresist layer 40 is formed on the word line mask layer 44. At this time, the first photoresist layer 40 has a photoresist opening 43. Due to the existence of the line mask layer 44, after the first photoresist layer 40 is formed, the groove 41 can be pre-etched on the isolation structure corresponding to the photoresist opening 43, and then the word line mask layer 44 can be used to etch the grooves 41.
  • the isolation structure forms the first groove 231 and the second groove 232 .
  • the word line mask layer 44 can not only prevent the photoresist opening 43 from being too large to cause the groove 41 formed in the isolation structure to directly contact the adjacent active region, but also serve as an etching mask for the isolation structure and the active region 11, The process flow can be simplified and the cost can be reduced.
  • the semiconductor structure formed by the method has a longer first protrusion, which can enhance the control ability of the word line to the transistor channel, reduce the leakage current problem of the semiconductor structure, thereby improving the performance of the semiconductor structure, and is suitable for small size and high performance. DRAM devices.

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Abstract

一种半导体结构及半导体结构的制造方法。半导体结构包括衬底（10）；形成于衬底内的隔离结构；字线，所述字线包括第一凸部（32）和第二凸部（33），其中，所述第一凸部和第二凸部位于所述隔离结构内，且所述第一凸部的深度大于所述第二凸部的深度。第一凸部具有较长的深度，可以增强字线对晶体管沟道的控制能力，改善漏电流。

Description

半导体结构及半导体结构的制造方法
交叉引用
本公开要求于2020年08月05日提交的申请号为202010777763.2、名称为“半导体结构及半导体结构的制造方法”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及半导体技术领域，尤其涉及一种半导体结构及半导体结构的制造方法。
背景技术
随着DRAM(Dynamic Random Access Memory)尺寸的不断缩小，存储区域的晶体管尺寸也在不断缩小，由此带来严重的漏电流问题，影响器件性能。
发明内容
本公开提供一种半导体结构及半导体结构的制造方法，以改善半导体结构的性能。
根据本公开的第一个方面，提供了一种半导体结构，包括：
衬底；
形成于衬底内的隔离结构；
字线，字线包括第一凸部和第二凸部，其中，第一凸部和第二凸部位于隔离结构内，且第一凸部的深度大于第二凸部的深度。
在本公开的一个实施例中，字线还包括：主体部，主体部与第一凸部和第二凸部连接。
在本公开的一个实施例中，第一凸部和第二凸部均为多个，多个第一凸部与多个第二凸部间隔设置。
在本公开的一个实施例中，隔离结构包括第一隔离结构和第二隔离结构；第一凸部位于第一隔离结构中，第二凸部位于第二隔离结构中，第一隔离结构的底部低于第二隔离结构的底部。
在本公开的一个实施例中，第一凸部和第二凸部的深度比大于1.05。
在本公开的一个实施例中，第一凸部的深度大于30nm。
在本公开的一个实施例中，第一凸部沿垂直字线延伸方向上的长度大于第二凸部沿垂 直字线延伸方向上的长度。
在本公开的一个实施例中，第一凸部包括：
凸下部，凸下部的侧壁具有第一斜率；
凸上部，凸上部的侧壁具有第二斜率；
其中，第一斜率不同于第二斜率。
在本公开的一个实施例中，第二凸部的侧壁具有第三斜率，第一斜率与第三斜率相同。
在本公开的一个实施例中，凸上部沿衬底表面方向上的截面为圆形或椭圆形，凸下部沿衬底表面方向上的截面为条形。
在本公开的一个实施例中，条形包括平行的两条线段以及连接两条线段端部的两条弧形线段。
在本公开的一个实施例中，衬底内设置有多个有源区，隔离结构设置在多个有源区之间；
其中，主体部与有源区相交。
在本公开的一个实施例中，多个有源区排布成多排；
其中，第一隔离结构位于两个有源区的端部之间，第二隔离结构位于相邻两个有源区的侧部之间。
根据本公开的第二个方面，提供了一种半导体结构的制造方法，包括：
提供具有隔离结构和多个有源区的衬底，隔离结构设置在多个有源区之间；
在隔离结构上形成间隔的第一凹槽和第二凹槽，且第一凹槽的深度大于第二凹槽的深度；
在衬底内形成字线，字线包括主体部、第一凸部以及第二凸部，第一凸部和第二凸部分别设置在第一凹槽和第二凹槽内。
在本公开的一个实施例中，在隔离结构上形成第一凹槽和第二凹槽，包括：
在隔离结构上形成凹槽，凹槽位于相邻两个有源区的端部之间；
在具有凹槽的隔离结构上形成第一凹槽和第二凹槽，第一凹槽形成于凹槽所在位置处。
在本公开的一个实施例中，在隔离结构上形成凹槽，包括：
在衬底上形成具有光刻胶开口的第一光刻胶层，光刻胶开口位于相邻两个有源区的端部之间；
利用光刻胶开口刻蚀隔离结构，以形成凹槽。
在本公开的一个实施例中，在衬底上形成第一光刻胶层之前，还包括：
在衬底上形成具有字线掩膜开口的字线掩膜层；
在字线掩膜层上形成第一光刻胶层。
在本公开的一个实施例中，字线掩膜开口具有垂直其延伸方向上的第一尺寸，第一光刻胶层上的光刻胶开口具有垂直字线掩膜开口延伸方向上的第二尺寸，第二尺寸大于第一尺寸。
在本公开的一个实施例中，在隔离结构上形成第一凹槽和第二凹槽，包括：
利用第一光刻胶层上的光刻胶开口和字线掩膜层刻蚀隔离结构形成凹槽；
利用字线掩膜开口刻蚀隔离结构形成第一凹槽和第二凹槽。
本公开的半导体结构通过使得字线的第一凸部具有较长的深度，可以增强字线对晶体管沟道的控制能力，改善漏电流。
附图说明
通过结合附图考虑以下对本公开的优选实施方式的详细说明，本公开的各种目标，特征和优点将变得更加显而易见。附图仅为本公开的示范性图解，并非一定是按比例绘制。在附图中，同样的附图标记始终表示相同或类似的部件。其中：
图1是根据一示例性实施方式示出的一种半导体结构的结构示意图；
图2是图1中A-A处的结构示意图；
图3是图1中B-B处的结构示意图；
图4是根据一示例性实施方式示出的一种半导体结构的第一凸部的结构示意图；
图5是根据另一示例性实施方式示出的一种半导体结构的第一凸部的结构示意图；
图6是根据一示例性实施方式示出的一种半导体结构的第二凸部的结构示意图；
图7是根据一示例性实施方式示出的一种半导体结构的制造方法的流程示意图；
图8是根据一示例性实施方式示出的一种半导体结构的制造方法形成第一光刻胶层后的结构示意图；
图9是根据一示例性实施方式示出的一种半导体结构的制造方法形成凹槽后的结构示意图；
图10A-10C是根据一示例性实施方式示出的一种半导体结构的制造方法的结构示意图；
图11是根据一示例性实施方式示出的一种半导体结构的制造方法形成第一凹槽和第 二凹槽后的结构示意图。
附图标记说明如下：
10、衬底；11、有源区；20、第一隔离结构；30、字线；31、主体部；32、第一凸部；33、第二凸部；321、凸下部；322、凸上部；40、第一光刻胶层；41、凹槽；43、光刻胶开口；44、字线掩膜层；231、第一凹槽；232、第二凹槽；45、字线掩膜开口；50、第二隔离结构。
具体实施方式
体现本公开特征与优点的典型实施例将在以下的说明中详细叙述。应理解的是本公开能够在不同的实施例上具有各种的变化，其皆不脱离本公开的范围，且其中的说明及附图在本质上是作说明之用，而非用以限制本公开。
在对本公开的不同示例性实施方式的下面描述中，参照附图进行，附图形成本公开的一部分，并且其中以示例方式显示了可实现本公开的多个方面的不同示例性结构，系统和步骤。应理解的是，可以使用部件，结构，示例性装置，系统和步骤的其他特定方案，并且可在不偏离本公开范围的情况下进行结构和功能性修改。而且，虽然本说明书中可使用术语“之上”，“之间”，“之内”等来描述本公开的不同示例性特征和元件，但是这些术语用于本文中仅出于方便，例如根据附图中的示例的方向。本说明书中的任何内容都不应理解为需要结构的特定三维方向才落入本公开的范围内。
本公开的一个实施例提供了一种半导体结构，请参考图1至图6，半导体结构包括：衬底10；形成于衬底10内的隔离结构；字线30，字线30包括第一凸部32和第二凸部33，其中，第一凸部32和第二凸部33位于所述隔离结构内，且第一凸部32的深度大于第二凸部33的深度。
本公开一个实施例的半导体结构通过使得字线30的第一凸部32相较第二凸部33具有较长的深度，可以增强字线30对晶体管沟道的控制能力，改善漏电流。具体的，第一凸部32的深度可以理解为第一凸部32的底部至字线30的主体部31的垂直距离。同理，第二凸部33的深度可以理解为第二凸部33的底部至字线30的主体部31的垂直距离。
在一实施例中，字线30还包括主体部31，主体部31与第一凸部32和第二凸部33连接。
在一实施例中，第一凸部32和第二凸部33均为多个，多个第一凸部32与多个第二凸部33间隔设置。具体的，在同一字线30下方，多个第一凸部32和多个第二凸部33间 隔设置在隔离结构中。
在一实施例中，隔离结构包括第一隔离结构20和第二隔离结构50；第一凸部32位于第一隔离结构20中，第二凸部33位于第二隔离结构50中，第一隔离结构20的底部低于第二隔离结构50的底部。
在一个实施例中，如图1所示，衬底10内设置有多个有源区11，隔离结构设置在多个有源区11之间；其中，主体部31与有源区11相交。
具体的，衬底10内形成有有源区11，相邻有源区11之间填充有隔离结构，各个隔离结构的深度可以均相同，也可以不同；结合图1可知，字线30跨过多个有源区11，即主体部31与有源区11相交。
在一个实施例中，多个有源区11排布成多排；其中，第一隔离结构20位于相邻两个有源区11的端部之间，第二隔离结构50位于相邻两个有源区11的侧部之间。
具体的，结合图1，多个有源区11排布成多排，且各排平行设置，而字线30跨过多排有源区11，相邻两排的相邻两个有源区11的侧部之间的距离较近，而一排中相邻两个有源区11的端部之间的距离较远。
在一实施例中，第一凸部32和第二凸部33的深度比大于1.05。需要说明的是，相关技术中，理想状态下字线的凸部深度尺寸均相等，即在刻蚀出用于容纳凸部的凹槽时，各个凹槽的深度也应该均相同，但受刻蚀工艺限制，在具体刻蚀时，各个凹槽的深度基本上会存在小规模的波动(但就波动值而言，依然可以认为是各个凹槽的深度均相等)，从而各个凸部也会存在相应的波动。但本实施例中的，第一凸部32和第二凸部33的深度比大于1.05区别于相关技术中由于波动而引发的高度差，是制造过程中通过工艺控制得到的满足小型化、高性能的半导体结构。在其他实施例中，第一凸部32和第二凸部33的深度比可以大于1.1，1.2，1.3，1.4，1.5或1.6。
在一个实施例中，衬底10可以是p型硅衬底、n型硅衬底、硅锗衬底等。
在一个实施例中，第一凸部32的深度大于30nm。在具体成型过程中通过确定第一凸部32和第二凸部33的深度比，并根据第一凸部32的深度值确定第二凸部33的深度。
在一个实施例中，第二凸部33的深度小于25nm。在具体成型过程中通过确定第一凸部32和第二凸部33的深度比，并根据第二凸部33的深度值确定第一凸部32的深度。
在一个实施例中，字线30上第一凸部32沿垂直字线30延伸方向上的长度大于第二凸部33沿垂直字线30延伸方向上的长度。
具体的，同一字线30上第一凸部32垂直字线30延伸方向上的长度可以理解为，第 一凸部32与主体部31相连接的面具有沿主体部31延伸方向的第一尺寸以及沿垂于与主体部31延伸方向的第二尺寸，相应的，第二凸部33也具有沿主体部31延伸方向的第三尺寸以及沿垂于与主体部31延伸方向的第四尺寸，而第二尺寸大于第四尺寸。
在一个实施例中，第一凸部32包括：凸下部321，凸下部321的侧壁具有第一斜率；凸上部322，凸上部322的侧壁具有第二斜率；其中，第一斜率不同于第二斜率。
结合图4和图5进行说明，示例的，凸上部322和凸下部321的侧壁可以为沿A-A截面上的凸上部322和凸下部321的侧壁；第一凸部32由凸下部321和凸上部322组成，凸上部322的顶端连接主体部31。第一斜率不同于第二斜率，即凸下部321的侧壁相对于竖直方向的倾斜度不同于凸上部322的侧壁相对于竖直方向的倾斜度，凸下部321的侧壁以及凸上部322的侧壁不平行也不在同一个平面上。
在一个实施例中，第一斜率大于第二斜率，即凸下部321的侧壁与竖直方向的夹角小于凸上部322的侧壁与竖直方向的夹角。当凸下部321的侧壁与竖直方向的夹角小于凸上部322的侧壁与竖直方向的夹角时，可以降低工艺难度以及增加工艺窗口。具体的，凸上部322的夹角较大，有利于字线的第一凸部的形成。
在一个实施例中，如图4至图6所示，第二凸部33的侧壁具有第三斜率，第一斜率与第三斜率相同，即凸下部321的侧壁与竖直方向的夹角与第二凸部33的侧壁与竖直方向的夹角相同。具体的，可以利用一步刻蚀工艺同时形成凸下部321和第二凸部33所在位置的凹槽，使得在所述凹槽中填充形成的凸下部321和第二凸部33的侧壁的斜率相同，可以简化形成步骤。
在一个实施例中，凸上部322的底部尺寸大于或等于凸下部321的顶部尺寸。
如图4所示，凸上部322的顶部尺寸大于凸上部322的底部尺寸，凸下部321的顶部尺寸大于凸下部321的底部尺寸，而凸下部321的顶部尺寸与凸上部322的底部尺寸相同，即凸上部322与凸下部321相连接的部分完全相重合。
如图5所示，凸上部322的顶部尺寸大于凸上部322的底部尺寸，凸下部321的顶部尺寸大于凸下部321的底部尺寸，而凸下部321的顶部尺寸小于凸上部322的底部尺寸相同，即凸上部322与凸下部321相连接的部分不完全相重合。以此增大工艺窗口，降低凸下部321与有源区直接接触的风险。
在一个实施例中，如图6所示，第二凸部33的顶部尺寸大于第二凸部33的底部尺寸，以此使得第二凸部33的侧壁具有第三斜率。
在一个实施例中，凸上部322沿所述衬底表面方向上的截面为圆形或椭圆形，凸下部 321沿所述衬底表面方向上的截面为条形。凸上部322以及凸下部321的具体形状可以由第一凹槽231和第二凹槽232进行控制，此处不作限定，可以根据实际需要进行选择。
在一个实施例中，条形包括平行的两条线段以及连接两条线段端部的两条弧形线段。凸下部321的截面由两条平行的线段和两条相对的弧形线段围成。具体的，所述线段与字线30的延伸方向平行。凸下部321的线段边可以减少与相邻的有源区直接接触的风险，同时结弧形线段边可以降低凸下部的形成难度。具体的，弧形线段边有利于导体材质的填充。
本公开的一个实施例还提供了一种半导体结构的制造方法，如图7至图11所示，半导体结构的制造方法包括：
S101，提供具有隔离结构和多个有源区11的衬底10，隔离结构设置在多个有源区11之间；
S103，在隔离结构上形成间隔的第一凹槽231和第二凹槽232，且第一凹槽231的深度大于第二凹槽232的深度；
S105在衬底10内形成字线30，字线30包括主体部31、第一凸部32以及第二凸部33，第一凸部32和第二凸部33分别设置在第一凹槽231和第二凹槽232内。
本公开一个实施例的半导体结构的制造方法通过在具有隔离结构和多个有源区11的衬底10上形成第一凹槽231和第二凹槽232，并在衬底10内形成字线30，且使得字线30的第一凸部32具有较长的深度，可有效改善半导体结构的漏电流现象。
需要说明的是，如图8所示，提供的衬底10为具有隔离结构和多个有源区11的衬底10，即不考虑隔离结构和多个有源区11的具体成型方法，直接在衬底10上形成第一凹槽231和第二凹槽232，并形成字线30。在形成第一凹槽231和第二凹槽232之前，可采用干法刻蚀或者化学机械研磨(Chemical Mechanical Polishing,CMP)平坦化衬底10。
需要注意的是，字线30为埋入式字线，字线30的材料包括钨、钛、镍、铝、铂、氮化钛等导电材料中的一种或其任意组合。在形成字线30后，可以采用干法刻蚀或者化学机械研磨(CMP)平坦化字线30。
在一个实施例中，在隔离结构上形成第一凹槽231和第二凹槽232，包括：在隔离结构上形成凹槽41，凹槽41位于相邻两个有源区11的端部之间；在具有凹槽41的隔离结构上形成第一凹槽231和第二凹槽232，第一凹槽231形成于凹槽41所在位置处。具体的，多个有源区11排布成平行的多排，隔离结构位于多个有源区11之间，所述隔离结构包括第一隔离结构20和第二隔离结构50，第一隔离结构20位于相邻两个有源区11的端 部之间，第二隔离结构50位于相邻两个有源区11的侧部之间。刻蚀部分第一隔离结构20形成凹槽41，然后在具有凹槽41的衬底10上刻蚀出第一凹槽231和第二凹槽232，且第一凹槽231是由凹槽41所在位置向下刻蚀的，以此实现对第一凹槽231和第二凹槽232形成深度的控制，且还能够保证刻蚀出深度较大的第一凹槽231。
在一个实施例中，在隔离结构上形成凹槽41，包括：在衬底10上形成具有光刻胶开口43的第一光刻胶层40，光刻胶开口43位于相邻两个有源区11的端部之间；利用光刻胶开口43刻蚀隔离结构，以形成凹槽41。具体的，光刻胶开口43位于第一隔离结构20的上方，刻蚀部分第一隔离结构20形成凹槽41。
在一个实施例中，在衬底10上形成字线掩膜层44，第一光刻胶层40位于字线掩膜层44上，先利用光刻胶开口43刻蚀字线掩膜层44，然后利用被刻蚀后的字线掩膜层44刻蚀第一隔离结构20形成凹槽41。
在一个实施例中，在具有凹槽41的隔离结构上形成第一凹槽231和第二凹槽232，包括：在衬底10上形成图案化的第二光刻胶层；利用图案化的第二光刻胶层蚀刻隔离结构，在隔离结构上形成第一凹槽231和第二凹槽232。
在一个实施例中，在第一凹槽231和第二凹槽232内形成栅介质层。通过向具有第一凹槽231和第二凹槽232的衬底10内填充钨、钛、镍、铝、铂、氮化钛等导电材料中的一种或其任意组合，以形成字线30。其中，字线30可采用化学气相沉积法、物理气相沉积法或其它沉积方法形成。
栅介质层可以选择为基于硅材质的膜层，例如氧化硅(SiOx)，氮化硅(Si3Nx)以及氮氧化硅(SiON)等，或者，可以选择基于高K材质的膜层，例如包括有铪(Hf)、锆(Zr)、氧化铝(AlOx)等。依据实际工艺需求，可以选择本实施例所列举材质的至少一种或组合，也可以选择其他材质，此处并不作限定。
例如，栅介质层可以采用化学气相沉积CVD工艺获得。或者先采用ISSG(原位水汽生成)方法长一薄层二氧化硅，然后再用ALD(原子层淀积)方法再长一薄层二氧化硅，以形成栅介质层。
在一个实施例中，如图10A至10C所示，在衬底10上形成第一光刻胶层40之前，还包括：在衬底10上形成具有字线掩膜开口45的字线掩膜层44；在在字线掩膜层44上形成第一光刻胶层40。第一光刻胶层40具有光刻胶开口43。具体的，多个光刻胶开口43呈阵列错位分布，且光刻胶开口43位于第一隔离结构20上方。
在一个实施例中，字线掩膜开口45具有垂直其延伸方向上的第一尺寸，光刻胶开口 43具有垂直字线掩膜开口45延伸方向上的第二尺寸，第二尺寸大于第一尺寸。利用字线掩膜层44可以保证光刻胶开口43落在字线掩膜开口45中的部分才会往下刻蚀隔离结构，使得隔离结构中形成的第一凹槽231的尺寸不至于过大而与临近的有源区直接接触造成缺陷。
在一个实施例中，在隔离结构上形成第一凹槽231和第二凹槽232，包括：利用第一光刻胶层40上的光刻胶开口43和字线掩膜层44刻蚀隔离结构形成凹槽41；利用字线掩膜开口45刻蚀隔离结构形成第一凹槽231和第二凹槽232。
如图10A所示，提供具有隔离结构和多个有源区11的衬底，所述隔离结构设置在多个有源区11之间；在图10B，形成具有字线掩膜开口45的字线掩膜层44；如图10C至图11所示，在字线掩膜层44上形成第一光刻胶层40，此时第一光刻胶层40具有光刻胶开口43，由于字线掩膜层44的存在，故在形成第一光刻胶层40后可以先在光刻胶开口43对应的隔离结构上预刻蚀出凹槽41，然后利用字线掩膜层44刻蚀隔离结构形成第一凹槽231和第二凹槽232。字线掩膜层44既能防止光刻胶开口43过大造成隔离结构中形成的凹槽41与临近的有源区直接接触，又能作为隔离结构和有源区11的刻蚀掩膜，可以简化工艺流程，降低成本。
本方法形成的半导体结构具有较长的第一凸部，可以增强字线对晶体管沟道的控制能力，降低半导体结构的漏电流问题，以此提升半导体结构的性能，且适用于小尺寸高性能的DRAM器件。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本公开旨在涵盖本发明的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和示例实施方式仅被视为示例性的，本公开的真正范围和精神由前面的权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限制。

Claims (19)

  1. 一种半导体结构，其特征在于，包括：
    衬底；
    形成于所述衬底内的隔离结构；
    字线，所述字线包括第一凸部和第二凸部，其中，所述第一凸部和所述第二凸部位于所述隔离结构内，且所述第一凸部的深度大于所述第二凸部的深度。
  2. 根据权利要求1所述的半导体结构，其特征在于，所述字线还包括：
    主体部，所述主体部与所述第一凸部和所述第二凸部连接。
  3. 根据权利要求2所述的半导体结构，其特征在于，所述第一凸部和所述第二凸部均为多个，多个所述第一凸部与多个所述第二凸部间隔设置。
  4. 根据权利要求2所述的半导体结构，其特征在于，所述隔离结构包括第一隔离结构和第二隔离结构；所述第一凸部位于所述第一隔离结构中，所述第二凸部位于所述第二隔离结构中，所述第一隔离结构的底部低于所述第二隔离结构的底部。
  5. 根据权利要求1所述的半导体结构，其特征在于，所述第一凸部和所述第二凸部的深度比大于1.05。
  6. 根据权利要求1所述的半导体结构，其特征在于，所述第一凸部的深度大于30nm。
  7. 根据权利要求1所述的半导体结构，其特征在于，所述第一凸部沿垂直所述字线延伸方向上的长度大于所述第二凸部沿垂直所述字线延伸方向上的长度。
  8. 根据权利要求1所述的半导体结构，其特征在于，所述第一凸部包括：
    凸下部，所述凸下部的侧壁具有第一斜率；
    凸上部，所述凸上部的侧壁具有第二斜率；
    其中，所述第一斜率不同于所述第二斜率。
  9. 根据权利要求8所述的半导体结构，其特征在于，所述第二凸部的侧壁具有第三斜率，所述第一斜率与所述第三斜率相同。
  10. 根据权利要求8所述的半导体结构，其特征在于，所述凸上部沿所述衬底表面方向上的截面为圆形或椭圆形，所述凸下部沿所述衬底表面方向上的截面为条形。
  11. 根据权利要求10所述的半导体结构，其特征在于，所述条形包括平行的两条线段以及连接两条所述线段端部的两条弧形线段。
  12. 根据权利要求4所述的半导体结构，其特征在于，所述衬底内设置有多个有源区， 所述隔离结构设置在多个所述有源区之间；
    其中，所述主体部与所述有源区相交。
  13. 根据权利要求12所述的半导体结构，其特征在于，多个有源区排布成多排；
    其中，所述第一隔离结构位于相邻两个所述有源区的端部之间，所述第二隔离结构位于相邻两个所述有源区的侧部之间。
  14. 一种半导体结构的制造方法，其特征在于，包括：
    提供具有隔离结构和多个有源区的衬底，所述隔离结构设置在多个所述有源区之间；
    在所述隔离结构上形成间隔的第一凹槽和第二凹槽，且所述第一凹槽的深度大于所述第二凹槽的深度；
    在所述衬底内形成字线，所述字线包括主体部、第一凸部以及第二凸部，所述第一凸部和所述第二凸部分别设置在所述第一凹槽和所述第二凹槽内。
  15. 根据权利要求14所述的半导体结构的制造方法，其特征在于，所述在所述隔离结构上形成第一凹槽和第二凹槽，包括：
    在所述隔离结构上形成凹槽，所述凹槽位于相邻两个有源区的端部之间；
    在具有所述凹槽的所述隔离结构上形成所述第一凹槽和第二凹槽，所述第一凹槽形成于所述凹槽所在位置处。
  16. 根据权利要求15所述的半导体结构的制造方法，其特征在于，在所述隔离结构上形成凹槽，包括：
    在所述衬底上形成具有光刻胶开口的第一光刻胶层，所述光刻胶开口位于相邻两个所述有源区的端部之间；
    利用所述光刻胶开口刻蚀所述隔离结构，以形成所述凹槽。
  17. 根据权利要求16所述的半导体结构的制造方法，其特征在于，在所述衬底上形成所述第一光刻胶层之前，还包括：
    在所述衬底上形成具有字线掩膜开口的字线掩膜层；
    在所述字线掩膜层上形成所述第一光刻胶层。
  18. 根据权利要求17所述的半导体结构的制造方法，其特征在于，所述字线掩膜开口具有垂直其延伸方向上的第一尺寸，所述第一光刻胶层上的所述光刻胶开口具有垂直所述字线掩膜开口延伸方向上的第二尺寸，所述第二尺寸大于所述第一尺寸。
  19. 根据权利要求17所述的半导体结构的制造方法，其特征在于，在所述隔离结构上形成第一凹槽和第二凹槽，包括：
    利用所述第一光刻胶层上的所述光刻胶开口和所述字线掩膜层刻蚀所述隔离结构形成所述凹槽；
    利用所述字线掩膜开口刻蚀所述隔离结构形成所述第一凹槽和所述第二凹槽。
PCT/CN2021/093135 2020-08-05 2021-05-11 半导体结构及半导体结构的制造方法 WO2022028028A1 (zh)

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