WO2022027587A1 - 用于芯片的激光注入攻击检测电路和安全芯片 - Google Patents

用于芯片的激光注入攻击检测电路和安全芯片 Download PDF

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Publication number
WO2022027587A1
WO2022027587A1 PCT/CN2020/107804 CN2020107804W WO2022027587A1 WO 2022027587 A1 WO2022027587 A1 WO 2022027587A1 CN 2020107804 W CN2020107804 W CN 2020107804W WO 2022027587 A1 WO2022027587 A1 WO 2022027587A1
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Prior art keywords
switch
clock signal
detection circuit
terminal
pmos transistor
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PCT/CN2020/107804
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English (en)
French (fr)
Inventor
薛建锋
李运宁
苏源
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深圳市汇顶科技股份有限公司
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Priority to PCT/CN2020/107804 priority Critical patent/WO2022027587A1/zh
Priority to EP20922472.4A priority patent/EP3979136A4/en
Priority to CN202080018323.7A priority patent/CN113711222B/zh
Priority to US17/468,221 priority patent/US11646276B2/en
Publication of WO2022027587A1 publication Critical patent/WO2022027587A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/57—Protection from inspection, reverse engineering or tampering
    • H01L23/576—Protection from inspection, reverse engineering or tampering using active circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
    • G01J1/00—Photometry, e.g. photographic exposure meter
    • G01J1/42—Photometry, e.g. photographic exposure meter using electric radiation detectors
    • G01J1/4257—Photometry, e.g. photographic exposure meter using electric radiation detectors applied to monitoring the characteristics of a beam, e.g. laser beam, headlamp beam
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/72—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/75—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/75—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation
    • G06F21/755—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation with measures against power attack
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
    • G01J1/00—Photometry, e.g. photographic exposure meter
    • G01J1/42—Photometry, e.g. photographic exposure meter using electric radiation detectors
    • G01J1/44—Electric circuits
    • G01J1/46—Electric circuits using a capacitor
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
    • G01J1/00—Photometry, e.g. photographic exposure meter
    • G01J1/42—Photometry, e.g. photographic exposure meter using electric radiation detectors
    • G01J1/44—Electric circuits
    • G01J2001/4446—Type of detector
    • G01J2001/446—Photodiode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/1443—Devices controlled by radiation with at least one potential jump or surface barrier

Definitions

  • Laser injection attack (Lazer Fault Injection Attack) is a semi-invasive attack method commonly used by attackers.
  • the attacker uses a pulsed laser to attack the chip from the front or back, resulting in wrong timing or abnormal flipping of the circuit, thereby changing the storage content and affecting the data. Transmission and proper functioning of the encryption module in the chip.
  • it is necessary to detect the laser injection attack against the chip in time and issue an alarm, so that the chip or the device to which the chip belongs can deal with the laser injection attack in time.
  • the present application provides a laser injection attack detection circuit for a chip and a security chip, which can detect a laser injection attack on a chip such as a security chip, and improve the robustness and security of the chip.
  • the present application provides a laser injection attack detection circuit for a chip, wherein the detection circuit is provided in the chip, and the detection circuit includes: a first capacitor; a second capacitor;
  • a first NMOS transistor the drain of the first NMOS transistor is connected to the second end of the first switch and used to output a first voltage signal, the source of the first NMOS transistor is connected to the photosensitive element, so the gate of the first NMOS transistor is connected to the second end of the second switch;
  • a second NMOS transistor the drain of the second NMOS transistor is connected to the second end of the second switch and used to output a second voltage signal, and the source of the second NMOS transistor is connected to the photosensitive element, so The gate of the second NMOS transistor is connected to the second end of the first switch, wherein the first voltage signal and the second voltage signal are used to indicate that the chip is attacked by laser injection.
  • the above-mentioned laser injection attack detection circuit can detect the laser injection attack aimed at the chip, thereby improving the robustness and security of the chip.
  • the method further includes: the first clock signal and the second clock signal have the same frequency and the same phase.
  • the method further includes: the first switch is turned on when the first clock signal is at a high level, and turned off when the first clock signal is at a low level; the second switch It is turned on when the second clock signal is at a high level, and turned off when the second clock signal is at a low level.
  • the first switch includes: a first inverter and a first PMOS transistor; wherein,
  • the input end of the first inverter is used as the control end of the first switch, the output end of the first inverter is connected to the gate of the first PMOS transistor, and the drain of the first PMOS transistor As the first terminal of the first switch, the source acts as the second terminal of the first switch.
  • the second switch includes: a second inverter and a second PMOS transistor; wherein,
  • the input end of the second inverter is used as the control end of the second switch, the output end of the second inverter is connected to the gate of the second PMOS transistor, and the drain of the second PMOS transistor As the first terminal of the second switch, the source acts as the second terminal of the second switch.
  • the first switch includes: a third PMOS transistor; wherein,
  • the gate of the third PMOS transistor is used as the control terminal of the first switch, the drain is used as the first terminal of the first switch, and the source is used as the second terminal of the first switch.
  • the second switch includes: a second inverter and a second PMOS transistor; wherein,
  • the input end of the first inverter is used as the control end of the first switch, the output end of the first inverter is connected to the gate of the first PMOS transistor, and the drain of the first PMOS transistor As the first terminal of the first switch, the source acts as the second terminal of the first switch.
  • the gate of the fourth PMOS transistor is used as the control terminal of the second switch, the drain is used as the first terminal of the second switch, and the source is used as the second terminal of the second switch.
  • the first voltage signal and the second voltage signal are used to control the clearing of the content of the storage circuit.
  • FIG. 2 is a schematic diagram of a structure between point B of the laser injection attack detection circuit of the present application and the substrate;
  • FIG. 7 is a structural diagram of another embodiment of the laser injection attack detection circuit of the present application.
  • FIG. 8 is a structural diagram of another embodiment of the laser injection attack detection circuit of the present application.
  • FIG. 9 is a structural diagram of an embodiment of the security chip of the application.
  • FIG. 10 is a structural diagram of another embodiment of the security chip of the present application.
  • the first input terminal IN21 of the processing unit 20 is connected to the first output terminal OUT1 of the detection unit 10 for receiving the first voltage signal; the second input terminal IN22 of the processing unit 20 is connected to the second output terminal OUT2 of the detection unit 10 for receiving the first voltage signal.
  • the processing unit 20 in the embodiment of the present application is an optional unit. If the laser injection attack detection circuit only includes the detection unit, the laser injection attack detection circuit in the embodiment of the present application can use the first voltage signal output by the detection unit. The first voltage signal and the second voltage signal are used to control the state of other circuits in the chip where the laser injection attack detection circuit is located. For example, the first voltage signal and the second voltage signal output by the detection unit can be directly output to the processor of the chip where the laser injection attack detection circuit is located, and the processor can output the first voltage signal as a low-level signal and/or the second voltage.
  • the detection unit 10 may include: a first switch S1, a second switch S2, a first N-channel metal oxide semiconductor (NMOS, Negative channel Metal Oxide Semiconductor) transistor N1, a second NMOS transistor N2, a first capacitor C1, a second Capacitor C2 and photosensitive element D.
  • NMOS N-channel metal oxide semiconductor
  • NMOS Negative channel Metal Oxide Semiconductor
  • the control terminal of the first switch S1 is used as the first input terminal IN11 of the detection unit 10; the first terminal of the first switch S1 is connected to the power supply voltage VDD; the second terminal of the first switch S1 is connected to the drain of the first NMOS transistor N1 And the gate of the second NMOS transistor N2 is also grounded to GND through the first capacitor C1, while the second end of the first switch S1 serves as the first output end OUT1 of the detection unit 10; the control end of the second switch S2 serves as the detection unit 10
  • the second capacitor C2 is grounded to GND, and the second terminal of the second switch S2 serves as the second output terminal OUT2 of the detection unit 10; One end is connected, and the second end of the photosensitive element D is suspended.
  • the first end of the photosensitive element D is denoted as point A
  • the second end of the photosensitive element is denoted as point B.
  • the first clock signal CLKA received by the first input terminal IN11 of the detection unit 10 is used to control the on-off state of the first switch S1;
  • the second clock signal CLKB received by the second input terminal IN12 of the detection unit 10 is used to control the first switch S1.
  • the photosensitive element D may be a photodiode, the first end of the photosensitive element D is the anode of the photodiode, and the second end of the photosensitive element D is the cathode of the photodiode.
  • the substrate of the laser injection attack detection circuit is generally a part of the substrate of the chip to which the laser injection attack detection circuit belongs.
  • the reverse-biased PN junction D2 between the B terminal and the substrate.
  • the reverse-biased PN junction will generate a ground current when a laser injection attack occurs, thereby discharging the charge stored at point A. When the current is large enough When the charge stored at point A is exhausted, the voltage at point A is pulled down to ground.
  • the specific control logic for the first clock signal CLKA to control the on-off state of the first switch S1 may be: when the first clock signal CLKA is at a low level, the first switch S1 is turned off, and when the first clock signal CLKA is at a high level, The first switch S1 is turned on;
  • the specific control logic for the second clock signal CLKB to control the on-off state of the second switch S2 may be: when the second clock signal CLKB is at a low level, the second switch S2 is turned off, and the second clock signal CLKB When it is at a high level, the second switch S2 is turned on.
  • the first clock signal CLKA periodically inputs a high-level signal to the control terminal of the first switch S1, which can keep the voltage of the first output terminal OUT1 at the power supply voltage VDD when no laser injection attack occurs.
  • the voltage of the first output terminal OUT1 is equal to the power supply voltage VDD.
  • the leakage current may cause the voltage of the first output terminal OUT1 to continuously decrease through long-term accumulation.
  • the signal output by an output terminal OUT1 is inverted from high level to low level, the processing unit 20 will output the processing signal after receiving the low level signal, and a false alarm occurs; and the first clock signal CLKA periodically controls the first switch S1
  • a high-level signal is input to the terminal, so as to control the first switch S1 to be regularly turned on, so that the power supply periodically charges the first capacitor C1, which can supplement the charge discharged by the first capacitor C1 due to leakage current, so as to ensure that there is no laser
  • the voltage of the first output terminal OUT1 is always kept at the power supply voltage VDD, that is, kept at a high level, so as to avoid false detection caused by capacitor leakage.
  • Using the second clock signal CLKB to control the on-off state of the second switch S2 in FIG. 1 is also based on the same principle, that is, using the second clock signal CLKB to control the on-off state of the second switch S2, and periodically inputting the second switch S2
  • a high-level signal controls the second switch S2 to be regularly turned on, so that the power supply periodically charges the second capacitor C2, which can supplement the charge discharged by the second capacitor C2 due to leakage current, so as to ensure that no laser injection attack occurs.
  • the voltage of the second output terminal OUT2 is maintained at the power supply voltage VDD.
  • the periods of the first clock signal and the second clock signal in the embodiments of the present application are generally 1us to 100us, and the laser pulse signal is generally used to attack the chip in the laser injection attack, and the laser pulse width is generally ns level, so the laser pulse signal
  • the width of the laser pulse is generally much smaller than the width of the high level or the low level in each cycle of the first clock signal and the second clock signal. Therefore, the laser pulse signal is generally located in each of the first clock signal and the second clock signal. High time or low time in the cycle.
  • the first clock signal CLKA and the second clock signal CLKB are the same signal.
  • the timing diagrams of the laser injection attack detection circuit shown in FIG. 1 are shown in FIGS. 3 and 4 .
  • the working timing diagram of the detection unit which includes the first output terminal OUT1, the first output terminal OUT1 of the detection unit, the The timing diagram of the two output terminals OUT2 and the voltage signal at point A.
  • the second NMOS transistor N2 When the voltage of the first output terminal OUT1 remains at a high level, the second NMOS transistor N2 is turned on, and when the voltage of the second output terminal OUT2 remains at a high level, the first NMOS transistor N1 is turned on, so that the voltage at point A remains at a high level level.
  • the laser injection attack may occur during the high level of the clock signal.
  • the first clock signal CLKA is high
  • the first switch S1 is turned on
  • the first output terminal OUT1 is connected to the power supply voltage VDD
  • the second clock signal CLKB is high. level
  • the second switch S2 is turned on, and the second output terminal OUT2 is connected to the power supply voltage VDD.
  • the photosensitive element D will generate a photo-generated current, and the charge at point A will be discharged.
  • the first NMOS transistor N1 and the second NMOS transistor N2 are in a conducting state, and the charges stored on the first capacitor C1 and the second capacitor C2 are discharged through the first NMOS transistor N1 and the second NMOS transistor N2 that are conducted; however, due to The first clock signal CLKA is at a high level, and the first output terminal OUT1 is connected to the power supply voltage VDD, so the first capacitor C1 is also being charged by the power supply while being discharged. When the current of the capacitor C1 is discharged, the voltage of the first output terminal OUT1 will eventually be converted from a high level to a low level.
  • the first output terminal OUT1 and the second output terminal OUT2 are connected to the power supply voltage VDD, and the power supply is the first capacitor C1 and the second capacitor C1 and the second capacitor C2 is charged, so the voltages of the first output terminal OUT1 and the second output terminal OUT2 are pulled up to the power supply voltage VDD again and become a high level.
  • a laser injection attack occurs when both the first clock signal CLKA and the second clock signal CLKB are at a low level, as an example, a working timing diagram of the detection unit is shown.
  • the first clock signal CLKA periodically inputs a high-level signal to the first switch S1 to control the first switch S1 to be periodically turned on, so that the power supply periodically becomes the first
  • the capacitor C1 is charged to ensure that the voltage of the first output terminal OUT1 is always maintained at the power supply voltage VDD, that is, at a high level.
  • the second clock signal CLKB periodically inputs a high level signal to the second switch S2 to control the second clock signal CLKB.
  • the second switch S2 is periodically turned on, so that the power supply periodically charges the second capacitor C2, so as to ensure that the voltage of the second output terminal OUT2 is always kept at the power supply voltage VDD, that is, at a high level.
  • the laser injection attack may occur during the low level period of the clock signal.
  • the first clock signal CLKA is low level
  • the first switch S1 is turned off
  • the first output terminal OUT1 is floating
  • the voltage is the power supply voltage VDD
  • the second clock signal CLKB is low level
  • the second switch S2 is turned off
  • the second output terminal OUT2 is suspended, and the voltage is the power supply voltage VDD. If a laser injection attack occurs at this time, the photosensitive element D will generate a photo-generated current, and the charge at point A will be discharged.
  • the charges stored on the first capacitor C1 and the second capacitor C2 are respectively discharged through the first NMOS transistor N1 and the second NMOS transistor N2 that are turned on. After discharging, the voltage of point A, the voltage of the first output terminal OUT1 and the voltage of the second output terminal OUT2 are converted from high level to low level.
  • the first output terminal OUT1 and the second output terminal OUT2 are left floating, and the voltage is still low level until the first clock signal CLKA and the second clock signal CLKB become high level, the first switch S1 and the second switch S2 are turned on respectively, the first output terminal OUT1 and the second output terminal OUT2 are connected to the power supply voltage VDD, and the power supply is the first capacitor C1 and the second The capacitor C2 is charged, and the voltages of the first output terminal OUT1 and the second output terminal OUT2 are again pulled up to the power supply voltage VDD and become a high level.
  • the laser injection attack detection circuit of the embodiment of the present application can be used when the first clock signal CLKA and the second clock signal CLKB are at a high level or a low level. Detecting laser injection attacks targeting chips ensures the robustness and security of chips.
  • the embodiment of the present application also provides another laser injection attack detection circuit.
  • the first clock The signal CLKA and the second clock signal CLKB are mutually inverse signals, that is, when the first clock signal CLKA is at a low level, the second clock signal CLKB is at a high level, and when the first clock signal CLKA is at a high level, the second clock signal CLKB is low.
  • the amplitudes of the two signals are not limited.
  • the timing diagrams of the laser injection attack detection circuit in this embodiment are shown in FIG. 5 and FIG. 6 .
  • a laser injection attack occurs when the first clock signal CLKA is at a high level and the second clock signal CLKB is at a low level as an example, showing a working timing diagram of the detection unit.
  • the first clock signal CLKA periodically inputs a high-level signal to the first switch S1 to control the first switch S1 to be periodically turned on, so that the power supply periodically becomes the first
  • the capacitor C1 is charged to ensure that the voltage of the first output terminal OUT1 is always maintained at the power supply voltage VDD, that is, at a high level.
  • the second clock signal CLKB periodically inputs a high level signal to the second switch S2 to control the second clock signal CLKB.
  • the second switch S2 is periodically turned on, so that the power supply periodically charges the second capacitor C2, so as to ensure that the voltage of the second output terminal OUT2 is always kept at the power supply voltage VDD, that is, at a high level.
  • the second NMOS transistor N2 When the voltage of the first output terminal OUT1 remains at a high level, the second NMOS transistor N2 is turned on, and when the voltage of the second output terminal OUT2 remains at a high level, the first NMOS transistor N1 is turned on, so that the voltage at point A remains at a high level level.
  • the laser injection attack may occur when the first clock signal CLKA is at a high level and the second clock signal CLKB is at a low level.
  • the first clock signal CLKA is at a high level
  • the first switch S1 is turned on
  • the first output terminal is turned on.
  • OUT1 is connected to the power supply voltage VDD
  • the second clock signal CLKB is at a low level
  • the second switch S2 is turned off
  • the second output terminal OUT2 is floating
  • the voltage is the power supply voltage VDD
  • the first NMOS transistor N1 and the second NMOS transistor N2 are in the conducting state, the charge stored on the first capacitor C1 is discharged through the conducting first NMOS transistor N1, and the second capacitor The charge stored on C2 is discharged through the second NMOS transistor N2 that is turned on.
  • the first clock signal CLKA is at a high level and the first output terminal OUT1 is connected to the power supply voltage VDD, the first capacitor C1 is discharged At the same time, it is also being charged by the power supply.
  • the voltage of the first output terminal OUT1 may drop slightly (not shown in FIG.
  • the discharge speed of the first capacitor C1 is slow. Since the second clock signal CLKB is at a low level and the second output terminal OUT2 is floating, the voltage of the second output terminal OUT2 is quickly changed.
  • the voltage of the second output terminal OUT2 remains at a low level until the second clock signal CLKB turns to a high level, the second switch S2 is turned on, the power supply voltage VDD is connected to the second capacitor C2, and the power supply is the first.
  • the second capacitor C2 is charged, and the voltage of the second output terminal OUT2 is pulled up to the power supply voltage VDD again and becomes a high level.
  • an example of a laser injection attack occurring when the first clock signal CLKA is at a low level and the second clock signal CLKB is at a high level is an example of a working timing diagram of the detection unit.
  • the voltage of the first output terminal OUT1 is pulled down to the ground, is low level, when the current charged by the power supply for the second capacitor C2 is greater than the current discharged by the second capacitor C2, the voltage of the second output terminal OUT2 may drop slightly, but it is always close to or equal to the power supply voltage VDD, and it is high. level.
  • the voltage of the first output terminal OUT1 remains at a low level until the first clock signal CLKA turns to a high level, the first switch S1 is turned on, the power supply voltage VDD is connected to the first capacitor C1, and the power supply is the first A capacitor C1 is charged, and the voltage of the first output terminal OUT1 is pulled up to the power supply voltage VDD again and becomes a high level.
  • the laser injection attack detection circuit of the embodiment of the present application has a high level when the first clock signal is at a high level and the second clock signal is at a low level, or when the first clock signal is at a low level and the second clock signal is at a low level When the second clock signal is at a high level, the laser injection attack on the chip can be effectively detected, which ensures the robustness and security of the chip.
  • the first switch S1 can be implemented by an inverter and a P-channel Metal Oxide Semiconductor (PMOS, positive channel Metal Oxide Semiconductor) transistor, as shown in FIG. 7 at 71.
  • PMOS Metal Oxide Semiconductor
  • the first switch S1 includes: the input terminal of the first inverter NO1 is used as the control terminal of the first switch S1 to be connected to the first input terminal IN11 of the detection unit 10 to receive the first clock signal CLKA;
  • the output end of the inverter NO1 is connected to the gate of the first PMOS transistor P1;
  • the drain of the first PMOS transistor P1 serves as the first end of the first switch S1 for connecting to the power supply voltage VDD;
  • the source of the first PMOS transistor P1 As the second end of the first switch S1, it is used to connect the drain of the first NMOS transistor N1 and the gate of the second NMOS transistor N2, and is also used to ground GND through the first capacitor C1, and is also used as the detection unit 10.
  • the second switch S2 can be implemented by an inverter and a PMOS transistor.
  • the second switch S2 includes: a second inverter The input end of NO2 is used as the control end of the second switch S2 to connect to the second input end IN12 of the detection unit 10 to receive the second clock signal CLKB; the output end of the second inverter NO2 is connected to the gate of the second PMOS transistor P2 pole; the drain of the second PMOS transistor P2 serves as the first end of the second switch S2 for connecting the power supply voltage VDD; the source of the second PMOS transistor P2 serves as the second end of the second switch S2 for connecting the second The drain of the NMOS transistor N2 and the gate of the first NMOS transistor N1 are also used for grounding GND through the second capacitor C2, and are also used as the second output terminal OUT2 of the detection unit 10.
  • the control logic for the first clock signal CLKA to control the on-off state of the first switch S1 may be as follows: when the first clock signal CLKA is at a high level, the first switch S1 is turned off, and when the first clock signal CLKA is at a low level, the first switch S1 is turned off. S1 is turned on; the control logic for the second clock signal CLKB to control the on-off state of the second switch S2 may be: when the second clock signal CLKB is at a high level, the second switch S2 is turned off, and when the second clock signal CLKB is at a low level , the second switch S2 is turned on.
  • the first switch S1 in the laser injection attack detection circuit in this embodiment can be implemented by a PMOS transistor.
  • the first switch S1 includes: the gate of the third PMOS transistor P3 serves as the first The control terminal of the switch S1 is used to connect to the first input terminal IN11 of the detection unit 10 to receive the first clock signal CLKA; the drain of the third PMOS transistor P3 is used as the first terminal of the first switch S1 to connect to the power supply voltage VDD ;
  • the source of the third PMOS transistor P3 is used as the second end of the first switch S1 to connect the drain of the first NMOS transistor N1 and the gate of the second NMOS transistor N2, and is also used to ground GND through the first capacitor C1 , and is simultaneously used as the first output terminal OUT1 of the detection unit 10 .
  • the second switch S2 can be implemented by an inverter and a PMOS transistor.
  • the second switch S2 includes: a fourth PMOS transistor P4
  • the gate of the second switch S2 is used as the control terminal of the second switch S2 to connect the second input terminal IN12 of the detection unit 10 to receive the second clock signal CLKB;
  • the drain of the fourth PMOS transistor P4 is used as the first terminal of the second switch S2, It is used to connect the power supply voltage VDD;
  • the source of the fourth PMOS transistor P4 is used as the second end of the second switch S2 to connect the drain of the second NMOS transistor N2 and the gate of the first NMOS transistor N1, and is also used to pass
  • the second capacitor C2 is grounded to GND, and is also used as the second output terminal OUT2 of the detection unit 10 .
  • the first switch S1 may be implemented by a PMOS, for example, as shown in part 81 in FIG. 8 .
  • the second switch S2 can be implemented by an inverter and a PMOS, for example, as shown in part 72 in FIG. 7 .
  • the control logic for the first clock signal CLKA to control the on-off state of the first switch S1 may be: when the first clock signal CLKA is at a low level, the first switch S1 is turned off, and when the first clock signal CLKA is at a high level, the first switch S1 is turned on;
  • the control logic for the second clock signal CLKB to control the on-off state of the second switch S2 may be: when the second clock signal CLKB is at a high level, the second switch S2 is turned off, and when the second clock signal CLKB is at a low level , the second switch S2 is turned on.
  • the first switch S1 may be implemented by an inverter and a PMOS, for example, as shown in part 71 in FIG. 7 .
  • the second switch S2 can be implemented by a PMOS, for example, as shown in part 82 in FIG. 8 .
  • the laser injection attack detection circuit of the present application can be applied to any chip, such as a security chip.
  • a security chip Referring to FIG. 9 , a schematic diagram of the structure of a security chip is shown.
  • the security chip 90 may include: a processor 91 , a Laser injection attack detection circuit 92; wherein,
  • the processor 91 can output the first clock signal CLKA and the second clock signal CLKB for the laser injection attack detection circuit 92, and the laser injection attack detection circuit 92 outputs a processing signal to the processor 91 when detecting that the security chip 90 is attacked by laser injection,
  • the processor 91 may perform corresponding processing based on the processing signal, such as interrupt or chip reset, etc.
  • the subsequent processing performed by the processor 91 based on the processing signal is not limited in this embodiment of the present application.
  • the security chip 100 may include: a laser injection attack detection circuit 101 and a storage circuit 102 , wherein,
  • the first voltage signal and the second voltage signal output by the laser injection attack detection circuit 101 are used to control the clearing of the content of the storage circuit 102 .
  • the first clock signal CLKA and the second clock signal CLKB may be sent to the laser injection attack detection circuit by the processor of the security chip.
  • “at least one” refers to one or more, and “multiple” refers to two or more.
  • “And/or”, which describes the association relationship of the associated objects means that there can be three kinds of relationships, for example, A and/or B, which can indicate the existence of A alone, the existence of A and B at the same time, and the existence of B alone. where A and B can be singular or plural.
  • the character “/” generally indicates that the associated objects are an “or” relationship.
  • “At least one of the following” and similar expressions refer to any combination of these items, including any combination of single or plural items.
  • At least one of a, b, and c may represent: a, b, c, a and b, a and c, b and c or a and b and c, where a, b, c may be single, or Can be multiple.
  • any function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium.
  • the technical solution of the present application can be embodied in the form of a software product in essence, or the part that contributes to the prior art or the part of the technical solution.
  • the computer software product is stored in a storage medium, including Several instructions are used to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application.
  • the aforementioned storage medium includes: U disk, mobile hard disk, Read-Only Memory (Read-Only Memory; hereinafter referred to as: ROM), Random Access Memory (Random Access Memory; hereinafter referred to as: RAM), magnetic disk or optical disk and other various A medium on which program code can be stored.
  • ROM Read-Only Memory
  • RAM Random Access Memory
  • magnetic disk or optical disk and other various A medium on which program code can be stored.

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Abstract

一种用于芯片的激光注入攻击检测电路和安全芯片，该检测电路包括第一电容（C1）、第二电容（C2）、第一开关（S1）、第二开关（S2）、感光元件（D）、第一NMOS管（N1）以及第二NMOS管（N2），第一NMOS管（N1）的漏极用于输出第一电压信号，第二NMOS管（N2）的漏极用于输出第二电压信号，第一电压信号和第二电压信号用于指示芯片受到激光注入攻击，从而实现激光注入攻击的检测，保证所属芯片的鲁棒性与安全性。

Description

用于芯片的激光注入攻击检测电路和安全芯片 技术领域
本申请涉及芯片安全技术领域，特别涉及用于芯片的激光注入攻击检测电路和安全芯片。
背景技术
为了达到窃取芯片中保存的数据、影响芯片正常工作等目的，黑客可能会对芯片进行攻击。尤其是安全芯片，基于广泛应用于身份识别、关键数据存储、以及金融领域等要求数据高可靠性的场景、保存的一般是机密数据等原因，往往是黑客攻击的重点对象。攻击者一般通过攻击手段为芯片注入故障，使芯片的工作状态发生错误，进而获取芯片中存储的机密数据。
激光注入攻击(Lazer Fault Injection Attack)是攻击者常用的一种半侵入式攻击手段，攻击者使用脉冲激光从正面或者背面攻击芯片，导致电路产生错误时序或异常翻转，进而改变存储内容、影响数据传输和芯片中加密模块的正常工作。为了保证芯片以及芯片所属设备的鲁棒性与安全性，需要及时检测出针对芯片的激光注入攻击并进行报警，以便芯片或者芯片所属设备能够及时针对激光注入攻击作出处理。
发明内容
本申请提供了一种用于芯片的激光注入攻击检测电路和安全芯片，能够检测出针对于芯片例如安全芯片的激光注入攻击，提高芯片的鲁棒性与安全性。
第一方面，本申请提供了一种用于芯片的激光注入攻击检测电路，其中所述检测电路设置在所述芯片内，所述检测电路包括：第一电容； 第二电容；
第一开关，所述第一开关的控制端用于接收第一时钟信号以控制所述第一开关的通断状态，所述第一开关的第一端连接至电源电压，所述第一开关的第二端通过所述第一电容接地；
第二开关，所述第二开关的控制端用于接收第二时钟信号以控制所述第二开关的通断状态，所述第二开关的第一端连接至所述电源电压，所述第二开关的第二端通过所述第二电容接地；
感光元件；
第一NMOS管，所述第一NMOS管的漏极连接至所述第一开关的第二端并用于输出第一电压信号，所述第一NMOS管的源极连接至所述感光元件，所述第一NMOS管的栅极连接至所述第二开关的第二端；以及
第二NMOS管，所述第二NMOS管的漏极连接至所述第二开关的第二端并用于输出第二电压信号，所述第二NMOS管的源极连接至所述感光元件，所述第二NMOS管的栅极连接至所述第一开关的第二端，其中所述第一电压信号和所述第二电压信号用于指示所述芯片受到激光注入攻击。
上述激光注入攻击检测电路，能够检测出针对于芯片的激光注入攻击，提高芯片的鲁棒性与安全性。
在一种可能的实现方式中，还包括：所述第一时钟信号和所述第二时钟信号的频率相同、相位相同。
在一种可能的实现方式中，还包括：所述第一时钟信号和所述第二时钟信号互为反相信号。
在一种可能的实现方式中，还包括：所述第一开关在所述第一时钟信号为高电平时导通，在所述第一时钟信号为低电平时关断；所述第二开关在所述第二时钟信号为高电平时导通，在所述第二时钟信号为低电平时关断。
在一种可能的实现方式中，所述第一开关包括：第一反相器和第一PMOS管；其中，
所述第一反相器的输入端作为所述第一开关的控制端，所述第一反相器的输出端连接所述第一PMOS管的栅极，所述第一PMOS管的漏极作为所述第一开关的第一端，源极作为所述第一开关的第二端。
在一种可能的实现方式中，所述第二开关包括：第二反相器和第二PMOS管；其中，
所述第二反相器的输入端作为所述第二开关的控制端，所述第二反相器的输出端连接所述第二PMOS管的栅极，所述第二PMOS管的漏极作为所述第二开关的第一端，源极作为所述第二开关的第二端。
在一种可能的实现方式中，还包括：所述第一开关在所述第一时钟信号为低电平时导通，在所述第一时钟信号为高电平时关断；所述第二开关在所述第二时钟信号为低电平时导通，在所述第二时钟信号为高电平时关断。
在一种可能的实现方式中，所述第一开关包括：第三PMOS管；其中，
所述第三PMOS管的栅极作为所述第一开关的控制端，漏极作为所述第一开关的第一端，源极作为所述第一开关的第二端。
在一种可能的实现方式中，所述第二开关包括：第四PMOS管；其中，
所述第四PMOS管的栅极作为所述第二开关的控制端，漏极作为所述第二开关的第一端，源极作为所述第二开关的第二端。
在一种可能的实现方式中，还包括：所述第一开关在所述第一时钟信号为低电平时导通，在所述第一时钟信号为高电平时关断；所述第二开关在所述第二时钟信号为高电平时导通，在所述第二时钟信号为低电平时关断。
在一种可能的实现方式中，所述第一开关包括：第三PMOS管；其中，
所述第三PMOS管的栅极作为所述第一开关的控制端，漏极作为所述第一开关的第一端，源极作为所述第一开关的第二端。
在一种可能的实现方式中，所述第二开关包括：第二反相器和第 二PMOS管；其中，
所述第二反相器的输入端作为所述第二开关的控制端，所述第二反相器的输出端连接所述第二PMOS管的栅极，所述第二PMOS管的漏极作为所述第二开关的第一端，源极作为所述第二开关的第二端。
在一种可能的实现方式中，还包括：所述第一开关在所述第一时钟信号为高电平时导通，在所述第一时钟信号为低电平时关断；所述第二开关在所述第二时钟信号为低电平时导通，在所述第二时钟信号为高电平时关断。
在一种可能的实现方式中，所述第一开关包括：第一反相器和第一PMOS管；其中，
所述第一反相器的输入端作为所述第一开关的控制端，所述第一反相器的输出端连接所述第一PMOS管的栅极，所述第一PMOS管的漏极作为所述第一开关的第一端，源极作为所述第一开关的第二端。
在一种可能的实现方式中，所述第二开关包括：第四PMOS管；其中，
所述第四PMOS管的栅极作为所述第二开关的控制端，漏极作为所述第二开关的第一端，源极作为所述第二开关的第二端。
在一种可能的实现方式中，所述感光元件为光电二极管。
在一种可能的实现方式中，进一步包括信号处理电路，用于根据所述第一电压信号和第二电压信号输出处理信号，所述处理信号用于控制所述芯片内其他电路的状态。
第二方面，本申请实施例提供一种安全芯片，包括：第一方面任一项所述的激光注入攻击检测电路和存储电路，其中，
所述第一电压信号和所述第二电压信号用于控制所述存储电路内容的清除。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅 仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1为本申请激光注入攻击检测电路一种实施例的结构图；
图2是本申请激光注入攻击检测电路B点与衬底之间的结构示例图；
图3～图6为图1所示本申请激光注入攻击检测电路的检测单元工作原理的时序示例图；
图7为本申请激光注入攻击检测电路另一种实施例的结构图；
图8为本申请激光注入攻击检测电路又一种实施例的结构图；
图9为本申请安全芯片的一种实施例结构图；
图10为本申请安全芯片的另一种实施例结构图。
具体实施方式
本申请的实施方式部分使用的术语仅用于对本申请的具体实施例进行解释，而非旨在限定本申请。
本申请实施例提供一种用于芯片的激光注入攻击检测电路，能够检测出针对于芯片例如安全芯片的激光注入攻击，提高芯片的鲁棒性和安全性。以下对本申请实施例激光注入攻击检测电路的实现进行示例性说明。
图1为本申请激光注入攻击检测电路的一种实施例的结构图，如图1所示，激光注入攻击检测电路包括：检测单元10、处理单元20，其中，
检测单元10的第一输入端IN11接收第一时钟信号CLKA，第二输入端IN12接收第二时钟信号CLKB；其中，在本实施例中，第一时钟信号CLKA和第二时钟信号CLKB是相同的信号，也即第一时钟信号CLKA为高电平时，第二时钟信号CLKB也为高电平，第一时钟信号CLKA为低电平时，第二时钟信号CLKB也为低电平。在保证第一时钟信号CLKA和第二时钟信号CLKB频率相同、相位相同的情况下，两者的信号幅度不限制。检测单元10的第一输出端 OUT1用于输出第一电压信号，第二输出端OUT2用于输出第二电压信号。
处理单元20的第一输入端IN21连接检测单元10的第一输出端OUT1，用于接收第一电压信号；处理单元20的第二输入端IN22连接检测单元10的第二输出端OUT2，用于接收第二电压信号；处理单元20在第一输入端IN21接收到的第一电压信号为低电平信号和/或第二输入端IN22接收到第二电压信号为低电平信号时，输出处理信号，即只要第一输入端IN21接收到的第一电压信号和第二输入端IN22接收到的第二电压信号其中至少有一个为低电平信号的时候，处理单元20就输出处理信号，该处理信号用于控制激光注入攻击检测电路所在芯片内其他电路的状态。例如，处理单元20可以将处理信号输出至激光注入攻击检测电路所在芯片的处理器，由处理器执行中断或者芯片复位等针对于激光注入攻击预设的处理；或者，也可以输出至所在芯片的存储电路，存储电路执行存储内容的清除。
需要说明的是，本申请实施例中的处理单元20是可选单元，如果激光注入攻击检测电路仅包括检测单元，本申请实施例的激光注入攻击检测电路可以通过检测单元输出的第一电压信号和第二电压信号来指示激光注入攻击检测电路所在芯片是否发生激光注入攻击,第一电压信号和第二电压信号用于控制激光注入攻击检测电路所在芯片内其他电路的状态。例如，检测单元输出的第一电压信号和第二电压信号可以直接输出至激光注入攻击检测电路所在芯片的处理器等，由处理器在第一电压信号为低电平信号和/或第二电压信号为低电平信号时执行终端或者芯片复位等针对于激光注入攻击预设的处理；或者，检测单元输出的第一电压信号和第二电压信号也可以直接输出至所在芯片的存储电路，由存储电路在第一电压信号为低电平信号和/或第二电压信号为低电平信号时执行存储内容的清除。
检测单元10可以包括：第一开关S1、第二开关S2、第一N沟道金属氧化物半导体(NMOS，Negative channel Metal Oxide Semiconductor)管N1、第二NMOS管N2、第一电容C1、第二电容 C2和感光元件D。其中，第一开关S1的控制端作为检测单元10的第一输入端IN11；第一开关S1的第一端连接电源电压VDD；第一开关S1的第二端连接第一NMOS管N1的漏极以及第二NMOS管N2的栅极，还通过第一电容C1接地GND，同时第一开关S1的第二端作为检测单元10的第一输出端OUT1；第二开关S2的控制端作为检测单元10的第二输入端IN12；第二开关S2的第一端连接电源电压VDD；第二开关S2的第二端连接第二NMOS管N2的漏极以及第一NMOS管N1的栅极，还通过第二电容C2接地GND，同时第二开关S2的第二端作为检测单元10的第二输出端OUT2；第一NMOS管N1的源极、第二NMOS管N2的源极均与感光元件D的第一端连接，感光元件D的第二端悬空。在图1中将感光元件D的第一端记为A点，将感光元件的第二端记为B点。
检测单元10的第一输入端IN11接收到的第一时钟信号CLKA用于控制第一开关S1的通断状态；检测单元10的第二输入端IN12接收到的第二时钟信号CLKB用于控制第二开关S2的通断状态。
可选地，感光元件D可以是光电二极管，感光元件D的第一端为光电二极管的阳极，感光元件D的第二端为光电二极管的阴极。
接下来对B点悬空时，B点与激光注入攻击检测电路的衬底之间的结构关系进行说明。其中，激光注入攻击检测电路的衬底一般是激光注入攻击检测电路所属芯片的衬底的一部分。如图2所示，B端与衬底之间存在反偏PN结D2，反偏PN结在出现激光注入攻击时会产生到地电流，从而将A点存储的电荷泄放，当电流足够大时，A点存储的电荷被泄放完，使得A点电压被拉低到地。
其中，第一时钟信号CLKA控制第一开关S1的通断状态的具体控制逻辑可以为：第一时钟信号CLKA为低电平时，第一开关S1关断，第一时钟信号CLKA为高电平时，第一开关S1导通；第二时钟信号CLKB控制第二开关S2的通断状态的具体控制逻辑可以为：第二时钟信号CLKB为低电平时，第二开关S2关断，第二时钟信号CLKB为高电平时，第二开关S2导通。
对于图1所示的激光注入攻击检测电路的工作原理进行说明。
首先对图1中使用第一时钟信号CLKA控制第一开关S1的工作原理进行说明。
第一时钟信号CLKA定期向第一开关S1的控制端输入高电平信号，可以在未出现激光注入攻击时，使得第一输出端OUT1的电压保持在电源电压VDD，原理在于：在未出现激光注入攻击时，一旦第一电容C1连接电源电压VDD，完成充电，第一输出端OUT1的电压等于电源电压VDD，但是，电路中存在漏电流，漏电流会造成第一电容C1上的电荷被泄放，第一输出端OUT1的电压降低，如果第一电容C1长时间不充电，通过长期累积，漏电流可能使得第一输出端OUT1的电压不断降低，一旦降至预设第一数值以下，第一输出端OUT1输出的信号从高电平翻转为低电平，处理单元20接收到低电平信号将输出处理信号，发生误报警；而通过第一时钟信号CLKA定期向第一开关S1的控制端输入高电平信号，从而控制第一开关S1定期导通，让电源定期为第一电容C1充电，可以补充第一电容C1因为漏电流而被泄放的电荷，从而可以保证在未出现激光注入攻击时，第一输出端OUT1的电压始终保持在电源电压VDD，也即保持在高电平，避免因为电容漏电造成的误检测。
图1中使用第二时钟信号CLKB控制第二开关S2的通断状态也是基于同样的原理，也即：使用第二时钟信号CLKB控制第二开关S2的通断状态，定期向第二开关S2输入高电平信号，控制第二开关S2定期导通，让电源定期为第二电容C2充电，可以补充第二电容C2因为漏电流而被泄放的电荷，从而可以保证在未出现激光注入攻击时，第二输出端OUT2的电压保持在电源电压VDD。
以下，结合图3～图6所示的时序图，对图1所示激光注入攻击检测电路进行激光注入攻击检测的工作原理进行说明。
本申请实施例中的第一时钟信号和第二时钟信号的周期一般为1us～100us，而激光注入攻击中一般使用激光脉冲信号对芯片进行攻击，激光脉冲宽度一般为ns级别，所以激光脉冲信号的激光脉冲宽 度一般远远小于第一时钟信号和第二时钟信号每个周期中的高电平或低电平的宽度，因此，激光脉冲信号一般位于第一时钟信号和第二时钟信号每个周期中的高电平时间内或者低电平时间。
本实施例中，第一时钟信号CLKA和第二时钟信号CLKB是相同的信号，此时图1所示激光注入攻击检测电路的时序图如图3和图4所示。
图3中以第一时钟信号CLKA和第二时钟信号CLKB均为高电平时，发生激光注入攻击为例，示出了检测单元的工作时序图，其中包括检测单元的第一输出端OUT1、第二输出端OUT2、以及A点的电压信号时序图。
在检测电路处于检测状态，未发生激光注入攻击的期间，第一时钟信号CLKA通过周期性向第一开关S1输入高电平信号，控制第一开关S1周期性导通，让电源周期性为第一电容C1充电，保证第一输出端OUT1的电压始终保持在电源电压VDD，也即保持在高电平，同样的，第二时钟信号CLKB通过周期性向第二开关S2输入高电平信号，控制第二开关S2周期性导通，让电源周期性为第二电容C2充电，保证第二输出端OUT2的电压始终保持在电源电压VDD，也即保持在高电平。第一输出端OUT1的电压保持在高电平时，第二NMOS管N2导通，第二输出端OUT2的电压保持在高电平时，第一NMOS管N1导通，从而，A点电压保持在高电平。
激光注入攻击可能发生在时钟信号的高电平期间，此时第一时钟信号CLKA为高电平，第一开关S1导通，第一输出端OUT1连接电源电压VDD，第二时钟信号CLKB为高电平，第二开关S2导通，第二输出端OUT2连接电源电压VDD，此时如果发生激光注入攻击，则感光元件D产生光生电流，A点的电荷被泄放，由于第一NMOS管N1和第二NMOS管N2处于导通状态，第一电容C1和第二电容C2上存储的电荷分别经由导通的第一NMOS管N1和导通的第二NMOS管N2被泄放；但是，由于第一时钟信号CLKA为高电平，第一输出端OUT1连接电源电压VDD，所以第一电容C1在被放电的同 时，也在被电源充电，在电源为第一电容C1充电的电流小于第一电容C1放电的电流时，第一输出端OUT1的电压最终将从高电平转换为低电平，同样的原理，在电源为第二电容C2充电的电流小于第二电容C2放电的电流时，第二输出端OUT2的电压从高电平转换为低电平。激光注入攻击结束后，由于第一时钟信号CLKA和第二时钟信号CLKB均为高电平，第一输出端OUT1和第二输出端OUT2连接电源电压VDD，电源为第一电容C1和第二电容C2充电，所以第一输出端OUT1和第二输出端OUT2的电压重新被拉高至电源电压VDD，变为高电平。
图4中以第一时钟信号CLKA和第二时钟信号CLKB均为低电平时，发生激光注入攻击为例，示出了检测单元的工作时序图。
在检测电路处于检测状态，未发生激光注入攻击的期间，第一时钟信号CLKA通过周期性向第一开关S1输入高电平信号，控制第一开关S1周期性导通，让电源周期性为第一电容C1充电，保证第一输出端OUT1的电压始终保持在电源电压VDD，也即保持在高电平，同样的，第二时钟信号CLKB通过周期性向第二开关S2输入高电平信号，控制第二开关S2周期性导通，让电源周期性为第二电容C2充电，保证第二输出端OUT2的电压始终保持在电源电压VDD，也即保持在高电平。第一输出端OUT1的电压保持在高电平时，第二NMOS管N2导通，第二输出端OUT2的电压保持在高电平时，第一NMOS管N1导通，从而，A点电压保持在高电平。
激光注入攻击可能发生在时钟信号的低电平期间，此时第一时钟信号CLKA为低电平，第一开关S1关断，第一输出端OUT1悬空，电压为电源电压VDD，第二时钟信号CLKB为低电平，第二开关S2关断，第二输出端OUT2悬空，电压为电源电压VDD，此时如果发生激光注入攻击，则感光元件D产生光生电流，A点的电荷被泄放，由于第一NMOS管N1和第二NMOS管N2处于导通状态，第一电容C1和第二电容C2上存储的电荷分别经由导通的第一NMOS管N1和导通的第二NMOS管N2被泄放，A点的电压、第一输出端OUT1 和第二输出端OUT2的电压从高电平转换为低电平。激光注入攻击结束后，由于第一时钟信号CLKA和第二时钟信号CLKB均为低电平，第一输出端OUT1和第二输出端OUT2悬空，电压仍为低电平，直到第一时钟信号CLKA和第二时钟信号CLKB变为高电平，第一开关S1和第二开关S2分别导通，第一输出端OUT1和第二输出端OUT2连接电源电压VDD，电源为第一电容C1和第二电容C2充电，第一输出端OUT1和第二输出端OUT2的电压重新被拉高至电源电压VDD，变为高电平。
基于图3和图4以及对应的描述内容可知，本申请实施例的激光注入攻击检测电路，在第一时钟信号CLKA和第二时钟信号CLKB为高电平或低电平的情况下，都能检测针对于芯片的激光注入攻击，保证了芯片的鲁棒性与安全性。
区别于上述实施例第一时钟信号CLKA和第二时钟信号CLKB为同相信号，本申请实施例还提供另一种激光注入攻击检测电路，在图1所示电路结构的基础上，第一时钟信号CLKA和第二时钟信号CLKB互为反相信号，也即第一时钟信号CLKA为低电平时，第二时钟信号CLKB为高电平，第一时钟信号CLKA为高电平时，第二时钟信号CLKB为低电平。在保证第一时钟信号CLKA和第二时钟信号CLKB频率相同、相位相反的情况下，两者的信号幅度不限制。此时本实施例中激光注入攻击检测电路的时序图如图5和图6所示。
图5中以第一时钟信号CLKA为高电平、第二时钟信号CLKB为低电平时，发生激光注入攻击为例，示出了检测单元的工作时序图。
在检测电路处于检测状态，未发生激光注入攻击的期间，第一时钟信号CLKA通过周期性向第一开关S1输入高电平信号，控制第一开关S1周期性导通，让电源周期性为第一电容C1充电，保证第一输出端OUT1的电压始终保持在电源电压VDD，也即保持在高电平，同样的，第二时钟信号CLKB通过周期性向第二开关S2输入高电平信号，控制第二开关S2周期性导通，让电源周期性为第二电容C2充 电，保证第二输出端OUT2的电压始终保持在电源电压VDD，也即保持在高电平。第一输出端OUT1的电压保持在高电平时，第二NMOS管N2导通，第二输出端OUT2的电压保持在高电平时，第一NMOS管N1导通，从而，A点电压保持在高电平。
激光注入攻击可能发生在第一时钟信号CLKA为高电平、第二时钟信号CLKB为低电平期间，此时第一时钟信号CLKA为高电平，第一开关S1导通，第一输出端OUT1连接电源电压VDD，第二时钟信号CLKB为低电平，第二开关S2关断，第二输出端OUT2悬空，电压为电源电压VDD，此时如果发生激光注入攻击：感光元件D产生光生电流，A点的电荷被泄放，由于第一NMOS管N1和第二NMOS管N2处于导通状态，第一电容C1上存储的电荷经由导通的第一NMOS管N1被泄放，第二电容C2上存储的电荷经由导通的第二NMOS管N2被泄放，但是，由于第一时钟信号CLKA为高电平，第一输出端OUT1连接电源电压VDD，所以第一电容C1在被放电的同时，也在被电源充电，在电源为第一电容C1充电的电流大于第一电容C1放电的电流时，第一输出端OUT1的电压可能会产生小幅度下降(图5中未示出)，但是，相对于第二电容C2的放电速度，第一电容C1的放电速度慢，由于第二时钟信号CLKB为低电平，第二输出端OUT2悬空，所以第二输出端OUT2的电压很快被拉低到地，变为低电平；当第二输出端OUT2的电压被拉低到地以后，第一NMOS管N1关断，第一电容C1的电荷停止泄放，而VDD继续给第一电容C1充电，从而第一输出端OUT1的电压被拉高至电源电压VDD；从而，第一时钟信号CLKA为高电平，第二时钟信号CLKB为低电平，且激光注入攻击存在时，第一输出端OUT1的电压为高电平，第二输出端OUT2的电压为低电平。激光注入攻击结束后，第二输出端OUT2的电压保持低电平，直到第二时钟信号CLKB翻转为高电平，第二开关S2导通，电源电压VDD与第二电容C2连接，电源为第二电容C2充电，第二输出端OUT2的电压重新被拉高至电源电压VDD，变为高电平。
图6中以第一时钟信号CLKA为低电平、第二时钟信号CLKB为高电平时，发生激光注入攻击为例，示出了检测单元的工作时序图。
与图5中类似的工作原理，在第一时钟信号CLKA为低电平、第二时钟信号CLKB为高电平，且激光注入攻击存在时，第一输出端OUT1的电压被拉低到地，为低电平，在电源为第二电容C2充电的电流大于第二电容C2放电的电流时，第二输出端OUT2的电压可能发生小幅度的下降，但是始终接近或等于电源电压VDD，为高电平。激光注入攻击结束后，第一输出端OUT1的电压保持低电平，直到第一时钟信号CLKA翻转为高电平，第一开关S1导通，电源电压VDD与第一电容C1连接，电源为第一电容C1充电，第一输出端OUT1的电压重新被拉高至电源电压VDD，变为高电平。
基于图5和图6可知，本申请实施例的激光注入攻击检测电路，在第一时钟信号为高电平、第二时钟信号为低电平，或者，第一时钟信号为低电平、第二时钟信号为高电平的情况下，都能有效检测针对于芯片的激光注入攻击，保证了芯片的鲁棒性与安全性。
可选地，对于图1所示的激光注入攻击检测电路，第一开关S1可以通过反相器和P沟道金属氧化物半导体(PMOS，positive channel Metal Oxide Semiconductor)管实现，如图7中71部分所示，第一开关S1包括：第一反相器NO1的输入端作为第一开关S1的控制端，用于连接检测单元10的第一输入端IN11，接收第一时钟信号CLKA；第一反相器NO1的输出端连接第一PMOS管P1的栅极；第一PMOS管P1的漏极作为第一开关S1的第一端，用于连接电源电压VDD；第一PMOS管P1的源极作为第一开关S1的第二端，用于连接第一NMOS管N1的漏极、第二NMOS管N2的栅极，还用于通过第一电容C1接地GND，同时用于作为检测单元10的第一输出端OUT1。
可选地，对于图1所示的激光注入攻击检测电路，第二开关S2可以通过反相器和PMOS管实现，如图7中72部分所示，第二开关S2包括：第二反相器NO2的输入端作为第二开关S2的控制端，用于连接检测单元10的第二输入端IN12，接收第二时钟信号CLKB； 第二反相器NO2的输出端连接第二PMOS管P2的栅极；第二PMOS管P2的漏极作为第二开关S2的第一端，用于连接电源电压VDD；第二PMOS管P2的源极作为第二开关S2的第二端，用于连接第二NMOS管N2的漏极、第一NMOS管N1的栅极，还用于通过第二电容C2接地GND，同时用于作为检测单元10的第二输出端OUT2。
图7所示激光注入攻击检测电路的工作原理请参考图1的相关说明，这里不赘述。
区别于图1所示的激光注入攻击检测电路中第一时钟信号CLKA对于第一开关S1通断状态的控制逻辑、以及第二时钟信号CLKB对于第二开关S2通断状态的控制逻辑，在另一个实施例中：
第一时钟信号CLKA控制第一开关S1的通断状态的控制逻辑可以为：第一时钟信号CLKA为高电平时，第一开关S1关断，第一时钟信号CLKA为低电平时，第一开关S1导通；第二时钟信号CLKB控制第二开关S2的通断状态的控制逻辑可以为：第二时钟信号CLKB为高电平时，第二开关S2关断，第二时钟信号CLKB为低电平时，第二开关S2导通。
可选地，本实施例激光注入攻击检测电路中的第一开关S1可以通过PMOS管实现，如图8中81部分所示，第一开关S1包括：第三PMOS管P3的栅极作为第一开关S1的控制端，用于连接检测单元10的第一输入端IN11，接收第一时钟信号CLKA；第三PMOS管P3的漏极作为第一开关S1的第一端，用于连接电源电压VDD；第三PMOS管P3的源极作为第一开关S1的第二端，用于连接第一NMOS管N1的漏极、第二NMOS管N2的栅极，还用于通过第一电容C1接地GND，同时用于作为检测单元10的第一输出端OUT1。
可选地，对于图1所示的激光注入攻击检测电路，第二开关S2可以通过反相器和PMOS管实现，如图8中82部分所示，第二开关S2包括：第四PMOS管P4的栅极作为第二开关S2的控制端，用于连接检测单元10的第二输入端IN12，接收第二时钟信号CLKB；第 四PMOS管P4的漏极作为第二开关S2的第一端，用于连接电源电压VDD；第四PMOS管P4的源极作为第二开关S2的第二端，用于连接第二NMOS管N2的漏极、第一NMOS管N1的栅极，还用于通过第二电容C2接地GND，同时用于作为检测单元10的第二输出端OUT2。
本实施例激光注入攻击检测电路的工作原理可参考图1所示激光注入攻击检测电路的工作原理，这里不赘述。
区别于图1所示的激光注入攻击检测电路中第一时钟信号CLKA对于第一开关S1通断状态的控制逻辑、以及第二时钟信号CLKB对于第二开关S2通断状态的控制逻辑，在另一个实施例中：
第一时钟信号CLKA控制第一开关S1的通断状态的控制逻辑可以为：第一时钟信号CLKA为高电平时，第一开关S1关断，第一时钟信号CLKA为低电平时，第一开关S1导通；第二时钟信号CLKB控制第二开关S2的通断状态的控制逻辑可以为：第二时钟信号CLKB为低电平时，第二开关S2关断，第二时钟信号CLKB为高电平时，第二开关S2导通。
可选地，第一开关S1可以通过PMOS实现，例如图8中81部分所示。第二开关S2可以通过反相器和PMOS实现，例如图7中72部分所示。
本实施例激光注入攻击检测电路的工作原理可参考图1所示激光注入攻击检测电路的工作原理，这里不赘述。
区别于图1所示的激光注入攻击检测电路中第一时钟信号CLKA对于第一开关S1通断状态的控制逻辑、以及第二时钟信号CLKB对于第二开关S2通断状态的控制逻辑，在另一个实施例中：
第一时钟信号CLKA控制第一开关S1的通断状态的控制逻辑可以为：第一时钟信号CLKA为低电平时，第一开关S1关断，第一时钟信号CLKA为高电平时，第一开关S1导通；第二时钟信号CLKB 控制第二开关S2的通断状态的控制逻辑可以为：第二时钟信号CLKB为高电平时，第二开关S2关断，第二时钟信号CLKB为低电平时，第二开关S2导通。
可选地，第一开关S1可以通过反相器和PMOS实现，例如图7中71部分所示。第二开关S2可以通过PMOS实现，例如图8中82部分所示。
本实施例激光注入攻击检测电路的工作原理可参考图1所示激光注入攻击检测电路的工作原理，这里不赘述。
本申请激光注入攻击检测电路可以应用于任意芯片例如安全芯片中，参见图9所示，示出了一种安全芯片的结构示例图，安全芯片90可以包括：处理器91、本申请实施例的激光注入攻击检测电路92；其中，
处理器91可以为激光注入攻击检测电路92输出第一时钟信号CLKA和第二时钟信号CLKB，激光注入攻击检测电路92在检测到安全芯片90受到激光注入攻击时，向处理器91输出处理信号，处理器91可以基于处理信号进行对应处理，例如中断或者芯片复位等，处理器91基于处理信号进行的后续处理本申请实施例不作限定。
如图10所示，示出了另一种安全芯片的结构示例图，安全芯片100可以包括：激光注入攻击检测电路101和存储电路102，其中，
激光注入攻击检测电路101输出的第一电压信号和第二电压信号用于控制存储电路102内容的清除。
可选地，第一时钟信号CLKA和第二时钟信号CLKB可以由安全芯片的处理器发送至激光注入攻击检测电路。
本申请实施例中，“至少一个”是指一个或者多个，“多个”是指两个或两个以上。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示单独存在A、同时存在A和B、单独存在B的情况。其中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。“以下至少一项”及其 类似表达，是指的这些项中的任意组合，包括单项或复数项的任意组合。例如，a，b和c中的至少一项可以表示：a，b，c，a和b，a和c，b和c或a和b和c，其中a，b，c可以是单个，也可以是多个。
本领域普通技术人员可以意识到，本文中公开的实施例中描述的各单元及算法步骤，能够以电子硬件、计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，任一功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(Read-Only Memory；以下简称：ROM)、随机存取存储器(Random Access Memory；以下简称：RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本申请的具体实施方式，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。本申请的保护范围应以所述权利要求的保护范围为准。

Claims (18)

  1. 一种用于芯片的激光注入攻击检测电路，其中所述检测电路设置在所述芯片内，其特征在于，所述检测电路包括：第一电容；第二电容；
    第一开关，所述第一开关的控制端用于接收第一时钟信号以控制所述第一开关的通断状态，所述第一开关的第一端连接至电源电压，所述第一开关的第二端通过所述第一电容接地；
    第二开关，所述第二开关的控制端用于接收第二时钟信号以控制所述第二开关的通断状态，所述第二开关的第一端连接至所述电源电压，所述第二开关的第二端通过所述第二电容接地；
    感光元件；
    第一NMOS管，所述第一NMOS管的漏极连接至所述第一开关的第二端并用于输出第一电压信号，所述第一NMOS管的源极连接至所述感光元件，所述第一NMOS管的栅极连接至所述第二开关的第二端；以及
    第二NMOS管，所述第二NMOS管的漏极连接至所述第二开关的第二端并用于输出第二电压信号，所述第二NMOS管的源极连接至所述感光元件，所述第二NMOS管的栅极连接至所述第一开关的第二端，其中所述第一电压信号和所述第二电压信号用于指示所述芯片受到激光注入攻击。
  2. 根据权利要求1所述的检测电路，其特征在于，还包括：所述第一时钟信号和所述第二时钟信号的频率相同、相位相同。
  3. 根据权利要求1所述的检测电路，其特征在于，还包括：所述第一时钟信号和所述第二时钟信号互为反相信号。
  4. 根据权利要求1至3任一项所述的检测电路，其特征在于，还包括：所述第一开关在所述第一时钟信号为高电平时导通，在所述第一时钟信号为低电平时关断；所述第二开关在所述第二时钟信号为高电平时导通，在所述第二时钟信号为低电平时关断。
  5. 根据权利要求4所述的检测电路，其特征在于，所述第一开 关包括：第一反相器和第一PMOS管；其中，
    所述第一反相器的输入端作为所述第一开关的控制端，所述第一反相器的输出端连接所述第一PMOS管的栅极，所述第一PMOS管的漏极作为所述第一开关的第一端，源极作为所述第一开关的第二端。
  6. 根据权利要求4所述的检测电路，其特征在于，所述第二开关包括：第二反相器和第二PMOS管；其中，
    所述第二反相器的输入端作为所述第二开关的控制端，所述第二反相器的输出端连接所述第二PMOS管的栅极，所述第二PMOS管的漏极作为所述第二开关的第一端，源极作为所述第二开关的第二端。
  7. 根据权利要求1至3任一项所述的检测电路，其特征在于，还包括：所述第一开关在所述第一时钟信号为低电平时导通，在所述第一时钟信号为高电平时关断；所述第二开关在所述第二时钟信号为低电平时导通，在所述第二时钟信号为高电平时关断。
  8. 根据权利要求7所述的检测电路，其特征在于，所述第一开关包括：第三PMOS管；其中，
    所述第三PMOS管的栅极作为所述第一开关的控制端，漏极作为所述第一开关的第一端，源极作为所述第一开关的第二端。
  9. 根据权利要求7所述的检测电路，其特征在于，所述第二开关包括：第四PMOS管；其中，
    所述第四PMOS管的栅极作为所述第二开关的控制端，漏极作为所述第二开关的第一端，源极作为所述第二开关的第二端。
  10. 根据权利要求1至3任一项所述的检测电路，其特征在于，还包括：所述第一开关在所述第一时钟信号为低电平时导通，在所述第一时钟信号为高电平时关断；所述第二开关在所述第二时钟信号为高电平时导通，在所述第二时钟信号为低电平时关断。
  11. 根据权利要求10所述的检测电路，其特征在于，所述第一开关包括：第三PMOS管；其中，
    所述第三PMOS管的栅极作为所述第一开关的控制端，漏极作为所述第一开关的第一端，源极作为所述第一开关的第二端。
  12. 根据权利要求10所述的检测电路，其特征在于，所述第二开关包括：第二反相器和第二PMOS管；其中，
    所述第二反相器的输入端作为所述第二开关的控制端，所述第二反相器的输出端连接所述第二PMOS管的栅极，所述第二PMOS管的漏极作为所述第二开关的第一端，源极作为所述第二开关的第二端。
  13. 根据权利要求1至3任一项所述的检测电路，其特征在于，还包括：所述第一开关在所述第一时钟信号为高电平时导通，在所述第一时钟信号为低电平时关断；所述第二开关在所述第二时钟信号为低电平时导通，在所述第二时钟信号为高电平时关断。
  14. 根据权利要求13所述的检测电路，其特征在于，所述第一开关包括：第一反相器和第一PMOS管；其中，
    所述第一反相器的输入端作为所述第一开关的控制端，所述第一反相器的输出端连接所述第一PMOS管的栅极，所述第一PMOS管的漏极作为所述第一开关的第一端，源极作为所述第一开关的第二端。
  15. 根据权利要求13所述的检测电路，其特征在于，所述第二开关包括：第四PMOS管；其中，
    所述第四PMOS管的栅极作为所述第二开关的控制端，漏极作为所述第二开关的第一端，源极作为所述第二开关的第二端。
  16. 根据权利要求1至3任一项所述的检测电路，其特征在于，所述感光元件为光电二极管。
  17. 根据权利要求1-16任意一项所述的检测电路，其特征在于，进一步包括信号处理电路，用于根据所述第一电压信号和第二电压信号输出处理信号，所述处理信号用于控制所述芯片内其他电路的状态。
  18. 一种安全芯片，其特征在于，包括：权利要求1至17任一项所述的激光注入攻击检测电路和存储电路，其中，
    所述第一电压信号和所述第二电压信号用于控制所述存储电路内容的清除。
PCT/CN2020/107804 2020-08-07 2020-08-07 用于芯片的激光注入攻击检测电路和安全芯片 WO2022027587A1 (zh)

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