WO2022022214A1 - 半导体结构的形成方法 - Google Patents

半导体结构的形成方法 Download PDF

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WO2022022214A1
WO2022022214A1 PCT/CN2021/103834 CN2021103834W WO2022022214A1 WO 2022022214 A1 WO2022022214 A1 WO 2022022214A1 CN 2021103834 W CN2021103834 W CN 2021103834W WO 2022022214 A1 WO2022022214 A1 WO 2022022214A1
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doping
ions
polysilicon layer
semiconductor structure
forming
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PCT/CN2021/103834
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English (en)
French (fr)
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元大中
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长鑫存储技术有限公司
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Priority to US17/445,649 priority Critical patent/US12087584B2/en
Publication of WO2022022214A1 publication Critical patent/WO2022022214A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET

Definitions

  • Embodiments of the present application relate to a method for forming a semiconductor structure.
  • the capacitance of the transistor is one of the performance indicators of the transistor.
  • the physical thickness of the gate dielectric layer is often increased to increase the capacitance of the transistor, but in doing so, there is a risk that the gate dielectric layer is too thin and is broken down.
  • the main technical means currently adopted is to reduce the thickness of the gate depletion layer under the condition that the thickness of the gate dielectric layer remains unchanged, thereby reducing the equivalent thickness of the capacitor and increasing the capacitance of the transistor.
  • an embodiment of the present application provides a method for forming a semiconductor structure, providing a substrate, a gate dielectric layer and an undoped polysilicon layer stacked in sequence; a doping ion; performing an ion implantation process, doping a second doping ion in a predetermined area of the polysilicon layer, and in a direction perpendicular to the surface of the substrate, the predetermined area is away from the polysilicon layer
  • Surfaces of the gate dielectric layer have a predetermined distance between them.
  • 1 to 3 are schematic diagrams corresponding to each step of a method for forming a semiconductor structure
  • FIG. 4 is a schematic diagram of the change of the doping ion concentration at a certain position in the polysilicon layer with the doping time
  • 5 is a schematic diagram of the variation of the capacitance equivalent thickness of the polysilicon layer with the doping time
  • 6 to 11 are schematic diagrams corresponding to each step of a method for forming a semiconductor structure according to an embodiment of the present application.
  • FIG. 12 and FIG. 13 are schematic diagrams corresponding to each step of a method for forming a semiconductor structure according to another embodiment of the present application.
  • FIG. 1 to FIG. 3 are schematic diagrams of a method for forming a semiconductor structure.
  • the method for forming the semiconductor structure includes: providing a substrate 11 , a gate dielectric layer 12 and an undoped polysilicon layer 130 stacked in sequence; performing a doping process, and doping doping in a surface region of the undoped polysilicon layer 130 away from the gate dielectric layer 12 ions to form an initial doping region 131 ; and a heat treatment process is performed, so that the doping ions located in the initial doping region 131 are diffused downward to form the doped polysilicon layer 13 .
  • Finite source diffusion means that during the diffusion process, the source of doping ions is limited to the total number of doping ions doped in the thin layer on the surface of the polysilicon layer before diffusion, and relying on these limited doping ions to spread to other areas in the polysilicon layer Diffusion;
  • constant surface source diffusion means that the polysilicon layer is always in a source-containing atmosphere during the diffusion process, that is, the concentration of the thin layer on the surface of the polysilicon layer remains unchanged, but the number of dopant ions in the polysilicon layer varies with time. growing.
  • finite source diffusion refers to the heat treatment process after the doping process
  • constant surface source diffusion refers to the heat treatment process during the doping process. Solubility limit.
  • the concentration difference is one of the basic conditions for diffusion
  • the concentration of the dopant ions must gradually decrease in the direction of diffusion of the dopant ions.
  • FIG. 4 is a schematic diagram of the change of the doping ion concentration at a certain position in the polysilicon layer with the doping time.
  • the horizontal axis represents the doping time
  • the vertical axis represents the doping ion concentration at a certain position.
  • the concentration of doping ions at a certain position tends to be saturated, which cannot break through the solid solubility limit, which in turn causes the doping process to be ineffective or the diffusion process to stop.
  • Figure 5 shows that the capacitance equivalent thickness of the polysilicon layer varies with doping. Schematic diagram of the time change, the horizontal axis represents the doping time, and the vertical axis represents the equivalent thickness of the capacitor. saturation.
  • the present application provides a method for forming a semiconductor structure. After the thermal doping process is performed, an ion implantation process is performed, so that the concentration of doping ions in the polysilicon layer can exceed the solid solubility limit of the doping ions.
  • the thickness of the depletion layer It is beneficial to reduce the thickness of the depletion layer, thereby reducing the equivalent thickness of the capacitor; in addition, doping the second dopant ions in the area with a distance from the top surface is beneficial to improve the diffusion rate of the second dopant ions and improve the
  • the doped ion concentration of the part of the polysilicon layer close to the gate dielectric layer is beneficial to make the thickness of the depletion layer thinner under the condition of a certain number of carrier migration, that is, the equivalent thickness of the capacitance is thinner and the capacitance is larger.
  • 6 to 11 are schematic diagrams corresponding to the steps of a method for forming a semiconductor structure according to an embodiment of the present application.
  • a substrate 21 , a gate dielectric layer 22 and an undoped polysilicon layer 230 are provided which are stacked in sequence.
  • Doping ions can be doped into the substrate 21 to form a doped region and a channel region between adjacent doped regions. After the substrate 21 is doped with doping ions, it can form a MOS tube together with the gate dielectric layer 22 and the doped polysilicon layer.
  • the type of the MOS tube depends on the type of doping ions doped in the substrate 21.
  • the type of the MOS tube includes NMOS. tube and PMOS tube.
  • the gate dielectric layer 22 is a nitrogen-doped oxide layer.
  • the nitrogen-doped oxide layer has a good ion blocking effect, which is beneficial to prevent the doping ions in the doped polysilicon layer from permeating into the substrate 21 , thereby ensuring that the substrate 21 has good performance.
  • the ion doping of the undoped polysilicon layer 230 may include multiple steps or at least one process.
  • the undoped polysilicon layer 230 is ion-doped by a thermal doping process. Taking the source diffusion process as an example, the ion doping of the undoped polysilicon layer 230 includes the following steps:
  • first doping ions are doped in the surface region of the undoped polysilicon layer 230 away from the gate dielectric layer 22 to form an initial doping region 231 .
  • a plasma ion implantation process can be used to dope the first dopant ions.
  • the type of the first dopant ions includes N-type ions or P-type ions, and the type of the first dopant ions is referred to as P-type ions herein. as an example.
  • the plasma ion implantation process has lower requirements on the target temperature and has a higher doping rate, which is beneficial to avoid damage to the polysilicon layer caused by thermal shock formed by heating; in addition, the plasma ion implantation process is used for ion implantation. , without the screening of the analytical electric field, the amount of ion implantation per unit time is large, the productivity is high, and the initial doping region 231 can have a relatively high concentration of first doping ions.
  • the concentration of the first dopant ions in the initial doping region 231 is greater than the solid solubility limit of the first dopant ions in the polysilicon layer. In this way, it is beneficial to increase the total number of doping ions in the finite source diffusion, thereby increasing the first doping ion concentration of the doped polysilicon layer.
  • a first heat treatment process is performed to diffuse the first dopant ions in the initial doping region 231 downward to form the doped polysilicon layer 23 .
  • the first heat treatment process includes Rapid Thermal Processing (RTP), such as a rapid heat treatment annealing process, which can heat the entire polysilicon layer to a temperature range of 400°C to 1300°C in a very short time.
  • RTP Rapid Thermal Processing
  • the rapid heat treatment annealing process has Low thermal budget, low impurity movement in silicon, low contamination and short processing time.
  • the concentration difference is the basic condition for diffusion
  • the concentration difference is the basic condition for diffusion
  • the concentration difference is the basic condition for diffusion
  • the concentration difference is the basic condition for diffusion
  • the concentration difference is the basic condition for diffusion
  • the concentration difference is the basic condition for diffusion
  • the actual concentration of the first dopant ions at each position in the doped polysilicon layer 23 is also different from the type of the first dopant ion (different dopant ion types have different solid solubility)
  • the energy of a heat treatment process is related to the thickness of the undoped polysilicon layer 230 (refer to FIG. 6 ) in the direction perpendicular to the surface of the substrate 21 and the first dopant ion concentration in the initial doped region 231 (refer to FIG. 7 ).
  • the first dopant ions in the area can be diffused to a greater degree, and the concentration of the first dopant ions in the area of the polysilicon layer 23 close to the gate dielectric layer 22 is higher after doping;
  • the polysilicon layer 23 is close to the gate dielectric layer. The lower the concentration of the first dopant ions in the portion 22; higher.
  • an ion implantation process is performed, and the second dopant ions are doped in the predetermined region 232 of the doped polysilicon layer 23 .
  • the second doping ions are the same as the first doping ions, the second doping ions include boron ions or boron-like ions, and the boron-like ions include at least one of BF2+ or BF2+.
  • the ion implantation process is performed after the thermal doping process, so that the doping ion concentration at any position in the doped polysilicon layer 23 exceeds the solid solubility limit of the doping ions, and when a fixed number of carriers (ie the second doping When the electric field acts to migrate away from the gate dielectric layer 22, the higher the concentration of the second dopant ions in the region close to the gate dielectric layer 22, the thinner the depletion layer and the smaller the capacitance equivalent thickness.
  • the second dopant ions are doped in the predetermined region 232 with a distance from the top surface. , which is beneficial to increase the difference between the dopant ion concentration in the preset region 232 and the dopant ion concentration in the regions on both sides of the preset region 232 , thereby increasing the diffusion rate of the second dopant ions and shortening the process cycle.
  • the diffusion rate of the second doping ions is related to the type of thermal doping process. Compared with the finite source diffusion process, after the constant surface source diffusion process, the doping ion concentration at any position in the polysilicon layer 23 after doping is higher. If the implanted dose is the same, the concentration difference between the preset area and the adjacent area will be smaller, and the diffusion rate will be slower.
  • doping the second dopant ions in the predetermined region 232 with a distance from the top surface is beneficial to shorten the distance between the predetermined region 232 and the surface of the doped polysilicon layer 23 close to the gate dielectric layer 22, thereby making the first
  • the second dopant ions are more easily diffused to the area of the doped polysilicon layer 23 close to the gate dielectric layer 22 , thereby increasing the dopant ion concentration of the doped polysilicon layer 23 close to the gate dielectric layer 22 , thereby increasing the number of carrier migration
  • the thickness of the depletion layer is thin, that is, the equivalent thickness of the capacitor is thin, and the capacitance of the semiconductor structure is large.
  • the preset distance d is 1 nm ⁇ 10 nm, for example, 3 nm, 5 nm or 7 nm. Since the concentration of the first dopant ions in the direction of the doped polysilicon layer 23 toward the gate dielectric layer 22 is gradually decreasing, the larger the preset distance d, the greater the concentration difference between the doping area and the surrounding area. , the diffusion speed of the second dopant ions is faster, and the dopant ion concentration on the side of the polysilicon layer 23 close to the gate dielectric layer 22 is higher after doping; The doped polysilicon layer 23 causes great damage, and the maximum value of the preset spacing d needs to be limited, so as to ensure that the doped polysilicon layer 23 has good performance.
  • the second doping ions can be diffused by means of the first heat treatment process in the thermal doping process. Specifically, due to the heat absorbed by the doped polysilicon layer 23 during the first heat treatment process It takes a certain time to conduct and release, therefore, the second doping ions can be diffused by the waste heat of the first heat treatment process; in other embodiments, the second doping ions rely on the second heat treatment process performed after the ion implantation process. diffusion.
  • a blocking layer 24 is formed on the surface of the doped polysilicon layer 23 away from the gate dielectric layer 22 , and the blocking layer 24 is used to block ion migration.
  • the blocking layer is used to block further migration of the first dopant ions and the second dopant ions, so as to ensure and further control the capacitance equivalent thickness range and ensure that the semiconductor structure has a relatively reasonable capacitance equivalent thickness.
  • the ion implantation process is performed after the thermal doping process, so that the concentration of the dopant ions in the polysilicon layer can exceed the solid solubility limit of the dopant ions, which is beneficial to reduce the thickness of the depletion layer, thereby reducing the thickness of the depletion layer.
  • the equivalent thickness of the capacitor; in addition, doping the second dopant ions in the area with a distance from the top surface is beneficial to improve the diffusion rate of the second dopant ions and increase the dopant ion concentration of the polysilicon layer near the gate dielectric layer. , which is beneficial to make the thickness of the depletion layer thinner under the condition of a certain number of carrier migration, that is, the equivalent thickness of the capacitance is thinner, and the capacitance of the semiconductor structure is larger.
  • FIGS. 12 and 13 are schematic diagrams corresponding to each step of a method for forming a semiconductor structure provided by another embodiment of the present application. For the parts that are the same as or corresponding to the previous embodiment, reference may be made to the corresponding description of the previous embodiment, which will not be repeated below.
  • the second doping ions are different from the first doping ions, and the weight of the second doping ions is smaller than the weight of the first doping ions.
  • the first dopant ions may be heavy ions
  • the second dopant ions may be light ions.
  • light ion implantation has a lower damage density on the doped polysilicon layer 33, and the damage with lower density can be better repaired by the second heat treatment process performed earlier or later, so as to ensure The doped polysilicon layer 33 has good properties.
  • a second heat treatment process is performed, and the second doping ions are diffused by means of the second heat treatment process performed after the ion implantation process.
  • the second heat treatment process performed after the ion implantation process may be dedicated to diffusing the second dopant ions, or may be used to process or form other components or layers.
  • the diffusion by the second heat treatment process performed later it is not necessary to control the time interval between the thermal doping process and the ion implantation process, so that in the After the thermal doping process, there is more time for cleaning, inspection and other steps, which is conducive to improving the flexibility of the process;
  • the doping ions are completely diffused, so that the area of the doped polysilicon layer 33 close to the gate dielectric layer 32 has a higher concentration of doping ions, so that the equivalent thickness of the capacitor is smaller, and the capacitance of the MOS transistor is larger.
  • a metal blocking film 341 is formed on the surface of the doped polysilicon layer 33 away from the gate dielectric layer 32 ; Metal blocking layer 34 .
  • the second dopant ions are diffused by the second heat treatment process performed on the metal barrier film 341.
  • the weight of the second dopant ions is smaller than the weight of the first dopant ions, which is beneficial to ensure that the damage caused by the ion implantation process can be effectively repaired by the second heat treatment process; in addition, the second dopant ions can be used later
  • the second heat treatment process is used for diffusion, which is beneficial to ensure that the second dopant ions can be effectively diffused, so that the area of the polysilicon layer close to the gate dielectric layer has a higher concentration of dopant ions, thereby making the equivalent thickness of the capacitor smaller, and the MOS tube Capacitance is large.

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Abstract

本申请实施例提供一种半导体结构的形成方法，包括：提供依次层叠的基底、栅介质层以及未掺杂的多晶硅层；进行热掺杂工艺，在多晶硅层内掺杂第一掺杂离子；进行离子注入工艺，在多晶硅层的预设区域内掺杂第二掺杂离子，在垂直于基底表面的方向上，预设区域与多晶硅层背离栅介质层的表面之间具有预设间距。

Description

半导体结构的形成方法
交叉引用
本申请要求于2020年7月28日递交的名称为“半导体结构的形成方法”、申请号为202010737116.9的中国专利申请的优先权，其通过引用被全部并入本申请。
技术领域
本申请实施例涉及一种半导体结构的形成方法。
背景技术
晶体管的电容大小是晶体管的性能指标之一，现有技术常通过减薄栅介质层的实体厚度提高晶体管的电容大小，但是这样做存在着栅介质层过薄而被击穿的风险。当前主要采取的技术手段是在栅介质层厚度不变的情况下，减薄栅极耗尽层的厚度，从而起到减小电容等效厚度，增大晶体管电容的目的。
发明内容
为解决上述问题，本申请实施例提供一种半导体结构的形成方法，提供依次层叠的基底、栅介质层以及未掺杂的多晶硅层；进行热掺杂工艺，在所述多晶硅层内掺杂第一掺杂离子；进行离子注入工艺，在所述多晶硅层的预设区域内掺杂第二掺杂离子，在垂直于所述基底表面的方向上，所述预设区域与所述多晶硅层背离所述栅介质层的表面之间具有预设间距。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，除非有特别申明，附图中的图不构成比例限制。
图1至图3为一种半导体结构的形成方法各步骤对应的示意图；
图4为多晶硅层中某一位置的掺杂离子浓度随掺杂时间变化的变化示意图；
图5为多晶硅层的电容等效厚度随掺杂时间变化的变化示意图；
图6至图11为本申请一实施例提供的一种半导体结构的形成方法各步骤对应的示意图；
图12和图13为本申请又一实施例提供的半导体结构的形成方法各步骤对应的示意图。
其中，11、21、31：基底；12、22、32：栅介质层；130、230：未掺杂多晶硅层；131、231：初始掺杂区；13、23、33：掺杂后多晶硅层；232：预设区域；d：预设间距；24：阻拦层；341：金属阻拦膜；34：金属阻拦层。
具体实施方式
参考图1至图3，图1至图3为一种半导体结构的形成方法示意图。
半导体结构的形成方法包括：提供依次层叠的基底11、栅介质层12以及未掺杂多晶硅层130；进行掺杂工艺，在未掺杂多晶硅层130背离栅介质层12的表层区域掺杂掺杂离子，形成初始掺杂区131；进行热处理工艺，以使位于初始掺杂区131内的掺杂离子向下扩散，形成掺杂后多晶硅层13。
需要说明的是，掺杂离子的热掺杂工艺通常可分为两种：有限源扩散和恒定表面源扩散。有限源扩散指的是在扩散过程中，掺杂离子源限定于扩散前掺杂在多晶硅层表面薄层内的掺杂离子总数不变，依靠这些有限的掺杂离子向多晶硅层内其他区域中进行扩散；恒定表面源扩散是指扩散过程中多晶硅层始终处于含源的气氛中，即多晶硅层表面薄层的浓度始终不变，只是随着时间的变化，多晶硅层内的掺杂离子数量在不断增多。
简单来说，有限源扩散指的是在掺杂工艺之后进行热处理工艺，恒定表面源扩散指的是在掺杂工艺过程中进行热处理工艺，但无论是哪种扩散方式，都会受到掺杂离子固溶度的限制。
具体来说，由于浓度差是扩散的基础条件之一，因此在进行热掺杂工艺的过程中，在掺杂离子的扩散方向上，掺杂离子的浓度必然是阶梯递减的。对于有限源扩散来说，当表面薄层内的掺杂离子完成浓度阶梯递减的再分布之后，扩散就会停止；对于恒定表面源扩散来说，需要表面薄层的掺杂离子浓度高于固溶度极限才能继续依靠浓度差扩散时，扩散就会停止。
也就是说，无论是有限源扩散还是恒定表面源扩散，由于浓度差的限定， 必然有部分区域的掺杂离子浓度无法到达固溶度极限，且任意位置的掺杂离子浓度都不会超过固溶度极限。这就导致多晶硅层内的掺杂离子总数有限，且掺杂离子更多地集中在多晶硅层背离栅介质层的部分，在掺杂离子受到电场作用发生迁移而形成耗尽层时，由于靠近栅介质层区域的掺杂离子浓度较低，因此更容易形成较厚的耗尽层，进而导致电容等效厚度较大，电容值较小。
参考图4，图4为多晶硅层中某一位置的掺杂离子浓度随掺杂时间变化的变化示意图，横轴表示掺杂时间，纵轴表示某一位置的掺杂离子浓度，随着掺杂工艺的进行，某一位置的掺杂离子浓度趋向饱和，无法突破固溶度极限，进而导致掺杂工艺无效或者扩散过程停止；参考图5，图5为多晶硅层的电容等效厚度随掺杂时间变化的变化示意图，横轴表示掺杂时间，纵轴表示电容等效厚度，随着掺杂工艺的进行，由于多晶硅层中掺杂离子浓度趋于饱和，电容等效厚度也随之趋于饱和。
为解决上问题，本申请实施提供一种半导体结构的形成方法，在进行热掺杂工艺之后进行离子注入工艺，使得多晶硅层内的掺杂离子浓度能够超过掺杂离子的固溶度极限，有利于减薄耗尽层的厚度，进而减小电容等效厚度；此外，在与顶面具有间距的区域内掺杂第二掺杂离子，有利于提高第二掺杂离子的扩散速率，以及提高多晶硅层靠近栅介质层部分的掺杂离子浓度，有利于使得在载流子迁移数量一定的情况下，耗尽层的厚度较薄，即电容等效厚度较薄，电容较大。
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合附图对本申请的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。
图6至图11为本申请一实施例提供的一种半导体结构的形成方法各步骤对应的示意图。
参考图6，提供依次层叠的基底21、栅介质层22以及未掺杂多晶硅层230。
基底21内可掺杂掺杂离子，以形成掺杂区和位于相邻掺杂区之间的沟道区。基底21在掺杂掺杂离子之后，可与栅介质层22以及掺杂后多晶硅层一同 构成MOS管，MOS管的类型取决于基底21内掺杂的掺杂离子类型，MOS管的类型包括NMOS管和PMOS管。
本实施例中，栅介质层22为掺氮的氧化物层。掺氮的氧化物层具有较好的离子阻隔效果，有利于阻拦掺杂后多晶硅层内的掺杂离子向基底21内渗透，从而保证基底21具有良好性能。
未掺杂多晶硅层230的离子掺杂可包括多个步骤或通过至少一种工艺实现，本申请实施例中通过热掺杂工艺对未掺杂多晶硅层230进行离子掺杂，具体地，以有限源扩散工艺为例，未掺杂多晶硅层230的离子掺杂包括以下步骤：
参考图7，进行掺杂工艺，在未掺杂多晶硅层230背离栅介质层22的表层区域内掺杂第一掺杂离子，形成初始掺杂区231。
本实施例中，可采用电浆式离子注入工艺掺杂第一掺杂离子，第一掺杂离子的类型包括N型离子或P型离子，本文以第一掺杂离子的类型为P型离子作为示例。电浆式离子注入工艺对靶材温度要求较低，且具有较高的掺杂速率，有利于避免加热形成的热冲击对多晶硅层造成损伤；此外，电浆式离子注入工艺在进行离子注入时，不经过解析电场筛选，单位时间内离子注入量较多，产能较高，且能够使得初始掺杂区231具有较高浓度的第一掺杂离子。
本实施例中，初始掺杂区231内的第一掺杂离子的浓度大于第一掺杂离子在多晶硅层内的固溶度极限。如此，有利于提高有限源扩散中的掺杂离子总数，进而提高掺杂后多晶硅层的第一掺杂离子浓度。
参考图8，进行第一热处理工艺，以使位于初始掺杂区231内的第一掺杂离子向下扩散，形成掺杂后多晶硅层23。
本实施例中，第一热处理工艺包括快速热处理(Rapid Thermal Processing，RTP)，例如快速热处理退火工艺，快速热处理退火工艺能够在非常短的时间内将整个多晶硅层加热至400℃～1300℃温度范围内，具有较短的退火时间，有利于减缓掺杂后多晶硅层23受到的热冲击，保证掺杂后多晶硅层23具有较优的结构性能；此外，相对于炉管退火，快速热处理退火工艺具有热预算少，硅中杂质运动小、玷污小以及加工时间短等优点。
需要说明的是，由于浓度差是扩散的基础条件，因此在第一热处理工艺 完成后，在掺杂后多晶硅层23顶面朝向掺杂后多晶硅层23底面的方向上，第一掺杂离子的浓度实际上是呈阶梯递减的。此外，在第一热处理工艺完成后，掺杂后多晶硅层23内每一位置的第一掺杂离子实际浓度还与第一掺杂离子的类型(掺杂离子类型不同固溶度不同)、第一热处理工艺的能量、未掺杂多晶硅层230(参考图6)在垂直于基底21表面方向上的厚度以及初始掺杂区231(参考图7)内的第一掺杂离子浓度有关。
具体地，第一掺杂离子的固溶度越高，掺杂后多晶硅层23内每一位置的第一掺杂离子的掺杂浓度越高；第一热处理工艺的能量较高时，位于表层区域的第一掺杂离子就能实现更大程度的扩散，掺杂后多晶硅层23靠近栅介质层22区域的第一掺杂离子浓度就越高；掺杂后多晶硅层23在垂直于基底21表面方向上的厚度越厚，第一掺杂离子在扩散方向上的浓度梯数越多，第一掺杂离子在扩散方向上的稀释次数就越多，掺杂后多晶硅层23靠近栅介质层22的部分的第一掺杂离子浓度就越低；初始掺杂区231内的第一掺杂离子浓度越高，掺杂后多晶硅层23内每一位置的第一掺杂离子的掺杂浓度越高。
参考图9，在进行热掺杂工艺之后，进行离子注入工艺，在掺杂后多晶硅层23的预设区域232内掺杂第二掺杂离子。
本实施例中，第二掺杂离子与第一掺杂离子相同，第二掺杂离子包括硼离子或类硼离子，类硼离子包括BF2+或BF2+中的至少一者。
本实施例中，在垂直于基底21表面的方向上，预设区域232与掺杂后多晶硅层23背离栅介质层22的表面之间具有预设间距d。在进行热掺杂工艺之后进行离子注入工艺，能够使得掺杂后多晶硅层23内任意位置的掺杂离子浓度超过掺杂离子的固溶度极限，当固定数量的载流子(即第二掺杂离子)在电场作用在朝远离栅介质层22的方向迁移时，靠近栅介质层22的区域的第二掺杂离子浓度越高，耗尽层的厚度越薄，电容等效厚度越小。
此外，由于在掺杂后多晶硅层23朝向栅介质层22的方向上，第一掺杂离子浓度呈阶梯下降，因此，在与顶面具有间距的预设区域232内掺杂第二掺杂离子，有利于提高预设区域232内的掺杂离子浓度与位于预设区域232两侧的区域的掺杂离子浓度之差，进而提高第二掺杂离子的扩散速率，缩短工艺制程周期。
需要说明的是，第二掺杂离子的扩散速率与热掺杂工艺的类型有关。相较于有限源扩散工艺而言，在进行恒定表面源扩散工艺之后，掺杂后多晶硅层23内任意位置的掺杂离子浓度都要较高，相应地，如果离子注入工艺在预设区域232内注入的剂量相同，那么预设区域与相邻区域之间的浓度差就会较小，扩散速度就较慢。
进一步地，在与顶面具有间距的预设区域232内掺杂第二掺杂离子，有利于缩短预设区域232与掺杂后多晶硅层23靠近栅介质层22的表面的间距，进而使得第二掺杂离子更容易扩散至掺杂后多晶硅层23靠近栅介质层22的区域，从而提高掺杂后多晶硅层23靠近栅介质层22部分的掺杂离子浓度，进而使得在载流子迁移数量一定的情况下，耗尽层的厚度较薄，即电容等效厚度较薄，半导体结构电容较大。
本实施例中，预设间距d为1nm～10nm，例如为3nm、5nm或7nm。由于在掺杂后多晶硅层23朝向栅介质层22的方向上，第一掺杂离子的浓度是阶梯递减的，因此，预设间距d越大，掺杂区域与周围区域的浓度差就越大，第二掺杂离子的扩散速度就越快，且掺杂后多晶硅层23靠近栅介质层22一侧的掺杂离子浓度就越高；同时，为避免离子注入工艺的射程较长而对掺杂后多晶硅层23造成较大的损伤，需要对预设间距d的最大值进行限制，从而保证掺杂后多晶硅层23具有良好性能。本实施例中，参考图10，第二掺杂离子可以依靠热掺杂工艺中的第一热处理工艺进行扩散，具体来说，由于掺杂后多晶硅层23在第一热处理工艺过程中吸收的热量需要一定的时间传导和释放，因此，第二掺杂离子可以依靠第一热处理工艺的余热进行扩散；在其他实施例中，第二掺杂离子依靠在离子注入工艺之后进行的第二热处理工艺进行扩散。
参考图11，在进行离子注入工艺之后，在掺杂后多晶硅层23远离栅介质层22的表面形成阻拦层24，阻拦层24用于阻拦离子迁移。
具体地，阻拦层用于阻拦第一掺杂离子和第二掺杂离子的进一步迁移，从而保证进而控制电容等效厚度范围，保证半导体结构具有较为合理的电容等效厚度。
本实施例中，在进行热掺杂工艺之后进行离子注入工艺，使得多晶硅层内的掺杂离子浓度能够超过掺杂离子的固溶度极限，有利于减薄耗尽层的厚度， 进而减小电容等效厚度；此外，在与顶面具有间距的区域内掺杂第二掺杂离子，有利于提高第二掺杂离子的扩散速率，以及提高多晶硅层靠近栅介质层部分的掺杂离子浓度，有利于使得在载流子迁移数量一定的情况下，耗尽层的厚度较薄，即电容等效厚度较薄，半导体结构电容较大。
本申请又一实施例还提供一种半导体结构的形成方法，与前一实施例不同的是，本实施例中，第二掺杂离子与第一掺杂离子不同，且第二掺杂离子依靠在后进行的第二热处理工艺进行扩散。以下将结合图12和图13进行详细说明，图12和图13为本申请又一实施例提供的半导体结构的形成方法各步骤对应的示意图。与上一实施例相同或者相应的部分，可参考上一实施例的相应说明，以下不做赘述。
本实施例中，第二掺杂离子与第一掺杂离子不同，第二掺杂离子的重量小于第一掺杂离子的重量。具体地，第一掺杂离子可以是重离子，第二掺杂离子可以是轻离子。相较于重离子注入，轻离子注入对掺杂后多晶硅层33产生的损伤密度更低，较低密度的损伤能够更好地通过在先或者在后进行的第二热处理工艺进行修复，从而保证掺杂后多晶硅层33具有良好性能。
本实施例中，在进行离子注入工艺之后，进行第二热处理工艺，第二掺杂离子依靠在离子注入工艺之后进行的第二热处理工艺进行扩散。在离子注入工艺之后进行的第二热处理工艺既可以是专门用于扩散第二掺杂离子的，也可以是用于处理或形成其他部件或膜层的。
相较于利用在离子注入之前进行的第一热处理工艺进行扩散，利用在后进行的第二热处理工艺进行扩散，一方面，无需控制热掺杂工艺与离子注入工艺之间的时间间隔，使得在进行热掺杂工艺之后，有更多的时间进行清洗、检查等步骤，有利于提高工艺灵活性；另一方面，在后进行的第二热处理工艺可以有一次或多次，有利于保证第二掺杂离子完全扩散，进而使得掺杂后多晶硅层33靠近栅介质层32的区域具有浓度更高的掺杂离子，使得电容等效厚度较小，MOS管的电容较大。
具体地，参考图12，在进行离子注入工艺之后，在掺杂后多晶硅层33远离栅介质层32的表面形成金属阻拦膜341；参考图13，对金属阻拦膜341进行第二热处理工艺，形成金属阻拦层34。其中，第二掺杂离子利用对金属阻拦膜 341进行的第二热处理工艺进行扩散。
本实施例中，第二掺杂离子的重量小于第一掺杂离子的重量，有利于保证离子注入工艺造成的损伤能够被第二热处理工艺有效修复；此外，第二掺杂离子可利用在后的第二热处理工艺进行扩散，有利于保证第二掺杂离子能够有效扩散，使得多晶硅层靠近栅介质层的区域具有浓度较高的掺杂离子，进而使得电容等效厚度较小，MOS管的电容较大。
本领域的普通技术人员可以理解，上述各实施方式是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。任何本领域技术人员，在不脱离本申请的精神和范围内，均可作各自更动与修改，因此本申请的保护范围应当以权利要求限定的范围为准。

Claims (11)

  1. 一种半导体结构的形成方法，包括：
    提供依次层叠的基底、栅介质层以及未掺杂的多晶硅层；
    进行热掺杂工艺，在所述多晶硅层内掺杂第一掺杂离子；
    进行离子注入工艺，在所述多晶硅层的预设区域内掺杂第二掺杂离子，在垂直于所述基底表面的方向上，所述预设区域与所述多晶硅层背离所述栅介质层的表面之间具有预设间距。
  2. 根据权利要求1所述的半导体结构的形成方法，其中，所述预设间距为1nm～10nm。
  3. 根据权利要求1所述的半导体结构的形成方法，其中，所述第二掺杂离子与所述第一掺杂离子不同，所述第二掺杂离子的重量小于所述第一掺杂离子的重量。
  4. 根据权利要求3所述的半导体结构的形成方法，其中，所述第二掺杂离子包括硼离子、氟化硼离子或二氟化硼离子中的至少一者。
  5. 根据权利要求1所述的半导体结构的形成方法，其中，所述热掺杂工艺包括依次进行的掺杂工艺和第一热处理工艺，所述掺杂工艺在所述多晶硅层远离所述栅介质层的表层区域内掺杂所述第一掺杂离子，所述第一热处理工艺使所述第一掺杂离子在所述多晶硅层内扩散。
  6. 根据权利要求5所述的半导体结构的形成方法，其中，所述掺杂工艺包括电浆式离子注入工艺。
  7. 根据权利要求6所述的半导体结构的形成方法，其中，所述电浆式离子注入工艺在所述表层区域内掺杂的所述第一掺杂离子的浓度大于所述第一掺杂离子在所述多晶硅层内的固溶度极限。
  8. 根据权利要求5所述的半导体结构的形成方法，其中，所述第一热处理工艺包括快速热处理退火工艺。
  9. 根据权利要求1所述的半导体结构的形成方法，其中，在进行所述离子注入工艺之后，进行第二热处理工艺，所述第二掺杂离子依靠所述第二热处理工 艺进行扩散。
  10. 根据权利要求1所述的半导体结构的形成方法，其中，在进行所述离子注入工艺之后，在所述多晶硅层远离所述栅介质层的表面形成阻拦层，所述阻拦层用于阻拦离子迁移。
  11. 根据权利要求1所述的半导体结构的形成方法，其中，还包括在所述多晶硅层远离所述栅介质层的表面形成金属阻拦膜；对所述金属阻拦膜进行第二热处理工艺，形成金属阻拦层，所述第二掺杂离子依靠所述第二热处理工艺进行扩散。
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