WO2023029196A1 - 场效应晶体管形成方法、电性能参数调节方法及结构 - Google Patents

场效应晶体管形成方法、电性能参数调节方法及结构 Download PDF

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WO2023029196A1
WO2023029196A1 PCT/CN2021/127880 CN2021127880W WO2023029196A1 WO 2023029196 A1 WO2023029196 A1 WO 2023029196A1 CN 2021127880 W CN2021127880 W CN 2021127880W WO 2023029196 A1 WO2023029196 A1 WO 2023029196A1
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ions
field effect
effect transistor
implantation
semiconductor substrate
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PCT/CN2021/127880
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French (fr)
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张书浩
陈海波
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长鑫存储技术有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present application relates to the technical field of semiconductor technology, and more specifically, to a method for forming a field effect transistor, a method for adjusting electrical performance parameters, and a structure.
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • the purpose of the embodiments of the present application is to provide a method for forming a field effect transistor, a method and a structure for adjusting electrical performance parameters, so as to alleviate the existing technical problems.
  • the first aspect of the present application provides a method for forming a field effect transistor, including: providing a semiconductor substrate and performing ion implantation on the semiconductor substrate to form an active region; forming a gate structure on the surface of the semiconductor substrate; Implanting more than two kinds of ions on both sides of the gate structure to form shallow doped regions; more than two kinds of ions include fluorine ions; annealing the semiconductor substrate.
  • the process parameters for implanting fluorine ions in the shallowly doped region include: implantation dose range of 1E14-1E16 atom/cm2, implantation energy range of 5KeV-20KeV, and implantation tilt angle range of 5°-60°.
  • the method further includes: determining the implantation dose of fluorine ions according to the adjustment value of the threshold voltage or the on-state current of the field effect transistor.
  • ions are implanted on both sides of the gate structure to form a halo region.
  • fluoride ions are implanted in the halo region.
  • the implantation depth of fluorine ions is greater than the implantation depth of ions other than fluorine ions in the shallowly doped region.
  • the annealing temperature of the annealing treatment is 1000°C-1200°C, and the duration is 9s-12s.
  • the annealing treatment includes spike annealing.
  • the embodiments of the present disclosure may/at least have the following advantages.
  • a single ion implantation process is used to achieve the purpose of adjusting the electrical properties of the field effect transistor.
  • the second aspect of the present application provides a method for adjusting electrical performance parameters of a field effect transistor, comprising: implanting fluorine ions in the shallow doped region and/or halo region of the field effect transistor; performing annealing treatment on the field effect transistor.
  • the process parameters of implanting fluorine ions include: implantation dose range of 1E14-1E16 atom/cm2, implantation energy range of 5KeV-20KeV, and implantation tilt angle range of 5°-60°.
  • the method further includes: determining the implantation dose of fluorine ions according to the adjustment value of the threshold voltage or the on-state current of the field effect transistor.
  • the annealing treatment includes spike annealing.
  • the embodiments of the present disclosure may/at least have the following advantages: when the low threshold voltage type field effect transistor and the non-low threshold voltage type field effect transistor share a photomask for electrical performance adjustment, a fluorine ion implantation process is used to achieve low threshold voltage The purpose of adjusting the electrical performance of the type field effect transistor does not affect the electrical performance of the non-low threshold voltage type field effect transistor.
  • the third aspect of the present application provides a field effect transistor structure, including: a semiconductor substrate, a gate structure and a lightly doped region; the active region is located in the semiconductor substrate; the gate structure is formed on the semiconductor substrate The bottom surface; the shallow doped region is formed on both sides of the gate structure by implanting more than two kinds of ions through an ion implantation process; the more than two kinds of ions include fluorine ions.
  • it further includes: a halo region, the halo region is formed on both sides of the gate structure by using an ion implantation process.
  • the implantation depth of fluorine ions is greater than the implantation depth of ions other than fluorine ions in the shallowly doped region.
  • FIG. 1 is a schematic flow chart of a method for forming a field effect transistor according to an embodiment of the present application
  • FIGS. 2 to 5 are schematic diagrams of a field effect transistor forming process of a method for forming a field effect transistor according to an embodiment of the present application
  • FIG. 6 is a schematic flowchart of a method for adjusting electrical performance parameters of a field effect transistor according to an embodiment of the present application
  • Fig. 7 is a schematic structural diagram of a field effect transistor according to an embodiment of the present application for adjusting the electrical performance parameters of a field effect transistor;
  • Fig. 8 (a) - Fig. 8 (b) is the schematic diagram of parameter adjustment parameter of electric performance parameter of low-threshold voltage type field effect transistor of the embodiment of the present application;
  • Fig. 9 (a) - Fig. 9 (b) is the schematic diagram of adjusting parameters of electrical performance parameters of the non-low threshold voltage type field effect transistor of the embodiment of the present application;
  • FIG. 10 is a schematic structural diagram of a field effect transistor according to an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of another field effect transistor according to the embodiment of the present application.
  • 10 low threshold voltage field effect transistor
  • 20 non-low threshold voltage field effect transistor
  • 100 semiconductor substrate
  • 200 gate structure
  • 210 gate electrode layer
  • 220 gate oxide layer
  • 300 shallow doping 400: distribution of fluorine ions in shallow doping area
  • 500 distribution of ions implanted in halo area
  • 600 source
  • 700 drain.
  • FIG. 1 A schematic diagram of a layer structure according to an embodiment of the present application is shown in the accompanying drawings.
  • the figures are not drawn to scale, with certain details exaggerated and possibly omitted for clarity.
  • the shapes of the various regions and layers shown in the figure, as well as their relative sizes and positional relationships are only exemplary, and may deviate due to manufacturing tolerances or technical limitations in practice, and those skilled in the art will Regions/layers with different shapes, sizes, and relative positions can be additionally designed as needed.
  • FIG. 1 is a schematic flow chart of a method for forming a field effect transistor according to an embodiment of the present application.
  • the method for forming a field effect transistor provided in the embodiment of the present application mainly includes four steps, and the four steps will be described in detail below.
  • Step S1 providing a semiconductor substrate and performing ion implantation on the semiconductor substrate to form an active region.
  • N-type ions are implanted into the semiconductor substrate 100 to form an active region with a certain depth, for example, arsenic ions are implanted.
  • Arsenic is a pentavalent element
  • other pentavalent impurity elements include phosphorus, antimony, etc.
  • the pentavalent impurities doped inside the semiconductor substrate 100 its four valence electrons form a covalent relationship with the valence electrons of the four adjacent main atoms.
  • Valence bond the fifth valence electron cannot form a covalent bond and becomes a free electron.
  • This doping method has a surplus of free electrons, so doping with pentavalent impurity elements forms an N-type semiconductor.
  • the ion implantation method uses an electric field to accelerate impurity ions and inject them into a semiconductor substrate.
  • the active region may also be formed by implanting P-type ions into the semiconductor substrate, for example, implanting boron ions.
  • Boron is a trivalent impurity element. Its three valence electrons form a covalent bond with the valence electrons of the three adjacent main atoms. A vacancy will be formed due to the lack of one valence electron, and it will be doped into a P-type semiconductor.
  • the semiconductor substrate 100 may be, but not limited to, commonly used semiconductor substrate materials such as silicon, germanium, and silicon germanium, and the type of implanted ions is selected according to actual requirements.
  • Step S2 forming a gate structure on the surface of the semiconductor substrate.
  • FIG. 2 schematically shows a schematic diagram of a gate structure formed on the surface of a semiconductor substrate.
  • the gate oxide layer 220 is located on the surface of the gate electrode layer 210 .
  • the material of the gate electrode layer 210 is polysilicon, doped polysilicon or metal, and the material of the gate oxide layer 220 is silicon oxide or high dielectric material.
  • a silicon oxide layer or a silicon nitride layer is formed on the surface of the gate structure, and the use of the silicon oxide layer or silicon nitride layer can prevent impurity ions from being implanted into the gate oxide layer or the gate electrode in the subsequent ion implantation process, Affects the electrical performance of the gate structure.
  • the gate structure 200 is formed by exposure etching of polysilicon.
  • Step S3 implanting ions to form shallowly doped regions. Specifically, more than two kinds of ions are implanted on both sides of the gate structure to form shallow doped regions
  • FIG. 3 schematically shows a schematic diagram of the structure of the shallow doped region
  • FIG. 4 schematically shows a schematic diagram of the structure of the shallow doped region after implanting fluorine ions.
  • FIG. 3 and FIG. 4 there are more than two kinds of ions implanted in the shallowly doped region in the figure.
  • the other ion distribution 300 in the shallow doped region contains at least one kind of ion.
  • the other ion distribution 300 in the shallow doped region is doped with boron ions or boron difluoride or a combination of both.
  • Fluorine ions can be implanted first to form the fluorine ion distribution 400 in the shallow doped region, or the fluorine ion distribution 400 in the shallow doped region can be implanted first. Ions implanted into the other ion distribution 300 of the shallowly doped region form the other ion distribution 300 of the shallowly doped region.
  • doping in the shallowly doped region can alleviate the short channel effect and the hot carrier effect.
  • the short channel effect means that when the channel length of the MOSFET transistor is shortened to be comparable to the width of the depletion layer of the source and drain, the short channel effect occurs.
  • the charge in the depletion region under the gate of the MOSFET is no longer completely controlled by the gate, and part of it is controlled by the source and drain, resulting in charge sharing in the depletion region, and as the channel length decreases, the depletion region controlled by the gate The charge keeps decreasing.
  • the charge in the depletion region controlled by the gate is continuously reduced, only less gate charge is needed to achieve inversion, thereby reducing the threshold voltage of the field effect transistor.
  • the carrier When the carrier obtains a lot of energy from the outside world, it can become a hot carrier. For example, under the action of a strong electric field, the carriers continuously drift along the direction of the electric field and accelerate continuously, which can obtain a lot of kinetic energy and thus become hot carriers.
  • the hot carrier effect is an important reason for the failure of devices and integrated circuits in the field of semiconductors.
  • Implanting fluorine ions in the shallowly doped region can improve the threshold voltage and on-state current of the field effect transistor.
  • the other ion distribution 300 in the shallow doped region contains boron ions
  • the fluorine ions in the fluorine ion distribution 400 in the shallow doped region can enhance the diffusion of boron ions in the semiconductor substrate.
  • fluorine in terms of atomic structure, fluorine is 7-valent, and it is easy to obtain electrons and provide holes, thereby increasing the on-state current of the field effect transistor. It should be noted that, in the ion implantation process, atoms need to be ionized first to charge them to form ions.
  • B+ ions can be formed by ionizing boron atoms or boron fluoride.
  • the ions are accelerated by the electric field, and the ions are driven into the semiconductor substrate under the action of the electric field. If it is a neutral atom, the ion implantation process cannot be accelerated by an electric field.
  • the process parameters for implanting fluorine ions in the shallowly doped region include: the implantation dose ranges from 1E14 to 1E16 atom/cm 2 , the implantation energy ranges from 5KeV to 20KeV, and the implantation tilt angle ranges from 5 degrees to 60 degrees.
  • the energy of fluorine ion implantation is 15KeV, and the inclination angle of implantation is 21 degrees.
  • the dose of fluorine ion implantation determines the doping concentration, that is, the higher the implanted dose, the higher the doping concentration, and the higher the doping concentration, the higher the concentration of majority carriers in the semiconductor.
  • the energy and tilt angle of the fluorine ion implantation determine the depth and shape of the doping profile.
  • the ion implantation method can precisely control the low-concentration doping distribution that is difficult to obtain by the diffusion method, that is, realize the precise control of the implanted dose.
  • the ion implanted amount can be accurately controlled by measuring the magnitude of the current flowing through the substrate.
  • the implantation depth of fluorine ions is greater than the implantation depth of ions other than fluorine ions in the shallowly doped region.
  • the energy and inclination angle of the fluorine ion implantation are adjusted, so that the implantation depth of the fluorine ion is greater than the implantation depth of other ions except the fluorine ion in the shallowly doped region.
  • the implantation dose of fluorine ions is determined according to the adjustment amount of the threshold voltage or the on-state current of the field effect transistor. For example, increasing the implantation dose of fluorine ions can reduce the threshold voltage of the field effect transistor and increase the on-state current of the field effect transistor. For example, when the dose of implanted fluorine ions increases by 1E15atom/cm 2 , the threshold voltage of the field effect transistor decreases by 50mV, and the on-state current of the field effect transistor increases by 26uA/um. Therefore, the implantation dose of fluorine ions can be determined according to the adjustment amount of the threshold voltage or the on-state current of the field effect transistor.
  • Step S4 performing annealing treatment on the semiconductor substrate.
  • annealing treatment is required, and the damage to the semiconductor substrate caused by the implantation of dopant atoms will be repaired by the annealing treatment.
  • the implanted fluorine ions do not need to be annealed separately, but can be annealed together with the ions implanted in the shallowly doped region.
  • the process of fluorine ions entering the semiconductor substrate is destructive, which will ionize part of the semiconductor substrate atoms or destroy the valence bonds of the semiconductor substrate atoms.
  • the atomic radius of the semiconductor substrate is small, and the energy barrier crossed to maintain a stable form is small.
  • the semiconductor substrate atoms will automatically repair, that is, the wrong valence bond arrangement will be repaired, and the fixed charges will be supplemented by external electrons.
  • the atoms of the semiconductor substrate recover, just as the neutral atoms diffuse into the atoms of the semiconductor substrate.
  • the process of thermal repair is annealing treatment. Schematically, boron ions and fluorine ions implanted in shallowly doped regions are annealed together to repair semiconductor substrate atoms.
  • the annealing temperature of the annealing treatment is 1000°C-1200°C, and the duration is 9s-12s.
  • the annealing treatment includes a spike anneal.
  • the spike annealing is a kind of immersion annealing.
  • the wafer is raised to the set temperature at a very fast heating rate, and the heating rate can reach nearly 250°C/s at the fastest. It is cooled to below 600°C at a faster cooling rate, and the fastest cooling rate can reach nearly 90°C/s.
  • Spike annealing is mainly used in the manufacturing process of field effect transistor devices below 0.13um. It is located after lightly doped drain and source-drain ion implantation. It repairs the lattice damage and defects caused by ion implantation while forming ultra-shallow junctions.
  • the spike annealing process is: heating up to 1020° C. at a heating rate of 220° C./s, maintaining for 10 seconds, and then lowering the temperature to below 600° C. at a cooling rate of 90° C./s.
  • ions are implanted on both sides of the gate structure to form a halo region.
  • an ion distribution 500 implanted in the halo region is formed in the substrate 100 by implanting the same type of doping ions as the substrate.
  • the halo region is a doped region where the substrate is heavily doped near the source and drain.
  • the doping type of the Halo region is N+, so that the depletion region or the space charge region of the PN junction is narrowed, and the depletion region at the source and the drain is prevented from being connected, resulting in Source-drain conduction.
  • the doping of the Halo region not only prevents source-drain conduction, but also suppresses the drain-induced barrier lowering effect.
  • the Drain Induced Barrier Lowering Effect is an important physical effect in ultra-large-scale MOSFET devices, which is reflected in the decrease of the threshold voltage caused by the drain terminal voltage, resulting in an increase of the drain-source current.
  • the angle of ions implanted in the halo region is larger than the angle of ions implanted in the shallowly doped region, so as to suppress the degradation of the sub-threshold current of the field effect transistor.
  • the ion implantation depth in the ion distribution 500 implanted in the halo region is greater than the ion implantation depth in the other ion distribution 300 in the shallow doped region and the fluorine ion distribution 400 in the shallow doped region.
  • the ions implanted in the halo regions on both sides of the gate structure 200 can be implanted in a symmetrical manner or an asymmetrical implantation manner, and there is no limitation on the implantation manner.
  • fluoride ions are implanted in the halo region.
  • the other ion distribution 300 in the shallow doped region, the fluorine ion distribution 400 in the shallow doped region, and the implanted ion distribution 500 in the halo region all of which overlap.
  • the inclination angle of the ions implanted in the halo region is 40 to 50 degrees
  • the inclination angle range of the fluorine ion implantation is 5 degrees to 60 degrees
  • the inclination angle implantation range of the fluorine ions includes the inclination angle range of the ions implanted in the halo region, Therefore, fluorine ions can be implanted in the halo region.
  • the formation process of the field effect transistor also includes the formation of the source and the drain, and the source and the drain can be formed by ion implantation.
  • the substrate 100 is a P-type substrate
  • the doping type of the ion distribution 500 implanted in the halo region is P+
  • the source and drain are doped with N+ type by ion implantation
  • the substrate 100 for an N-type substrate the doping type of the source and drain is P+; there is no restriction on the doping type and doped ions.
  • FIG. 6 is a schematic flowchart of a method for adjusting electrical performance parameters of a field effect transistor according to an embodiment of the present application.
  • the method for adjusting electrical performance parameters of a field effect transistor mainly includes two steps, which will be described in detail below.
  • Step S31 implanting fluorine ions in the lightly doped region and/or the halo region.
  • FIG. 7 is a schematic structural diagram of a field effect transistor according to a method for adjusting electrical performance parameters of a field effect transistor according to an embodiment of the present application.
  • the low threshold voltage field effect transistor 10 and the non-low threshold voltage field effect transistor 20 are adjusted for electrical performance parameters under the same mask. If the shallow doped region is adjusted in combination with ion implantation in the halo region, the electrical properties of the two devices will drift at the same time.
  • Figure 8(a)- Figure 8(b) is a schematic diagram of adjusting parameters of the electrical performance parameters of the low threshold voltage type field effect transistor of the embodiment of the present application, wherein Figure 8(a) is a schematic diagram of threshold voltage parameter adjustment, and Figure 8(b) is an open Schematic diagram of state current parameter adjustment.
  • Figure 8( a ) and FIG. 8( b ) none in the figure represents the case of not doping fluorine ions, and F represents the case of doping fluorine ions.
  • implanting fluorine ions in the shallowly doped region and/or the halo region can significantly reduce the threshold voltage Vt and increase the on-state current IDS for the low-threshold voltage type field effect transistor 10 compared to the case of not implanting fluorine ions. .
  • Figure 9(a)- Figure 9(b) is a schematic diagram of the adjustment parameters of the electrical performance parameters of the non-low threshold voltage field effect transistor of the embodiment of the present application, wherein Figure 9(a) is a schematic diagram of threshold voltage parameter adjustment, and Figure 9(b) is Schematic diagram of on-state current parameter adjustment.
  • Figure 9( a ) and FIG. 9( b ) none in the figure represents the case of not doping fluorine ions, and F represents the case of doping fluorine ions.
  • the threshold voltage Vt of the field effect transistor is about 0.55V.
  • the value of the on-state current IDS of the field effect transistor is about 510uA/um. Therefore, for the non-low threshold voltage field effect transistor 20 , the threshold voltage Vt and the on-state current IDS do not change significantly compared to the case of not implanting fluorine ions. In this way, only one fluorine ion implantation process can be used to adjust the electrical performance parameters of the low threshold voltage field effect transistor 10 without affecting the non-low threshold voltage field effect transistor 20 .
  • the table below is a summary table of changes in electrical performance parameters of the low-threshold voltage field effect transistor 10 and the non-low threshold voltage field effect transistor 20 with and without fluorine ion implantation.
  • the electrical performance parameters of the low threshold voltage type field effect transistor 10 are significantly improved after the fluorine ions are implanted into the lightly doped region and/or the halo region.
  • the implantation of fluorine ions in the shallowly doped region and/or the halo region may first implant the fluorine ions, and then implant other ions in the shallowly doped region and/or the halo region.
  • other ions may also be implanted in the shallowly doped region and/or the halo region to form the shallowly doped region or the halo region, and then implanted with fluorine ions.
  • the process parameters for implanting fluorine ions in the shallowly doped region include: the implantation dose ranges from 1E14 to 1E16 atom/cm 2 , the implantation energy ranges from 5KeV to 20KeV, and the implantation tilt angle ranges from 5 degrees to 60 degrees.
  • the energy of fluorine ion implantation is 15KeV, and the inclination angle of implantation is 21 degrees.
  • the implantation dose of fluorine ions is determined according to the adjustment amount of the threshold voltage or the on-state current of the field effect transistor. For example, increasing the implantation dose of fluorine ions can reduce the threshold voltage of the field effect transistor and increase the on-state current of the field effect transistor. For example, when the dose of implanted fluorine ions increases by 1E15atom/cm 2 , the threshold voltage of the field effect transistor decreases by 50mV, and the on-state current of the field effect transistor increases by 26uA/um.
  • Step S41 performing annealing treatment.
  • the implanted fluorine ions do not require a separate annealing treatment, but can be annealed together with the ions implanted in the shallow doped region and/or the halo region.
  • the annealing treatment includes a spike anneal.
  • the spike annealing process is: heating up to 1020° C. at a heating rate of 220° C./s, maintaining for 10 seconds, and then lowering the temperature to below 600° C. at a cooling rate of 90° C./s.
  • FIG. 10 is a schematic structural diagram of a field effect transistor according to an embodiment of the present application.
  • the field effect transistor structure shown in FIG. 10 includes: a semiconductor substrate 100, a gate structure 200 and a lightly doped region; the active region is located in the semiconductor substrate 100; the gate structure 200 is formed on the surface of the semiconductor substrate; The shallow doped region is formed on both sides of the gate structure by implanting more than two kinds of ions by ion implantation process; the more than two kinds of ions include fluorine ions.
  • the doped ion distribution in the shallow doped region includes the distribution of other ions in the shallow doped region 300 and the distribution of fluorine ions in the shallow doped region 400 .
  • the field effect transistor further includes a source 600 and a drain 700.
  • the source 600 and the drain 700 are formed by an ion implantation process.
  • the ions doped in the other ion distribution 300 in the shallow doped region are boron ions, and the boron ions can be ionized by boron fluoride, and then implanted into the field effect transistor structure through an ion implantation process after ionization to form other ions in the shallow doped region
  • fluorine ions can also be implanted after ionization of fluorine simple substance or compound to form the fluorine ion distribution 400 in the shallowly doped region.
  • the implantation depth of fluorine ions is greater than the implantation depth of ions other than fluorine ions in the shallowly doped region, so as to further increase the on-state current of the field effect transistor.
  • FIG. 11 is a schematic structural diagram of another field effect transistor according to the embodiment of the present application.
  • the structure embodiment of the field effect transistor shown in FIG. 11 also includes: a halo region, the halo region is formed on both sides of the gate structure by an ion implantation process, and the ion distribution 500 implanted in the halo region is as shown in the figure As shown, thereby further alleviating the short channel effect and suppressing the drain-induced barrier lowering effect.

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Abstract

本申请实施例公开了一种场效应晶体管形成方法、电性能参数调节方法及结构。该形成方法包括：提供半导体衬底并对半导体衬底进行离子注入，形成有源区；在半导体衬底表面形成栅极结构；在栅极结构的两侧注入两种以上离子形成浅掺杂区；两种以上离子包含氟离子；对半导体衬底进行退火处理。另外，该形成方法还包括：根据场效应晶体管阈值电压或开态电流的调节量，确定氟离子的注入剂量。本申请通过在场效应晶体管浅掺杂区注入氟离子，实现了使用一道离子注入工艺，达到场效应晶体管电性能调节的目的。

Description

场效应晶体管形成方法、电性能参数调节方法及结构
交叉引用
本申请基于申请号为202111010377.1、申请日为2021年08月31日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请涉及半导体工艺技术领域，更具体地，涉及一种场效应晶体管形成方法、电性能参数调节方法及结构。
背景技术
在半导体生产领域，金属氧化物半导体场效应晶体管(Metal Oxide Semiconductor Field Effect Transistor，MOSFET)作为半导体制造工艺中最常用的器件，其主要结构的生成主要是通过离子注入的方式。
为了调节场效应晶体管的电性能参数，通常需要两道离子注入工艺来调节，生产成本较高。另一方面，低阈值电压型场效应晶体管和非低阈值电压型场效应晶体管在共用一道光罩进行电性能调节时，如果使用浅掺杂区结合halo区离子注入的方式调节，两种器件的电性能会同时漂移。
发明内容
鉴于此，本申请实施例的目的是提供一种场效应晶体管形成方法、电性能参数调节方法及结构，以缓解现有的技术问题。
根据一些实施例，本申请第一方面提供了一种场效应晶体管形成方法，包括：提供半导体衬底并对半导体衬底进行离子注入，形成有源区；在半导体衬底表面形成栅极结构；在栅极结构的两侧注入两种以上离子形成浅掺杂区；两种以上离子包含氟离子；对半导体衬底进行退火处理。
可选地，在浅掺杂区注入氟离子的工艺参数，包括：注入的剂量范围为1E14—1E16atom/cm2，注入的能量范围为5KeV—20KeV，注入的倾斜角度范围为5度—60度。
可选地，还包括：根据场效应晶体管的阈值电压或开态电流的调节量，确定氟离子的注入剂量。
可选地，在栅极结构的两侧注入离子形成halo区。
可选地，在halo区注入氟离子。
可选地，氟离子的注入深度，大于浅掺杂区除氟离子外其它离子的注入深度。
可选地，退火处理的退火温度为1000℃-1200℃，持续时间为9s-12s。
可选地，退火处理包括尖峰退火。
本公开实施例可以/至少具有以下优点，通过在场效应晶体管浅掺杂区注入氟离子，实现了使用一道离子注入工艺，达到场效应晶体管电性能调节的目的。
根据一些实施例，本申请第二方面提供了一种场效应晶体管电性能参数调节方法，包括：在场效应晶体管浅掺杂区和/或halo区注入 氟离子；对场效应晶体管进行退火处理。
可选地，注入氟离子的工艺参数，包括：注入的剂量范围为1E14—1E16atom/cm2，注入的能量范围为5KeV—20KeV，注入的倾斜角度范围为5度—60度。
可选地，还包括：根据场效应晶体管的阈值电压或开态电流的调节量，确定氟离子的注入剂量。
可选地，退火处理包括尖峰退火。
本公开实施例可以/至少具有以下优点，低阈值电压型场效应晶体管和非低阈值电压型场效应晶体管在共用一道光罩进行电性能调节时，使用一道氟离子注入工艺，达到对低阈值电压型场效应晶体管电性能调节的目的，不影响非低阈值电压型场效应晶体管的电性能。
根据一些实施例，本申请第三方面提供了一种场效应晶体管结构，包括：半导体衬底、栅极结构和浅掺杂区；有源区位于半导体衬底中；栅极结构形成在半导体衬底表面；浅掺杂区采用离子注入工艺注入两种以上的离子形成在栅极结构的两侧；两种以上的离子包含氟离子。
可选地，还包括：halo区，halo区采用离子注入工艺形成在栅极结构的两侧。
可选地，氟离子的注入深度，大于浅掺杂区除氟离子外其它离子的注入深度。
附图说明
为了更清楚地说明本申请实施例或传统技术中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描 述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例一种场效应晶体管形成方法流程示意图；
图2至图5是本申请实施例一种场效应晶体管形成方法场效应晶体管形成过程示意图；
图6是本申请实施例一种场效应晶体管电性能参数调节方法流程示意图；
图7是本申请实施例一种场效应晶体管电性能参数调节方法场效应晶体管结构示意图；
图8(a)—图8(b)是本申请实施例低阈值电压型场效应晶体管电性能参数调节参数示意图；
图9(a)—图9(b)是本申请实施例非低阈值电压型场效应晶体管电性能参数调节参数示意图；
图10是本申请实施例一种场效应晶体管结构示意图；
图11是本申请实施例另一种场效应晶体管结构示意图。
附图标记：
10：低阈值电压型场效应晶体管；20：非低阈值电压型场效应晶体管；100：半导体衬底；200：栅极结构；210：栅电极层；220：栅氧化层；300：浅掺杂区其它离子分布；400：浅掺杂区氟离子分布；500：halo区注入的离子分布；600：源极；700：漏极。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚明了，下面结合具体实施方式并参照附图，对本申请进一步详细说明。应该理解，这些描述只是示例性的，而并非要限制本申请的范围。此外，在以下说明 中，省略了对公知结构和技术的描述，以避免不必要地混淆本申请的概念。
在附图中示出了根据本申请实施例的层结构示意图。这些图并非是按比例绘制的，其中为了清楚的目的，放大了某些细节，并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能由于制造公差或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。以下将参照附图更详细地描述本申请。在各个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的各个部分没有按比例绘制。
图1是本申请实施例一种场效应晶体管形成方法流程示意图。
如图1所示，本申请实施例提供的场效应晶体管形成方法主要包括4个步骤，以下对4个步骤进行详细说明。
步骤S1，提供半导体衬底并对半导体衬底进行离子注入，形成有源区。
以PMOS(P-Metal-Oxide-Semiconductor，P型金属-氧化物-半导体)为例，向半导体衬底100内部注入N型离子形成具有一定深度的有源区，例如注入砷离子。砷是五价元素，其它五价杂质元素还包括磷、锑等，在半导体衬底100内部掺入的五价杂质，它的四个价电子与其相邻的四个主原子的价电子形成共价键，第五个价电子不能形成共价键而变成自由电子。这种掺杂方式有盈余的自由电子，所以五 价杂质元素掺杂形成为N型半导体。离子注入法利用电场加速杂质离子，将其注入半导体衬底中。
在其他实施方式中，还可以是向半导体衬底内部注入P型离子形成有源区,例如注入硼离子。硼是三价杂质元素，它的三个价电子与其相邻的三个主原子的价电子形成共价键，会因缺少一个价电子而形成一个空位，掺杂为P型半导体。需要说明的是，半导体衬底100可采用但不限于硅、锗、锗硅等常用的半导体衬底材料，注入离子的类型根据实际需求选择。
步骤S2，在半导体衬底表面形成栅极结构。
图2示意性示出了半导体衬底表面形成栅极结构示意图，参考图2，在半导体衬底100表面形成栅极结构200，栅极结构200包括位于半导体衬底100表面的栅电极层210、位于栅电极层210表面的栅氧化层220。栅电极层210的材料为多晶硅、掺杂的多晶硅或者金属，栅氧化层220的材料为氧化硅或高介质材料。在其它实施例中，在栅极结构表面形成氧化硅层或氮化硅层，利用氧化硅层或氮化硅层可防止后续的离子注入工艺将杂质离子注入到栅氧化层或栅电极内，影响栅极结构的电学性能。
在一些实施例中，栅极结构200的由多晶硅曝光蚀刻形成。
步骤S3，注入离子形成浅掺杂区。具体地，在栅极结构的两侧注入两种以上离子形成浅掺杂区
图3示意性示出了浅掺杂区结构示意图；在图3基础上，图4示意性示出了浅掺杂区注入氟离子后结构示意图。参考图3和图4，在图中浅掺杂区注入的离子为两种以上。浅掺杂区其它离子分布300，以及浅掺杂区氟离子分布400。浅掺杂区其它离子分布300中包含至 少一种离子，示例性地，浅掺杂区其它离子分布300中采用硼离子或二氟化硼或二者的组合进行掺杂。因此，浅掺杂区注入的离子为两种以上。需要进行说明的是，对形成浅掺杂区其它离子分布300，以及浅掺杂区氟离子分布400的顺序没有限制，既可以先注入氟离子形成浅掺杂区氟离子分布400，也可以先注入浅掺杂区其它离子分布300中的离子形成浅掺杂区其它离子分布300。
需要进行说明的是，在浅掺杂区进行掺杂，可以缓解短沟道效应和热载流子效应。短沟道效应是指当MOSFET晶体管的沟道长度变短到可以与源漏的耗尽层宽度相比拟时，发生短沟道效应。MOSFET栅极下耗尽区电荷不再完全受栅极控制，其中有一部分受源、漏控制，产生耗尽区电荷共享，并且随着沟道长度的减小，受栅极控制的耗尽区电荷不断减少。当受栅极控制的耗尽区电荷不断减少，只需要较少的栅极电荷就可以达到反型，从而使场效应晶体管阈值电压降低。当载流子从外界获得了很大能量时，即可成为热载流子。例如在强电场作用下，载流子沿着电场方向不断漂移，不断加速，可获得很大的动能，从而可成为热载流子。热载流子效应是半导体领域导致器件和集成电路产生失效的重要原因。
在浅掺杂区注入氟离子，则可以改善场效应晶体管阈值电压及开态电流。例如，浅掺杂区其它离子分布300中包含硼离子，浅掺杂区氟离子分布400中的氟离子可以增强硼离子在半导体衬底中的扩散。此外，从原子结构而言，氟为7价，容易得电子，提供空穴，从而提高场效应晶体管开态电流。需要进行说明的是，采用离子注入工艺，需要先电离原子，使其带上电荷形成离子，例如B+离子可以由硼原子或者氟化硼电离而成。利用电场加速离子，在电场作用下离子打进半导体衬底内部。如果为中性原子，则无法利用电场加速实现离子注入工艺。
在一些实施例中，在浅掺杂区注入氟离子的工艺参数，包括：注入的剂量范围为1E14—1E16atom/cm 2，注入的能量范围为5KeV—20KeV，注入的倾斜角度范围为5度—60度。示例性地，氟离子注入的能量为15KeV，注入的倾斜角为21度。需要进行说明的是，氟离子注入的剂量决定了掺杂浓度，即注入的剂量大则掺杂浓度高，掺杂浓度高则半导体中多数载流子的浓度高。氟离子注入的能量和倾斜角度决定了掺杂分布的深度和形状。离子注入法可以精密地控制扩散法难以得到的低浓度掺杂分布，即实现注入的剂量的精确控制，示例性地，离子的注入量可以通过测量流过基片的电流大小来精确控制。
在一些实施例中，氟离子的注入深度，大于浅掺杂区除氟离子外其它离子的注入深度。相对于浅掺杂区注入的其它离子，氟离子打入较深的深度时，从而进一步提高场效应晶体管开态电流。示例性地，调节氟离子注入的能量和倾斜角度，从而使氟离子的注入深度大于浅掺杂区除氟离子外其它离子的注入深度。
在一些实施例中，根据场效应晶体管阈值电压或开态电流的调节量，确定氟离子的注入剂量。示例性地，增加氟离子的注入剂量，可以降低场效应晶体管的阈值电压、提高场效应晶体管的开态电流。例如，注入氟离子的剂量每增加1E15atom/cm 2，场效应晶体管的阈值电压降低50mV，场效应晶体管的开态电流升高26uA/um。因此，可以根据场效应晶体管阈值电压或开态电流的调节量，确定氟离子的注入剂量。
步骤S4，对半导体衬底进行退火处理。示例性地，在浅掺杂区离子注入完成后，需要退火处理，掺杂原子的注入所造成的半导体衬底损伤会被退火处理修复。需要进行说明的是，注入的氟离子不需要单独的退火处理，与浅掺杂区注入的离子一起退火处理即可。
需要进行说明的是，氟离子进入半导体衬底的过程是破坏性的，会使部分半导体衬底原子被电离，或者破坏了半导体衬底原子的价键。半导体衬底原子半径小，向维持稳定形态转变所越过的能垒小。通过加热时，半导体衬底原子将自动修复，即错误的价键排列将被修复，固定电荷会被外来的电子补充。经过恰当温度和时间的处理后，半导体衬底原子复原，就如中性的原子扩散进了半导体衬底原子中一样。热修复的过程就是退火处理，示意性地，浅掺杂区离子注入的硼离子和氟离子一起退火处理，以修复半导体衬底原子。
在一些实施例中，退火处理的退火温度为1000℃-1200℃，持续时间为9s-12s。
在一些实施例中，退火处理包括尖峰退火。需要进行说明的是，尖峰退火是浸入式退火的一种，在尖峰退火过程中,晶圆以极快的升温速率升高到设定的温度,升温速率最快可达近250℃/s，又以较快的降温速率将其冷却到600℃以下，降温速率最快可达近90℃/s。尖峰退火主要应用在0.13um以下的场效应管器件制造工艺中,位于轻掺杂漏和源漏极离子注入之后,在形成超浅结的同时,修复离子注入造成的晶格损伤和缺陷。示例性地，尖峰退火处理过程为：以220℃/s的升温速率升温到1020℃，维持10s，然后以90℃/s降温速率的降低到600℃以下。
在一些实施例中，参考图5，本申请实施例提供的场效应晶体管形成方法，在在栅极结构的两侧注入离子形成halo区。为了进一步缓解短沟道效应，以及抑制漏致势垒降低效应，通过注入与衬底相同类型的掺杂离子，在衬底100中形成halo区注入的离子分布500。
需要进行说明的是，halo区是衬底靠近源、漏处进行重掺杂衬底的掺杂区域。示例性地，如果衬底100为N型衬底，那么Halo区的 掺杂类型是N+，使PN结的耗尽区或空间电荷区变窄，防止源、漏处的耗尽区连通，造成源漏导通。Halo区的掺杂除了防止源漏导通，还能抑制漏致势垒降低效应。漏致势垒降低效应(Drain Induced Barrier Lowering Effect,DIBL)是超大规模MOSFET器件中重要的物理效应,体现在漏端电压引起阈值电压的降低,导致漏源电流增大。
示例性地，halo区注入的离子角度大于浅掺杂区离子注入的角度，以抑制场效应晶体管亚阈值电流退化。参考图5，halo区注入的离子分布500中离子注入的深度，大于浅掺杂区其它离子分布300和浅掺杂区氟离子分布400的离子注入的深度。需要进行说明的是，栅极结构200两侧halo区注入的离子，既可以是对称方式注入，也可以是非对称注入方式，对于注入方式没有限制。
在一些实施例中，在halo区注入氟离子。参考图4和图5，浅掺杂区其它离子分布300、浅掺杂区氟离子分布400、以及halo区注入的离子分布500，三者存在重合区域。示例性地，halo区注入的离子的倾斜角度为40至50度，氟离子注入的倾斜角度范围为5度—60度，氟离子的倾斜角度注入范围包含halo区注入的离子的倾斜角度范围，因此可以在halo区注入氟离子。
需要进行说明的是，对形成浅掺杂区其它离子分布300、浅掺杂区氟离子分布400、以及halo区注入的离子分布500的形成顺序没有限制。
此外，场效应晶体管形成过程还包括源极和漏极的形成，源极和漏极可以通过离子注入的方式形成。示例性地，如果衬底100为P型衬底，halo区注入的离子分布500的掺杂类型是P+，源极和漏极通过离子注入的方式形成N+类型的掺杂；同样如果衬底100为N型衬底，则源极和漏极的掺杂类型为P+；对于掺杂类型和掺杂的离子没有限制。
图6是本申请实施例一种场效应晶体管电性能参数调节方法流程示意图。
如图1所示，本申请实施例场效应晶体管电性能参数调节方法主要包括2个步骤，以下对2个步骤进行详细说明。
步骤S31，在浅掺杂区和/或halo区注入氟离子。
图7是本申请实施例一种场效应晶体管电性能参数调节方法场效应晶体管结构示意图。
参考图7，低阈值电压型场效应晶体管10，及非低阈值电压型场效应晶体管20，在同一道光罩下进行电性能参数的调节。如果浅掺杂区结合halo区离子注入的方式调节，两种器件的电性能会同时漂移。
图8(a)—图8(b)是本申请实施例低阈值电压型场效应晶体管电性能参数调节参数示意图，其中图8(a)为阈值电压参数调节示意图，图8(b)为开态电流参数调节示意图。参考图8(a)和图8(b)，图中none表示不掺杂氟离子的情况，F表示掺杂氟离子的情况。在图8(a)中，不掺杂氟离子时，场效应晶体管阈值电压Vt的值在0.29V左右；掺杂氟离子时，场效应晶体管阈值电压Vt的值在0.24V左右。在图8(b)中，不掺杂氟离子时，场效应晶体管开态电流IDS的值在272uA/um左右；掺杂氟离子时，场效应晶体管开态电流IDS的值在298uA/um左右。因此，在浅掺杂区和/或halo区注入氟离子，对低阈值电压型场效应晶体管10而言，相对于不注入氟离子的情况，可以显著降低阈值电压Vt，及提高开态电流IDS。
图9(a)—图9(b)是本申请实施例非低阈值电压型场效应晶体管电性能参数调节参数示意图，其中图9(a)为阈值电压参数调节示意图，图9(b)为开态电流参数调节示意图。参考图9(a)和图9(b)，图中none表示不掺杂氟离子的情况，F表示掺杂氟离子的情况。在图9(a)中，不掺杂氟离子及掺杂氟离子时，场效应晶体管阈 值电压Vt的值在0.55V左右。在图9(b)中，不掺杂氟离子及掺杂氟离子时，场效应晶体管开态电流IDS的值在510uA/um左右。因此，对非低阈值电压型场效应晶体管20而言，相对于不注入氟离子的情况，阈值电压Vt和开态电流IDS无明显变化。这样就达到了只用一道氟离子注入工艺，就可以调节低阈值电压型场效应晶体管10电性能参数，而对非低阈值电压型场效应晶体管20无影响的技术效果。
下表是低阈值电压型场效应晶体管10和非低阈值电压型场效应晶体管20，在有无氟离子注入的两种情况下，电性能参数的变化情况汇总表。
Figure PCTCN2021127880-appb-000001
由上表可知低阈值电压型场效应晶体管10，在经过浅掺杂区和/或halo区注入氟离子后，电性能参数明显改善。
需要进行说明的是，在浅掺杂区和/或halo区注入氟离子，可以先注入氟离子，之后在浅掺杂区和/或halo区注入其它离子。此外，也可以在浅掺杂区和/或halo区注入其它离子，形成浅掺杂区或者halo区，之后再注入氟离子。
在一些实施例中，在浅掺杂区注入氟离子的工艺参数，包括：注入的剂量范围为1E14—1E16atom/cm 2，注入的能量范围为5KeV—20KeV，注入的倾斜角度范围为5度—60度。示例性地，氟离子注入的能量为15KeV，注入的倾斜角为21度。
在一些实施例中，根据所述场效应晶体管阈值电压或开态电流的调节量，确定氟离子的注入剂量。示例性地，增加氟离子的注入剂量， 可以降低场效应晶体管的阈值电压、提高场效应晶体管的开态电流。例如，注入氟离子的剂量每增加1E15atom/cm 2，场效应晶体管的阈值电压降低50mV，场效应晶体管的开态电流升高26uA/um。
步骤S41，进行退火处理。需要进行说明的是，注入的氟离子不需要单独的退火处理，与浅掺杂区和/或halo区注入的离子一起退火即可。
在一些实施例中，退火处理包括尖峰退火。示例性地，尖峰退火处理过程为：以220℃/s的升温速率升温到1020℃，维持10s，然后以90℃/s降温速率的降低到600℃以下。
图10是本申请实施例一种场效应晶体管结构示意图。
如图10所示的场效应晶体管结构中，包括：半导体衬底100、栅极结构200和浅掺杂区；有源区位于半导体衬底100中；栅极结构200形成在半导体衬底表面；浅掺杂区采用离子注入工艺注入两种以上的离子形成在栅极结构的两侧；两种以上的离子包含氟离子。参考图10，浅掺杂区掺杂的离子分布，包括浅掺杂区其它离子分布300，以及浅掺杂区氟离子分布400。此外，场效应晶体管还包括源极600和漏极700，可选的，源极600和漏极700通过离子注入工艺形成。
示例性地，浅掺杂区其它离子分布300中掺杂地离子为硼离子，硼离子可以是氟化硼电离出来，电离后通过离子注入工艺注入到场效应晶体管结构中形成浅掺杂区其它离子分布300，同样氟离子也可以由氟的单质或化合物电离后注入形成浅掺杂区氟离子分布400。
在一些实施例中，氟离子的注入深度，大于浅掺杂区除氟离子外其它离子的注入深度，以利于进一步提高场效应晶体管开态电流。
图11是本申请实施例另一种场效应晶体管结构示意图。
与图10相比，图11中所示的场效应晶体管结构实施例，还包括：halo区，halo区采用离子注入工艺形成在栅极结构的两侧，halo区注入的离子分布500如图中所示，从而进一步缓解短沟道效应，以及抑制漏致势垒降低效应。
应当理解的是，本申请的上述具体实施方式仅仅用于示例性说明或解释本申请的原理，而不构成对本申请的限制。因此，在不偏离本申请的精神和范围的情况下所做的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。此外，本申请所附权利要求旨在涵盖落入所附权利要求范围和边界、或者这种范围和边界的等同形式内的全部变化和修改例。

Claims (15)

  1. 一种场效应晶体管形成方法，包括：
    提供半导体衬底并对所述半导体衬底进行离子注入，形成有源区；
    在所述半导体衬底表面形成栅极结构；
    在所述栅极结构的两侧注入两种以上离子形成浅掺杂区；
    所述的两种以上离子包含氟离子；
    对所述半导体衬底进行退火处理。
  2. 根据权利要求1所述的形成方法，其中，在所述浅掺杂区注入氟离子的工艺参数，包括：
    注入的剂量范围为1E14—1E16atom/cm 2，注入的能量范围为5KeV—20KeV，注入的倾斜角度范围为5度—60度。
  3. 根据权利要求1所述的形成方法，其中，还包括：
    根据所述场效应晶体管的阈值电压或开态电流的调节量，确定氟离子的注入剂量。
  4. 根据权利要求1所述的形成方法，其中，
    在所述栅极结构的两侧注入离子形成halo区。
  5. 根据权利要求4所述的形成方法，其中，
    在所述halo区注入氟离子。
  6. 根据权利要求1所述的形成方法，其中，
    所述氟离子的注入深度，大于所述浅掺杂区除氟离子外其它离子的注入深度。
  7. 根据权利要求1所述的形成方法，其中，所述的退火处理的退火 温度为1000℃-1200℃，持续时间为9s-12s。
  8. 根据权利要求1所述的形成方法，其中，所述的退火处理包括尖峰退火。
  9. 一种场效应晶体管电性能参数调节方法，包括：
    在所述场效应晶体管浅掺杂区和/或halo区注入氟离子；
    对所述场效应晶体管进行退火处理。
  10. 根据权利要求9所述的调节方法，其中，所述注入氟离子的工艺参数，包括：
    注入的剂量范围为1E14—1E16atom/cm 2，注入的能量范围为5KeV—20KeV，注入的倾斜角度范围为5度—60度。
  11. 根据权利要求9所述的调节方法，其中，还包括：
    根据所述场效应晶体管的阈值电压或开态电流的调节量，确定氟离子的注入剂量。
  12. 根据权利要求9所述的调节方法，其中，所述的退火处理包括尖峰退火。
  13. 一种场效应晶体管结构，包括：
    半导体衬底、栅极结构和浅掺杂区；
    有源区位于所述半导体衬底中；
    所述栅极结构形成在半导体衬底表面；
    所述浅掺杂区采用离子注入工艺注入两种以上的离子形成在栅极结构的两侧；
    所述两种以上的离子包含氟离子。
  14. 根据权利要求13所述的场效应晶体管结构，其中，还包括：
    halo区，所述halo区采用离子注入工艺形成在栅极结构的两侧。
  15. 根据权利要求13所述的场效应晶体管结构，其中，
    所述氟离子的注入深度，大于所述浅掺杂区除氟离子外其它离子的注入深度。
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1527368A (zh) * 2003-03-04 2004-09-08 松下电器产业株式会社 半导体装置及其制造方法
CN102386097A (zh) * 2010-09-01 2012-03-21 中芯国际集成电路制造(上海)有限公司 Mos晶体管及其制作方法
CN102738000A (zh) * 2011-04-12 2012-10-17 中芯国际集成电路制造(上海)有限公司 一种超浅结形成方法
CN102938375A (zh) * 2011-08-15 2013-02-20 中芯国际集成电路制造(上海)有限公司 一种场效应晶体管及形成方法
CN103187276A (zh) * 2011-12-27 2013-07-03 中芯国际集成电路制造(上海)有限公司 n型MOS场效应管及形成方法，半导体器件及形成方法
US20140021545A1 (en) * 2012-07-17 2014-01-23 Texas Instruments Incorporated Pocket counterdoping for gate-edge diode leakage reduction

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1527368A (zh) * 2003-03-04 2004-09-08 松下电器产业株式会社 半导体装置及其制造方法
CN102386097A (zh) * 2010-09-01 2012-03-21 中芯国际集成电路制造(上海)有限公司 Mos晶体管及其制作方法
CN102738000A (zh) * 2011-04-12 2012-10-17 中芯国际集成电路制造(上海)有限公司 一种超浅结形成方法
CN102938375A (zh) * 2011-08-15 2013-02-20 中芯国际集成电路制造(上海)有限公司 一种场效应晶体管及形成方法
CN103187276A (zh) * 2011-12-27 2013-07-03 中芯国际集成电路制造(上海)有限公司 n型MOS场效应管及形成方法，半导体器件及形成方法
US20140021545A1 (en) * 2012-07-17 2014-01-23 Texas Instruments Incorporated Pocket counterdoping for gate-edge diode leakage reduction

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