WO2022017486A1 - Résonateur réglable et son procédé de fabrication - Google Patents

Résonateur réglable et son procédé de fabrication Download PDF

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Publication number
WO2022017486A1
WO2022017486A1 PCT/CN2021/108055 CN2021108055W WO2022017486A1 WO 2022017486 A1 WO2022017486 A1 WO 2022017486A1 CN 2021108055 W CN2021108055 W CN 2021108055W WO 2022017486 A1 WO2022017486 A1 WO 2022017486A1
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WIPO (PCT)
Prior art keywords
upper electrode
layer
lower electrode
resonant cavity
electrode
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PCT/CN2021/108055
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English (en)
Chinese (zh)
Inventor
吴明
唐兆云
赖志国
杨清华
王家友
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苏州汉天下电子有限公司
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Publication of WO2022017486A1 publication Critical patent/WO2022017486A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/30—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator
    • H03B5/32—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/15—Constructional features of resonators consisting of piezoelectric or electrostrictive material
    • H03H9/17—Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator

Definitions

  • the present invention relates to an adjustable resonator and its manufacturing method, in particular to an adjustable adjustable resonator and its manufacturing method.
  • RF filters are used as an intermediary to filter specific frequency signals to reduce signal interference in different frequency bands, and to implement functions such as image cancellation, spurious filtering, and channel selection in wireless transceivers.
  • the design of RF front-end is developing towards miniaturization, low power consumption and integration, and the market has higher and higher requirements for filtering performance. Due to the small size, high operating frequency, low power consumption, high quality factor (Q value), direct With the characteristics of output frequency signal and compatibility with CMOS process, it has become an important device in the field of radio frequency communication and is widely used.
  • FBAR is a thin film device with an electrode-piezoelectric film-electrode sandwich structure fabricated on a substrate material.
  • the structure of FBAR has cavity type, Bragg reflection type (SMR) and backside etching type.
  • SMR Bragg reflection type
  • the cavity type FBAR has higher Q value, lower loss and higher electromechanical coupling coefficient; compared with the backside etching type FBAR, it does not need to remove a large area of the substrate and has higher mechanical strength. Therefore, cavity-type FBAR is the first choice for integration on CMOS devices.
  • the resonant frequency of the device is determined accordingly.
  • a large number of resonant cavities of different sizes must be fabricated on the same substrate, which unnecessarily increases the size of the system, and in some cases The resonator works while most of the other resonators are idle, resulting in low system utilization.
  • the purpose of the present invention is to provide a tunable resonator and a preparation method thereof that overcome the above technical obstacles.
  • the present invention provides a tunable resonator, comprising:
  • the resonant cavity, in the substrate at least includes a first resonant cavity in the center and a second resonant cavity in the periphery;
  • the first stack structure on the first resonant cavity, sequentially includes a first part of the lower electrode, a first part of the piezoelectric layer and a first part of the upper electrode;
  • the second stack structure on the second resonant cavity, sequentially includes a second part of the lower electrode, a second part of the piezoelectric layer and a second part of the upper electrode;
  • a first insulating layer, on the substrate, is located between the first portion of the lower electrode and the second portion of the lower electrode.
  • the first resonant cavity, the first part of the lower electrode and the first part of the upper electrode are polygonal, circular or elliptical in plan view; preferably, the size of the top of the first resonant cavity is larger than that of the first part of the lower electrode or the first part of the upper electrode , optionally, the size of the top of the second resonant cavity is larger than the size of the second part of the lower electrode or the second part of the upper electrode;
  • the two parts are edge-aligned.
  • the resonance state including at least one of amplitude, frequency, phase or a combination thereof.
  • the substrate material is Si, SOI, Ge, GeOI, compound semiconductor; optionally, the materials of the first part of the piezoelectric layer and the second part of the piezoelectric layer are ZnO, AlN, BST (barium strontium titanate), BT ( barium titanate), PZT (lead zirconate titanate), PBLN (lead barium lithium niobate), PT (lead titanate), and further preferably the piezoelectric material is doped with rare earth elements; optionally, the first or second The material of the insulating layer is nitride, such as silicon nitride, silicon oxynitride, aluminum nitride, boron nitride; optionally, the first part of the lower electrode, the second part of the lower electrode, the first part of the upper electrode, the second part of the upper electrode Any one of the materials is selected from Mo, W, Ru, Al, Cu, Ti, Ta, In, Zn, Zr, Fe, M
  • the present invention also provides a method for manufacturing a tunable resonator, comprising:
  • a sacrificial layer in the substrate including a first sacrificial layer pattern in the center and a second sacrificial layer pattern in the periphery;
  • a lower electrode layer is formed on the sacrificial layer, comprising a first portion of the lower electrode on the first sacrificial layer pattern and a second portion of the lower electrode on the second sacrificial layer pattern;
  • a piezoelectric layer on the first insulating layer and the lower electrode layer, including at least a first part of the piezoelectric layer above the first sacrificial layer pattern and a second part of the piezoelectric layer above the second sacrificial layer pattern;
  • an upper electrode layer on the piezoelectric layer including a first part of the upper electrode on the first part of the piezoelectric layer, and a second part of the upper electrode on the second part of the piezoelectric layer;
  • the sacrificial layer is removed, leaving a cavity in the substrate, including a first cavity in the center and a second cavity in the periphery.
  • the upper electrode layer After forming the upper electrode layer, it further includes, at least forming a second insulating layer between the first part of the upper electrode and the second part of the upper electrode; preferably, the first part of the piezoelectric layer and the second part of the piezoelectric layer are connected, or by the second insulating layer The layers are spaced apart.
  • the first resonant cavity, the first part of the lower electrode and the first part of the upper electrode are polygonal, circular or elliptical in plan view; preferably, the size of the top of the first resonant cavity is larger than that of the first part of the lower electrode or the first part of the upper electrode , optionally, the size of the top of the second resonant cavity is larger than the size of the second part of the lower electrode or the second part of the upper electrode;
  • the two parts are edge-aligned.
  • the substrate material is Si, SOI, Ge, GeOI, compound semiconductor; optionally, the materials of the first part of the piezoelectric layer and the second part of the piezoelectric layer are ZnO, AlN, BST (barium strontium titanate), BT ( barium titanate), PZT (lead zirconate titanate), PBLN (lead barium lithium niobate), PT (lead titanate), and further preferably the piezoelectric material is doped with rare earth elements; optionally, the first or second The material of the insulating layer is nitride, such as silicon nitride, silicon oxynitride, aluminum nitride, boron nitride; optionally, the first part of the lower electrode, the second part of the lower electrode, the first part of the upper electrode, the second part of the upper electrode Any one of the materials is selected from Mo, W, Ru, Al, Cu, Ti, Ta, In, Zn, Zr, Fe, M
  • the auxiliary resonator is added around the main resonator to actively adjust the resonance state, which is beneficial to improve the integration degree and efficiency of the device.
  • FIG. 1 shows a cross-sectional view of a resonator fabrication process according to an embodiment of the present invention
  • FIG. 2 shows a cross-sectional view of a resonator fabrication process according to an embodiment of the present invention
  • FIG. 3 shows a cross-sectional view of a resonator fabrication process according to an embodiment of the present invention
  • FIG. 4 shows a cross-sectional view of a resonator fabrication process according to an embodiment of the present invention
  • FIG. 5 shows a cross-sectional view of a resonator fabrication process according to an embodiment of the present invention
  • FIG. 6 shows a cross-sectional view of a resonator fabrication process according to an embodiment of the present invention
  • FIG. 7 shows a cross-sectional view of a resonator fabrication process according to an embodiment of the present invention
  • FIG. 8 shows a cross-sectional view of a resonator fabrication process according to an embodiment of the present invention
  • FIG. 9 shows a cross-sectional view of a resonator fabrication process according to an embodiment of the present invention.
  • Figure 10 shows a plan view of a resonator top electrode according to an embodiment of the present invention.
  • a sacrificial layer 2 is formed in the substrate 1 .
  • the material can be bulk Si or silicon-on-insulator (SOI) or bulk Ge, GeOI to be compatible with CMOS process and integrated with other digital and analog circuits, and can also be a compound for MEMS, optoelectronic devices, power devices Semiconductors such as GaN, GaAs, SiC, InP, GaP, etc., further preferably, the substrate 1 is a single crystal material.
  • the substrate 1 is etched to form a plurality of cavities (not shown in FIG. 1 ), and a sacrificial layer 2 is deposited to fill it.
  • the etching process is preferably anisotropic dry etching or wet etching, such as reactive ion etching with a fluorocarbon-based etching gas, or wet etching with TMAH.
  • the deposition process is a low temperature process such as LPCVD, APCVD, PECVD (deposition temperature is lower than 500 degrees Celsius, preferably 100 to 400 degrees Celsius), and the sacrificial layer 2 is made of silicon oxide-based materials, such as boron-doped silicon oxide (BSG), phosphorus-doped silicon oxide ( PSG), undoped silicon oxide (USG), porous silicon oxide, etc., so that the residual thermal stress in the substrate 1 can be reduced, and it is beneficial to improve the speed of subsequent etching and removal to save time and cost.
  • BSG boron-doped silicon oxide
  • PSG phosphorus-doped silicon oxide
  • USG undoped silicon oxide
  • porous silicon oxide etc.
  • the sacrificial layer 2 includes at least two parts, that is, the first part 2 a is used to fill the main resonant cavity, and the second part 2 b is used to fill the secondary resonant cavity around the main resonant cavity.
  • the sacrificial layer 2 is processed by a CMP planarization process until the surface of the substrate 1 is exposed.
  • the central part of the cavity formed by etching the substrate 1, that is, the projection of the main resonant cavity in a plan view is a polygon (such as a quadrilateral, pentagon, hexagon, octagon, etc.
  • the 1S is used as a subsequent mechanical support or isolation structure, and the first part 2a and the second part 2b of the filled sacrificial layer also have corresponding morphologies.
  • a patterned lower electrode 3 is formed on the substrate 1 .
  • a conductive material layer is formed, such as Mo, W, Ru, Al, Cu, Ti, Ta, In, Zn, Zr, Fe, Mg and other metal elements or metal alloys , or conductive oxides of these metals, conductive nitrides, and any combination of the above materials.
  • a seed layer (not shown) is further formed on the substrate 1 and the sacrificial layer 2 to improve the crystal orientation of the electrode layer and the upper functional layer.
  • the seed layer is AlN, HfN, HfAlN, TiN, TaN, etc., and preferably can be used as a barrier layer preventing the downward migration of the lower electrode metal material to avoid affecting the top of the resonant cavity and the bottom The interface state between the film layers.
  • a photolithography-etching process is used, such as spin coating photoresist, exposure and development to form a photoresist pattern, and the photoresist pattern is used as a mask to etch the conductive material layer to pattern the conductive material layer, and form Figure 2 Lower electrode 3 shown.
  • the lower electrode 3 includes at least a first portion 3a at the center, and a second portion 3b at the periphery.
  • the first part 3a of the lower electrode is the same as the first part 2a of the sacrificial layer and the main resonant cavity.
  • the projection in the plan view is a polygon (such as a quadrilateral, a pentagon, a hexagon, an octagon, etc.), a circle, an ellipse, etc.
  • the second portion 3b is an annular structure concentric with the first portion 3a with a gap therebetween. It is worth noting that, in order to ensure sufficient insulation isolation between the main resonator and the lower electrode of the adjustment sub-resonator, the distance between the second peripheral part 3b and the central first part 3a should be at least greater than that of the main and auxiliary resonators.
  • the edge of the first portion 3a of the lower electrode is indented inwardly from the edge of the first portion 2a of the sacrificial layer by 0.1-10 microns, preferably 0.05-5 microns, optimally 1-3 microns. Further or similarly, the edge of the second portion 3b of the lower electrode is also retracted inward by the same distance from the edge of the second portion 2b of the sacrificial layer.
  • an insulating layer 4 is filled between the lower electrode patterns.
  • the insulating dielectric material is filled between the first part 3a and the second part 3b of the lower electrode layer to form an annular insulating layer pattern 4 .
  • the material of the insulating layer 4 is different from that of the sacrificial layer 2, so as to avoid excessive erosion during the subsequent process of removing the sacrificial layer 2 to form a resonant cavity.
  • the material of the insulating layer 4 is nitride, such as silicon nitride, silicon oxynitride, aluminum nitride, boron nitride, and the like.
  • the insulating layer is processed by a planarization process of etchback or CMP until the lower electrode patterns 3a and 3b are exposed.
  • the piezoelectric layer 5 is formed on the lower electrode patterns 3 a and 3 b and the insulating layer 4 .
  • a process such as PECVD, UHVCVD, HDPCVD, MOCVD, MBE, ALD, magnetron sputtering, thermal evaporation, etc. is used to form the piezoelectric layer 5 , preferably the material of which is different from the insulating layer 4 .
  • the piezoelectric layer 5 is made of materials such as ZnO, AlN, BST (barium strontium titanate), BT (barium titanate), PZT (lead zirconate titanate), PBLN (lead barium lithium niobate) ), PT (lead titanate) and other piezoelectric ceramic materials, and preferably, the piezoelectric layer 5 is doped with rare earth elements, such as scandium (Sc), yttrium (Y), lanthanum (La), cerium (Ce), Praseodymium (Pr), Neodymium (Nd), Promethium (Pm), Samarium (Sm), Europium (Eu), Gadolinium (Gd), Terbium (Tb), Dysprosium (Dy), Holmium (Ho), Erbium (Er), Any one of thulium (Tm), ytterbium (Yb), and lutetium (Lu) and
  • rare earth elements such as scandium
  • the piezoelectric layer 5 is doped with Sc, or mixed with Sc and Yb, or doped with Sc and Gd, or mixed with Sc, Yb, and Sm.
  • the upper conductive material layer 6 is formed on the piezoelectric layer 5 .
  • the preparation process and materials of the conductive material layer 6 are the same as those of the lower electrode layer 3 , and details are not repeated here.
  • the conductive material layer 6 is patterned to form an upper electrode first portion 6a and an upper electrode second portion 6b.
  • the photoresist is spin-coated, a photoresist pattern is formed through an exposure and development process, and the conductive material layer 6 is etched with the photoresist pattern as a mask to form a first portion 6a of an upper electrode located in the center, and a second annular upper electrode located in the periphery. Section 6b.
  • the edge of the first portion 6a of the upper electrode is aligned with the edge of the first portion 3a of the lower electrode, and the edge of the second portion 6b of the upper electrode is aligned with the edge of the second portion 3b of the lower electrode, so that there is a gap between the first portion 6a and the second portion 6b.
  • the photoresist pattern is preferably removed by a wet etching process.
  • a second insulating layer 7 is formed on the piezoelectric layer 5 and the upper electrode patterns 6a/6b.
  • the material and process of the second insulating layer 7 are the same as or similar to those of the insulating layer 4 , and details are not repeated here.
  • the sacrificial layer pattern 2 is removed, leaving a resonant cavity in the substrate 1 .
  • a wet etchant is applied to remove the sacrificial layer pattern through release holes (not shown) provided at the periphery of the device.
  • an HF-based etching solution such as dHF (diluted HF), dBOE (slow release etchant, a mixture of HF and NH 4 F) to remove the sacrificial layer pattern 2, leaving multiple resonant cavities with at least It comprises a first portion 1c in the center, and a second portion 1c' in an annular shape in the periphery.
  • the width of the insulating layer 4 is larger than the width of the top of the support structure 1S, and the width of the first part 3a and the second part 3b of the lower electrode is smaller than that of the sacrificial layer patterns 2a and 2b, so the width of the main resonant cavity 1c left is larger than that of the first part 3a and the second part 3b of the lower electrode.
  • the width of the sub-resonant cavity 1c' is larger than that of the second portion 3b of the lower electrode.
  • the second insulating layer 7 is processed by a planarization process such as etchback, CMP, etc., until the upper electrode patterns 6a and 6b are exposed.
  • the finally formed resonator structure is shown in FIG. 8 and includes a substrate 1, a first part 1c of the resonator cavity, a second part 1c' of the resonator cavity located in the substrate 1, a first part 3a of the lower electrode above the first part 1c of the resonator cavity,
  • the piezoelectric layer 5 and the first part 6a of the upper electrode constitute the main resonator, and the second part 3b of the lower electrode, the piezoelectric layer 5, and the second part 6b of the upper electrode above the second part 1c' of the resonant cavity constitute the sub-resonator.
  • the distribution morphology of the upper electrodes 6a/6b and the second insulating layer 7 is shown in FIG. 10, which is the same as or conformal or similar to the lower electrodes 3a/3b and the insulating layer pattern 4, and both are concentric polygons or circles, ellipses
  • the second insulating layer 7 is sandwiched between the central part of the upper electrode, that is, the first part 6a and the peripheral second part 6b, and the second part 6b has at least one gap to accommodate the lead-out part of the first part 6a. Pass through the second insulating layer 7 under wrapping to realize external electrical connection.
  • the device by applying a signal different from that of the main resonator to the electrodes (3b, 6b) of the sub-resonator, for example, at least one of amplitude, frequency, and phase is different, so that the sub-resonator around the main resonator generates a different signal from the main resonator.
  • a signal different from that of the main resonator to the electrodes (3b, 6b) of the sub-resonator for example, at least one of amplitude, frequency, and phase is different, so that the sub-resonator around the main resonator generates a different signal from the main resonator.
  • the different vibrations of the resonator and the superposition of two mechanical waves with different states change the final signal waveform.
  • the vibration state of the sub-resonator can be flexibly changed in real time by controlling the input waveform of the sub-resonator, thereby affecting the working state of the entire resonator, so as to adjust the frequency response of the entire resonator system when needed, which is conducive to saving Chip area, improve integration, reduce product cost, and improve device utilization.
  • the piezoelectric layers 5 are no longer connected as a whole, but the second insulating layer 7 penetrates through the support structure 1S directly on the surface of the substrate 1, thereby The insulation isolation effect between the electrodes of the main resonator and the sub-resonator is improved, and the lateral crosstalk of signals between the upper and lower electrodes of different resonators is prevented.
  • the manufacturing process is basically the same as that shown in FIG. 1 to FIG. 8, except that in the process steps shown in FIG. 5, after etching and patterning the upper electrodes 6a and 6b, the photoresist pattern or the upper electrode pattern is used as a mask.
  • the mold continue to etch the piezoelectric layer 5 until the support structure 1S on the surface of the substrate 1 is exposed, and in the process steps shown in FIG. insulating layer 7.
  • the resulting device structure is similar to that shown in FIG. 8, the difference is that the second insulating layer 7 is not only sandwiched between the first part 6a and the second part 6b of the upper electrode, but also penetrates the piezoelectric layer 5 to the surface of the substrate, and is sandwiched therebetween. between the first part 3a and the second part 3b of the lower electrode.
  • the auxiliary resonator is added around the main resonator to actively adjust the resonance state, which is beneficial to improve the integration degree and efficiency of the device.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Acoustics & Sound (AREA)
  • Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)

Abstract

La présente invention concerne un résonateur réglable et son procédé de fabrication. Le résonateur comprend : des cavités résonantes dans un substrat, les cavités résonantes comprenant au moins une première cavité résonante centrale et une deuxième cavité résonante périphérique ; une première structure empilée agencée sur la première cavité résonante, et comprenant séquentiellement une première partie d'une électrode inférieure, une première partie d'une couche piézoélectrique, et une première partie d'une électrode supérieure ; une deuxième structure empilée agencée sur la deuxième cavité résonante, et comprenant séquentiellement une deuxième partie de l'électrode inférieure, une deuxième partie de la couche piézoélectrique, et une deuxième partie de l'électrode supérieure ; et une première couche isolante disposée sur le substrat et située entre la première partie de l'électrode inférieure et la deuxième partie de l'électrode inférieure. Selon le résonateur réglable et son procédé de fabrication, un résonateur secondaire supplémentaire est disposé à la périphérie d'un résonateur primaire pour ajuster activement un état résonant, ce qui facilite l'augmentation d'un niveau d'intégration et d'efficacité d'un dispositif.
PCT/CN2021/108055 2020-07-24 2021-07-23 Résonateur réglable et son procédé de fabrication WO2022017486A1 (fr)

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CN202010728289.4A CN111786636A (zh) 2020-07-24 2020-07-24 可调式谐振器及其制造方法

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024078171A1 (fr) * 2022-10-14 2024-04-18 浙江大学 Transducteur ultrasonore micro-usiné piézoélectrique multifréquence et procédé de fabrication

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111786636A (zh) * 2020-07-24 2020-10-16 苏州汉天下电子有限公司 可调式谐振器及其制造方法
CN115178314A (zh) * 2022-08-08 2022-10-14 深圳市麦科思技术有限公司 一种微机电系统微流体装置及其制作方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4529904A (en) * 1983-03-16 1985-07-16 International Standard Electric Corporation Piezo-electric terminal station for communications system
US4870313A (en) * 1985-04-11 1989-09-26 Toyo Communication Equipment Co., Ltd. Piezoelectric resonators for overtone oscillations
US20030001689A1 (en) * 2001-07-02 2003-01-02 Murata Manufacturing Co., Ltd Piezoelectric resonator, manufacturing method for the same, piezoelectric filter, manufacturing method for the same, duplexer, and electronic communication device
CN101069344A (zh) * 2004-12-07 2007-11-07 松下电器产业株式会社 薄膜弹性波谐振器
US7408429B2 (en) * 2005-06-17 2008-08-05 Matsushita Electric Industrial Co., Ltd. Coupled FBAR filter
CN105339297A (zh) * 2013-06-27 2016-02-17 索泰克公司 用于制造包括填充有牺牲材料的腔体的半导体结构的方法
CN111786636A (zh) * 2020-07-24 2020-10-16 苏州汉天下电子有限公司 可调式谐振器及其制造方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4529904A (en) * 1983-03-16 1985-07-16 International Standard Electric Corporation Piezo-electric terminal station for communications system
US4870313A (en) * 1985-04-11 1989-09-26 Toyo Communication Equipment Co., Ltd. Piezoelectric resonators for overtone oscillations
US20030001689A1 (en) * 2001-07-02 2003-01-02 Murata Manufacturing Co., Ltd Piezoelectric resonator, manufacturing method for the same, piezoelectric filter, manufacturing method for the same, duplexer, and electronic communication device
CN101069344A (zh) * 2004-12-07 2007-11-07 松下电器产业株式会社 薄膜弹性波谐振器
US7408429B2 (en) * 2005-06-17 2008-08-05 Matsushita Electric Industrial Co., Ltd. Coupled FBAR filter
CN105339297A (zh) * 2013-06-27 2016-02-17 索泰克公司 用于制造包括填充有牺牲材料的腔体的半导体结构的方法
CN111786636A (zh) * 2020-07-24 2020-10-16 苏州汉天下电子有限公司 可调式谐振器及其制造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024078171A1 (fr) * 2022-10-14 2024-04-18 浙江大学 Transducteur ultrasonore micro-usiné piézoélectrique multifréquence et procédé de fabrication

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