WO2022017486A1

WO2022017486A1 - Adjustable resonator and manufacturing method therefor

Info

Publication number: WO2022017486A1
Application number: PCT/CN2021/108055
Authority: WO
Inventors: 吴明; 唐兆云; 赖志国; 杨清华; 王家友
Original assignee: 苏州汉天下电子有限公司
Priority date: 2020-07-24
Filing date: 2021-07-23
Publication date: 2022-01-27
Also published as: CN111786636A

Abstract

An adjustable resonator and a manufacturing method therefor. The resonator comprises: resonant cavities in a substrate, the resonant cavities at least including a central first resonant cavity and a peripheral second resonant cavity; a first stacked structure arranged on the first resonant cavity, and sequentially comprising a first portion of a lower electrode, a first portion of a piezoelectric layer, and a first portion of an upper electrode; a second stacked structure arranged on the second resonant cavity, and sequentially comprising a second portion of the lower electrode, a second portion of the piezoelectric layer, and a second portion of the upper electrode; and a first insulating layer disposed on the substrate and located between the first portion of the lower electrode and the second portion of the lower electrode. According to the adjustable resonator and the manufacturing method therefor of the present invention, an additional secondary resonator is arranged at the periphery of a primary resonator to actively adjust a resonant state, thereby facilitating increasing a level of integration and efficiency of a device.

Description

Tunable resonator and method of making the same

technical field

The present invention relates to an adjustable resonator and its manufacturing method, in particular to an adjustable adjustable resonator and its manufacturing method.

Background technique

In wireless communications, RF filters are used as an intermediary to filter specific frequency signals to reduce signal interference in different frequency bands, and to implement functions such as image cancellation, spurious filtering, and channel selection in wireless transceivers. With the deployment of 4GLTE network and the growth of the market, the design of RF front-end is developing towards miniaturization, low power consumption and integration, and the market has higher and higher requirements for filtering performance. Due to the small size, high operating frequency, low power consumption, high quality factor (Q value), direct With the characteristics of output frequency signal and compatibility with CMOS process, it has become an important device in the field of radio frequency communication and is widely used.

FBAR is a thin film device with an electrode-piezoelectric film-electrode sandwich structure fabricated on a substrate material. The structure of FBAR has cavity type, Bragg reflection type (SMR) and backside etching type. Compared with the SMR type, the cavity type FBAR has higher Q value, lower loss and higher electromechanical coupling coefficient; compared with the backside etching type FBAR, it does not need to remove a large area of the substrate and has higher mechanical strength. Therefore, cavity-type FBAR is the first choice for integration on CMOS devices.

Traditionally, after the resonant cavity is fabricated in the substrate, the resonant frequency of the device is determined accordingly. When it needs to be applied to different frequencies or a wide range of frequency bands, in order to improve the filtering accuracy, a large number of resonant cavities of different sizes must be fabricated on the same substrate, which unnecessarily increases the size of the system, and in some cases The resonator works while most of the other resonators are idle, resulting in low system utilization.

SUMMARY OF THE INVENTION

Therefore, the purpose of the present invention is to provide a tunable resonator and a preparation method thereof that overcome the above technical obstacles.

The present invention provides a tunable resonator, comprising:

The resonant cavity, in the substrate, at least includes a first resonant cavity in the center and a second resonant cavity in the periphery;

The first stack structure, on the first resonant cavity, sequentially includes a first part of the lower electrode, a first part of the piezoelectric layer and a first part of the upper electrode;

The second stack structure, on the second resonant cavity, sequentially includes a second part of the lower electrode, a second part of the piezoelectric layer and a second part of the upper electrode;

A first insulating layer, on the substrate, is located between the first portion of the lower electrode and the second portion of the lower electrode.

It further comprises a second insulating layer, on the first part of the piezoelectric layer and the second part of the piezoelectric layer, between the first part of the upper electrode and the second part of the upper electrode; preferably, the first part of the piezoelectric layer and the second part of the piezoelectric layer Partially connected, or separated by a second insulating layer.

Wherein, the first resonant cavity, the first part of the lower electrode and the first part of the upper electrode are polygonal, circular or elliptical in plan view; preferably, the size of the top of the first resonant cavity is larger than that of the first part of the lower electrode or the first part of the upper electrode , optionally, the size of the top of the second resonant cavity is larger than the size of the second part of the lower electrode or the second part of the upper electrode; The two parts are edge-aligned.

Wherein, applying a different signal to the second stack structure than the first stack structure to adjust the resonance state of the resonator, the resonance state including at least one of amplitude, frequency, phase or a combination thereof.

Wherein, the substrate material is Si, SOI, Ge, GeOI, compound semiconductor; optionally, the materials of the first part of the piezoelectric layer and the second part of the piezoelectric layer are ZnO, AlN, BST (barium strontium titanate), BT ( barium titanate), PZT (lead zirconate titanate), PBLN (lead barium lithium niobate), PT (lead titanate), and further preferably the piezoelectric material is doped with rare earth elements; optionally, the first or second The material of the insulating layer is nitride, such as silicon nitride, silicon oxynitride, aluminum nitride, boron nitride; optionally, the first part of the lower electrode, the second part of the lower electrode, the first part of the upper electrode, the second part of the upper electrode Any one of the materials is selected from Mo, W, Ru, Al, Cu, Ti, Ta, In, Zn, Zr, Fe, Mg metal element or metal alloy, or conductive oxides or conductive nitrides of these metals , and any combination of the above materials.

The present invention also provides a method for manufacturing a tunable resonator, comprising:

forming a sacrificial layer in the substrate, including a first sacrificial layer pattern in the center and a second sacrificial layer pattern in the periphery;

A lower electrode layer is formed on the sacrificial layer, comprising a first portion of the lower electrode on the first sacrificial layer pattern and a second portion of the lower electrode on the second sacrificial layer pattern;

forming a first insulating layer between the first part of the lower electrode and the second part of the lower electrode;

forming a piezoelectric layer on the first insulating layer and the lower electrode layer, including at least a first part of the piezoelectric layer above the first sacrificial layer pattern and a second part of the piezoelectric layer above the second sacrificial layer pattern;

forming an upper electrode layer on the piezoelectric layer, including a first part of the upper electrode on the first part of the piezoelectric layer, and a second part of the upper electrode on the second part of the piezoelectric layer;

The sacrificial layer is removed, leaving a cavity in the substrate, including a first cavity in the center and a second cavity in the periphery.

After forming the upper electrode layer, it further includes, at least forming a second insulating layer between the first part of the upper electrode and the second part of the upper electrode; preferably, the first part of the piezoelectric layer and the second part of the piezoelectric layer are connected, or by the second insulating layer The layers are spaced apart.

Wherein, the substrate material is Si, SOI, Ge, GeOI, compound semiconductor; optionally, the materials of the first part of the piezoelectric layer and the second part of the piezoelectric layer are ZnO, AlN, BST (barium strontium titanate), BT ( barium titanate), PZT (lead zirconate titanate), PBLN (lead barium lithium niobate), PT (lead titanate), and further preferably the piezoelectric material is doped with rare earth elements; optionally, the first or second The material of the insulating layer is nitride, such as silicon nitride, silicon oxynitride, aluminum nitride, boron nitride; optionally, the first part of the lower electrode, the second part of the lower electrode, the first part of the upper electrode, the second part of the upper electrode Any one of the materials is selected from Mo, W, Ru, Al, Cu, Ti, Ta, In, Zn, Zr, Fe, Mg metal element or metal alloy, or conductive oxides or conductive nitrides of these metals , and any combination of the above materials; optionally, the sacrificial layer material is an oxide, such as boron-doped silicon oxide (BSG), phosphorus-doped silicon oxide (PSG), undoped silicon oxide (USG), porous silicon oxide.

After forming the upper electrode layer and before removing the sacrificial layer, further comprising, etching the piezoelectric layer between the first part of the upper electrode and the second part of the upper electrode to form an opening exposing the substrate, on the upper electrode layer and the bottom and sidewalls of the opening A second insulating layer is formed thereon.

According to the tunable resonator and the manufacturing method thereof of the present invention, the auxiliary resonator is added around the main resonator to actively adjust the resonance state, which is beneficial to improve the integration degree and efficiency of the device.

The stated objects of the invention, as well as other objects not listed here, are met within the scope of the independent claims of the present application. Embodiments of the invention are defined in the independent claims and specific features are defined in the dependent claims.

Description of drawings

The technical solutions of the present invention are described in detail below with reference to the accompanying drawings, wherein:

1 shows a cross-sectional view of a resonator fabrication process according to an embodiment of the present invention;

2 shows a cross-sectional view of a resonator fabrication process according to an embodiment of the present invention;

3 shows a cross-sectional view of a resonator fabrication process according to an embodiment of the present invention;

4 shows a cross-sectional view of a resonator fabrication process according to an embodiment of the present invention;

5 shows a cross-sectional view of a resonator fabrication process according to an embodiment of the present invention;

6 shows a cross-sectional view of a resonator fabrication process according to an embodiment of the present invention;

7 shows a cross-sectional view of a resonator fabrication process according to an embodiment of the present invention;

8 shows a cross-sectional view of a resonator fabrication process according to an embodiment of the present invention;

FIG. 9 shows a cross-sectional view of a resonator fabrication process according to an embodiment of the present invention; and

Figure 10 shows a plan view of a resonator top electrode according to an embodiment of the present invention.

detailed description

The features and technical effects of the technical solutions of the present invention are described in detail below with reference to the accompanying drawings and in conjunction with the schematic embodiments, and a resonator and a manufacturing method thereof are disclosed which are beneficial to improve the integration degree and efficiency of the device. It should be noted that similar reference numerals denote similar structures, and the terms "first", "second", "upper", "lower", etc. used in this application may be used to modify various device structures. These modifications do not imply a spatial, sequential, or hierarchical relationship of the modified device structures unless specifically stated.

As shown in FIG. 1 , a sacrificial layer 2 is formed in the substrate 1 . Provide a substrate 1, the material can be bulk Si or silicon-on-insulator (SOI) or bulk Ge, GeOI to be compatible with CMOS process and integrated with other digital and analog circuits, and can also be a compound for MEMS, optoelectronic devices, power devices Semiconductors such as GaN, GaAs, SiC, InP, GaP, etc., further preferably, the substrate 1 is a single crystal material. The substrate 1 is etched to form a plurality of cavities (not shown in FIG. 1 ), and a sacrificial layer 2 is deposited to fill it. The etching process is preferably anisotropic dry etching or wet etching, such as reactive ion etching with a fluorocarbon-based etching gas, or wet etching with TMAH. The deposition process is a low temperature process such as LPCVD, APCVD, PECVD (deposition temperature is lower than 500 degrees Celsius, preferably 100 to 400 degrees Celsius), and the sacrificial layer 2 is made of silicon oxide-based materials, such as boron-doped silicon oxide (BSG), phosphorus-doped silicon oxide ( PSG), undoped silicon oxide (USG), porous silicon oxide, etc., so that the residual thermal stress in the substrate 1 can be reduced, and it is beneficial to improve the speed of subsequent etching and removal to save time and cost. As shown in FIG. 1 , the sacrificial layer 2 includes at least two parts, that is, the first part 2 a is used to fill the main resonant cavity, and the second part 2 b is used to fill the secondary resonant cavity around the main resonant cavity. Preferably, the sacrificial layer 2 is processed by a CMP planarization process until the surface of the substrate 1 is exposed. In a preferred embodiment of the present invention, the central part of the cavity formed by etching the substrate 1, that is, the projection of the main resonant cavity in a plan view is a polygon (such as a quadrilateral, pentagon, hexagon, octagon, etc. etc.), circle, ellipse, etc., and the projection of the peripheral part, that is, the secondary resonant cavity in the plan view, is a similar figure concentric with the main resonant cavity, so a part of the annular substrate is sandwiched between the main and secondary resonant cavity. The 1S is used as a subsequent mechanical support or isolation structure, and the first part 2a and the second part 2b of the filled sacrificial layer also have corresponding morphologies.

As shown in FIG. 2 , a patterned lower electrode 3 is formed on the substrate 1 . Through magnetron sputtering, thermal evaporation, MOCVD and other processes, a conductive material layer is formed, such as Mo, W, Ru, Al, Cu, Ti, Ta, In, Zn, Zr, Fe, Mg and other metal elements or metal alloys , or conductive oxides of these metals, conductive nitrides, and any combination of the above materials. Preferably, before forming the conductive material layer, a seed layer (not shown) is further formed on the substrate 1 and the sacrificial layer 2 to improve the crystal orientation of the electrode layer and the upper functional layer. In a preferred embodiment of the present invention, the seed layer is AlN, HfN, HfAlN, TiN, TaN, etc., and preferably can be used as a barrier layer preventing the downward migration of the lower electrode metal material to avoid affecting the top of the resonant cavity and the bottom The interface state between the film layers. Then, a photolithography-etching process is used, such as spin coating photoresist, exposure and development to form a photoresist pattern, and the photoresist pattern is used as a mask to etch the conductive material layer to pattern the conductive material layer, and form Figure 2 Lower electrode 3 shown. The lower electrode 3 includes at least a first portion 3a at the center, and a second portion 3b at the periphery. The first part 3a of the lower electrode is the same as the first part 2a of the sacrificial layer and the main resonant cavity. The projection in the plan view is a polygon (such as a quadrilateral, a pentagon, a hexagon, an octagon, etc.), a circle, an ellipse, etc., and The second portion 3b is an annular structure concentric with the first portion 3a with a gap therebetween. It is worth noting that, in order to ensure sufficient insulation isolation between the main resonator and the lower electrode of the adjustment sub-resonator, the distance between the second peripheral part 3b and the central first part 3a should be at least greater than that of the main and auxiliary resonators. The width of the top of the substrate support structure IS sandwiched between the cavities. Preferably, the edge of the first portion 3a of the lower electrode is indented inwardly from the edge of the first portion 2a of the sacrificial layer by 0.1-10 microns, preferably 0.05-5 microns, optimally 1-3 microns. Further or similarly, the edge of the second portion 3b of the lower electrode is also retracted inward by the same distance from the edge of the second portion 2b of the sacrificial layer. After the patterned lower electrode 3 is formed, the photoresist pattern is removed by wet etching.

As shown in FIG. 3, an insulating layer 4 is filled between the lower electrode patterns. For example, using LPCVD, PECVD, spin coating, spray coating, screen printing and other processes, the insulating dielectric material is filled between the first part 3a and the second part 3b of the lower electrode layer to form an annular insulating layer pattern 4 . The material of the insulating layer 4 is different from that of the sacrificial layer 2, so as to avoid excessive erosion during the subsequent process of removing the sacrificial layer 2 to form a resonant cavity. In a preferred embodiment of the present invention, the material of the insulating layer 4 is nitride, such as silicon nitride, silicon oxynitride, aluminum nitride, boron nitride, and the like. Preferably, the insulating layer is processed by a planarization process of etchback or CMP until the

lower electrode patterns

3a and 3b are exposed.

As shown in FIG. 4 , the piezoelectric layer 5 is formed on the

lower electrode patterns

3 a and 3 b and the insulating layer 4 . For example, a process such as PECVD, UHVCVD, HDPCVD, MOCVD, MBE, ALD, magnetron sputtering, thermal evaporation, etc. is used to form the piezoelectric layer 5 , preferably the material of which is different from the insulating layer 4 . In a preferred embodiment of the present invention, the piezoelectric layer 5 is made of materials such as ZnO, AlN, BST (barium strontium titanate), BT (barium titanate), PZT (lead zirconate titanate), PBLN (lead barium lithium niobate) ), PT (lead titanate) and other piezoelectric ceramic materials, and preferably, the piezoelectric layer 5 is doped with rare earth elements, such as scandium (Sc), yttrium (Y), lanthanum (La), cerium (Ce), Praseodymium (Pr), Neodymium (Nd), Promethium (Pm), Samarium (Sm), Europium (Eu), Gadolinium (Gd), Terbium (Tb), Dysprosium (Dy), Holmium (Ho), Erbium (Er), Any one of thulium (Tm), ytterbium (Yb), and lutetium (Lu) and combinations thereof to improve the piezoelectric coefficient. In a preferred embodiment of the present invention, the piezoelectric layer 5 is doped with Sc, or mixed with Sc and Yb, or doped with Sc and Gd, or mixed with Sc, Yb, and Sm. Subsequently, the upper conductive material layer 6 is formed on the piezoelectric layer 5 . The preparation process and materials of the conductive material layer 6 are the same as those of the lower electrode layer 3 , and details are not repeated here.

As shown in FIG. 5, the conductive material layer 6 is patterned to form an upper electrode first portion 6a and an upper electrode second portion 6b. The photoresist is spin-coated, a photoresist pattern is formed through an exposure and development process, and the conductive material layer 6 is etched with the photoresist pattern as a mask to form a first portion 6a of an upper electrode located in the center, and a second annular upper electrode located in the periphery. Section 6b. Preferably, the edge of the first portion 6a of the upper electrode is aligned with the edge of the first portion 3a of the lower electrode, and the edge of the second portion 6b of the upper electrode is aligned with the edge of the second portion 3b of the lower electrode, so that there is a gap between the first portion 6a and the second portion 6b. A lower void aligned with the insulating layer 4 between the

lower electrode patterns

3a, 3b. Afterwards, the photoresist pattern is preferably removed by a wet etching process.

As shown in FIG. 6, a second insulating layer 7 is formed on the piezoelectric layer 5 and the upper electrode patterns 6a/6b. The material and process of the second insulating layer 7 are the same as or similar to those of the insulating layer 4 , and details are not repeated here.

As shown in FIG. 7 , the sacrificial layer pattern 2 is removed, leaving a resonant cavity in the substrate 1 . A wet etchant is applied to remove the sacrificial layer pattern through release holes (not shown) provided at the periphery of the device. For silicon oxide-based materials, use an HF-based etching solution such as dHF (diluted HF), dBOE (slow release etchant, _{a mixture of HF and NH 4} F) to remove the sacrificial layer pattern 2, leaving multiple resonant cavities with at least It comprises a first portion 1c in the center, and a second portion 1c' in an annular shape in the periphery. As shown before, the width of the insulating layer 4 is larger than the width of the top of the support structure 1S, and the width of the first part 3a and the second part 3b of the lower electrode is smaller than that of the

sacrificial layer patterns

2a and 2b, so the width of the main resonant cavity 1c left is larger than that of the first part 3a and the second part 3b of the lower electrode. In a portion 3a, the width of the sub-resonant cavity 1c' is larger than that of the second portion 3b of the lower electrode.

As shown in FIG. 8 , the second insulating layer 7 is processed by a planarization process such as etchback, CMP, etc., until the

upper electrode patterns

6a and 6b are exposed. The finally formed resonator structure is shown in FIG. 8 and includes a substrate 1, a first part 1c of the resonator cavity, a second part 1c' of the resonator cavity located in the substrate 1, a first part 3a of the lower electrode above the first part 1c of the resonator cavity, The piezoelectric layer 5 and the first part 6a of the upper electrode constitute the main resonator, and the second part 3b of the lower electrode, the piezoelectric layer 5, and the second part 6b of the upper electrode above the second part 1c' of the resonant cavity constitute the sub-resonator. The distribution morphology of the upper electrodes 6a/6b and the second insulating layer 7 is shown in FIG. 10, which is the same as or conformal or similar to the lower electrodes 3a/3b and the insulating layer pattern 4, and both are concentric polygons or circles, ellipses The second insulating layer 7 is sandwiched between the central part of the upper electrode, that is, the first part 6a and the peripheral second part 6b, and the second part 6b has at least one gap to accommodate the lead-out part of the first part 6a. Pass through the second insulating layer 7 under wrapping to realize external electrical connection. During the operation of the device, by applying a signal different from that of the main resonator to the electrodes (3b, 6b) of the sub-resonator, for example, at least one of amplitude, frequency, and phase is different, so that the sub-resonator around the main resonator generates a different signal from the main resonator. The different vibrations of the resonator and the superposition of two mechanical waves with different states change the final signal waveform. In this way, the vibration state of the sub-resonator can be flexibly changed in real time by controlling the input waveform of the sub-resonator, thereby affecting the working state of the entire resonator, so as to adjust the frequency response of the entire resonator system when needed, which is conducive to saving Chip area, improve integration, reduce product cost, and improve device utilization.

In another preferred embodiment of the present invention, as shown in FIG. 9 , the piezoelectric layers 5 are no longer connected as a whole, but the second insulating layer 7 penetrates through the support structure 1S directly on the surface of the substrate 1, thereby The insulation isolation effect between the electrodes of the main resonator and the sub-resonator is improved, and the lateral crosstalk of signals between the upper and lower electrodes of different resonators is prevented. The manufacturing process is basically the same as that shown in FIG. 1 to FIG. 8, except that in the process steps shown in FIG. 5, after etching and patterning the

upper electrodes

6a and 6b, the photoresist pattern or the upper electrode pattern is used as a mask. mold, continue to etch the piezoelectric layer 5 until the support structure 1S on the surface of the substrate 1 is exposed, and in the process steps shown in FIG. insulating layer 7. The resulting device structure is similar to that shown in FIG. 8, the difference is that the second insulating layer 7 is not only sandwiched between the first part 6a and the second part 6b of the upper electrode, but also penetrates the piezoelectric layer 5 to the surface of the substrate, and is sandwiched therebetween. between the first part 3a and the second part 3b of the lower electrode.

Although the invention has been described with reference to one or more exemplary embodiments, those skilled in the art will recognize various suitable changes and equivalents in device structure without departing from the scope of the invention. In addition, many modifications, as may be adapted to a particular situation or material, may be made from the disclosed teachings without departing from the scope of the invention. Therefore, the present invention is not intended to be limited to the particular embodiments disclosed as the best mode for carrying out the present invention, and the disclosed device structures and methods of making the same are to include all embodiments that fall within the scope of the present invention .

Claims

A tunable resonator comprising:

The resonant cavity, in the substrate, at least includes a first resonant cavity in the center and a second resonant cavity in the periphery;

The first stack structure, on the first resonant cavity, sequentially includes a first part of the lower electrode, a first part of the piezoelectric layer and a first part of the upper electrode;

The second stack structure, on the second resonant cavity, sequentially includes a second part of the lower electrode, a second part of the piezoelectric layer and a second part of the upper electrode;

A first insulating layer, on the substrate, is located between the first portion of the lower electrode and the second portion of the lower electrode.

The peripheral second resonant cavity is arranged around the first resonant cavity.
The resonator of claim 1, further comprising a second insulating layer, on the piezoelectric layer first portion and the piezoelectric layer second portion, between the upper electrode first portion and the upper electrode second portion; preferably, the piezoelectric layer The first portion and the second portion of the piezoelectric layer are connected or separated by a second insulating layer.
The tunable resonator according to claim 1, wherein the first resonant cavity, the first part of the lower electrode and the first part of the upper electrode are polygonal, circular or elliptical in plan view; preferably, the size of the top of the first resonant cavity is larger than that of the lower electrode The size of the first part of the electrode or the first part of the upper electrode, optionally, the size of the top of the second resonant cavity is larger than the size of the second part of the lower electrode or the second part of the upper electrode; preferably, the first part of the lower electrode and the first part of the upper electrode are edge-aligned , the edges of the second part of the lower electrode and the second part of the upper electrode are aligned.
The tunable resonator of claim 1, wherein a different signal is applied to the second stack structure than the first stack structure to adjust a resonance state of the resonator, the resonance state comprising at least one of amplitude, frequency, phase, or a combination thereof .
The tunable resonator according to any one of claims 1 to 4, wherein the substrate material is Si, SOI, Ge, GeOI, compound semiconductor; optionally, the material of the first part of the piezoelectric layer and the second part of the piezoelectric layer is ZnO, AlN, BST (barium strontium titanate), BT (barium titanate), PZT (lead zirconate titanate), PBLN (lead barium lithium niobate), PT (lead titanate), further preferably piezoelectric materials doped with rare earth elements; optionally, the material of the first or second insulating layer is nitride, such as silicon nitride, silicon oxynitride, aluminum nitride, boron nitride; optionally, the first part of the lower electrode, the lower The material of any one of the second part of the electrode, the first part of the upper electrode, and the second part of the upper electrode is a metal element selected from Mo, W, Ru, Al, Cu, Ti, Ta, In, Zn, Zr, Fe, Mg or Metal alloys, or conductive oxides of these metals, or conductive nitrides, and any combination of the foregoing.
A method for manufacturing a tunable resonator, comprising:

forming a sacrificial layer in the substrate, including a first sacrificial layer pattern in the center and a second sacrificial layer pattern in the periphery;

forming a lower electrode layer on the sacrificial layer, including a first part of the lower electrode on the first sacrificial layer pattern and a second part of the lower electrode on the second sacrificial layer pattern;

forming a first insulating layer between the first part of the lower electrode and the second part of the lower electrode;

forming a piezoelectric layer on the first insulating layer and the lower electrode layer, including at least a first part of the piezoelectric layer above the first sacrificial layer pattern and a second part of the piezoelectric layer above the second sacrificial layer pattern;

forming an upper electrode layer on the piezoelectric layer, including a first part of the upper electrode on the first part of the piezoelectric layer, and a second part of the upper electrode on the second part of the piezoelectric layer;

The sacrificial layer is removed to leave a resonant cavity in the substrate, including a first resonant cavity in the center and a second resonant cavity in the periphery; the second resonant cavity in the periphery is arranged around the first resonant cavity.
The method for manufacturing a tunable resonator according to claim 6, further comprising, after forming the upper electrode layer, forming a second insulating layer between at least the first part of the upper electrode and the second part of the upper electrode; preferably, the first part of the piezoelectric layer and the pressure A second portion of the electrical layer is connected or separated by a second insulating layer.
The method for manufacturing a tunable resonator according to claim 6, wherein the first resonant cavity, the first part of the lower electrode, and the first part of the upper electrode are polygonal, circular or elliptical in plan view; preferably, the size of the top of the first resonant cavity is larger than the size of the first part of the lower electrode or the first part of the upper electrode, optionally, the size of the top of the second resonant cavity is larger than the size of the second part of the lower electrode or the second part of the upper electrode; preferably, the first part of the lower electrode and the first part of the upper electrode The edges are aligned, and the second part of the lower electrode and the second part of the upper electrode are edge-aligned.
The method for manufacturing a tunable resonator according to claim 6, wherein the substrate material is Si, SOI, Ge, GeOI, compound semiconductor; optionally, the materials of the first part of the piezoelectric layer and the second part of the piezoelectric layer are ZnO, AlN, BST (barium strontium titanate), BT (barium titanate), PZT (lead zirconate titanate), PBLN (lead barium lithium niobate), PT (lead titanate), further preferably doped in the piezoelectric material rare earth element; optionally, the material of the first or second insulating layer is nitride, such as silicon nitride, silicon oxynitride, aluminum nitride, boron nitride; optionally, the first part of the lower electrode, the second lower electrode The material of any one of the part, the first part of the upper electrode, and the second part of the upper electrode is a metal element or metal alloy selected from Mo, W, Ru, Al, Cu, Ti, Ta, In, Zn, Zr, Fe, Mg, Or conductive oxides of these metals, or conductive nitrides, and any combination of the above; optionally, the sacrificial layer material is an oxide, such as boron-doped silicon oxide (BSG), phosphorus-doped silicon oxide (PSG), undoped silicon oxide Heterosilica (USG), porous silica.
The method for manufacturing a tunable resonator according to claim 7, further comprising, after forming the upper electrode layer and before removing the sacrificial layer, etching the piezoelectric layer between the first portion of the upper electrode and the second portion of the upper electrode to form an opening for exposing the substrate, A second insulating layer is formed on the upper electrode layer and on the bottom and sidewalls of the opening.