WO2022017110A1 - 一种半导体器件的制造方法、半导体器件 - Google Patents

一种半导体器件的制造方法、半导体器件 Download PDF

Info

Publication number
WO2022017110A1
WO2022017110A1 PCT/CN2021/101751 CN2021101751W WO2022017110A1 WO 2022017110 A1 WO2022017110 A1 WO 2022017110A1 CN 2021101751 W CN2021101751 W CN 2021101751W WO 2022017110 A1 WO2022017110 A1 WO 2022017110A1
Authority
WO
WIPO (PCT)
Prior art keywords
region
conductivity type
well
type
deep well
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2021/101751
Other languages
English (en)
French (fr)
Inventor
金华俊
孙贵鹏
林峰
陈淑娴
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CSMC Technologies Fab2 Co Ltd
Original Assignee
CSMC Technologies Fab2 Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CSMC Technologies Fab2 Co Ltd filed Critical CSMC Technologies Fab2 Co Ltd
Priority to JP2022557168A priority Critical patent/JP7589257B2/ja
Publication of WO2022017110A1 publication Critical patent/WO2022017110A1/zh
Priority to US17/886,609 priority patent/US12593465B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/65—Lateral DMOS [LDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0281—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of lateral DMOS [LDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/65—Lateral DMOS [LDMOS] FETs
    • H10D30/655—Lateral DMOS [LDMOS] FETs having edge termination structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H10D62/107—Buried supplementary regions, e.g. buried guard rings 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/101—Integrated devices comprising main components and built-in components, e.g. IGBT having built-in freewheel diode
    • H10D84/151—LDMOS having built-in components
    • H10D84/153—LDMOS having built-in components the built-in component being PN junction diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/22—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping using masks

Definitions

  • the present invention relates to the technical field of semiconductors, and in particular, to a method for manufacturing a semiconductor device and a semiconductor device.
  • LDMOS Lateral Double Diffused MOSFET
  • the present invention provides a method for manufacturing a semiconductor device, comprising:
  • a channel region of a first conductivity type, a well region of a first conductivity type, and a well region of a second conductivity type are formed in the deep well, and the well region of the first conductivity type and the channel region are formed by a region of a portion of the deep well spaced apart, the drift region being located between the channel region and the well region of the first conductivity type;
  • An ion implantation region of a first conductivity type is formed in the deep well, and the ion implantation region of the first conductivity type is located under the drift region, so that the channel region, the well region of the first conductivity type and an ion implantation region of the first conductivity type surrounding the drift region;
  • the present invention also provides a semiconductor device, comprising:
  • a deep well of the second conductivity type extends from the upper surface of the semiconductor substrate to the interior of the semiconductor substrate;
  • an ion implantation region of a first conductivity type located in the deep well and below the drift region, the channel region, the well region of the first conductivity type and the ion implantation region surrounding the drift region;
  • a source region of a second conductivity type and a drain region of a second conductivity type the source region being located in the channel region, and the drain region being located in the drift region.
  • FIGS. 1A-1E are schematic structural diagrams of a semiconductor device formed in a method for manufacturing a semiconductor device according to an embodiment of the present invention
  • FIG. 2 is a flowchart of a method of manufacturing a semiconductor device according to an embodiment of the present invention.
  • An exemplary high-voltage NMOS device structure with reduced on-resistance uses an epitaxial and buried layer implantation process to form an NPNP structure. Since the N-type drift region is surrounded by the P-type region, a better drift region depletion effect can be obtained. Therefore, The drift region concentration can be made more concentrated, so that the device on-resistance can be made lower. However, due to the need for an additional epitaxial process and a buried layer process, it not only increases the process cost but also increases the process difficulty.
  • the present invention provides a method for manufacturing a semiconductor device, comprising:
  • a channel region of a first conductivity type, a well region of a first conductivity type, and a well region of a second conductivity type are formed in the deep well, and the well region of the first conductivity type and the channel region are formed by a region of a portion of the deep well spaced apart, the drift region being located between the channel region and the well region of the first conductivity type;
  • An ion implantation region of a first conductivity type is formed in the deep well, and the ion implantation region of the first conductivity type is located under the drift region, so that the channel region, the well region of the first conductivity type and an ion implantation region of the first conductivity type surrounding the drift region;
  • a source region of the second conductivity type and a drain region of the second conductivity type are formed in the deep well, wherein the source region is located in the channel region and the drain region is located in the drift region.
  • FIG. 1A-FIG. 1E and FIG. 2 will be a schematic illustration of the manufacturing method of the semiconductor device according to the present invention, wherein FIG. 1A-FIG. 1E is formed in a semiconductor device manufacturing method according to an embodiment of the present invention.
  • FIG. 2 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
  • step S1 is performed: a semiconductor substrate of a first conductivity type is provided, and a deep well of a second conductivity type is formed in the semiconductor substrate.
  • a semiconductor substrate 300 is provided, specifically, at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs or other III/ V compound semiconductors also include multilayer structures composed of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator ( SiGeOI) and germanium-on-insulator (GeOI).
  • the semiconductor substrate is of the first conductivity type.
  • the first conductivity type and the second conductivity type generally refer to P-type or N-type.
  • the first conductivity type is one of P-type, low-doped P-type, and highly-doped P+ type.
  • the second conductivity type is one of N-type, low-doped N- type, and high-doped N+ type.
  • the first conductivity type is one of N-type, low-doped N-type, and highly-doped N+ type
  • the second conductivity type is P-type, low-doped P-type, and highly-doped P+ type one.
  • the semiconductor substrate of the first conductivity type is a P-type low-doped substrate.
  • the semiconductor substrate is a non-epitaxial substrate.
  • the manufacturing method of the semiconductor device described in this embodiment is performed on a non-epitaxial process platform, and the entire manufacturing method is performed on a non-epitaxial process platform so that no additional epitaxial process and buried layer process are required in the manufacturing process, that is, by Optimizing the device structure design can obtain better device characteristics in the non-epitaxial process, reduce the process cost, reduce the process difficulty, and also improve the process platform compatibility.
  • a deep well 301 of the second conductivity type is formed in a semiconductor substrate 300 .
  • the method of forming the deep well of the second conductivity type includes: forming a patterned mask layer on the semiconductor substrate, the patterned mask layer exposing the deep well of the second conductivity type to be formed region; performing deep well ion implantation of the second conductivity type to form a deep well of the second conductivity type in the first conductivity type semiconductor substrate; removing the patterned mask layer.
  • the deep well ion implantation of the second conductivity type is high energy ion implantation.
  • the step of performing deep well annealing of the second conductivity type is further included.
  • the semiconductor substrate of the first conductivity type is a P-type low-doped substrate, that is, a P-substrate, and the deep well of the second conductivity type is an N-well.
  • the doping concentration of the deep well of the second conductivity type increases as the depth increases in the depth direction.
  • Setting the doping concentration of the deep well of the second conductivity type to increase with the depth in the depth direction can further enhance the isolation effect of the deep well of the second conductivity type in the device structure, especially for subsequent
  • the other well regions formed in the deep well of the second conductivity type provide better isolation, and the other well regions formed in the deep well of the second conductivity type may be well regions of the first conductivity type.
  • the step of forming an isolation structure 302 in the semiconductor substrate 300 is further included.
  • the isolation structure 302 is a shallow trench isolation structure, and the method for forming the shallow trench isolation structure includes: performing a photolithography process to form a patterned mask layer on the semiconductor substrate, and the patterned mask layer is exposed to be formed isolating the region of the structure; performing an etching process to etch the semiconductor substrate with the patterned mask layer as a mask to form a shallow trench in the semiconductor substrate; performing a deposition process to form a filling of the shallow trench The isolation material layer of the trench; a chemical mechanical polishing process is performed to remove the isolation material layer outside the shallow trench.
  • the isolation structure includes a first isolation structure and a second isolation structure, the first isolation structure is located between a region where a drift region is to be formed and a region where a well region of the first conductivity type is to be formed, and the second isolation structure is The structure is located between the well region where the first conductivity type is to be formed and the well region where the second conductivity type is to be formed.
  • step S2 is performed: a first conductivity type channel region, a first conductivity type well region and a second conductivity type well region are formed in the deep well, the first conductivity type A well region is spaced apart from the channel region by a region of a portion of the deep well, and the drift region is located between the channel region and the well region of the first conductivity type.
  • FIG. 1B a schematic structural diagram of a semiconductor device in which a channel region and a well region of a first conductivity type are formed in a deep well of a second conductivity type according to an embodiment of the present invention is shown.
  • a channel region 303 of the first conductivity type and a well region 304 of the first conductivity type are formed in the region of the deep well 301 of the second conductivity type in the semiconductor substrate 300 .
  • the well region 304 of the first conductivity type and the channel region 303 are separated by a portion of the deep well 301 of the second conductivity type.
  • the step of forming the channel region 303 of the first conductivity type includes: performing a photolithography process to form a patterned mask layer exposing the channel region to be formed; and performing an ion implantation process to form the channel region.
  • the semiconductor substrate of the first conductivity type is a P-type low-doped substrate, that is, a P-substrate, the deep well of the second conductivity type is an N-well, and the first conductivity type is an N-well.
  • the type of channel region is a P-type doped region.
  • the step of forming the well region 304 of the first conductivity type includes: performing a photolithography process to form a patterned mask layer exposing the well region to be formed of the first conductivity type; performing an ion implantation process to form the first conductivity type well region.
  • a conductivity type well region includes: performing a photolithography process to form a patterned mask layer exposing the well region to be formed of the first conductivity type; performing an ion implantation process to form the first conductivity type well region.
  • the semiconductor substrate of the first conductivity type is a P-type low-doped substrate, that is, a P-substrate, the deep well of the second conductivity type is an N-well, and the first conductivity type is an N-well.
  • the type of well region is a P-type doped region.
  • a first-conductivity-type well region is formed in the deep well, the first-conductivity-type well region is formed for the drift region together with the first-conductivity-type channel region, and a first-conductivity-type ion implantation region subsequently formed under the drift region
  • the surrounding structure can effectively improve the depletion of the drain drift region and increase the breakdown voltage.
  • the NPNP device structure in the LDMOS device is realized, which greatly improves the performance of the device. And the process of forming a buried layer is not required, that is, a high-voltage device structure can be realized.
  • the step of forming the channel region of the first conductivity type and the step of forming the well region of the first conductivity type use the same mask and the same ion implantation step to reduce process steps, Reduce process costs.
  • the example that the channel region of the first conductivity type and the well region of the first conductivity type are formed in the same step is only exemplary, and those skilled in the art should understand that the first The channel region of the conductivity type and the well region of the first conductivity type can also be formed in different steps, which can also achieve the technical effect of the present invention.
  • FIG. 1C a schematic structural diagram of a semiconductor device after a drift region of a second conductivity type is formed in a deep well of the second conductivity type according to an embodiment of the present invention is shown.
  • a drift region 305 of the second conductivity type is formed in the deep well 301 of the second conductivity type of the semiconductor substrate 300 , and the drift region 305 is located between the channel region 303 and the well region 304 of the first conductivity type. area.
  • the step of forming the drift region 305 of the second conductivity type includes: performing a photolithography process to form a patterned mask layer exposing the drift region of the second conductivity type to be formed; performing an ion implantation process to form the first A drift region of two conductivity types.
  • the semiconductor substrate of the first conductivity type is a P-type low-doped substrate, that is, a P-substrate, the deep well of the second conductivity type is an N-well, and the second conductivity type is an N-well.
  • the type of drift region is an N-type doped region.
  • the process of forming the drift region further includes the step of forming a well region of the second conductivity type in the deep well, the well region of the second conductivity type is provided on the side of the well region of the first conductivity type away from the channel region.
  • the well region of the second conductivity type is used to form the contact region of the deep well of the second conductivity type, connecting the deep well of the second conductivity type, and at the same time, it plays a role between the well region of the first conductivity type and the semiconductor substrate. isolation.
  • a second conductivity type well region 306 is formed in the second conductivity type deep well 301 of the semiconductor substrate 300, wherein the second conductivity type well region 306 is provided in the first conductivity type well region 304 A side away from the channel region 303 .
  • the step of forming the well region 306 of the second conductivity type includes: performing a photolithography process to form a patterned mask layer exposing the well region to be formed of the second conductivity type; performing an ion implantation process to form the first Well regions of two conductivity types.
  • the semiconductor substrate of the first conductivity type is a P-type low-doped substrate, that is, a P-substrate
  • the deep well of the second conductivity type is an N-well
  • the second conductivity type is an N-well.
  • type of well regions are N-type doped regions.
  • the formation of the well region of the second conductivity type after the drift region is formed is only exemplary, and those skilled in the art should understand that in the process of performing the steps to form the drift region and before the drift region is formed Forming a well region of the second conductivity type can also implement the present invention.
  • step S3 is performed: forming a first conductivity type ion implantation region in the deep well, and the first conductivity type ion implantation region is located under the drift region, so that the channel region, The first conductivity type well region and the first conductivity type ion implantation region surround the drift region.
  • FIG. 1D a schematic structural diagram of a semiconductor device after forming an ion implantation region of a first conductivity type under a drift region of a second conductivity type according to an embodiment of the present invention is shown.
  • a first conductivity type ion implantation region 307 is formed in the deep well 301 of the second conductivity type of the semiconductor substrate 300 , and the first conductivity type ion implantation region 307 is located under the drift region 305 , so that the first conductivity type ion implantation region 307 is The channel region 303 , the well region 304 of the first conductivity type and the ion implantation region 307 of the first conductivity type surround the drift region 305 .
  • the step of forming the first conductivity type ion implantation region 307 includes: performing a photolithography process to form a patterned mask layer exposing the drift region to be formed; performing an ion implantation process to form the first conductivity type ion implantation process District 307.
  • the semiconductor substrate of the first conductivity type is a P-type low-doped substrate, that is, a P-substrate, the deep well of the second conductivity type is an N-well, and the first conductivity type is an N-well.
  • the type ion implantation region 307 is a P-type doped region.
  • a first conductivity type ion implantation region is formed under the drift region, and the first conductivity type ion implantation region forms a surrounding structure for the drift region together with the first conductivity type channel region and the first conductivity type well region, which effectively improves the drain drift
  • the depletion of the region increases the breakdown voltage.
  • the NPNP device structure in the LDMOS device is realized, so that the channel region and the semiconductor substrate are isolated by the deep well region, so that the channel region is not affected by the substrate voltage, and the performance of the device is greatly improved. And the process of forming a buried layer is not required, that is, a high-voltage device structure can be realized.
  • the step of forming the drift region in the deep well and the step of forming the ion implantation region of the first conductivity type in the deep well share a set of masks, so as to reduce the process cost.
  • the step of forming the first conductivity type ion implantation region in the deep well is performed after the drift region is formed in the deep well, so that the step of forming the drift region is performed
  • the same mask layer is used as the step of forming the ion implantation region of the first conductivity type.
  • the channel region, the well region of the first conductivity type, the drift region, the well region of the second conductivity type, the ion implantation region of the first conductivity type, etc. are formed in steps S2 and S3 respectively. , it is not intended to limit the order of forming the channel region, the well region of the first conductivity type, the drift region, the well region of the second conductivity type, and the ion implantation region of the first conductivity type, and those skilled in the art can use any feasible method.
  • the conductive type well region, the drift region, the second conductive type well region, and the first conductive type ion implantation region are formed in order, which can realize the semiconductor device of the present invention without using epitaxy and forming a buried layer. manufacture, and realize the technical effect of the present invention.
  • step S4 is performed: a source region of a second conductivity type and a drain region of the second conductivity type are formed in the deep well, wherein the source region is located in the channel region, the A drain region is located in the drift region.
  • FIG. 1E a schematic structural diagram of a semiconductor device after forming source and drain regions according to an embodiment of the present invention is shown.
  • a source region 308 and a drain region 309 are formed in the semiconductor substrate 300 , wherein the source region 308 is located in the channel region 303 and the drain region 309 is located in the drift region 305 .
  • the semiconductor substrate of the first conductivity type is a P-type low-doped substrate, that is, a P-substrate
  • the deep well of the second conductivity type is an N-well
  • the source region and the The drain region is an N+ type doped region.
  • the step of forming a gate structure is further included before forming the source and drain regions.
  • a gate structure including a gate dielectric layer 310 and a gate material layer 311 is formed on the surface of the semiconductor substrate 300 , and the gate structure exposes regions where source and drain regions are to be formed.
  • the step of forming the gate structure adopts a process commonly used in the art, and details are not described herein again.
  • the method further includes forming a well region lead-out region of the first conductivity type and a well region lead-out region of the second conductivity type in the semiconductor substrate.
  • the first conductivity type is P-type and the second conductivity type is N-type, so the semiconductor substrate of the first conductivity type is a P-type low-doped substrate, that is, a P-substrate.
  • the drift region of two conductivity types is an N-type drift region.
  • the well region 304 of the first conductivity type, the ion implantation region 307 of the first conductivity type, and the channel region 303 form a first P-type surrounding structure surrounding the drift region 305 of the second conductivity type;
  • the well region 306 of the second conductivity type and the deep well 301 of the second conductivity type form an N-type surrounding structure surrounding the above-mentioned first P-type surrounding structure;
  • the outermost semiconductor substrate 300 of the first conductivity type forms a second P-type surrounding structure surrounding the N-type surrounding structure.
  • the N-type drift region, the first P-type surrounding structure, the N-type surrounding structure, and the second P-type surrounding structure constitute an NPNP structure in the device structure, which improves the breakdown voltage and reduces the on-resistance.
  • the well region lead-out region 312 of the first conductivity type and the well region lead-out region 313 of the second conductivity type are used to lead out the well region 304 of the first conductivity type and the well region 306 of the second conductivity type to the external circuit.
  • the drain region 309 is independently separated from the well region 306 of the second conductivity type, and the drain region 309 is also independently separated from the deep well 301 of the second conductivity type, so that the drain region 309 is separated from the well region 313 of the second conductivity type.
  • Different voltages can be split in circuit applications.
  • the well region lead-out region 312 of the first conductivity type and the semiconductor substrate 300 of the first conductivity type are separated by the well region 306 of the second conductivity type and the deep well 301 of the second conductivity type. That is to say, the first P-type surrounding structure and the second P-type surrounding structure are separated by the N-type surrounding structure, which can ensure that the first P-type surrounding structure can be lifted as a body region but is not affected by the second P-type surrounding structure. The effect of , realizes that the body region can be lifted but not affected by the substrate, and can also improve the breakdown voltage and reduce the on-resistance.
  • the NPNP structure can be realized without the need for epitaxy and the process of forming a buried layer, which greatly reduces the process flow and the production cost.
  • the semiconductor device according to the present invention has higher breakdown voltage and lower on-resistance.
  • the semiconductor substrate of the first conductivity type is a P-type low-doped substrate, that is, a P-substrate
  • the deep well of the second conductivity type is an N well
  • the deep well of the second conductivity type is an N-well.
  • the well region is a P-type doped region
  • the well region of the second conductivity type is an N-type doped region
  • the well region of the first conductivity type is a P+ type doped region
  • the well region of the second conductivity type is an N+ type doped region. type doped region.
  • the present invention also provides a semiconductor device, comprising:
  • the source region is located in the channel region, and the drain region is located in the drift region;
  • a first conductivity type ion implantation region located under the drift region, the channel region, the first conductivity type well region and the first conductivity type ion implantation region surround the drift region.
  • FIG. 1E a schematic structural diagram of a semiconductor device according to an embodiment of the present invention is shown.
  • the semiconductor device includes a semiconductor substrate 300 of a first conductivity type.
  • the semiconductor substrate 300 may be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs or other III/V compound semiconductors, including these Multilayer structures composed of semiconductors, etc., or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI) and germanium-on-insulator ( GeOI) etc.
  • the semiconductor substrate is of the first conductivity type.
  • the first conductivity type and the second conductivity type generally refer to P-type or N-type.
  • the first conductivity type is one of P-type, low-doped P-type, and highly-doped P+ type.
  • the second conductivity type is one of N-type, low-doped N- type, and high-doped N+ type.
  • the first conductivity type is one of N-type, low-doped N-type, and highly-doped N+ type
  • the second conductivity type is P-type, low-doped P-type, and highly-doped P+ type one.
  • the semiconductor substrate of the first conductivity type is a P-type low-doped substrate.
  • the semiconductor substrate is a non-epitaxial substrate.
  • the semiconductor device described in this embodiment is formed on a non-epitaxial process platform, and the entire manufacturing method is performed on a non-epitaxial process platform, so that no additional epitaxial process and buried layer process are required in the manufacturing process, that is, by optimizing the device structure.
  • the design can obtain better device characteristics on the non-epitaxial process, reduce the process cost, reduce the process difficulty, and also improve the process platform compatibility.
  • the semiconductor device according to the present invention further includes a deep well 301 of the second conductivity type in the semiconductor substrate 300 .
  • the semiconductor substrate of the first conductivity type is a P-type low-doped substrate, that is, a P-substrate
  • the deep well of the second conductivity type is an N-well
  • the second conductivity type is an N-well.
  • Type deep wells are low-doped regions of N-type doping.
  • the doping concentration of the deep well of the second conductivity type increases as the depth increases in the depth direction.
  • the doping concentration of the deep well of the second conductivity type is set to increase as the depth increases in the depth direction, and when the well region of the first conductivity type is subsequently formed, the semiconductor can be isolated by the deep well region with the increased doping concentration a substrate and a first doping type well region.
  • the subsequently formed NPNP structure from the drain terminal to the semiconductor substrate is more stable and reliable.
  • the semiconductor device further includes a first conductivity type channel region 303 in the second conductivity type deep well 301 , a first conductivity type well region 304 , and a second conductivity type drift region 305 , wherein the drift region 305 is located between the channel region 303 and the well region 304 of the first conductivity type.
  • the semiconductor substrate of the first conductivity type is a P-type low-doped substrate, that is, a P-substrate, the deep well of the second conductivity type is an N-well, and the first conductivity type is an N-well.
  • the channel region of the type is a P-type doped region, the well region of the first conductivity type is a P-type doped region, and the drift region of the second conductivity type is an N-type doped region.
  • a first-conductivity-type well region is formed in the deep well, and the first-conductivity-type well region is formed for the drift region together with the first-conductivity-type channel region and the first-conductivity-type ion implantation region subsequently formed under the drift region
  • the surrounding structure can effectively improve the depletion of the drain drift region and increase the breakdown voltage.
  • the NPNP device structure in the LDMOS device is realized, which greatly improves the performance of the device. And the process of forming a buried layer is not required, that is, a high-voltage device structure can be realized.
  • the semiconductor device according to the present invention further includes a source region 308 and a drain region 309 , the source region 308 is located in the channel region 303 , and the drain region 309 is located in the drift region 305 .
  • the semiconductor substrate of the first conductivity type is a P-type low-doped substrate, that is, a P-substrate
  • the deep well of the second conductivity type is an N-well
  • the source region and the The drain region is an N+ type doped region.
  • the semiconductor device according to the present invention further includes a first conductivity type ion implantation region 307 located under the drift region 305 , the channel region 303 , the first conductivity type well region 304 and the first conductivity type ion implantation region 307 .
  • the first conductivity type ion implantation region 307 surrounds the drift region 305 .
  • a first conductivity type ion implantation region is formed under the drift region, and the first conductivity type ion implantation region forms a surrounding structure for the drift region together with the first conductivity type channel region and the first conductivity type well region, which effectively improves the drain drift
  • the depletion of the region increases the breakdown voltage.
  • the NPNP device structure in the LDMOS device is realized, which greatly improves the performance of the device. And the process of forming a buried layer is not required, that is, a high-voltage device structure can be realized.
  • the semiconductor substrate of the first conductivity type is a P-type low-doped substrate, that is, a P-substrate, the deep well of the second conductivity type is an N-well, and the first conductivity type is an N-well.
  • the type ion implantation region 307 is a P-type doped region.
  • the semiconductor device further includes a well region 306 of a second conductivity type, and the well region 306 of the second conductivity type is disposed far from the channel of the well region 304 of the first conductivity type one side of zone 303.
  • the well region of the second conductivity type is used to form the contact region of the deep well of the second conductivity type, connecting the deep well of the second conductivity type, and at the same time, it plays a role between the well region of the first conductivity type and the semiconductor substrate. isolation.
  • the semiconductor substrate of the first conductivity type is a P-type low-doped substrate, that is, a P-substrate
  • the deep well of the second conductivity type is an N-well
  • the second conductivity type is an N-well.
  • type of well regions are N-type doped regions.
  • the method further includes forming a well region lead-out region of the first conductivity type and a well region lead-out region of the second conductivity type in the semiconductor substrate.
  • a well region lead-out region 312 of the first conductivity type and a well region lead-out region 313 of the second conductivity type are used to lead out and connect the well region 304 of the first conductivity type and the well region 306 of the second conductivity type to the external circuit.
  • the drain region 309 is independently separated from the well region 306 of the second conductivity type, and the drain region 309 is also independently separated from the deep well 301 of the second conductivity type, so that the drain region 309 is separated from the well region 313 of the second conductivity type.
  • Different voltages can be split in circuit applications.
  • the well region lead-out region 312 of the first conductivity type and the semiconductor substrate 300 of the first conductivity type are separated by the well region 306 of the second conductivity type and the deep well 301 of the second conductivity type, which can improve the breakdown voltage and lower on-resistance.
  • the NPNP structure can be realized without the need for epitaxy and the process of forming a buried layer, which greatly reduces the process flow and the production cost.
  • the semiconductor device according to the present invention has higher breakdown voltage and lower on-resistance.
  • a gate structure is also included.
  • a gate structure including a gate dielectric layer 310 and a gate material layer 311 is further provided on the surface of the semiconductor substrate 300 .
  • an isolation structure 302 formed in the semiconductor substrate is also included.
  • the isolation structure includes a first isolation structure and a second isolation structure, the first isolation structure is located between the drift region and the region of the well region of the first conductivity type, and the second isolation structure is located in the first isolation structure. between the well region of the conductivity type and the well region of the second conductivity type.
  • a semiconductor device is manufactured according to the method for manufacturing a semiconductor device as described in the first embodiment.
  • the device by arranging the well region, the ion implantation region and the channel region surrounding the drift region, the device has a novel structure while effectively improving the depletion of the drain drift region, increasing the breakdown voltage and reducing the conduction. On resistance.
  • the semiconductor device according to the present invention realizes the NPNP device structure in the LDMOS device by arranging the drift region, the well region, the ion implantation region and the channel region in the deep well of the semiconductor substrate, so that the channel region and the semiconductor substrate are connected with each other. It is isolated by the deep well region, so that the channel region is not affected by the substrate voltage, which greatly improves the performance of the device; no buried layer is provided in the device structure, which can limit the simplification of the manufacturing process and reduce the production cost.

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

一种半导体器件的制造方法、半导体器件，所述方法包括：提供第一导电类型的半导体衬底，在所述半导体衬底中形成第二导电类型的深阱；在所述深阱中形成第一导电类型的沟道区、第一导电类型的阱区和第二导电类型的阱区，所述第一导电类型的阱区与所述沟道区之间被部分所述深阱的区域间隔开，所述漂移区位于所述沟道区和所述第一导电类型的阱区之间；在所述深阱中形成第一导电类型离子注入区，所述第一导电类型离子注入区位于所述漂移区下方，以使所述沟道区、所述第一导电类型的阱区和所述第一导电类型离子注入区包围所述漂移区；在所述深阱中形成第二导电类型的源区和第二导电类型的漏区。

Description

一种半导体器件的制造方法、半导体器件
相关申请的交叉引用
本申请要求于2020年07月20日提交中国专利局、申请号为2020106980174、发明名称为“一种半导体器件的制造方法、半导体器件”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及半导体技术领域，具体而言涉及一种半导体器件的制造方法、半导体器件。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成现有技术。
随着半导体技术的不断发展，横向双扩散金属氧化物半导体场效应晶体管(Lateral Double Diffused MOSFET，LDMOS)器件由于其具有良好的短沟道特性而被广泛的应用。LDMOS作为一种功率开关器件，具有工作电压相对较高、工艺简易，易于同低压CMOS电路在工艺上兼容等特点。
业界希望能够提供具有更高的击穿电压和更低的导通电阻的横向双扩散金属氧化物半导体场效应晶体管。
发明内容
在发明内容部分中引入了一系列简化形式的概念，这将在具体实施方式部分中进一步详细说明。本发明的发明内容部分并不意味着要试图限定出所要求保护的技术方案的关键特征和必要技术特征，更不意味着试图确定所要求保护的技术方案的保护范围。
为了解决现有技术中的问题，本发明提供了一种半导体器件的制造方法，包括：
提供第一导电类型的半导体衬底，在所述半导体衬底中形成第二导电类型的深阱；
在所述深阱中形成第一导电类型的沟道区、第一导电类型的阱区和第二导电类型的阱区，所述第一导电类型的阱区与所述沟道区之间被部分所述深阱的区域间隔开，所述漂移区位于所述沟道区和所述第一导电类型的阱区之间；
在所述深阱中形成第一导电类型的离子注入区，所述第一导电类型的离子注入区位于所述漂移区下方，以使所述沟道区、所述第一导电类型的阱区和所述第一导电类型的离子注入区包围所述漂移区；以及
第二导电类型的源区和第二导电类型的漏区，其中，所述源区位于所述沟道区中，所述漏区位于所述漂移区中。
本发明还提供了一种半导体器件，包括：
第一导电类型的半导体衬底；
第二导电类型的深阱，自所述半导体衬底上表面向所述半导体衬底内部延伸；
位于所述深阱中的第一导电类型的沟道区、第一导电类型的阱区、以及第二导电类型的漂移区，所述漂移区位于所述沟道区与所述第一导电类型的阱区之间，且所述漂移区与所述沟道区间隔设置，所述漂移区与所述第一导电类型的阱区相邻设置；
第一导电类型离子注入区，位于所述深阱中且在所述漂移区下方，所述沟道区、所述第一导电类型的阱区和所述离子注入区包围所述漂移区；
栅极结构，位于所述深阱上；以及
第二导电类型的源区和第二导电类型的漏区，所述源区位于所述沟道区中，所述漏区位于所述漂移区中。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
本发明的下列附图在此作为本发明的一部分用于理解本发明。附图中示出了本发明的实施例及其描述，用来解释本发明的原理。
附图中：
图1A-图1E为根据本发明的一个实施例的一种半导体器件的制造方法中形成的半导体器件的结构示意图；
图2为根据本发明的一个实施例的一种半导体器件的制造方法的流程图。
具体实施方式
在下文的描述中，给出了大量具体的细节以便提供对本发明更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本发明可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本发明发生混淆，对于本领域公知的一些技术特征未进行描述。
为了彻底理解本发明，将在下列的描述中提出详细的描述，以说明本发明的半导体器件的制造方法、半导体器件和电子装置。显然，本发明的施行并不限于半导体领域技术人员所熟习的特殊细节。本发明的较佳实施例详细描述如下，然而除了这些详细描述外，本发明还可以具有其他实施方式。
应予以注意的是，这里所使用的术语仅是为了描述具体实施例，而非意图限制根据本发明的示例性实施例。如在这里所使用的，除非上下文另外明确指出，否则单数形式也意图包括复数形式。此外，还应当理解的是，当在本说明书中使用术语“包含”和/或“包括”时，其指明存在所述特征、整体、步骤、操作、元件和/或组件，但不排除存在或附加一个或多个其他特征、整体、步骤、操作、元件、组件和/或它们的组合。
现在，将参照附图更详细地描述根据本发明的示例性实施例。然而，这些示例性实施例可以多种不同的形式来实施，并且不应当被解释为只限于这里所阐述的实施例。应当理解的是，提供这些实施例是为了使得本发明的公开彻底且完整，并且将这些示例性实施例的构思充分传达给本领域普通技术人员。在附图中，为了清楚起见，夸大了层和区域的厚度，并且使用相同的附图标记表示相同的元件，因而将省略对它们的描述。
实施例一
一种示例性的降低导通电阻的高压NMOS器件结构利用外延加埋层注入的工艺形成NPNP的结构由于N型漂移区被P型区包住，能够获得更好的漂移区耗尽效果，因此漂移区浓度可以做得更浓，从而器件导通电阻可以做得更低。但是由于需要额外的外延工艺以及埋层的工艺，不但增加了工艺成本 还增加了工艺难度。
本发明提供了一种半导体器件的制造方法，包括：
提供第一导电类型的半导体衬底，在所述半导体衬底中形成第二导电类型的深阱；
在所述深阱中形成第一导电类型的沟道区、第一导电类型的阱区和第二导电类型的阱区，所述第一导电类型的阱区与所述沟道区之间被部分所述深阱的区域间隔开，所述漂移区位于所述沟道区和所述第一导电类型的阱区之间；
在所述深阱中形成第一导电类型的离子注入区，所述第一导电类型的离子注入区位于所述漂移区下方，以使所述沟道区、所述第一导电类型的阱区和所述第一导电类型的离子注入区包围所述漂移区；
在所述深阱中形成第二导电类型的源区和第二导电类型的漏区，其中，所述源区位于所述沟道区中，所述漏区位于所述漂移区中。
下面参考图1A-图1E和图2对根据本发明的半导体器件的制造方法进行示意性说明，其中图1A-图1E为根据本发明的一个实施例的一种半导体器件的制造方法中形成的半导体器件的结构示意图；图2为根据本发明的一个实施例的一种半导体器件的制造方法的流程图。
首先，参看图2，执行步骤S1：提供第一导电类型的半导体衬底，在所述半导体衬底中形成第二导电类型的深阱。
参看图1A，示出了根据本发明的一个实施例的在第一导电类型的半导体衬底中形成第二导电类型的深阱的半导体器件的结构示意图。如图1A所示，提供半导体衬底300，具体地，可以是以下所提到的材料中的至少一种：Si、Ge、SiGe、SiC、SiGeC、InAs、GaAs、InP、InGaAs或者其它III/V化合物半导体，还包括这些半导体构成的多层结构等，或者为绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。示例性的，所述半导体衬底为第一导电类型。
需要说明的是，本说明书中第一导电类型和第二导电类型泛指P型或N型，比如第一导电类型是P型，低掺杂P-型，高掺杂P+型其中之一，第二导电类型是N型，低掺杂N-型，高掺杂N+型其中之一。或者相反地，第一导 电类型是N型，低掺杂N-型，高掺杂N+型其中之一，第二导电类型是P型，低掺杂P-型，高掺杂P+型其中之一。
示例性的，在本实施例中，所述第一导电类型的半导体衬底为P型低掺杂的衬底。
示例性的，所述半导体衬底为非外延衬底。本实施例所述的半导体器件的制造方法在非外延的工艺平台上进行，将整个制造方法在非外延工艺平台上进行使制造过程中并不需要额外的外延工艺以及埋层的工艺，即通过优化器件结构设计可以在非外延工艺上获得更好的器件特性，减少了工艺成本，降低了工艺难度，还提高了工艺平台兼容性。
继续参看图1A在半导体衬底300中形成第二导电类型的深阱301。形成所述第二导电类型的深阱的方法包括：在所述半导体衬底上形成图案化的掩膜层，所述图案化的掩膜层露出所述拟形成第二导电类型的深阱的区域；执行第二导电类型的深阱离子注入，在所述第一导电类型半导体衬底中形成第二导电类型的深阱；去除所述图案化的掩膜层。示例性的，第二导电类型的深阱离子注入为高能离子注入。
示例性的，在完成所述第二导电类型的深阱离子注入之后，还包括执行第二导电类型的深阱退火的步骤。
在本实施例中，所述第一导电类型的半导体衬底为P型低掺杂的衬底，即P-衬底，所述第二导电类型的深阱为N阱。
示例性的，所述第二导电类型的深阱的掺杂浓度在深度方向上随着深度增加而增加。
将第二导电类型的深阱的掺杂浓度设置为在深度方向上随着深度的增加而增加，可进一步加强第二导电类型的深阱在器件结构中所起的隔离作用，尤其是对后续在第二导电类型的深阱中形成的其他阱区起到更好的隔离，在在第二导电类型的深阱中形成的其他阱区可以为第一导电类型的阱区。
示例性的，如图1A所示，在半导体衬底300中形成第二导电类型的深阱301之前还包括在半导体衬底300中形成隔离结构302的步骤。隔离结构302为浅沟槽隔离结构，形成浅沟槽隔离结构的方法包括：执行光刻工艺，以在半导体衬底上形成图案化的掩膜层，所述图案化的掩膜层露出拟形成隔离结构的区域；执行刻蚀工艺，以所述图案化的掩膜层为掩膜刻蚀半导体衬底，以在半导体衬底中形成浅沟槽；执行沉积工艺，以形成填充所述浅沟槽的隔离材料层；执行化学机械研磨工艺，以移除所述浅沟槽以外的隔离材料 层。
示例性的，所述隔离结构包括第一隔离结构和第二隔离结构，所述第一隔离结构位于拟形成漂移区和拟形成第一导电类型的阱区的区域之间，所述第二隔离结构位于拟形成第一导电类型的阱区和拟形成第二导电类型的阱区之间。
接着，继续参看图2，执行步骤S2：在所述深阱中形成第一导电类型的沟道区、第一导电类型的阱区和第二导电类型的阱区，所述第一导电类型的阱区与所述沟道区之间被部分所述深阱的区域间隔开，所述漂移区位于所述沟道区和所述第一导电类型的阱区之间。
参看图1B，示出了根据本发明的一个实施例的在第二导电类型的深阱中形成第一导电类型的沟道区、第一导电类型的阱区的半导体器件的结构示意图。如图1B所示，在半导体衬底300中的第二导电类型的深阱301的区域形成第一导电类型的沟道区303和第一导电类型的阱区304。其中，第一导电类型的阱区304与沟道区303之间被部分第二导电类型的深阱301的区域间隔。
示例性的，形成第一导电类型的沟道区303的步骤包括：执行光刻工艺，形成露出拟形成沟道区的图案化的掩膜层；执行离子注入工艺，形成所述沟道区。
在本实施例中，所述第一导电类型的半导体衬底为P型低掺杂的衬底，即P-衬底，所述第二导电类型的深阱为N阱，所述第一导电类型的沟道区为P型掺杂区。
示例性的，形成第一导电类型的阱区304的步骤包括：执行光刻工艺，形成露出拟形成第一导电类型的阱区的图案化的掩膜层；执行离子注入工艺，形成所述第一导电类型的阱区。
在本实施例中，所述第一导电类型的半导体衬底为P型低掺杂的衬底，即P-衬底，所述第二导电类型的深阱为N阱，所述第一导电类型的阱区为P型掺杂区。
在深阱中形成第一导电类型的阱区，该第一导电类型的阱区与第一导电类型沟道区、以及后续在漂移区下方形成的第一导电类型离子注入区一起对漂移区形成包围结构，有效提升漏端漂移区的耗尽，提升击穿电压。最终实现LDMOS器件中的NPNP器件结构，大大提升了器件的性能。并且在其中 并不需要形成埋层的过程，即能实现高压器件结构。
在根据本发明的一个示例中，所述形成第一导电类型的沟道区的步骤和所述形成第一导电类型的阱区的步骤使用同一掩膜和同一离子注入步骤，以减少工艺步骤，减少工艺成本。
需要理解的是，本实施例中以第一导电类型的沟道区和第一导电类型的阱区在同一步骤中形成为示例进行说明仅仅是示例性的，本领域技术人员应当理解，第一导电类型的沟道区和第一导电类型的阱区也可以在不同的步骤中形成，其亦能实现本发明的技术效果。
参看图1C，示出了根据本发明的一个实施例的在第二导电类型的深阱中形成第二导电类型的漂移区后的半导体器件的结构示意图。
如图1C所示，在半导体衬底300的第二导电类型的深阱301中形成第二导电类型漂移区305，漂移区305位于沟道区303和第一导电类型的阱区304之间的区域。
示例性的，形成第二导电类型的漂移区305的步骤包括：执行光刻工艺，形成露出拟形成第二导电类型的漂移区的图案化的掩膜层；执行离子注入工艺，形成所述第二导电类型的漂移区。
在本实施例中，所述第一导电类型的半导体衬底为P型低掺杂的衬底，即P-衬底，所述第二导电类型的深阱为N阱，所述第二导电类型的漂移区为N型掺杂区。
示例性的，在根据本发明的一个示例中，在形成漂移区的过程中，还包括在所述深阱中形成第二导电类型的阱区的步骤，所述第二导电类型的阱区设置在所述第一导电类型的阱区的远离所述沟道区的一侧。第二导电类型的阱区用于形成第二导电类型的深阱的接触区，将第二导电类型的深阱接出，同时，对第一导电类型的阱区与半导体衬底之间起到隔离作用。
继续参看图1C，在半导体衬底300的第二导电类型的深阱301中形成第二导电类型的阱区306，其中，第二导电类型的阱区306设置在第一导电类型的阱区304远离沟道区303的一侧。
示例性的，形成第二导电类型的阱区306的步骤包括：执行光刻工艺，形成露出拟形成第二导电类型的阱区的图案化的掩膜层；执行离子注入工艺，形成所述第二导电类型的阱区。
在本实施例中，所述第一导电类型的半导体衬底为P型低掺杂的衬底，即P-衬底，所述第二导电类型的深阱为N阱，所述第二导电类型的阱区为N 型掺杂区。
需要理解的是，本实施例中，在形成漂移区之后形成第二导电类型的阱区仅仅是示例性的，本领域技术人员应当理解，在执行步骤形成漂移区的过程中、形成漂移区之前形成第二导电类型的阱区也可以实现本发明。
接着，继续参看图2，执行步骤S3：在所述深阱中形成第一导电类型离子注入区，所述第一导电类型离子注入区位于所述漂移区下方，以使所述沟道区、所述第一导电类型的阱区和所述第一导电类型离子注入区包围所述漂移区。
参看图1D，示出了根据本发明的一个实施例的在第二导电类型的漂移区下方形成第一导电类型离子注入区后的半导体器件的结构示意图。
如图1D所示，在半导体衬底300的第二导电类型的深阱301中形成第一导电类型离子注入区307，第一导电类型离子注入区307位于漂移区305下方，使第一导电类型的沟道区303、第一导电类型的阱区304和第一导电类型离子注入区307将漂移区305包围。
示例性的，形成第一导电类型离子注入区307的步骤包括：执行光刻工艺，形成露出拟形成漂移区的图案化的掩膜层；执行离子注入工艺，形成所述第一导电类型离子注入区307。
在本实施例中，所述第一导电类型的半导体衬底为P型低掺杂的衬底，即P-衬底，所述第二导电类型的深阱为N阱，所述第一导电类型离子注入区307为P型掺杂区。
在漂移区下方形成第一导电类型离子注入区，该第一导电类型离子注入区与第一导电类型沟道区、第一导电类型的阱区一起对漂移区形成包围结构，有效提升漏端漂移区的耗尽，提升击穿电压。最终实现LDMOS器件中的NPNP器件结构，使沟道区与半导体衬底之间被深阱的区域隔离开来，使沟道区不受衬底电压的影响，大大提升了器件的性能。并且在其中并不需要形成埋层的过程，即能实现高压器件结构。
在根据本发明的一个示例中，所述在所述深阱中形成漂移区的步骤和所述在所述深阱中形成第一导电类型离子注入区的步骤共用一套掩膜版，以减少工艺成本。
进一步，在根据本发明的一个示例中，在所述深阱中形成漂移区之后执行所述在所述深阱中形成第一导电类型离子注入区的步骤，以使所述形成漂 移区的步骤和所述形成第一导电类型离子注入区的步骤使用同一掩膜层，相对于现有工艺，并不需要增加额外的工艺流程，实现新的器件结构，大大减少了工艺成本。
需要指出的是，本实施例中，将沟道区与第一导电类型的阱区、漂移区、第二导电类型的阱区、第一导电类型离子注入区等分别在步骤S2和S3中形成，其并不是要对形成沟道区、第一导电类型的阱区、漂移区、第二导电类型的阱区、第一导电类型离子注入区的顺序进行限定，本领域技术人员可以以任何可行的顺序形成导电类型阱区、漂移区、第二导电类型的阱区、第一导电类型离子注入区，其均能实现在不采用外延和形成埋层的情况下，实现本发明的半导体器件的制造，实现本发明的技术效果。
接着，继续参看图2，执行步骤S4：在所述深阱中形成第二导电类型的源区和第二导电类型的漏区，其中，所述源区位于所述沟道区中，所述漏区位于所述漂移区中。
参看图1E，示出了根据本发明的一个实施例的形成源区和漏区后的半导体器件的结构示意图。如图1E所示，在半导体衬底300中形成源区308和漏区309，其中源区308位于沟道区303之中，漏区309位于漂移区305之中。
在本实施例中，所述第一导电类型的半导体衬底为P型低掺杂的衬底，即P-衬底，所述第二导电类型的深阱为N阱，所述源区和漏区为N+型掺杂区。
在根据本发明的一个示例中，在形成源区和漏区之前还包括形成栅极结构的步骤。如图1E所示，在半导体衬底300的表面形成包括栅极介电层310和栅极材料层311的栅极结构，栅极结构露出拟形成源区和漏区的区域。示例性的，形成栅极结构的步骤采用本领域所通用的工艺，在此不再赘述。
在根据本发明的一个示例中，还包括在半导体衬底中形成第一导电类型的阱区引出区和第二导电类型的阱区引出区。
在本实施例中，所述第一导电类型为P型，第二导电类型为N型，则第一导电类型的半导体衬底为P型低掺杂的衬底，即P-衬底，第二导电类型的漂移区为N型漂移区。
如图1E所示，第一导电类型的阱区304、第一导电类型离子注入区307、 沟道区303组成包围第二导电类型的漂移区305的第一P型包围结构；
第二导电类型的阱区306、第二导电类型的深阱301组成包围上述第一P型包围结构的N型包围结构；
最外围的第一导电类型的半导体衬底300组成包围N型包围结构的第二P型包围结构。
N型漂移区、第一P型包围结构、N型包围结构、第二P型包围结构在器件结构中构成NPNP结构，提高击穿电压和降低导通电阻。
对于该NPNP结构，第一导电类型的阱区引出区312和第二导电类型的阱区引出区313，用于将第一导电类型的阱区304和第二导电类型的阱区306引出连接至外电路。漏区309与第二导电类型的阱区306之间独立分开，漏区309与第二导电类型的深阱301之间也独立分开，使得漏区309与第二导电类型的阱区引出区313可以在电路应用中分开接不同的电压。同时，第一导电类型的阱区引出区312和第一导电类型的半导体衬底300被第二导电类型的阱区306和第二导电类型的深阱301分隔开来。也就是说，第一P型包围结构与第二P型包围结构被N型包围结构分隔开来，能够确保第一P型包围结构作为体区可以抬压但不受第二P型包围结构的影响，实现了体区可以抬压但不受衬底的影响，还能够提高击穿电压和降低导通电阻。不需要外延和形成埋层的工艺，就能实现NPNP结构，大大减少了工艺流程，减小了生产成本。同时，根据本发明的半导体器件具有更高的击穿电压和更低的导通电阻。
在本实施例中，所述第一导电类型的半导体衬底为P型低掺杂的衬底，即P-衬底，所述第二导电类型的深阱为N阱，第一导电类型的阱区为P型掺杂区，第二导电类型的阱区为N型掺杂区，第一导电类型的阱区引出区为P+型掺杂区和第二导电类型的阱区引出区为N+型掺杂区。
实施例二
本发明还提供了一种半导体器件，包括：
第一导电类型的半导体衬底；
位于所述半导体衬底中的第二导电类型的深阱；
位于所述深阱中的第一导电类型的沟道区、第一导电类型的阱区、以及第二导电类型漂移区，所述漂移区位于所述沟道区与所述第一导电类型的阱区之间；以及
源区和漏区，所述源区位于所述沟道区中，所述漏区位于所述漂移区中；
其中，还包括：
位于所述漂移区下方的第一导电类型离子注入区，所述沟道区、所述第一导电类型的阱区和所述第一导电类型离子注入区包围所述漂移区。
参看图1E，示出了根据本发明的一个实施例的半导体器件的结构示意图。
如图1E所示，根据本发明的半导体器件包括第一导电类型的半导体衬底300。半导体衬底300，具体地，可以是以下所提到的材料中的至少一种：Si、Ge、SiGe、SiC、SiGeC、InAs、GaAs、InP、InGaAs或者其它III/V化合物半导体，还包括这些半导体构成的多层结构等，或者为绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。示例性的，所述半导体衬底为第一导电类型。
需要说明的是，本说明书中第一导电类型和第二导电类型泛指P型或N型，比如第一导电类型是P型，低掺杂P-型，高掺杂P+型其中之一，第二导电类型是N型，低掺杂N-型，高掺杂N+型其中之一。或者相反地，第一导电类型是N型，低掺杂N-型，高掺杂N+型其中之一，第二导电类型是P型，低掺杂P-型，高掺杂P+型其中之一。
示例性的，在本实施例中，所述第一导电类型的半导体衬底为P型低掺杂的衬底。
示例性的，所述半导体衬底为非外延衬底。本实施例所述的半导体器件在非外延的工艺平台上形成，将整个制造方法在非外延工艺平台上进行使制造过程中并不需要额外的外延工艺以及埋层的工艺，即通过优化器件结构设计可以在非外延工艺上获得更好的器件特性，减少了工艺成本，降低了工艺难度，还提高了工艺平台兼容性。
继续参看图1E，根据本发明的半导体器件还包括位于半导体衬底300中的第二导电类型的深阱301。
在本实施例中，所述第一导电类型的半导体衬底为P型低掺杂的衬底，即P-衬底，所述第二导电类型的深阱为N阱，所述第二导电类型的深阱为N型掺杂的低掺杂区域。
示例性的，所述第二导电类型的深阱的掺杂浓度在深度方向上随着深度增加而增加。
将第二导电类型的深阱的掺杂浓度设置为在深度方向上随着深度的增加而增加，在后续形成第一导电类型的阱区时，能够通过掺杂浓度增加的深阱区域隔离半导体衬底和第一掺杂类型阱区。使后续形成的从漏端到半导体衬底之间的NPNP结构更加稳定可靠。
继续参看图1E，根据本发明的半导体器件还包括位于第二导电类型的深阱301中的第一导电类型的沟道区303、第一导电类型的阱区304、以及第二导电类型漂移区305，其中，所述漂移区305位于所述沟道区303与所述第一导电类型的阱区304之间。
在本实施例中，所述第一导电类型的半导体衬底为P型低掺杂的衬底，即P-衬底，所述第二导电类型的深阱为N阱，所述第一导电类型的沟道区为P型掺杂区，所述第一导电类型的阱区为P型掺杂区，所述第二导电类型的漂移区为N型掺杂区。
在深阱中形成第一导电类型的阱区，该第一导电类型的阱区与第一导电类型沟道区，以及后续在漂移区下方形成的第一导电类型离子注入区一起对漂移区形成包围结构，有效提升漏端漂移区的耗尽，提升击穿电压。最终实现LDMOS器件中的NPNP器件结构，大大提升了器件的性能。并且在其中并不需要形成埋层的过程，即能实现高压器件结构。
继续参看图1E，根据本发明的半导体器件还包括源区308和漏区309，所述源区308位于所述沟道区303中，所述漏区309位于所述漂移区305中。
在本实施例中，所述第一导电类型的半导体衬底为P型低掺杂的衬底，即P-衬底，所述第二导电类型的深阱为N阱，所述源区和漏区为N+型掺杂区。
继续参看图1E，根据本发明的半导体器件还包括位于所述漂移区305下方的第一导电类型离子注入区307，所述沟道区303、所述第一导电类型的阱区304和所述第一导电类型离子注入区307包围所述漂移区305。
在漂移区下方形成第一导电类型离子注入区，该第一导电类型离子注入区与第一导电类型沟道区、第一导电类型的阱区一起对漂移区形成包围结构，有效提升漏端漂移区的耗尽，提升击穿电压。最终实现LDMOS器件中的NPNP器件结构，大大提升了器件的性能。并且在其中并不需要形成埋层的过程，即能实现高压器件结构。
在本实施例中，所述第一导电类型的半导体衬底为P型低掺杂的衬底，即P-衬底，所述第二导电类型的深阱为N阱，所述第一导电类型离子注入区 307为P型掺杂区。
在根据本发明的一个示例中，半导体器件还包括第二导电类型的阱区306，所述第二导电类型的阱区306设置在所述第一导电类型的阱区304的远离所述沟道区303的一侧。第二导电类型的阱区用于形成第二导电类型的深阱的接触区，将第二导电类型的深阱接出，同时，对第一导电类型的阱区与半导体衬底之间起到隔离作用。
在本实施例中，所述第一导电类型的半导体衬底为P型低掺杂的衬底，即P-衬底，所述第二导电类型的深阱为N阱，所述第二导电类型的阱区为N型掺杂区。
在根据本发明的一个示例中，还包括在半导体衬底中形成第一导电类型的阱区引出区和第二导电类型的阱区引出区。
如图1E所示，第一导电类型的阱区引出区312和第二导电类型的阱区引出区313，用于将第一导电类型的阱区304和第二导电类型的阱区306引出连接至外电路。漏区309与第二导电类型的阱区306之间独立分开，漏区309与第二导电类型的深阱301之间也独立分开，使得漏区309与第二导电类型的阱区引出区313可以在电路应用中分开接不同的电压。同时，第一导电类型的阱区引出区312和第一导电类型的半导体衬底300被第二导电类型的阱区306和第二导电类型的深阱301分隔开来，能够提高击穿电压和降低导通电阻。不需要外延和形成埋层的工艺，就能实现NPNP结构，大大减少了工艺流程，减小了生产成本。同时，根据本发明的半导体器件具有更高的击穿电压和更低的导通电阻。
在根据本发明的一个示例中，还包括栅极结构。
如图1E所示，在半导体衬底300的表面还设置有包括栅极介电层310和栅极材料层311的栅极结构。
在根据本发明的一个示例中，还包括形成在半导体衬底中的隔离结构302。示例性的，所述隔离结构包括第一隔离结构和第二隔离结构，所述第一隔离结构位于漂移区和第一导电类型的阱区的区域之间，所述第二隔离结构位于第一导电类型的阱区和第二导电类型的阱区之间。
在根据本发明的一个示例中，根据如实施例一所述的半导体器件的制造方法制造的半导体器件。
根据本发明的半导体器件，通过设置包围漂移区的阱区、离子注入区和沟道区，具有新颖的结构的同时有效改善了漏端漂移区的耗尽，提升了击穿 电压，降低了导通电阻。根据本发明的半导体器件通过将漂移区、阱区、离子注入区和沟道区设置在位于半导体衬底的深阱中，实现LDMOS器件中的NPNP器件结构，使沟道区与半导体衬底之间被深阱的区域隔离开来，使沟道区不受衬底电压的影响，大大提升了器件的性能；器件结构中不设置埋层，可以限制简化制造流程，降低生产成本。
本发明已经通过上述实施例进行了说明，但应当理解的是，上述实施例只是用于举例和说明的目的，而非意在将本发明限制于所描述的实施例范围内。此外本领域技术人员可以理解的是，本发明并不局限于上述实施例，根据本发明的教导还可以做出更多种的变型和修改，这些变型和修改均落在本发明所要求保护的范围以内。本发明的保护范围由附属的权利要求书及其等效范围所界定。

Claims (15)

  1. 一种半导体器件的制造方法，包括：
    提供第一导电类型的半导体衬底，在所述半导体衬底中形成第二导电类型的深阱；
    在所述深阱中形成第一导电类型的沟道区、第一导电类型的阱区和第二导电类型的漂移区，所述第一导电类型的阱区与所述沟道区之间被部分所述深阱的区域间隔开，所述漂移区位于所述沟道区和所述第一导电类型的阱区之间；
    在所述深阱中形成第一导电类型的离子注入区，所述第一导电类型的离子注入区位于所述漂移区下方，以使所述沟道区、所述第一导电类型的阱区和所述第一导电类型的离子注入区包围所述漂移区；以及
    在所述深阱中形成第二导电类型的源区和第二导电类型的漏区，其中，所述源区位于所述沟道区中，所述漏区位于所述漂移区中。
  2. 根据权利要求1所述的制造方法，其特征在于，所述在所述深阱中形成漂移区的步骤和所述在所述深阱中形成第一导电类型的离子注入区的步骤共用一套掩膜版和/或同一掩膜层。
  3. 根据权利要求1所述的制造方法，其特征在于，所述第一导电类型的沟道区和所述第一导电类型的阱区在同一离子注入步骤中形成。
  4. 根据权利要求1所述的制造方法，其特征在于，还包括在所述深阱中形成第二导电类型的阱区，所述第二导电类型的阱区设置在所述第一导电类型的阱区的远离所述沟道区的一侧。
  5. 根据权利要求1所述的制造方法，其特征在于，所述深阱的掺杂浓度在深度方向上随着深度增加而增加。
  6. 根据权利要求1所述的制造方法，其特征在于，在非外延的工艺平台上进行。
  7. 根据权利要求1所述的制造方法，其特征在于，所述在所述深阱中形成第二导电类型的源区和第二导电类型的漏区的步骤之前，还包括形成栅极结构的步骤。
  8. 一种半导体器件，包括：
    第一导电类型的半导体衬底；
    第二导电类型的深阱，自所述半导体衬底上表面向所述半导体衬底内部延伸；
    第一导电类型的沟道区，位于所述深阱中；
    第一导电类型的阱区，位于所述深阱中；
    第二导电类型的漂移区，位于所述深阱中，且所述漂移区位于所述沟道区与所述第一导电类型的阱区之间，所述漂移区与所述沟道区间隔设置，所述漂移区与所述第一导电类型的阱区相邻设置；
    第一导电类型离子注入区，位于所述深阱中且在所述漂移区下方，所述沟道区、所述第一导电类型的阱区和所述离子注入区包围所述漂移区；
    第二导电类型的源区位于所述沟道区中；以及
    第二导电类型的漏区，位于所述漂移区中。
  9. 根据权利要求8所述的半导体器件，其特征在于，还包括位于所述深阱上的栅极结构。
  10. 根据权利要求8所述的半导体器件，其特征在于，所述半导体器件是横向双扩散金属氧化物半导体场效应晶体管。
  11. 根据权利要求8所述的半导体器件，其特征在于，所述半导体衬底为非外延衬底。
  12. 根据权利要求8所述的半导体器件，其特征在于，还包括位于所述深阱中的第二导电类型的阱区，所述第二导电类型的阱区设置在所述第一导电类型的阱区的远离所述沟道区的一侧。
  13. 根据权利要求12所述的半导体器件，其特征在于，还包括位于所述第一导电类型的阱区中的第一导电类型的阱区引出区，以及位于所述第二导电类型的阱区中的第二导电类型的阱区引出区。
  14. 根据权利要求12所述的半导体器件，其特征在于，还包括隔离结构，所述隔离结构，所述隔离结构包括第一隔离结构和第二隔离结构，所述第一隔离结构位于所述漂移区和所述第一导电类型的阱区之间，所述第二隔离结构位于所述第一导电类型的阱区和所述第二导电类型的阱区之间。
  15. 根据权利要求8所述的半导体器件，其特征在于，所述深阱的掺杂浓度在深度方向上随着深度增加而增加。
PCT/CN2021/101751 2020-07-20 2021-06-23 一种半导体器件的制造方法、半导体器件 Ceased WO2022017110A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2022557168A JP7589257B2 (ja) 2020-07-20 2021-06-23 半導体デバイスの製造方法、半導体デバイス
US17/886,609 US12593465B2 (en) 2020-07-20 2022-08-12 Method for manufacturing semiconductor device, and semiconductor device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010698017.4 2020-07-20
CN202010698017.4A CN113964035B (zh) 2020-07-20 2020-07-20 一种半导体器件的制造方法、半导体器件

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/886,609 Continuation US12593465B2 (en) 2020-07-20 2022-08-12 Method for manufacturing semiconductor device, and semiconductor device

Publications (1)

Publication Number Publication Date
WO2022017110A1 true WO2022017110A1 (zh) 2022-01-27

Family

ID=79459737

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/101751 Ceased WO2022017110A1 (zh) 2020-07-20 2021-06-23 一种半导体器件的制造方法、半导体器件

Country Status (4)

Country Link
US (1) US12593465B2 (zh)
JP (1) JP7589257B2 (zh)
CN (1) CN113964035B (zh)
WO (1) WO2022017110A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115274859B (zh) * 2022-09-30 2023-01-20 北京芯可鉴科技有限公司 Ldmos晶体管及其制造方法
CN116313811A (zh) * 2023-04-23 2023-06-23 上海华虹宏力半导体制造有限公司 高压nldmos器件及工艺方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102044563A (zh) * 2009-10-16 2011-05-04 上海华虹Nec电子有限公司 Ldmos器件及其制造方法
CN104617139A (zh) * 2013-11-05 2015-05-13 上海华虹宏力半导体制造有限公司 Ldmos器件及制造方法
CN105226058A (zh) * 2014-06-30 2016-01-06 万国半导体股份有限公司 利用深扩散区在单片功率集成电路中制备jfet和ldmos晶体管
CN106663699A (zh) * 2014-08-07 2017-05-10 德州仪器公司 用于具有经级联resurf植入部及双缓冲器的ldmos装置的方法及设备
US20170263763A1 (en) * 2014-12-23 2017-09-14 Magnachip Semiconductor, Ltd. Semiconductor device
CN107425046A (zh) * 2016-05-23 2017-12-01 中芯国际集成电路制造(北京)有限公司 一种ldmos器件及其制作方法
CN109979801A (zh) * 2017-12-28 2019-07-05 无锡华润上华科技有限公司 一种半导体器件的制造方法和半导体器件

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6548874B1 (en) * 1999-10-27 2003-04-15 Texas Instruments Incorporated Higher voltage transistors for sub micron CMOS processes
TW200741892A (en) * 2006-03-02 2007-11-01 Volterra Semiconductor Corp A lateral double-diffused MOSFET (LDMOS) transistor and a method of fabricating
JP5172223B2 (ja) * 2007-06-19 2013-03-27 ローム株式会社 半導体装置
JP4568325B2 (ja) * 2007-12-20 2010-10-27 シャープ株式会社 半導体装置及びその製造方法
JP5311003B2 (ja) * 2008-07-03 2013-10-09 セイコーエプソン株式会社 半導体装置
US8482063B2 (en) * 2011-11-18 2013-07-09 United Microelectronics Corporation High voltage semiconductor device
US8492835B1 (en) * 2012-01-20 2013-07-23 United Microelectronics Corporation High voltage MOSFET device
US9269806B2 (en) * 2013-10-03 2016-02-23 Macronix International Co., Ltd. Semiconductor device and method of fabricating same
CN105720098B (zh) * 2014-12-02 2019-01-29 中芯国际集成电路制造(上海)有限公司 Nldmos及其制作方法
US10340357B2 (en) * 2017-09-25 2019-07-02 Taiwan Semiconductor Manufacturing Co., Ltd. Dishing prevention dummy structures for semiconductor devices

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102044563A (zh) * 2009-10-16 2011-05-04 上海华虹Nec电子有限公司 Ldmos器件及其制造方法
CN104617139A (zh) * 2013-11-05 2015-05-13 上海华虹宏力半导体制造有限公司 Ldmos器件及制造方法
CN105226058A (zh) * 2014-06-30 2016-01-06 万国半导体股份有限公司 利用深扩散区在单片功率集成电路中制备jfet和ldmos晶体管
CN106663699A (zh) * 2014-08-07 2017-05-10 德州仪器公司 用于具有经级联resurf植入部及双缓冲器的ldmos装置的方法及设备
US20170263763A1 (en) * 2014-12-23 2017-09-14 Magnachip Semiconductor, Ltd. Semiconductor device
CN107425046A (zh) * 2016-05-23 2017-12-01 中芯国际集成电路制造(北京)有限公司 一种ldmos器件及其制作方法
CN109979801A (zh) * 2017-12-28 2019-07-05 无锡华润上华科技有限公司 一种半导体器件的制造方法和半导体器件

Also Published As

Publication number Publication date
US12593465B2 (en) 2026-03-31
JP2023518495A (ja) 2023-05-01
CN113964035A (zh) 2022-01-21
CN113964035B (zh) 2023-05-02
US20220384641A1 (en) 2022-12-01
JP7589257B2 (ja) 2024-11-25

Similar Documents

Publication Publication Date Title
US8334567B2 (en) LDMOS using a combination of enhanced dielectric stress layer and dummy gates
US7508032B2 (en) High voltage device with low on-resistance
CN107425046B (zh) 一种ldmos器件及其制作方法
CN112825327B (zh) 半导体结构及其形成方法
WO2011066730A1 (zh) 混合晶向反型模式全包围栅cmos场效应晶体管
WO2011066728A1 (zh) 混合材料积累型全包围栅cmos场效应晶体管
US9748377B2 (en) Semiconductor device and method of manufacturing the same
KR100279264B1 (ko) 더블 게이트 구조를 갖는 에스·오·아이 트랜지스터 및 그의제조방법
US12230693B2 (en) Semiconductor device and manufacturing method therefor
US12593465B2 (en) Method for manufacturing semiconductor device, and semiconductor device
CN113764502B (zh) 一种ldmos半导体器件及其制造方法
WO2020073459A1 (zh) 半导体器件及其制造方法及包括该器件的电子设备
EP4672903A1 (en) SEMICONDUCTOR DEVICE AND ITS MANUFACTURING PROCESS
CN106952960B (zh) 一种具有槽形结构的应变nldmos器件
WO2025001381A1 (zh) Soi半导体结构及其制造方法
US9929283B1 (en) Junction field effect transistor (JFET) with first and second top layer of opposite conductivity type for high driving current and low pinch-off voltage
US11545396B2 (en) Semiconductor structure and method for forming the same
CN109980010B (zh) 一种半导体器件的制造方法和集成半导体器件
WO2023108789A1 (zh) 一种半导体器件及其制造方法
CN108878505B (zh) 半导体装置及其制造方法
CN116053279B (zh) 一种半导体器件及其制造方法
JPH0669502A (ja) Ｍｉｓ型高耐圧トランジスタ
CN115394654A (zh) Dddmos器件及其制造方法
CN121888674A (zh) 半导体结构及其形成方法
CN119521733A (zh) 结型场效应晶体管装置及其制造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21846964

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2022557168

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21846964

Country of ref document: EP

Kind code of ref document: A1