WO2022017108A1 - 半导体结构的制备方法及半导体结构 - Google Patents

半导体结构的制备方法及半导体结构 Download PDF

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WO2022017108A1
WO2022017108A1 PCT/CN2021/101628 CN2021101628W WO2022017108A1 WO 2022017108 A1 WO2022017108 A1 WO 2022017108A1 CN 2021101628 W CN2021101628 W CN 2021101628W WO 2022017108 A1 WO2022017108 A1 WO 2022017108A1
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layer
semiconductor structure
passivation
protective layer
fabricating
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French (fr)
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徐亚超
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W99/00—Subject matter not provided for in other groups of this subclass

Definitions

  • the present disclosure relates to the technical field of semiconductors, and in particular, to a method for preparing a semiconductor structure and a semiconductor structure.
  • FIG. 1 representatively shows a layered diagram of a conventional semiconductor structure.
  • a semiconductor substrate 110 in the existing semiconductor structure, a semiconductor substrate 110 , a silicon dioxide layer 121 (SiO 2 ), a silicon nitride layer 122 (SIN) and a polyimide layer 123 (Polyimide) are included.
  • a metal connection layer 111 is formed on the material 110 , and a silicon dioxide layer 121 , a silicon nitride layer 122 and a polyimide layer 123 are sequentially formed on the metal connection layer 111 of the semiconductor substrate 110 . Due to the integrity of the crystal structure of the silicon dioxide crystal layer, water vapor will penetrate into the metal connection layer 111 through the silicon dioxide layer 121 in a certain way, thereby affecting the performance of the semiconductor device. The process requirements for thickness and film quality are high.
  • a silicon nitride layer 122 is usually grown before the polyimide layer 123 is coated, and the high density of the silicon nitride layer 122 is used to block the penetration of water vapor.
  • high-density plasma (HDP) technology as a high-density plasma dielectric layer process, is often used in the back-end preparation process of the passivation layer.
  • high-density plasma chemical vapor deposition (HDP-CVD) is a high-power deposition process, which easily damages the metal conductive layer on the top layer of the metal connection layer 111 and reduces the reliability of the metal connection layer 111 .
  • the discontinuous spare areas of the metal conductive layer are not protected by high-density materials, and water vapor still penetrates into the metal connection layer 111 through silicon dioxide, corroding the metal, and reducing the service life of the semiconductor device.
  • a main purpose of the present disclosure is to overcome at least one of the above-mentioned defects of the prior art, and to provide a method for fabricating a semiconductor structure that can sufficiently block water vapor penetration and reduce parasitic capacitance.
  • Another primary object of the present disclosure is to provide a semiconductor structure that overcomes at least one of the above-mentioned drawbacks of the prior art.
  • a method for preparing a semiconductor structure comprising the following steps:
  • the passivation layer includes a multilayer thin film structure, and the ion concentrations of the multilayer thin film structures are not identical;
  • a barrier layer and a second protective layer are sequentially formed on the insulating layer.
  • a semiconductor structure includes a semiconductor substrate, a conductive layer, a passivation layer, an insulating layer, a barrier layer and a second protective layer; the conductive layer is provided on the on the semiconductor substrate; the passivation layer is formed by passivation treatment of the first protective layer disposed on the surface of the conductive layer, the passivation layer includes a multilayer thin film structure, and the ions of the multilayer thin film structure are formed by passivation treatment.
  • the concentrations are not exactly the same; the insulating layer, the blocking layer and the second protective layer are sequentially arranged on the passivation layer.
  • the method for preparing a semiconductor structure and the semiconductor structure proposed by the present disclosure have at least the following advantages and positive effects:
  • the semiconductor structure proposed by the present disclosure by forming the first protective layer on the surface of the conductive layer, the conductive layer can be protected by the first protective layer.
  • the present disclosure forms a passivation layer with a multi-layer structure by performing passivation treatment on the first protective layer, and the ion concentration of at least a part of the passivation layer is larger than that of the first protective layer, which significantly optimizes the water vapor barrier effect. . Accordingly, the semiconductor structure proposed in the present disclosure can provide effective protection to the conductive layer thereof, and in particular, has a good water vapor barrier effect.
  • 1 is a layered diagram of a conventional semiconductor structure
  • FIG. 2 is a layered diagram of a semiconductor structure according to an exemplary embodiment
  • FIG. 3 is a layered view of a semiconductor structure in one step of a method for fabricating a semiconductor structure according to an exemplary embodiment
  • FIG. 4 is a layered view of a semiconductor structure in one step of a method for fabricating a semiconductor structure according to an exemplary embodiment
  • FIG. 5 is a layered view of a semiconductor structure in one step of a method for fabricating a semiconductor structure according to an exemplary embodiment
  • FIG. 6 is a layered view of a semiconductor structure in one step of a method for fabricating a semiconductor structure according to an exemplary embodiment
  • Fig. 7 is an enlarged view of part A in Fig. 6;
  • FIG. 8 is a layered view of a semiconductor structure in one step of a method for fabricating a semiconductor structure according to an exemplary embodiment
  • FIG. 9 is a layered view of a semiconductor structure in one step of a method for fabricating a semiconductor structure according to an exemplary embodiment
  • FIG. 10 is a layered view of a semiconductor structure in one step of a method for fabricating a semiconductor structure according to an exemplary embodiment
  • FIG. 11 is a layered view of a semiconductor structure in one step of a method for fabricating a semiconductor structure according to an exemplary embodiment.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments can be embodied in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.
  • FIG. 2 a layered diagram of the semiconductor structure proposed by the present disclosure is representatively shown, and the semiconductor structure is fabricated through the preparation method of the semiconductor structure proposed by the present disclosure.
  • the method for fabricating the semiconductor structure proposed in the present disclosure is described by taking the application to the fabrication of the transistor semiconductor structure as an example.
  • Those skilled in the art can easily understand that, in order to apply the related preparation methods of the present disclosure to other types of semiconductor structure preparation processes, various modifications, additions, substitutions, deletions or other modifications may be made to the following specific embodiments. variations, which are still within the scope of the principles of the method of making semiconductor structures presented in this disclosure.
  • FIG. 3 to FIG. 6 and FIG. 8 to FIG. 11 respectively represent layered diagrams of a semiconductor structure in one step of a method for fabricating a semiconductor structure that can embody the principles of the present disclosure.
  • Figure 7 representatively shows an enlarged view of part A in Figure 6. The process, material or sequence of each main step of the fabrication method of the semiconductor structure proposed by the present disclosure will be described in detail below with reference to the above drawings.
  • the preparation method of the semiconductor structure proposed by the present disclosure comprises the following steps:
  • a first protective layer 221 eg, silicon nitride, SiN
  • a passivation treatment is performed on the first protective layer 221, so that the first protective layer 221 forms a passivation layer 2211, and the passivation layer 2211 includes a multilayer thin film structure, and the ion concentrations of the multilayer thin film structure are not identical;
  • an insulating layer 222 eg, silicon dioxide, SiO 2 .
  • a barrier layer 223 and a second protective layer 224 are sequentially formed on the insulating layer 222 .
  • the present disclosure makes the first protective layer 221 form the passivation layer 2211 by performing passivation treatment on the first protective layer 221.
  • the passivation layer 2211 includes a multilayer thin film structure, and the ion concentrations of the multilayer thin film structure are not identical.
  • the ion concentration of at least one thin film structure of the passivation layer 2211 is larger than that of the first protective layer 221, which increases the density and significantly optimizes the water vapor barrier effect.
  • the multilayer thin film structure included in the passivation layer 2211 formed by the first protective layer 221 refers to the first protective layer 221
  • the ion concentration in some regions changes, so that the formed passivation layer 2211 has multiple regions with different ion concentrations. area.
  • the multilayer thin film structure of the passivation layer 2211 can be, for example, multiple layers stacked in sequence on the surface of the conductive layer 211, that is, multiple layered regions with different ion concentrations stacked in sequence, but not This is limited.
  • FIG. 3 which specifically shows a layered structure of a semiconductor substrate 210 , which can be used as a representative of the semiconductor substrate 210 in the step of “providing the semiconductor substrate 210 ” in this embodiment mode Example.
  • the semiconductor substrate 210 is formed with a conductive layer 211, and the conductive layer 211 has discontinuous empty regions 2113 in the extending direction.
  • the semiconductor substrate 210 provided in this step can also be selected in other forms, which is not limited to this embodiment.
  • the preparation method of the semiconductor structure proposed by the present disclosure may include the step of “forming a dielectric layer 226 on the conductive layer 211 before forming the first protective layer 221 on the conductive layer 211”, the dielectric layer
  • the 226 can be, for example, a material with a low dielectric constant such as SiCO, which can reduce the parasitic capacitance of the semiconductor device.
  • FIG. 4 specifically shows the layered structure after the dielectric layer 226 is formed on the conductive layer 211 of the semiconductor substrate 210 .
  • the dielectric layer 226 may preferably be a thin layer structure.
  • the so-called thin layer structure can be understood as, relative to other layers (such as the insulating layer 222 , the barrier layer 223 or the second protective layer 224 ) in the subsequent process
  • the thickness is thin.
  • the present disclosure can utilize the dielectric layer 226 with high density to release the stress of the first protective layer 221 that will be deposited on the upper layer in the subsequent process, and at the same time can utilize the dielectric layer 226 to protect the conductive layer 211.
  • the dielectric layer 226 since the dielectric layer 226 not only has a lower dielectric constant, but also has better density, the dielectric layer can also reduce the structural stress while reducing the parasitic capacitance of the semiconductor device.
  • the step of forming the dielectric layer 226 may also be omitted, or materials, process steps, etc. with similar functions may be used, which are not limited to this embodiment.
  • the method for preparing a semiconductor structure based on the present disclosure includes the step of forming a dielectric layer 226.
  • the thickness of the dielectric layer 226 may preferably be 10 nm ⁇ 100 nm, such as 10 nm, 35 nm, 80 nm, 100 nm. Wait.
  • the deposition thickness of the dielectric layer 226 may also be less than 10 nm, or may be greater than 100 nm, such as 8 nm, 110 nm, etc., which is not limited to this embodiment.
  • the first protective layer 221 is formed on the dielectric layer 226 .
  • the first protective layer 221 may preferably be a thin layer structure, and the so-called thin layer structure can be understood as, relative to other layers (for example, the insulating layer 222 , the barrier layer 223 or the second protective layer 224 ) in the subsequent process Thinner thickness.
  • the present disclosure can utilize the first protective layer 221 to provide protection for the sidewall of the conductive layer 211 in the discontinuous space region 2113 , and can optimize the water vapor barrier effect of the conductive layer 211 , especially the sidewall region.
  • the first protective layer 221 may be formed on the conductive layer 211, or may be formed on other protective structures formed on the conductive layer 211. It is not limited to this embodiment.
  • the thickness of the first protective layer 221 may preferably be 10 nm ⁇ 100 nm, such as 10 nm, 35 nm, 80 nm, 100 nm, and the like. In other embodiments, the thickness of the first protective layer 221 may also be less than 10 nm, or may be greater than 100 nm, such as 8 nm, 110 nm, etc., which is not limited to this embodiment.
  • FIG. 6 which specifically shows the layered structure after the passivation treatment is performed on the first protective layer 221 , which can be used as the “passivation of the first protective layer 221 in this embodiment”
  • FIG. 6 and FIG. 7 A representative example of a semiconductor structure in the "Processing" step.
  • the first protective layer 221 is treated by a passivation process such as plasma treatment technology, so that the first protective layer 221 is processed.
  • a passivation layer 2211 is formed by a protective layer 221 .
  • the passivation layer 2211 has a two-layer thin film structure, which are a first layer adjacent to the conductive layer 211 and a second layer disposed on the surface of the first layer, respectively.
  • the density of the second layer is increased, that is, the ion concentration of the second layer is increased (eg, the nitrogen ion content is increased), and the ion concentration of the second layer is higher than that of the first layer.
  • the present disclosure can make the first protective layer 221 form the passivation layer 2211 by performing plasma treatment on the first protective layer 221 , so that the ion concentration of each thin film structure of the passivation layer 2211 having a multi-layer thin film structure They are not completely the same, and the ion concentration of at least one thin film structure of the passivation layer 2211 is greater than that of the first protective layer 221, which further optimizes the water vapor barrier effect.
  • the passivation layer 2211 formed by the passivation treatment of the first protective layer 221 may also include three or more thin film structures, and the ion concentrations of the multilayer thin film structures are not identical.
  • the passivation may also use other processing techniques, such as ion implantation or thermal oxidation.
  • the passivation layer 2211 may include three or more thin film structures, and is not limited to the passivation formed after the passivation treatment in this embodiment.
  • Layer 221 is roughly divided into a two-layer design.
  • the ion concentrations of each layer of the multi-layer thin film structure of the passivation layer 2211 are not completely the same.
  • ions can be implanted into the middle region of the first protective layer 221, so that the first protective layer 221 is The density of ions (such as nitrogen ions) in the central region is greater than that of the remaining regions, so that the formed passivation layer 2211 generally includes three or more thin film structures, that is, at least one thin film structure in the central region has different ion concentrations The ion concentration of the thin film structure in (eg, greater than) the rest of the region.
  • ions can also be implanted into a region of the first protective layer 221 adjacent to the conductive layer 211 or a region away from the conductive layer 211 , so that the ion concentrations of the formed multilayer thin film structure of the passivation layer 2211 have different relationships. , are not limited to this embodiment.
  • the conductive layer 211 is described by taking a conductive structure including an upper metal 2111 and, for example, a titanium nitride layer 2112 as an example, and the titanium nitride layer 2112 is formed on the upper layer. Surface of metal 2111.
  • the lowermost thin film structure of the multilayer thin film structure of the passivation layer 2211 is actually adjacent to the layer of titanium nitride 2112 .
  • the plasma treatment may include ammonia gas plasma treatment, ie, ammonia gas (NH 3 )-based plasma treatment.
  • ammonia gas plasma treatment ie, ammonia gas (NH 3 )-based plasma treatment.
  • other plasma-based plasma treatment processes such as argon (Ar)-based plasma treatment, nitrogen (N 2 )-based plasma treatment, and other low-temperature plasma treatment processes may also be used, or Other types of plasma treatment processes are not limited to this embodiment.
  • FIG. 8 which specifically shows the layered structure after the insulating layer 222 is formed on the passivation layer 2211 , which can be used as “forming the insulating layer 222 on the passivation layer 2211” in this embodiment mode
  • this step is to form the insulating layer 222 on the passivation layer 2211 after the first protective layer 221 is subjected to plasma treatment to form the passivation layer 2211 from the first protective layer 221 .
  • the insulating layer 222 is not only formed on the part above the passivation layer 2211, but also filled in the discontinuous empty region 2113 of the conductive layer 211.
  • the forming process of the insulating layer 222 may include a high-density plasma chemical vapor deposition process.
  • the insulating layer 222 may also be formed on the passivation layer 2211 by other types of deposition processes or other processes, which is not limited to this embodiment.
  • an air hole 225 (Air Gap) can be formed in the discontinuous empty region 2113 of the conductive layer 211 .
  • the parasitic capacitance of the conductive layer 211 can be reduced, thereby reducing defects such as RC delay.
  • the present disclosure adopts the process step of forming the dielectric layer 226 on the surface of the conductive layer 211, the side and bottom surfaces of the discontinuous spare regions 2113 of the conductive layer 211 are also covered with the dielectric layer 226.
  • the discontinuous free region 2113 in the manufacturing method proposed in the present disclosure has a narrower width, that is, the height-to-width ratio of the discontinuous free region 2113 is increased compared to the corresponding structure in the prior art. Accordingly, compared with the design of the existing preparation method that requires multiple processes to form the air cavity, in the above-mentioned step of forming the air cavity 225 of the present disclosure, the air cavity 225 can be formed at one time, which further simplifies the process steps and improves the preparation process. efficient.
  • FIG. 9 which specifically shows the layered structure after forming the barrier layer 223 on the insulating layer 222 , which can be used as the step of “forming the barrier layer 223 on the insulating layer 222” in this embodiment mode
  • this step is to form a barrier layer 223 on the insulating layer 222 after the insulating layer 222 is formed.
  • the barrier layer 223 can protect the metal connection layer (conductive layer 211 ) and block water vapor.
  • the material of the barrier layer 223 may include silicon nitride. In other embodiments, the material of the barrier layer 223 may also include other materials such as silicon oxynitride (SiON), which is not limited to this embodiment.
  • the barrier layer 223 can be formed on the insulating layer 222 through a deposition process.
  • the blocking layer 223 may also be formed on the insulating layer 222 by other processes, which is not limited to this embodiment.
  • FIG. 10 which specifically shows the layered structure after the second protective layer 224 is formed on the barrier layer 223 , which can be used as “formed sequentially on the insulating layer 222 in this embodiment”
  • the implementation of subsequent processes such as etching.
  • the material of the second protective layer 224 may include polyimide. In other embodiments, the material of the second protective layer 224 may also include other materials, which is not limited to this embodiment.
  • the second protective layer 224 may be covered on the surface of the barrier layer 223 through a spin coating process. In other embodiments, the second protective layer 224 may also be formed on the barrier layer 223 by other processes, which is not limited to this embodiment.
  • the main process of the semiconductor structure is substantially completed, thereby making the semiconductor substrate 210
  • Various film layers and related structures are formed on the conductive layer 211 , such as a thin dielectric layer 226 , a thin passivation layer 2211 , an insulating layer 222 , an air hole 225 , a barrier layer 223 and a second protective layer 224 .
  • the preparation method of the semiconductor structure proposed by the present disclosure may include the step of “etching each film layer”.
  • FIG. 11 specifically shows the layered structure of each film layer of the semiconductor structure after etching, and the layered structure of the semiconductor structure shown in FIG. 11 is substantially the same as the layered structure of the semiconductor structure shown in FIG. 2 .
  • FIG. 2 a layered diagram of the semiconductor structure proposed by the present disclosure is representatively shown.
  • the semiconductor structure proposed by the present disclosure is illustrated by taking a transistor semiconductor as an example. It will be easily understood by those skilled in the art that, in order to apply the semiconductor structure of the present disclosure to other types of semiconductors, various modifications, additions, substitutions, deletions or other changes may be made to the following specific embodiments. Still within the scope of the principles of the semiconductor structures presented in this disclosure.
  • the semiconductor structure proposed by the present disclosure includes a semiconductor substrate 210 , a conductive layer 211 , a passivation layer 2211 , an insulating layer 222 , a barrier layer 223 and a second protective layer 224 .
  • the conductive layer 211 is disposed on the semiconductor substrate 210 .
  • the passivation layer 2211 may be formed by performing a passivation process on the first protective layer 221 disposed on the conductive layer 211 .
  • the insulating layer 222 , the blocking layer 223 and the second protective layer 224 are sequentially disposed on the passivation layer 2211 .
  • the semiconductor structure proposed in this disclosure can be fabricated by the preparation method of the semiconductor structure proposed in this disclosure and described in detail in the above embodiments, and in other embodiments, the semiconductor structure proposed in this disclosure can also be fabricated by other preparation methods It is not limited to this embodiment.
  • the semiconductor structure proposed by the present disclosure can provide effective protection to its conductive layer 211 by using the passivation layer 2211 , and especially has a good water vapor barrier effect.
  • the conductive layer has a discontinuous free area 2113, and on this basis, an air hole 225 may be provided in the discontinuous free area 2113.
  • the semiconductor structure proposed by the present disclosure may further include a dielectric layer 226 .
  • the dielectric layer 226 is disposed between the conductive layer 211 and the passivation layer 2211 .
  • the present disclosure in the method for preparing a semiconductor structure proposed by the present disclosure, by forming the first protective layer on the surface of the conductive layer, the conductive layer can be protected by the first protective layer.
  • the present disclosure forms a passivation layer with a multi-layer structure by performing passivation treatment on the first protective layer, and the ion concentration of at least a part of the passivation layer is larger than that of the first protective layer, which significantly optimizes the water vapor barrier effect.
  • the semiconductor structure proposed in the present disclosure can provide effective protection to the conductive layer thereof, and in particular, has a good water vapor barrier effect.

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Abstract

本公开实施例提出一种半导体结构的制备方法及半导体结构，半导体结构的制备方法包含以下步骤：提供半导体基材(210)，在半导体基材(210)形成导电层(211)；在导电层(211)表面形成第一保护层(221)；对第一保护层(221)进行钝化处理，使第一保护层(221)形成钝化层(2211)，钝化层(2211)包含多层薄膜结构，多层薄膜结构的离子浓度不完全相同；在钝化层(2211)上形成绝缘层(222)；在绝缘层(222)上依次形成阻挡层(223)和第二保护层(224)。通过上述设计，本公开能够利用第一保护层(221)对导电层(211)提供保护。本公开通过对第一保护层(221)进行钝化处理而形成具有多层结构的钝化层(2211)，钝化层(2211)至少部分区域的离子浓度比第一保护层(221)的离子浓度大，显著优化水汽阻隔效果。据此，本公开提出的半导体结构能够对其导电层(221)提供有效的保护，特别是具有良好的水汽阻隔效果。

Description

半导体结构的制备方法及半导体结构
相关申请的交叉引用
本公开要求基于2020年7月20日提交的申请号为202010696959.9的中国申请“半导体结构的制备方法及半导体结构”的优先权，通过援引将其全部内容并入本文中。
技术领域
本公开涉及半导体技术领域，尤其涉及一种半导体结构的制备方法及半导体结构。
背景技术
图1代表性地示出了一种现有半导体结构的层状图。如图1所示，在现有半导体结构中，包含半导体基材110、二氧化硅层121(SiO 2)、氮化硅层122(SIN)和聚酰亚胺层123(Polyimide)，半导体基材110上形成有金属连接层111，二氧化硅层121、氮化硅层122和聚酰亚胺层123依次形成于半导体基材110的金属连接层111之上。由于二氧化硅晶体层的晶体结构的完整性，水汽会通过一定的途径经由二氧化硅层121渗透到金属连接层111中，进而影响半导体器件性能，因此半导体的制备工艺中对形成阻挡水汽薄膜厚度及薄膜质量的工艺要求较高。
在现有制备工艺中，通常会在涂布聚酰亚胺层123之前，先生长一层氮化硅层122，利用氮化硅层122所具有的高致密性阻挡水汽的渗透。
另外，高密度等离子体(High density plasma，HDP)技术作为一种高密度等离子体介电层的工艺，经常被应用在钝化层的后段制备工艺中。然而，高密度等离子体化学气相沉积(HDP-CVD)属于高功率沉积工艺，容易破坏金属连接层111顶层的金属导电层，降低金属连接层111的可靠性。同时，现有工艺中，金属导电层的间断空余区域并未被高致密性的材料保护，水汽仍然会经由二氧化硅渗透到金属连接层111，腐蚀金属，降低半导体器件的使用寿命。
发明内容
本公开的一个主要目的在于克服上述现有技术的至少一种缺陷，提供一种能够充分阻挡水汽渗透并减少寄生电容的半导体结构的制备方法。
本公开的另一个主要目的在于克服上述现有技术的至少一种缺陷，提供一种半导体结 构。
为实现上述目的，本公开采用如下技术方案：
根据本公开的一个方面，提供一种半导体结构的制备方法；其中，该方法包含以下步骤：
提供半导体基材，在所述半导体基材上形成导电层；
在所述导电层表面形成第一保护层；
对所述第一保护层进行钝化处理，使所述第一保护层形成钝化层，所述钝化层包含多层薄膜结构，所述多层薄膜结构的离子浓度不完全相同；
在所述钝化层上形成绝缘层；以及
在所述绝缘层上依次形成阻挡层和第二保护层。
根据本公开的另一个方面，提供一种半导体结构；其中，所述半导体结构包含半导体基材、导电层、钝化层以及绝缘层、阻挡层和第二保护层；所述导电层设置于所述半导体基材上；所述钝化层由设置于所述导电层表面的第一保护层通过钝化处理而形成，所述钝化层包含多层薄膜结构，所述多层薄膜结构的离子浓度不完全相同；所述绝缘层、所述阻挡层和所述第二保护层依次设置于所述钝化层上。
由上述技术方案可知，本公开提出的半导体结构的制备方法及半导体结构至少具有以下优点和积极效果：
本公开提出的半导体结构的制备方法，通过在导电层表面形成第一保护层，能够利用第一保护层对导电层提供保护。同时，本公开通过对该第一保护层进行钝化处理而形成具有多层结构的钝化层，钝化层至少部分区域的离子浓度比第一保护层的离子浓度大，显著优化水汽阻隔效果。据此，本公开提出的半导体结构能够对其导电层提供有效的保护，特别是具有良好的水汽阻隔效果。
附图说明
图1是一种现有半导体结构的层状图；
图2是根据一示例性实施方式示出的一种半导体结构的层状图；
图3是根据一示例性实施方式示出的一种半导体结构的制备方法的其中一个步骤中的半导体结构的层状图；
图4是根据一示例性实施方式示出的一种半导体结构的制备方法的其中一个步骤中的半导体结构的层状图；
图5是根据一示例性实施方式示出的一种半导体结构的制备方法的其中一个步骤中的半导体结构的层状图；
图6是根据一示例性实施方式示出的一种半导体结构的制备方法的其中一个步骤中的半导体结构的层状图；
图7是图6中A部分的放大图；
图8是根据一示例性实施方式示出的一种半导体结构的制备方法的其中一个步骤中的半导体结构的层状图；
图9是根据一示例性实施方式示出的一种半导体结构的制备方法的其中一个步骤中的半导体结构的层状图；
图10是根据一示例性实施方式示出的一种半导体结构的制备方法的其中一个步骤中的半导体结构的层状图；
图11是根据一示例性实施方式示出的一种半导体结构的制备方法的其中一个步骤中的半导体结构的层状图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
参阅图2，其代表性地示出了本公开提出的半导体结构的层状图，该半导体结构是经由本公开提出的半导体结构的制备方法制备而成。在该示例性实施方式中，本公开提出的半导体结构的制备方法是以应用于制备晶体管半导体结构为例进行说明的。本领域技术人员容易理解的是，为将本公开的相关制备方法应用于其他类型的半导体结构制备工艺中，而对下述的具体实施方式做出多种改型、添加、替代、删除或其他变化，这些变化仍在本公开提出的半导体结构的制备方法的原理的范围内。
配合参阅图3至图11，图3至图6、图8至图11中分别代表性地示出了能够体现本公开原理的半导体结构的制备方法的其中一个步骤中的半导体结构的层状图；图7中代表性地示出了图6中A部分的放大图。以下将结合上述附图，对本公开提出的半导体结构的制备方法的各主要步骤的工艺、材质或者顺序进行详细说明。
如图3至图11所示，在本实施方式中，本公开提出的半导体结构的制备方法包含以 下步骤：
提供半导体基材210，在半导体基材210上形成导电层211；
在导电层211上形成第一保护层221(例如氮化硅，SiN)；
对第一保护层221进行钝化处理，使第一保护层221形成钝化层2211，钝化层2211包含多层薄膜结构，多层薄膜结构的离子浓度不完全相同；
在钝化层2211上形成绝缘层222(例如二氧化硅，SiO 2)；以及
在绝缘层222上依次形成阻挡层223和第二保护层224。
至此，半导体结构基本制备完成。
通过上述设计，本公开提出的半导体结构的制备方法，通过在导电层211表面形成第一保护层221，能够利用第一保护层221对导电层211提供保护。同时，本公开通过对该第一保护层221进行钝化处理而使第一保护层221形成钝化层2211，钝化层2211包含多层薄膜结构，多层薄膜结构的离子浓度不完全相同，且钝化层2211的至少一层薄膜结构的离子浓度比第一保护层221的离子浓度大，增加了致密性，显著优化水汽阻隔效果。
需说明的是，在上述的“对第一保护层221进行钝化处理”的步骤中，第一保护层221形成的钝化层2211所包含的多层薄膜结构，是指第一保护层221经由钝化处理后部分区域的离子浓度产生变化，从而使形成的钝化层2211具有不同的离子浓度的多个区域，所谓多层薄膜结构即可理解为所述的具有不同的离子浓度的多个区域。从结构角度观之，钝化层2211的多层薄膜结构可以例如为在导电层211的表面依次层叠的多层，即依次层叠的具有不同的离子浓度的多个层状区域，但并不以此为限。
具体地，如图3所示，其具体示出了一种半导体基材210的层状结构，其可以作为本实施方式中的“提供半导体基材210”步骤中的半导体基材210的代表性示例。其中，该半导体基材210形成有导电层211，导电层211在延伸方向上具有间断空余区域2113。在其他实施方式中，该步骤中提供的半导体基材210亦可选择其他形式，并不以本实施方式为限。
如图4所示，本公开提出的半导体结构的制备方法，可以包含“在导电层211上形成第一保护层221之前，在导电层211上形成介电层226”的步骤，该介电层226可以例如为SiCO等具有低介电常数的材质，可以减小半导体器件的寄生电容。图4具体示出了在半导体基材210的导电层211上形成介电层226之后的层状结构。其中，该介电层226可以优选为一层薄层结构，所谓薄层结构可以理解为，相对于后段制程中的其他层(例如绝缘层222、阻挡层223或者第二保护层224)的厚度较薄。通过上述设计，本公开能够利 用具有高致密性的介电层226，释放将于后续制程中沉积于其上层的第一保护层221的应力，同时能够利用介电层226保护导电层211。通过上述设计，由于介电层226不但具有较低的介电常数，且具有较好的致密性，因此在减小半导体器件的寄生电容的同时，介电层还可以减小结构应力。在其他实施方式中，亦可省去该形成介电层226的步骤，或者采用具有相似功效的材料、工艺步骤等，均不以本实施方式为限。
进一步地，基于本公开提出的半导体结构的制备方法包含形成介电层226的步骤，在本实施方式中，该介电层226的厚度可以优选为10nm～100nm，例如10nm、35nm、80nm、100nm等。在其他实施方式中，该介电层226的沉积厚度亦可小于10nm，或可大于100nm，例如8nm、110nm等，并不以本实施方式为限。
具体地，如图5所示，其具体示出了在该介电层226上形成第一保护层221之后的层状结构，其可以作为本实施方式中的“形成第一保护层221”步骤中的半导体结构的代表性示例。在本实施方式中，基于上述介电层226的形成步骤，该层第一保护层221是形成在该介电层226上。其中，第一保护层221可以优选为一层薄层结构，所谓薄层结构可以理解为，相对于后段制程中的其他层(例如绝缘层222、阻挡层223或者第二保护层224)的厚度较薄。通过上述设计，本公开能够利用第一保护层221为导电层211位于间断空余区域2113的侧壁提供保护，同时能够优化对导电层211，特别是该侧壁区域的水汽阻隔效果。在其他实施方式中，当导电层211上未形成该介电层226时，该第一保护层221可以形成在导电层211上，或者可以形成在导电层211上形成的其他保护结构上，均不以本实施方式为限。
进一步地，基于形成第一保护层221的步骤，在本实施方式中，该第一保护层221的厚度可以优选为10nm～100nm，例如10nm、35nm、80nm、100nm等。在其他实施方式中，该第一保护层221的厚度亦可小于10nm，或可大于100nm，例如8nm、110nm等，并不以本实施方式为限。
具体地，如图6所示，其具体示出了在对该第一保护层221经由钝化处理之后的层状结构，其可以作为本实施方式中的“对该第一保护层221进行钝化处理”步骤中的半导体结构的代表性示例。具体而言，如图6和图7所示，该步骤是在沉积第一保护层221之后，利用例如等离子体处理技术的钝化处理工艺，对该第一保护层221进行处理，使得该第一保护层221形成钝化层2211。其中，钝化层2211具有两层薄膜结构，分别为邻接导电层211的第一层以及设置于该第一层表面的第二层。第二层的致密性增加，即第二层的离子浓度升高(例如氮离子含量升高)，且该第二层的离子浓度高于第一层的离子浓度。通过 上述设计，本公开能够利用对第一保护层221进行等离子体处理而使第一保护层221形成钝化层2211，使得具有多层薄膜结构的钝化层2211的各层薄膜结构的离子浓度不完全相同，且钝化层2211的至少一层薄膜结构的离子浓度大于第一保护层221的离子浓度，进一步优化水汽阻隔效果。在其他实施方式中，第一保护层221经过钝化处理后形成的钝化层2211，亦可包含三层或者三层以上薄膜结构，且多层薄膜结构的离子浓度不完全相同。
在其他实施方式中，对于“对第一保护层221进行钝化处理，形成钝化层2211”的步骤而言，该钝化处理亦可采用其他处理工艺，例如离子注入或者热氧化处理等。并且，根据不同的工艺需求，当采用合适的钝化处理工艺时，钝化层2211可以包含三层或者三层以上薄膜结构，并不限于本实施方式中经由钝化处理后的形成的钝化层221大致分为两层的设计。并且，钝化层2211的多层薄膜结构的各层的离子浓度不完全相同。
举例而言，在另一实施方式中，当采用离子注入工艺对第一保护层221进行钝化处理时，可以将离子注入至第一保护层221的中部区域，从而使第一保护层221的中部区域的离子(例如氮离子)密度大于其余区域的离子浓度，进而使得所形成的钝化层2211大致包含三层或三层以上的薄膜结构，即中部区域至少一层薄膜结构的离子浓度不同于(例如大于)其余区域的薄膜结构的离子浓度。再者，亦可将离子注入至第一保护层221的邻接导电层211的区域或者远离导电层211的区域，而使所形成的钝化层2211的多层薄膜结构的离子浓度呈现不同的关系，均不以该实施方式为限。
需说明的是，如图7所示，导电层211在本实施方式中是以包含上层金属2111和例如氮化钛层2112的导电结构为例进行说明，该层氮化钛层2112形成于上层金属2111的表面。在此基础上，该钝化层2211的多层薄膜结构的最下层薄膜结构实际上是邻接于该层氮化钛2112。
进一步地，基于对该第一保护层221进行等离子体处理的步骤，在本实施方式中，该等离子体处理可以包含氨气等离子体处理，即，基于氨气(NH 3)的等离子体处理。在其他实施方式中，亦可采用基于其他等离子的等离子体处理工艺，例如基于氩气(Ar)的等离子体处理、基于氮气(N 2)的等离子体处理等低温等离子体处理工艺，或可采用其他类型的等离子体处理工艺，均不以本实施方式为限。
具体地，如图8所示，其具体示出了在该钝化层2211形成绝缘层222之后的层状结构，其可以作为本实施方式中的“在钝化层2211上形成绝缘层222”步骤中的半导体结构的代表性示例。具体而言，该步骤是在对该第一保护层221进行等离子体处理而使第一保护层221形成钝化层2211之后，在该钝化层2211上形成绝缘层222。其中，该绝缘层 222除形成在该钝化层2211上方的部分以外，还填充于导电层211的间断空余区域2113中。
进一步地，基于形成绝缘层222的步骤，在本实施方式中，该绝缘层222的形成工艺可以包含高密度等离子体化学气相淀积工艺。在其他实施方式中，该绝缘层222亦可采用其他类型的沉积工艺或者其他工艺，形成于该钝化层2211上，并不以本实施方式为限。
进一步地，如图8所示，基于形成绝缘层222的步骤，在本实施方式中，在形成绝缘层222时，可以在导电层211的间断空余区域2113形成空气洞225(Air Gap)。通过上述设计，能够减少导电层211的寄生电容，进而缓解RC延迟等不良。其中，由于本公开采用了在导电层211表面形成介电层226的工艺步骤，则导电层211的间断空余区域2113的侧面和底面也覆盖有介电层226，因此相比于现有工艺中的间断空余区域，本公开提出的制备方法中的间断空余区域2113具有更窄的宽度，即间断空余区域2113相比于现有工艺中的对应结构的高度宽度比增大。据此，相比于现有制备方法中需要多次工艺形成空气洞的设计，本公开的上述形成空气洞225的步骤中，能够实现对空气洞225的一次成形，进一步简化工艺步骤，提高制备效率。
具体地，如图9所示，其具体示出了在绝缘层222上形成阻挡层223之后的层状结构，其可以作为本实施方式中的“在绝缘层222上形成阻挡层223”步骤中的半导体结构的代表性示例。具体而言，该步骤是在形成绝缘层222之后，在该绝缘层222上形成一层阻挡层223，该阻挡层223能够起到保护金属连接层(导电层211)、阻隔水汽的功效。
进一步地，基于形成阻挡层223的步骤，在本实施方式中，阻挡层223的材质可以包含氮化硅。在其他实施方式中，阻挡层223的材质亦可包含氮氧化硅(SiON)等其他材质，并不以本实施方式为限。
进一步地，基于形成阻挡层223的步骤，在本实施方式中，阻挡层223可以经由沉积工艺形成于该绝缘层222上。在其他实施方式中，阻挡层223亦可采用其他工艺形成于该绝缘层222上，并不以本实施方式为限。
具体地，如图10所示，其具体示出了在该层阻挡层223上形成第二保护层224之后的层状结构，其可以作为本实施方式中的“在该绝缘层222上依次形成阻挡层223和第二保护层224”步骤中的半导体结构的代表性示例。具体而言，该步骤是形成阻挡层223之后，在该阻挡层223上形成一层第二保护层224，该第二保护层224能够起到保护半导体结构的功效，同时便于对各膜层的蚀刻等后续制程的实施。
进一步地，基于形成第二保护层224的步骤，在本实施方式中，第二保护层224的材 质可以包含聚酰亚胺。在其他实施方式中，第二保护层224的材质亦可包含其他材质，并不以本实施方式为限。
进一步地，基于形成第二保护层224的步骤，在本实施方式中，第二保护层224可以经由旋涂工艺覆盖在阻挡层223的表面上。在其他实施方式中，第二保护层224亦可采用其他工艺形成于阻挡层223上，并不以本实施方式为限。
承上所述，如图10所示，当“在该绝缘层222上依次形成阻挡层223和第二保护层224”步骤完成时，半导体结构的主要制程大致完成，据此使得半导体基材210在其导电层211上形成各膜层及相关结构，例如包含薄层的介电层226、薄层的钝化层2211、绝缘层222、空气洞225、阻挡层223和第二保护层224。
如图11所示，本公开提出的半导体结构的制备方法，可以包含“对各膜层进行蚀刻”的步骤。图11具体示出了半导体结构的各膜层经过蚀刻之后的层状结构，且图11示出的半导体结构的层状结构与图2示出的半导体结构的层状结构大致相同。
在此应注意，附图中示出而且在本说明书中描述的半导体结构的制备方法仅仅是能够采用本公开原理的许多种方法中的几个示例。应当清楚地理解，本公开的原理绝非仅限于附图中示出或本说明书中描述的半导体结构的制备方法的任何细节或任何步骤。
参阅图2，其代表性地示出了本公开提出的半导体结构的层状图。在该示例性实施方式中，本公开提出的半导体结构是以晶体管半导体为例进行说明的。本领域技术人员容易理解的是，为将本公开的半导体结构应用于其他类型的半导体中，而对下述的具体实施方式做出多种改型、添加、替代、删除或其他变化，这些变化仍在本公开提出的半导体结构的原理的范围内。
如图2所示，在本实施方式中，本公开提出的半导体结构包含半导体基材210、导电层211、钝化层2211以及绝缘层222、阻挡层223和第二保护层224。具体而言，导电层211设置于半导体基材210上。钝化层2211可以通过对设置于导电层211上的第一保护层221进行钝化处理形成。绝缘层222、阻挡层223和第二保护层224依次设置于钝化层2211上。其中，该本公开提出的半导体结构可以采用本公开提出的并在上述实施方式中详细说明的半导体结构的制备方法制成，在其他实施方式中，本公开提出的半导体结构亦可采用其他制备方法制成，并不以本实施方式为限。通过上述设计，本公开提出的半导体结构能够利用钝化层2211对其导电层211提供有效的保护，特别是具有良好的水汽阻隔效果。
如图2所示，在本实施方式中，导电层具有间断空余区域2113，在此基础上，间断 空余区域2113内可以设置有空气洞225。
如图2所示，在本实施方式中，本公开提出的半导体结构还可以包含介电层226。该介电层226设置于导电层211与钝化层2211之间。
在此应注意，附图中示出而且在本说明书中描述的半导体结构仅仅是能够采用本公开原理的许多种半导体结构中的几个示例。应当清楚地理解，本公开的原理绝非仅限于附图中示出或本说明书中描述的半导体结构的任何细节或任何部件。
综上所述，本公开提出的半导体结构的制备方法，通过在导电层表面形成第一保护层，能够利用第一保护层对导电层提供保护。同时，本公开通过对该第一保护层进行钝化处理而形成具有多层结构的钝化层，钝化层至少部分区域的离子浓度比第一保护层的离子浓度大，显著优化水汽阻隔效果。据此，本公开提出的半导体结构能够对其导电层提供有效的保护，特别是具有良好的水汽阻隔效果。
虽然已参照几个典型实施例描述了本公开，但应当理解，所用的术语是说明和示例性、而非限制性的术语。由于本公开能够以多种形式具体实施而不脱离公开的精神或实质，所以应当理解，上述实施例不限于任何前述的细节，而应在随附权利要求所限定的精神和范围内广泛地解释，因此落入权利要求或其等效范围内的全部变化和改型都应为随附权利要求所涵盖。

Claims (20)

  1. 一种半导体结构的制备方法，其特征在于，该方法包含以下步骤：
    提供半导体基材，在所述半导体基材上形成导电层；
    在所述导电层表面形成第一保护层；
    对所述第一保护层进行钝化处理，使所述第一保护层形成钝化层，所述钝化层包含多层薄膜结构，所述多层薄膜结构的离子浓度不完全相同；
    在所述钝化层上形成绝缘层；以及
    在所述绝缘层上依次形成阻挡层和第二保护层。
  2. 根据权利要求1所述的半导体结构的制备方法，其特征在于，所述钝化处理包含等离子体处理、离子注入或者热氧化处理。
  3. 根据权利要求2所述的半导体结构的制备方法，其特征在于，所述钝化处理包含基于氨气的等离子体处理。
  4. 根据权利要求1所述的半导体结构的制备方法，其特征在于，所述钝化层包含两层薄膜结构，所述两层薄膜结构分别为第一层和第二层，所述第一层邻接于所述导电层，所述第二层位于所述第一层表面，所述第二层的离子浓度大于所述第一层的离子浓度。
  5. 根据权利要求1所述的半导体结构的制备方法，其特征在于，所述钝化层包含三层及三层以上薄膜结构，各层所述薄膜结构的离子浓度不完全相同，至少一层所述薄膜结构的离子浓度大于所述第一保护层的离子浓度。
  6. 根据权利要求1所述的半导体结构的制备方法，其特征在于，所述第一保护层的厚度为10nm～100nm。
  7. 根据权利要求1所述的半导体结构的制备方法，其特征在于，所述绝缘层的形成工艺包含高密度等离子体化学气相淀积工艺。
  8. 根据权利要求1所述的半导体结构的制备方法，其特征在于，形成所述绝缘层时，在所述导电层的间断空余区域形成空气洞。
  9. 根据权利要求1～8任一项所述的半导体结构的制备方法，其特征在于，该方法还包含以下步骤：
    在形成所述第一保护层之前，在所述导电层表面形成介电层。
  10. 根据权利要求9所述的半导体结构的制备方法，其特征在于，所述介电层的厚度为10nm～100nm。
  11. 根据权利要求9所述的半导体结构的制备方法，其特征在于，所述介电层的材质包含SiCO。
  12. 根据权利要求1所述的半导体结构的制备方法，其特征在于，所述第一保护层的材质包含氮化硅。
  13. 根据权利要求1所述的半导体结构的制备方法，其特征在于，所述绝缘层的材质包含氧化硅。
  14. 根据权利要求1所述的半导体结构的制备方法，其特征在于，所述绝缘层的形成工艺包含高密度等离子体化学气相淀积工艺。
  15. 根据权利要求1所述的半导体结构的制备方法，其特征在于，所述阻挡层的材质包含氮化硅、氮氧化硅。
  16. 根据权利要求1所述的半导体结构的制备方法，其特征在于，所述第二保护层的材质包含聚酰亚胺。
  17. 根据权利要求1所述的半导体结构的制备方法，其特征在于，所述第二保护层经由旋涂工艺覆盖在所述阻挡层表面。
  18. 一种半导体结构，其特征在于，所述半导体结构包含：
    半导体基材；
    导电层，设置于所述半导体基材上；
    钝化层，由设置于所述导电层表面的第一保护层通过钝化处理而形成，所述钝化层包含多层薄膜结构，所述多层薄膜结构的离子浓度不完全相同；以及
    绝缘层、阻挡层和第二保护层，依次设置于所述钝化层上。
  19. 根据权利要求18所述的半导体结构，其特征在于，所述导电层具有间断空余区域；其中，所述间断空余区域内设置有空气洞。
  20. 根据权利要求18所述的半导体结构，其特征在于，所述半导体结构还包含：
    介电层，设置于所述导电层与所述钝化层之间。
PCT/CN2021/101628 2020-07-20 2021-06-22 半导体结构的制备方法及半导体结构 Ceased WO2022017108A1 (zh)

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