WO2022016985A1 - 埋入式栅极及其制作方法 - Google Patents

埋入式栅极及其制作方法 Download PDF

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Publication number
WO2022016985A1
WO2022016985A1 PCT/CN2021/095654 CN2021095654W WO2022016985A1 WO 2022016985 A1 WO2022016985 A1 WO 2022016985A1 CN 2021095654 W CN2021095654 W CN 2021095654W WO 2022016985 A1 WO2022016985 A1 WO 2022016985A1
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Prior art keywords
word line
layer
line trench
substrate
conductive layer
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PCT/CN2021/095654
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English (en)
French (fr)
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金青洙
金容君
胡显锐
邵光速
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长鑫存储技术有限公司
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Priority to US17/595,936 priority Critical patent/US20230140073A1/en
Publication of WO2022016985A1 publication Critical patent/WO2022016985A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines

Definitions

  • the present application relates to the technical field of semiconductor memory devices, and in particular, to a buried gate and a fabrication method thereof.
  • buried word line dynamic random access memory has been developed in recent years, which is used to increase the number of memory cells. Transistor integration and improved device characteristics to meet the above requirements.
  • the area of the active region is often affected due to process limitations, so that the gate channel (formed between the source and drain on both sides of the word line trench) part) length becomes shorter, resulting in obvious short channel effect, which affects the performance of the device itself.
  • the present application provides a buried gate and a fabrication method thereof, so as to improve the short channel effect caused by the reduced device size.
  • a method of fabricating a buried gate comprising:
  • a conductive layer is formed in the word line trench, and a surface of the conductive layer has a convex structure matching the concave structure.
  • the forming a concave structure on the surface of the word line trench includes:
  • a plurality of the hemispherical silicon crystal particles are removed.
  • the hemispherical polysilicon particles are formed by an LPCVD process
  • the reaction gas in the LPCVD process includes SiH 4
  • the reaction temperature ranges from 500°C to 600°C
  • the reaction pressure ranges from 0.1torr to 0.5torr.
  • forming the conductive layer in the word line trench includes:
  • the metal material layer covering the upper surface of the substrate and a part of the metal material layer located in the word line trench are removed, and the remaining metal material layer is used as the conductive layer.
  • the method before forming the metal material layer, the method further includes:
  • the gate insulating layer covering the surface of the word line trench and the surface of the concave structure
  • a metal barrier layer is formed on the surface of the gate insulating layer, and the metal barrier layer is located between the gate insulating layer and the conductive layer.
  • the manufacturing method further includes:
  • a buried gate including:
  • a word line trench located in the substrate, and the surface of the word line trench has a groove structure
  • the conductive layer is located in the word line trench, and the surface of the conductive layer has a raised structure matched with the groove structure.
  • the buried gate further includes a gate insulating layer located between the conductive layer and the substrate.
  • the conductive layer includes a metal layer.
  • the buried gate further includes a metal barrier layer, and the metal barrier layer is located between the gate insulating layer and the metal layer.
  • the length of the word line trench is increased by changing the shape of the word line structure, thereby solving the short channel effect caused by the reduced device size and improving the device performance.
  • FIG. 1 is a flowchart of a method for fabricating a semiconductor device according to an embodiment
  • FIGS. 2-7 are schematic structural diagrams of a semiconductor structure after stepwise etching provided by an embodiment
  • first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or Sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.
  • Spatial relational terms such as “under”, “below”, “below”, “under”, “above”, “above”, etc., in This may be used to describe the relationship of one element or feature to other elements or features shown in the figures. It should be understood that in addition to the orientation shown in the figures, spatially relative terms encompass different orientations of the device in use and operation. For example, if the device in the figures is turned over, elements or features described as “below” or “beneath” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary terms “below” and “under” can encompass both an orientation of above and below. In addition, the device may also be otherwise oriented (eg, rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
  • the gate channel length is shortened to After a certain size, it will cause short-channel effects, such as lower threshold voltage, lower operating current, increased hot carrier effect, and degradation of threshold characteristics, resulting in devices that cannot be turned off.
  • an embodiment of the present application provides a method for fabricating a buried gate, please refer to FIG. 1 , and the method for fabricating the buried gate includes:
  • Step S110 providing the substrate 100
  • Step S120 forming word line trenches 200 in the substrate 100
  • Step S130 processing the surface of the word line trench 200 to form a concave structure 210 on the surface of the word line trench 200 ;
  • step S140 a conductive layer 300 is formed in the word line trench 200 , and a surface of the conductive layer 300 has a convex structure 310 matching the concave structure 210 .
  • the area of the active region is reduced, which leads to the shortening of the gate channel length.
  • the gate channel length is shortened to a certain size, the Short-channel effects will be induced, for example, the threshold voltage will be reduced, the operating current will be reduced, the hot carrier effect will be aggravated, and the threshold characteristics will be degraded and the device cannot be turned off.
  • the word line trench 200 is formed in the substrate 100, and the width of the word line trench 200 is the standard width of the word line trench 200;
  • the surface of 200 is etched, and a concave structure 210 is formed on the surface of the word line trench 200; finally, a conductive layer 300 is formed in the word line trench 200, and the surface of the conductive layer 300 has the same characteristics as the concave structure.
  • the convex structure 310 matched with the structure 210 can increase the relative area between the conductive layer 300 and the word line trench 200 through the concave structure 210 and the convex structure 310, so as to ensure that the width of the gate channel does not vary. Under the premise of changing, the length of the gate trench is increased to improve the short channel effect caused by the smaller device size.
  • Step S110 is performed to provide the substrate 100 .
  • the substrate 100 may include a semiconductor substrate such as a silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, or a silicon-on-insulator substrate, but is not limited to this, any method known to those skilled in the art for carrying The base material of the component of the semiconductor integrated circuit can be used.
  • a shallow trench isolation structure (not shown) and an active region (not shown) are formed on the substrate 100 , wherein the shallow trench isolation structure isolates the active region from the surrounding environment open.
  • the shallow trench isolation structure can isolate the active regions into an array arrangement to fabricate a storage array of the memory.
  • the shallow trench isolation structure may include a shallow trench in the substrate 100 and an isolation material filling the shallow trench, and the isolation material may include a thermal oxidation process formed and covered on the shallow trench. A line oxide layer and silicon dioxide on the surface of the line oxide layer and filling the shallow trench, thereby improving the isolation performance of the shallow trench isolation structure.
  • the base 100 includes an SOI (Silicon-On-Insulator, silicon on insulating substrate) substrate, and the SOI substrate includes a silicon material layer (not shown), a back substrate (not shown). shown) and an oxide material layer (not shown) interposed between the silicon material layer and the back substrate.
  • SOI Silicon-On-Insulator, silicon on insulating substrate
  • the SOI substrate is used in this embodiment, and the oxide material can be used as an etching stop layer during the etching of the word line trenches 200 , so as to control the depth of the word line trenches 200 .
  • the oxide material layer can eliminate the influence of leakage current in the base substrate, and further improve the performance of the semiconductor device.
  • the silicon material layer may be an undoped silicon material layer or a doped silicon material layer, and the doped silicon material layer may be an N-type or P-type doped silicon material layer.
  • step S120 is performed to form the word line trenches 200 on the substrate 100 .
  • the steps of forming the word line trench 200 mainly include:
  • the active region to form a source electrode (not shown) and/or a drain electrode (not shown) on both sides of the word line trench 200, specifically, forming in a single active region
  • a source electrode not shown
  • a drain electrode not shown
  • the formation time of the source electrode and the drain electrode in the process flow can be adjusted according to actual process conditions, which is not limited in this embodiment.
  • the source and drain electrodes may also be formed after the word line trench 200 is formed, and may also be formed after the conductive layer 300 is formed.
  • a hard mask layer can be formed by depositing a mask material on the surface having the shallow trench isolation structure and the lining oxide layer through a deposition process.
  • the deposition process includes chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and the like.
  • the organic mask material and the hard mask material are sequentially formed on the surface of the substrate to form an organic mask material layer and a hard mask material layer, respectively, and the stacked organic mask material layer and hard mask material layer The film material layers together constitute the hard mask layer.
  • the organic mask material layer is usually formed with a carbon-containing organic material; the organic mask material layer is formed with one or more of silicon nitride, silicon oxynitride, silicon carbonitride, metal nitride, metal oxide and metal carbide
  • the hard mask material layer is preferably silicon nitride (SiN), because the silicon nitride material has the advantages of easy acquisition, low cost, mature manufacturing method, etc., and has a higher etching selectivity ratio than the silicon oxide in the lining oxide layer .
  • a matching mask can be used to coat a layer of photoresist on the hard mask material layer, and use a laser to irradiate the photoresist layer through the mask to cause photoresist generation in the exposed area. Chemical reaction; then dissolve and remove the photoresist in the exposed area or unexposed area by developing technology (the former is called positive photoresist, the latter is called negative photoresist), and the pattern on the photomask is transferred to the photoresist layer , a pattern for defining the word line trenches 200 is formed. Then, using the photoresist layer with the pattern as a mask, the hard mask layer is etched to the surface of the lining oxide layer to form a patterned hard mask layer with an opening pattern.
  • the plurality of active regions are arranged in parallel and staggered arrays, each of the active regions is in the shape of a long strip, and the number of trenches formed on a single active region is not limited.
  • two wordline trenches 200 are formed in a single active region.
  • the word line trenches 200 of the buried conductive layer 300 are formed on the active region.
  • the word line trenches 200 are arranged in parallel at equal intervals, and there are two word line trenches 200 on a single active region.
  • a concave structure 210 is formed on the sidewall and bottom surface of the word line trench 200 by performing step S130 to increase the length of the gate channel .
  • forming the concave structure 210 on the surface of the word line trench 200 includes:
  • a plurality of the hemispherical silicon crystal particles 700 are removed.
  • the HSG process is used to form hemispherical silicon crystal particles 700 on the surface of the word line trenches 200 .
  • the process includes: placing the substrate on which the word line trenches 200 are formed in a reaction chamber for processing.
  • a plurality of hemispherical silicon crystal grains 700 are formed on the sidewall and bottom surface of the trench.
  • the size of the hemispherical silicon crystal particles 700 can be controlled by adjusting the reaction time and reaction conditions.
  • using a plurality of the hemispherical silicon crystal particles 700 as masks the surface of the word line trench 200 is etched by a dry etching process, and the sidewalls and the bottom of the word line trench 200 are etched.
  • a plurality of concave structures 210 are formed on the surface.
  • a plurality of the hemispherical silicon crystal particles 700 are removed.
  • the hemispherical silicon crystal particles 700 are fabricated by a deposition process, such as CVD, PVD, and LPCVD.
  • the hemispherical polysilicon particles are formed by an LPCVD process, the reaction gas in the LPCVD process includes SiH 4 , the reaction temperature ranges from 500°C to 600°C, and the reaction pressure ranges from 0.1torr to 0.5torr.
  • the lower part with the word line trenches 200 is placed in the reaction chamber, and then the reaction parameters are adjusted, wherein the reaction temperature ranges from 500° C. to 600° C. and the reaction pressure ranges from 0.1 torr to 0.5 torr.
  • the reaction temperature ranges from 500° C. to 600° C.
  • the reaction pressure ranges from 0.1 torr to 0.5 torr.
  • SiH 4 gas is passed into the fluidized bed reactor with small particles of silicon powder for continuous thermal decomposition reaction, and granular polysilicon is generated, which is attached to the surface of the substrate 100 and the surface of the word line trench 200 surface.
  • SiCl 4 (or SiF 4 ), H 2 , HCl reaction gas and metallurgical silicon can be used as raw materials to generate SiHCl 3 in a high temperature and high pressure fluidized bed (ebullated bed) reactor, and SiHCl 3 is further disproportionated and hydrogenated
  • the reaction generates SiH 2 Cl 2 , and then generates SiH 4 gas; the prepared SiH 4 gas is passed into a fluidized bed reactor with small particles of silicon powder for continuous thermal decomposition reaction, and granular polycrystalline silicon is generated and attached to the hard mask layer. surface and the surface of the word line trench 200 .
  • the hard mask layer and the hemispherical silicon crystal particles 700 on the surface can be retained first, and the substrate 100 can be protected by the hard mask layer and the hemispherical silicon crystal particles 700 on the surface to avoid any The source region is damaged; and, after forming a concave structure on the surface of the word line trench 200, the hemispherical silicon crystal particles 700 are removed by an etching gas including hydrofluoric acid and oxygen, or the concave structure is formed by forming a concave structure.
  • the substrate of structure 210 is exposed to a chlorine-based etching gas (which may include one or more of chlorine, boron trichloride, chlorine trifluoride, and hydrogen chloride), and the hemispherical silicon is removed using the chlorine-based etching gas Crystal particles 700; then remove the lining oxide layer and hard mask layer on the surface of the substrate 100 through an etching process or a chemical mechanical planarization process, etc., and further clean to expose the clean active area surface, word line trenches Sidewalls and bottom surfaces of the grooves 200 and inner surfaces of the concave structures 210 .
  • a chlorine-based etching gas which may include one or more of chlorine, boron trichloride, chlorine trifluoride, and hydrogen chloride
  • the method further includes:
  • gate insulating layer 400 covering the surface of the word line trench 200 and the surface of the concave structure 210;
  • a metal barrier layer 500 is formed on the surface of the gate insulating layer 400 , and the metal barrier layer 500 is located between the gate insulating layer 400 and the conductive layer 300 .
  • a gate insulating layer 400 is formed on the sidewall and bottom of the word line trench 200 , and the gate insulating layer 400 completely covers the sidewall and bottom surface of the gate of the word line trench 200 , and the surface of the concave structure 210; and the gate insulating layer 400 extends to the top of the word line trench 200, the top of which is flush with the top of the substrate. More specifically, the gate insulating layer 400 may form silicon oxide on the upper surface of the substrate 100 , the sidewalls and bottoms of the word line trenches 200 and the surface of the concave structure 210 by a deposition process or a thermal oxidation process.
  • the gate insulating layer 400 is formed.
  • the silicon oxide material can also be replaced by a high-K (dielectric constant K greater than 7) dielectric material.
  • high-K dielectric materials include Ta 2 O 5 , TiO 2 , Al 2 O 3 , Pr 2 O 3 , La Metal oxides of 2 O 3 , LaAlO 3 , HfO 2 , ZrO 2 or other components.
  • the metal barrier layer 500 can prevent the conductive material in the conductive layer 300 from diffusing to the gate insulating layer, thereby affecting the performance of the gate insulating layer.
  • the metal barrier layer 500 also has the function of enhancing the adhesion between the conductive layer 300 and the gate insulating layer.
  • the formed metal barrier layer 500 may have a multi-layer stacked composite structure.
  • the metal barrier layer 500 is made of titanium nitride (TiN) material.
  • TiN titanium nitride
  • the combination of the titanium nitride material layer and the gate insulating layer 400 is beneficial to increase the dielectric constant, reduce the gate length, increase the driving current and reduce the threshold voltage.
  • step S140 is performed to form a conductive layer 300 in the word line trench 200 , and the surface of the conductive layer 300 has a convex shape matching the concave structure 210 .
  • Structure 310 forming the conductive layer 300 in the word line trench 200 includes:
  • the metal material layer covering the upper surface of the substrate 100 and a part of the metal material layer located in the word line trench 200 are removed, and the remaining metal material layer is used as the conductive layer 300 .
  • a metal material layer is formed by a deposition process such as CVD or PVD, the metal material layer fills the word line trench 200 and the concave structure 210 , and covers the surface of the metal barrier layer 500 and the substrate 100; then, remove the metal material covering the upper surface of the metal barrier layer 500 and the upper surface of the substrate 100 and the metal material layer of the partial height in the word line trench 200, so that the metal material layer The upper surface of the substrate 100 is lower than the upper surface of the substrate 100 to form a buried gate.
  • the metal material includes one or more metal materials with good electrical conductivity, such as tungsten, cobalt, manganese, niobium, nickel, and molybdenum.
  • the barrier material layer and the metal material layer may be etched by the same etching process to form the metal barrier layer 500 and the conductive layer 300 .
  • the conductive layer 300 includes a stacked metal material layer and a semiconductor conductive material layer (not shown).
  • the material of the semiconductor conductive material layer includes polysilicon, silicon germanium, gallium arsenide, gallium phosphide, cadmium sulfide, and zinc sulfide, or any combination thereof.
  • the semiconductor conductive material layer and the metal material layer together constitute a dual work function gate. In this embodiment, the problem of gate-induced drain leakage current can be effectively solved by arranging the stacked conductive layers 300 .
  • the buried gate further includes the step of forming an equipotential dielectric layer between the metal material layer and the polysilicon material layer, using the equipotential dielectric layer as a metal barrier layer 500 prevents the conductive material in the metal material layer from diffusing to the semiconductor conductive material layer, and simultaneously makes the metal material layer communicate with the semiconductor conductive material layer to form an equipotential to improve device performance.
  • any one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride or any combination thereof may be used to form the equipotential dielectric layer.
  • the method for fabricating the buried gate further includes:
  • An insulating filling layer 600 is formed, the insulating filling layer 600 covers the surface of the substrate 100 and fills the word line trenches 200 .
  • the top of the formed conductive layer 300 is lower than the top of the word line trench 200 to increase the distance between the conductive layer 300 and the subsequently formed storage node plugs and bit line connection plugs , reducing parasitic capacitance.
  • the filling insulating layer is flush with the upper surface of the substrate 100 to form a flat surface, which is favorable for forming other structures thereon.
  • an embodiment of the present application also provides a buried gate.
  • the buried gate includes a substrate 100 , a word line trench 200 and a conductive layer 300 .
  • the word line trench 200 is located in the substrate 100, and the surface of the word line trench 200 has a groove structure.
  • the conductive layer 300 is located in the word line trench 200, and the surface of the conductive layer 300 has a convex structure matching the groove structure.
  • the concave structure 210 and the convex structure 310 increase the relative area between the conductive layer 300 and the word line trench 200, so as to increase the length of the gate trench on the premise that the width of the gate channel is kept unchanged, In order to improve the short channel effect caused by the shrinking device size.
  • the conductive layer 300 includes a metal layer.
  • one or more metal materials with good electrical conductivity such as tungsten, cobalt, manganese, niobium, nickel, and molybdenum are used to form the metal layer.
  • the conductive layer 300 includes a stacked metal layer and a semiconductor conductive layer 300, wherein the semiconductor conductive layer 300 is located above the metal layer.
  • the material of the semiconductor conductive material layer includes polysilicon, silicon germanium, gallium arsenide, gallium phosphide, cadmium sulfide, and zinc sulfide, or any combination thereof.
  • the semiconductor conductive material layer and the metal material layer together constitute a dual work function gate. In this embodiment, the problem of gate-induced drain leakage current can be effectively solved by arranging the stacked conductive layers 300 .
  • the buried gate further includes an equipotential dielectric layer between the metal material layer and the polysilicon material layer, and the equipotential dielectric layer is used as the metal barrier layer 500 to prevent
  • the conductive material in the first conductive layer 300 diffuses to the second conductive layer 300 , and at the same time, the first conductive layer 300 and the second conductive layer 300 are connected to form an equipotential, thereby improving device performance.
  • any one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride or any combination thereof may be used to form the equipotential dielectric layer.
  • the buried gate further includes a metal barrier layer 500 located between the gate insulating layer 400 and the metal layer.
  • the metal barrier layer 500 can prevent the conductive material in the conductive layer 300 from diffusing to the gate insulating layer, thereby affecting the performance of the gate insulating layer.
  • the metal barrier layer 500 also has the function of enhancing the adhesion between the conductive layer 300 and the gate insulating layer.
  • the formed metal barrier layer 500 may have a multi-layer stacked composite structure.
  • the metal barrier layer 500 in this embodiment can be made of titanium nitride (TiN) material. Compared with providing the gate insulating layer 400 alone, the combination of the titanium nitride material layer and the gate insulating layer 400 is beneficial to increase the dielectric constant, reduce the gate length, increase the driving current and reduce the threshold voltage.
  • the buried gate further includes a gate insulating layer 400 located between the conductive layer 300 and the substrate 100 .
  • the gate insulating layer 400 completely covers the sidewall and bottom surface of the gate of the word line trench 200 and the surface of the concave structure 210; and the gate insulating layer 400 extends to the word line trench 200, the top of which is flush with the top of the substrate.
  • the gate insulating layer 400 can be made of silicon oxide; in some other embodiments, a high-K (dielectric constant K greater than 7) dielectric material can also be used to replace the silicon oxide material, a commonly used high-K dielectric material Metal oxides including Ta 2 O 5 , TiO 2 , Al 2 O 3 , Pr 2 O 3 , La 2 O 3 , LaAlO 3 , HfO 2 , ZrO 2 or other components.
  • the buried gate further includes an insulating filling layer 600 .
  • the top of the conductive layer 300 is lower than the top of the word line trench 200 , which can increase the distance between the conductive layer 300 and the subsequently formed storage node plugs and bit line connection plugs, and reduce the distance. parasitic capacitance.
  • Filling the full word line trenches 200 with a low-K dielectric material such as silicon nitride, which has increased bandwidth and good insulation performance, can achieve good protection and insulation effects.
  • the filling insulating layer is flush with the upper surface of the substrate 100 to form a flat surface, which is favorable for forming other structures thereon.
  • the present application provides a buried gate and a fabrication method thereof.
  • the method for fabricating the buried gate includes: providing a substrate 100 ; forming word line trenches 200 in the substrate 100 ; A concave structure 210 is formed on the surface of the word line trench 200 ; a conductive layer 300 is formed in the word line trench 200 , and the surface of the conductive layer 300 has a convex structure 310 matching the concave structure 210 .
  • the concave structure 210 is formed on the surface of the word line trench 200 first, and then a conductive layer having a convex structure 310 matching the concave structure 210 is formed in the word line trench 200 Therefore, without changing the width of the word line trench 200, the length of the word line trench 200 can be increased by changing the shape of the word line structure, thereby solving the short channel effect caused by the smaller device size and improving the device quality. .

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Abstract

本申请涉及一种埋入式栅极及其制作方法。该埋入式栅极的制作方法包括：提供基底；在所述基底中形成字线沟槽；对所述字线沟槽的表面进行处理，以在所述字线沟槽的表面形成凹型结构；在所述字线沟槽内形成导电层，所述导电层的表面具有与所述凹型结构相匹配的凸型结构。

Description

埋入式栅极及其制作方法
相关申请的交叉引用
本申请要求于2020年7月22日提交中国专利局、申请号为202010708729X、发明名称为“埋入式栅极及其制作方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体存储器件技术领域，尤其涉及一种埋入式栅极及其制作方法。
背景技术
为提升动态随机存取存储器的集成度以加快器件的操作速度，以及符合消费者对于小型化电子装置的需求，近年来发展出埋入式字线动态随机存取存储器，用于增加存储单元的晶体管积集度及改善器件特性，以满足上述需求。
由于动态随机存取存储器器件本身的尺寸很小，所以往往会因为工艺限制而影响有源区的面积，使得栅极沟道(形成于字线沟槽两侧的源极和漏极之间的部分)长度变短，产生明显的短沟道效应，从而影响器件本身的性能。
发明内容
本申请提供了一种埋入式栅极及其制作方法，以改善因器件尺寸变小所引起的短沟道效应。
一种埋入式栅极的制作方法，包括：
提供基底；
在所述基底中形成字线沟槽；
对所述字线沟槽的表面进行处理，以在所述字线沟槽的表面形成凹型结构；
在所述字线沟槽内形成导电层，所述导电层的表面具有与所述凹型结构相匹配的凸型结构。
在其中一个实施例中，所述在所述字线沟槽的表面形成凹型结构，包括：
在所述字线沟槽的表面形成多个半球形硅晶颗粒；
以多个所述半球形硅晶颗粒为掩膜，对所述字线沟槽的表面进行刻蚀，形成所述凹型结构；
去除多个所述半球形硅晶颗粒。
在其中一个实施例中，采用LPCVD工艺形成所述半球多晶硅颗粒，所述LPCVD工艺中的反应气体包括SiH 4，反应温度范围为500℃～600℃，反应压力范围为0.1torr～0.5torr。
在其中一个实施例中，在所述字线沟槽内形成所述导电层，包括：
形成金属材料层，所述金属材料层覆盖所述基底的上表面，并填满所述字线沟槽和所述凹型结构；
去除覆盖所述基底的上表面的所述金属材料层以及位于所述字线沟槽内的部分所述金属材料层，保留的所述金属材料层作为所述导电层。
在其中一个实施例中，在形成所述金属材料层之前，还包括：
形成栅绝缘层，所述栅绝缘层覆盖所述字线沟槽的表面和所述凹型结构的表面；
在所述栅绝缘层表面形成金属阻挡层，所述金属阻挡层位于所述栅绝缘层与所述导电层之间。
在其中一个实施例中，所述制作方法还包括：
形成绝缘填充层，所述绝缘填充层覆盖所述基底表面且填充所述字线沟槽。
基于同一发明构思，还提供了一种埋入式栅极，包括：
基底；
字线沟槽，位于所述基底内，且所述字线沟槽的表面具有凹槽结构；以及
导电层，位于所述字线沟槽内，且所述导电层的表面具有与所述凹槽结构相匹配的凸起结构。
在其中一个实施例中，所述埋入式栅极还包括栅绝缘层，所述栅绝缘层位于所述导电层与所述基底之间。
在其中一个实施例中，所述导电层包括金属层。
在其中一个实施例中，所述埋入式栅极还包括金属阻挡层，所述金属阻挡层位于所述栅绝缘层与所述金属层之间。
综上，本申请中，通过先在字线沟槽的表面形成凹型结构，然后再在所述字线沟槽内形成其表面具有与所述凹型结构相匹配的凸型结构的导电层，从而在不改变字线沟槽宽度的前提下，通过改变字线结构的形状来增大字线沟槽长度，进而解决因器件尺寸变小所导致的短沟道效应，提高器件性能。
附图说明
图1为一实施例提供的一种半导体器件的制作方法流程图；
图2-图7为一实施例提供的逐步刻蚀后的半导体结构的结构示意图；
其中，附图标记如下：
基底-100，字线沟槽-200，凹型结构-210，导电层-300，凸型结构-310，栅绝缘层-400，金属阻挡层-500，绝缘填充层-600，半球形硅晶颗粒-700。
具体实施方式
为使本申请的上述目的、特征和优点能够更加明显易懂，下面结合附图对本申请的具体实施方式做详细的说明。在下面的描述中阐述了很多具体细节以便于充分理解本申请。但是本申请能够以很多不同于在此描述的其它方式来实施，本领域技术人员可以在不违背本申请内涵的情况下做类似改进，因此本申请不受下面公开的具体实施的限制。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。
应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层、掺杂类型和/或部分，这些元件、部件、区、层、掺杂类型和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层、掺杂类型或部分与另一个元件、部件、区、层、掺杂类型或部分。因此，在不脱离本申请教导之下，下面讨论的第一元件、部件、区、层、掺杂类型或部分可表示为第二元件、部件、区、层或部分。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可以用于描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语 还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。此外，器件也可以包括另外地取向(譬如，旋转90度或其它取向)，并且在此使用的空间描述语相应地被解释。
可以理解，由于动态随机存取存储器器件本身的尺寸很小，并且受工艺条件的限制，使得有源区面积减小，从而导致栅极沟道长度变短，当栅极沟道长度减短至一定尺寸后，就会引发短沟道效应，例如，阈值电压变小，工作电流降低，热载流子效应加重，以及阈值特性退化导致器件无法关断等问题。
基于此，本申请实施例提供了一种埋入式栅极的制作方法，请参见图1，所述埋入式栅极的制作方法包括：
步骤S110，提供基底100；
步骤S120，在所述基底100中形成字线沟槽200；
步骤S130，对所述字线沟槽200的表面进行处理，以在所述字线沟槽200的表面形成凹型结构210；
步骤S140，在所述字线沟槽200内形成导电层300，所述导电层300的表面具有与所述凹型结构210相匹配的凸型结构310。
可以理解，由于器件本身的尺寸很小，并且受工艺条件的限制，使得有源区面积减小，从而导致栅极沟道长度变短，当栅极沟道长度减短至一定尺寸后，就会引发短沟道效应，例如，阈值电压变小，工作电流降低，热载流子效应加重，以及阈值特性退化导致器件无法关断等。
基于此，本申请实施例中，首先在所述基底100中形成字线沟槽200， 该字线沟槽200的宽度为标准的字线沟槽200宽度；然后，对所述字线沟槽200的表面进行刻蚀，在所述字线沟槽200的表面形成凹型结构210；最后，在所述字线沟槽200内形成导电层300，所述导电层300的表面具有与所述凹型结构210相匹配的凸型结构310，通过所述凹型结构210和所述凸型结构310增大导电层300与字线沟槽200之间的相对面积，从而在保证栅极沟道的宽度不变的前提下，增大栅极沟槽的长度，以改善因器件尺寸变小所导致的短沟道效应。
为了便于描述本申请，下面按照工艺步骤的先后顺序，对本申请提供的半导体器件的制作方法进行详细的描述。
执行步骤S110，提供基底100。一般的，所述基底100可包括硅衬底、外延硅衬底、硅锗衬底或硅覆绝缘衬底等半导体衬底，但不以此为限，本领域技术人员熟知的任何用于承载半导体集成电路组成元件的基材均可。
本实施例中，在所述基底100上形成浅沟槽隔离结构(未图示)和有源区(未图示)，其中所述浅沟槽隔离结构将所述有源区与周围环境隔离开。当待制作的半导体器件为存储器时，浅沟槽隔离结构可以将有源区隔离成阵列排布，以制作存储器的存储阵列。所述浅沟槽隔离结构可以包括位于所述基底100中的浅沟槽和填充所述浅沟槽的隔离材料，所述隔离材料可以包括通过热氧化工艺形成并覆盖在所述浅沟槽的衬氧化层(line oxide)以及位于衬氧化层的表面上并填满所述浅沟槽的二氧化硅，由此提高浅沟槽隔离结构的隔离性能。
此外，在其他一些实施例中，所述基底100包括SOI(Silicon-On-Insulator，绝缘衬底上的硅)衬底，SOI衬底包括硅材料层(未图示)、背衬底(未图示)以及夹设在所述硅材料层和所述背衬底之间的氧化材料层(未图示)。
可以理解，本实施例中采用SOI衬底，在刻蚀所述字线沟槽200的过程中可以利用所述氧化材料作为刻蚀停止层，便于控制字线沟槽200的深度。并且，所述氧化材料层可以消除衬底基板中的漏电流影响，进一步提高半导体器件的效能。另，所述硅材料层可以是未掺杂的硅材料层或掺杂的硅材料层，掺杂的硅材料层可以是经N型或P型掺杂的硅材料层。
在形成基底100后，执行步骤S120，在所述基底100上形成字线沟槽200。请参见图2，本实施例中，形成字线沟槽200的步骤主要包括：
1)对所述有源区进行掺杂，以在字线沟槽200两侧分别形成源极(未图示)和/或漏极(未图示)，具体的，单个有源区中形成两个字线沟槽200时，两个字线沟槽200之间为公有的源极，两个字线沟槽200外侧分别对应漏极。可以理解的是，所述源极和所述漏极在工艺流程中的形成时间可根据实际工艺情况进行调整，本实施例并不对此进行限制。例如，源极和漏极也可以在形成字线沟槽200之后形成，还可以在形成导电层300之后形成。
2)形成硬掩膜层，具体的，可通过沉积工艺在具有浅沟槽隔离结构和衬氧化层的表面沉积掩膜材料，形成硬掩膜层。其中，所述沉积工艺包括化学气相沉积(CVD)、物理气相沉积(PVD)或原子层沉积(ALD)等。本实施例中，通过在所述基板表面依次衬底有机掩膜材料和硬掩膜材料，分别形成有机掩膜材料层和硬掩膜材料层，叠层设置的有机掩膜材料层和硬掩膜材料层共同构成所述硬掩膜层。通常采用含碳有机材料形成所述有机掩膜材料层；采用氮化硅、氮氧化硅、碳氮化硅、金属氮化物、金属氧化物和金属碳化物中的一种或多种形成所述硬掩膜材料层，优选为氮化硅(SiN)，因为氮化硅材料具有易获取、成本低、制造方法成熟等优点，且与衬氧化层中的氧化硅具有较高的刻蚀选择比。
3)图案化所述硬掩膜层，形成贯穿所述硬掩膜层的开口图形，所述开口图形定义出了字线沟槽200。具体的，可以利用匹配的掩膜板，通过在所述硬掩膜材料层上涂覆一层光刻胶，利用激光器通过光罩照射所述光刻胶层，引起曝光区域的光刻胶发生化学反应；再通过显影技术溶解去除曝光区域或未曝光区域的光刻胶(前者称正性光刻胶，后者称负性光刻胶)，将光罩上的图案转移到光刻胶层，形成用于定义字线沟槽200的图案。然后，以具有所述图案的光刻胶层为掩膜板，刻蚀硬掩膜层至衬氧化层表面，以形成具有开口图形的图案化硬掩膜层。
4)去除光刻胶，并以图案化的硬掩膜层为掩膜继续向下刻蚀，以在所述基板的有源区中形成字线沟槽200。在一些实施例中，多个有源区呈阵平行交错分布，每一所述有源区均为长条状，在单个有源区上形成的沟槽数量不限。通常情况下，单个有源区中形成有两个字线沟槽200。本实施例中，在所述有源区上形成埋伏导电层300的字线沟槽200。所述字线沟槽200为等间距平行排列，并且单个有源区上有两个所述字线沟槽200。
请参见图3和图4，在形成字线沟槽200后，通过执行步骤S130在所述字线沟槽200的侧壁和底表面上形成凹型结构210，以增大栅极沟道的长度。在其中一个实施例中，所述在所述字线沟槽200的表面形成凹型结构210，包括：
在所述字线沟槽200的表面形成多个半球形硅晶颗粒700；
以多个所述半球形硅晶颗粒700为掩膜，对所述字线沟槽200的表面进行刻蚀，形成所述凹型结构210；
去除多个所述半球形硅晶颗粒700。
本实施例中，首先利用HSG工艺在字线沟槽200的表面形成半球形硅晶 颗粒700，该过程包括：将形成有字线沟槽200的基板置于反应腔内进行处理，经过处理后沟槽的侧壁和底表面上会形成多个半球形硅晶颗粒700。所述半球形硅晶颗粒700的大小可通过调整反应时间和反应条件进行控制。然后，以多个所述半球形硅晶颗粒700为掩膜，利用干法刻蚀工艺对所述字线沟槽200的表面进行刻蚀，在所述字线沟槽200的侧壁和底表面上形成多个凹型结构210。最后，去除多个所述半球形硅晶颗粒700。
一般通过沉积工艺制作半球形硅晶颗粒700，如CVD、PVD和LPCVD等。在其中一个实施例中，采用LPCVD工艺形成所述半球多晶硅颗粒，所述LPCVD工艺中的反应气体包括SiH 4，反应温度范围为500℃～600℃，反应压力范围为0.1torr～0.5torr。
本实施例中，将具有字线沟槽200的降低放置在反应腔内，然后调整反应参数，其中应温度范围为500℃～600℃，反应压力范围为0.1torr～0.5torr。在反应过程中，将SiH 4气体通入加有小颗粒硅粉的流化床反应炉内进行连续热分解反应，生成粒状多晶硅，并附着在基底100的表面和所述字线沟槽200的表面。另外，还可以以SiCl 4(或SiF 4)、H 2、HCl的反应气体和冶金硅为原料在高温高压流化床(沸腾床)反应炉内生成SiHCl 3，将SiHCl 3再进一步歧化加氢反应生成SiH 2Cl 2，继而生成SiH 4气体；制得的SiH 4气体通入加有小颗粒硅粉的流化床反应炉内进行连续热分解反应，生成粒状多晶硅并附着在硬掩膜层的表面和所述字线沟槽200的表面。
此外，为了减少工艺流程以及降低生产成本，可以先保留硬掩膜层及其表面的半球形硅晶颗粒700，利用硬掩膜层及其表面的半球形硅晶颗粒700保护基底100，避免有源区受到损伤；并且，在对所述字线沟槽200的表面形成凹型结构后，利用包括氢氟酸和氧气的刻蚀气体去除所述半球形硅晶颗 粒700，或者通过将形成有凹型结构210的衬底暴露于氯基刻蚀气体(可以包括氯气、三氯化硼、三氟化氯、氯化氢中的一种或多种)中，利用氯基刻蚀气体去除所述半球形硅晶颗粒700；然后通过刻蚀工艺或者化学机械平坦化工艺等去除基底100表面上的衬氧化层和硬掩膜层等，并进一步进行清洗，以暴露出干净的有源区表面、字线沟槽200的侧壁和底表面以及凹型结构210的内表面。
请参见图5，在字线沟槽200的表面形成凹型结构210后，在形成所述导电层300之前，还包括：
形成栅绝缘层400，所述栅绝缘层400覆盖所述字线沟槽200的表面和所述凹型结构210的表面；
在所述栅绝缘层400表面形成金属阻挡层500，所述金属阻挡层500位于所述栅绝缘层400与所述导电层300之间。
本实施例中，于所述字线沟槽200的侧壁及底部形成栅绝缘层400，所述栅绝缘层400完全覆盖所述字线沟槽200栅的侧壁和底表面，以及所述凹型结构210的表面；并且栅绝缘层400延伸至所述字线沟槽200的顶部，其顶部与所述衬底顶部齐平。更具体的，所述栅绝缘层400可通过沉积工艺或热氧化工艺在所述基底100上表面、所述字线沟槽200的侧壁和底部以及所述凹型结构210的表面上形成氧化硅材料层，然后通过刻蚀工艺或化学机械研磨工艺去除所述基底100上表面的氧化硅材料，保留所述沟槽的侧壁和底部以及所述凹型结构210的表面上的氧化硅材料层，形成所述栅绝缘层400。此外，还可以利用高K(介电常数K大于7)介质材料替代所述氧化硅材料，常用的高K介质材料包括Ta 2O 5、TiO 2、Al 2O 3、Pr 2O 3、La 2O 3、LaAlO 3、HfO 2、ZrO 2或其它组分的金属氧化物。
在形成栅绝缘层400后，利用沉积工艺形成阻挡材料层，阻挡材料层覆盖所述基底100的上表面以及所述栅绝缘层400的表面；然后通过刻蚀或化学机械研磨工艺去除基底100的上表面的阻挡材料层，并将保留的阻挡材料层作为金属阻挡层500。本实施例中，所述金属阻挡层500能够防止导电层300中的导电材料扩散至栅绝缘层，导致影响栅绝缘层的性能。此外，所述金属阻挡层500还具有增强导电层300与栅绝缘层之间的粘附力的作用。另外，为确保所述金属阻挡层500能够为导电层300提供足够的保护，形成的金属阻挡层500可以具有多层堆叠复合结构。
在其中一个实施例中，所述金属阻挡层500采用氮化钛(TiN)材料制作。氮化钛材料层与栅绝缘层400的组合相比于单独设置栅绝缘层400，有利于提高介电常数、缩小栅长度、提高驱动电流以及降低阈值电压。
请参见图6，在形成金属阻挡层500后，执行步骤S140，在所述字线沟槽200内形成导电层300，所述导电层300的表面具有与所述凹型结构210相匹配的凸型结构310。在其中一个实施例中，在所述字线沟槽200内形成所述导电层300，包括：
形成金属材料层，所述金属材料层覆盖所述基底100的上表面，并填满所述字线沟槽200和所述凹型结构210；
去除覆盖所述基底100的上表面的所述金属材料层以及位于所述字线沟槽200内的部分所述金属材料层，保留的所述金属材料层作为所述导电层300。
本实施例中，通过CVD或PVD等沉积工艺形成金属材料层，所述金属材料层填满所述字线沟槽200和凹型结构210，且覆盖所述金属阻挡层500的表面和所述基底100的上表面；然后，去除覆盖所述金属阻挡层500的上表 面和所述基底100的上表面的金属材料以及位于字线沟槽200内的部分高度的金属材料层，以使金属材料层的上表面低于所述基底100的上表面，以形成埋入式栅极。具体的，所述金属材料包括钨、钴、锰、铌、镍、钼等导电性良好的金属材料一种或多种。另外，在一些实施例中，为了减少工艺、降低成本，可利用同一道刻蚀工艺对阻挡材料层和金属材料层进行刻蚀，以形成金属阻挡层500和导电层300。
在其他一些实施例中，所述导电层300包括堆叠的金属材料层和半导体导电材料层(未图示)。本实施例中，所述半导体导电材料层的材料包括多晶硅、锗化硅，砷化镓、磷化镓、硫化镉、硫化锌中的任一种或其任意组合。所述半导体导电材料层与所述金属材料层共同构成双功函数栅极。本实施例通过设置堆叠的导电层300可有效解决栅诱导漏极泄漏电流问题。
另外，在该双功函数栅极的制程中，经过热制程之后，会出现金属层中的金属向多晶硅层中扩散的问题，从而影响多晶硅层性能。基于此，在其中一个实施例中，所述埋入式栅极还包括在所述金属材料层和多晶硅材料层之间形成等电位介质层的步骤，利用所述等电位介质层作为金属阻挡层500防止金属材料层中的导电材料向半导体导电材料层扩散，同时使金属材料层与半导体导电材料层连通形成等电位，改善器件性能。本实施例中，可采用氧化硅、氮化硅、氮氧化硅、碳氧化硅、碳氮化硅中的任一种或其任意组合形成所述等电位介质层。
请参见图7，在其中一个实施例中，所述埋入式栅极的制作方法还包括：
形成绝缘填充层600，所述绝缘填充层600覆盖所述基底100表面且填充所述字线沟槽200。
本实施例中，形成的所述导电层300的顶部低于所述字线沟槽200的顶 部，以增大所述导电层300和后续形成的存储节点插塞以及位线连接插塞的距离，减少寄生电容。利用氮化硅等具有加高的带宽和良好的绝缘性能的低K介质材质填充满字线沟槽200，可以起到很好的保护和绝缘效果。此外，所述填充绝缘层与所述基底100的上表面齐平，形成平坦的表面，有利于在其上方形成其它结构。
基于同一发明构思，本申请实施例还提供了一种埋入式栅极。请继续参见图7，所述埋入式栅极包括基底100、字线沟槽200和导电层300。
其中，所述字线沟槽200位于所述基底100内，且所述字线沟槽200的表面具有凹槽结构。
所述导电层300位于所述字线沟槽200内，且所述导电层300的表面具有与所述凹槽结构相匹配的凸起结构。
本实施例中，通过在所述字线沟槽200的表面形成有凹槽结构，以及在所述导电层300表面设置具有与所述凹型结构210相匹配的凸型结构310，通过所述凹型结构210和所述凸型结构310增大导电层300与字线沟槽200之间的相对面积，从而在保证栅极沟道的宽度不变的前提下，增大栅极沟槽的长度，以改善因器件尺寸变小所导致的短沟道效应。
在其中一个实施例中，所述导电层300包括金属层。本实施例中，采用钨、钴、锰、铌、镍、钼等导电性良好的金属材料一种或多种形成所述金属层。
在其中一个实施例中，所述导电层300包括叠层设置的金属层和半导体导电层300，其中所述半导体导电层300位于所述金属层的上方。本实施例中，所述半导体导电材料层的材料包括多晶硅、锗化硅，砷化镓、磷化镓、硫化镉、硫化锌中的任一种或其任意组合。所述半导体导电材料层与所述金 属材料层共同构成双功函数栅极。本实施例通过设置堆叠的导电层300可有效解决栅诱导漏极泄漏电流问题。
另外，在该双功函数栅极的制程中，经过热制程之后，会出现金属层中的金属向多晶硅层中扩散的问题，从而影响多晶硅层性能。基于此，在其中一个实施例中，所述埋入式栅极还包括在所述金属材料层和多晶硅材料层之间的等电位介质层，利用所述等电位介质层作为金属阻挡层500防止第一导电层300中的导电材料向第二导电层300扩散，同时使第一导电层300与第二导电层300连通形成等电位，改善器件性能。本实施例中，可采用氧化硅、氮化硅、氮氧化硅、碳氧化硅、碳氮化硅中的任一种或其任意组合形成所述等电位介质层。
在其中一个实施例中，所述埋入式栅极还包括金属阻挡层500，所述金属阻挡层500位于所述栅绝缘层400与所述金属层之间。本实施例中，所述金属阻挡层500能够防止导电层300中的导电材料扩散至栅绝缘层，导致影响栅绝缘层的性能。此外，所述金属阻挡层500还具有增强导电层300与栅绝缘层之间的粘附力的作用。另外，为确保所述金属阻挡层500能够为导电层300提供足够的保护，形成的金属阻挡层500可以具有多层堆叠复合结构。另，本实施例所述金属阻挡层500可采用氮化钛(TiN)材料制作。氮化钛材料层与栅绝缘层400的组合相比于单独设置栅绝缘层400，有利于提高介电常数、缩小栅长度、提高驱动电流以及降低阈值电压。
在其中一个实施例中，所述埋入式栅极还包括栅绝缘层400，所述栅绝缘层400位于所述导电层300与所述基底100之间。本实施例中，所述栅绝缘层400完全覆盖所述字线沟槽200栅的侧壁和底表面，以及所述凹型结构210的表面；并且栅绝缘层400延伸至所述字线沟槽200的顶部，其顶部与 所述衬底顶部齐平。此外，所述栅绝缘层400的制作材料可以氧化硅；在其他一些实施例中，还可以利用高K(介电常数K大于7)介质材料替代所述氧化硅材料，常用的高K介质材料包括Ta 2O 5、TiO 2、Al 2O 3、Pr 2O 3、La 2O 3、LaAlO 3、HfO 2、ZrO 2或其它组分的金属氧化物。
在其中一个实施例中，所述埋入式栅极还包括绝缘填充层600。本实施例中，所述导电层300的顶部低于所述字线沟槽200的顶部，可增大所述导电层300和后续形成的存储节点插塞以及位线连接插塞的距离，减少寄生电容。利用氮化硅等具有加高的带宽和良好的绝缘性能的低K介质材质填充满字线沟槽200，可以起到很好的保护和绝缘效果。此外，所述填充绝缘层与所述基底100的上表面齐平，形成平坦的表面，有利于在其上方形成其它结构。
综上，本申请提供了一种埋入式栅极及其制作方法。其中埋入式栅极的制作方法包括：提供基底100；在所述基底100中形成字线沟槽200；对所述字线沟槽200的表面进行处理，以在所述字线沟槽200的表面形成凹型结构210；在所述字线沟槽200内形成导电层300，所述导电层300的表面具有与所述凹型结构210相匹配的凸型结构310。本申请中，通过先在字线沟槽200的表面形成凹型结构210，然后再在所述字线沟槽200内形成其表面具有与所述凹型结构210相匹配的凸型结构310的导电层300，从而在不改变字线沟槽200宽度的前提下，通过改变字线结构的形状来增大字线沟槽200长度，进而解决因器件尺寸变小所导致的短沟道效应，提高器件品质。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (10)

  1. 一种埋入式栅极的制作方法，包括：
    提供基底；
    在所述基底中形成字线沟槽；
    对所述字线沟槽的表面进行处理，以在所述字线沟槽的表面形成凹型结构；
    在所述字线沟槽内形成导电层，所述导电层的表面具有与所述凹型结构相匹配的凸型结构。
  2. 如权利要求1所述的方法，其中所述在所述字线沟槽的表面形成凹型结构，包括：
    在所述字线沟槽的表面形成多个半球形硅晶颗粒；
    以多个所述半球形硅晶颗粒为掩膜，对所述字线沟槽的表面进行刻蚀，形成所述凹型结构；
    去除多个所述半球形硅晶颗粒。
  3. 如权利要求2所述的方法，其中采用LPCVD工艺形成所述半球多晶硅颗粒，所述LPCVD工艺中的反应气体包括SiH 4，反应温度范围为500℃～600℃，反应压力范围为0.1torr～0.5torr。
  4. 如权利要求1所述的方法，其中在所述字线沟槽内形成所述导电层，包括：
    形成金属材料层，所述金属材料层覆盖所述基底的上表面，并填满所述字线沟槽和所述凹型结构；
    去除覆盖所述基底的上表面的所述金属材料层以及位于所述字线沟槽内的部分所述金属材料层，保留的所述金属材料层作为所述导电层。
  5. 如权利要求4所述的方法，其中在形成所述金属材料层之前，还包括：
    形成栅绝缘层，所述栅绝缘层覆盖所述字线沟槽的表面和所述凹型结构的表面；
    在所述栅绝缘层表面形成金属阻挡层，所述金属阻挡层位于所述栅绝缘层与所述导电层之间。
  6. 如权利要求1所述的方法，还包括：
    形成绝缘填充层，所述绝缘填充层覆盖所述基底表面且填充所述字线沟槽。
  7. 一种埋入式栅极，包括：
    基底；
    字线沟槽，位于所述基底内，且所述字线沟槽的表面具有凹槽结构；以及
    导电层，位于所述字线沟槽内，且所述导电层的表面具有与所述凹槽结构相匹配的凸起结构。
  8. 如权利要求7所述的埋入式栅极，还包括栅绝缘层，所述栅绝缘层位于所述导电层与所述基底之间。
  9. 如权利要求8所述的埋入式栅极，其中所述导电层包括金属层。
  10. 如权利要求9所述的埋入式栅极，其中还包括金属阻挡层，所述金属阻挡层位于所述栅绝缘层与所述金属层之间。
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