WO2022016706A1 - 像素电路、其驱动方法及显示装置 - Google Patents

像素电路、其驱动方法及显示装置 Download PDF

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Publication number
WO2022016706A1
WO2022016706A1 PCT/CN2020/118660 CN2020118660W WO2022016706A1 WO 2022016706 A1 WO2022016706 A1 WO 2022016706A1 CN 2020118660 W CN2020118660 W CN 2020118660W WO 2022016706 A1 WO2022016706 A1 WO 2022016706A1
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Prior art keywords
terminal
signal
control
transistor
light
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Ceased
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PCT/CN2020/118660
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English (en)
French (fr)
Inventor
青海刚
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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Priority to CN202080002226.9A priority Critical patent/CN114270430B/zh
Priority to US17/296,295 priority patent/US11922882B2/en
Publication of WO2022016706A1 publication Critical patent/WO2022016706A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
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    • G09G2300/0421—Structural details of the set of electrodes
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    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a pixel circuit, a driving method thereof, and a display device.
  • OLED Organic Light Emitting Diode
  • a data writing circuit electrically connected to the first end of the drive transistor, and configured to provide the signal of the data signal end to the first end of the drive transistor under the control of the signal of the scan signal end;
  • the first end of the compensation capacitor is electrically connected to the first power supply end, and the second end of the compensation capacitor is electrically connected to the first end of the driving transistor;
  • a storage circuit which is respectively electrically connected to the control terminal of the driving transistor and the first power supply terminal;
  • a second reset circuit electrically connected to the control terminal of the driving transistor, and configured to initialize the control terminal of the driving transistor according to the signal of the initialization signal terminal;
  • a light-emitting control circuit is electrically connected to the first power supply terminal, the first and second terminals of the driving transistor, and the light-emitting device, and is configured to, under the control of the signal of the light-emitting control signal terminal, connect the A power supply terminal is connected to the first terminal of the driving transistor, and the second terminal of the driving transistor is connected to the light-emitting device to drive the light-emitting device to emit light.
  • the pixel circuit further includes:
  • a threshold compensation circuit respectively electrically connected to the control terminal and the second terminal of the driving transistor, and configured to turn on the control terminal and the second terminal of the driving transistor under the control of the signal of the first control signal terminal, for threshold compensation.
  • the threshold compensation circuit includes:
  • control terminal of the first transistor is electrically connected to the first control signal terminal
  • first terminal of the first transistor is electrically connected to the control terminal of the driving transistor
  • first terminal of the first transistor is electrically connected to the control terminal of the driving transistor.
  • the two terminals are electrically connected to the second terminal of the driving transistor.
  • the pixel circuit further includes:
  • the first reset circuit is electrically connected to the light emitting device, and is configured to provide the signal of the initialization signal end to the light emitting device under the control of the signal of the second control signal end.
  • the first reset circuit includes:
  • a second transistor the control terminal of the second transistor is electrically connected to the second control signal terminal, the first terminal of the second transistor is electrically connected to the initialization signal terminal, and the second terminal of the second transistor is electrically connected is electrically connected to the light emitting device.
  • the storage circuit includes:
  • a storage capacitor a first terminal of the storage capacitor is electrically connected to the first power supply terminal, and a second terminal of the storage capacitor is electrically connected to the control terminal of the driving transistor.
  • the second reset circuit includes:
  • control terminal of the third transistor is electrically connected to the reset signal terminal
  • first terminal of the third transistor is electrically connected to the initialization signal terminal
  • second terminal of the third transistor is electrically connected to the reset signal terminal
  • the control terminal of the driving transistor is electrically connected.
  • the second reset circuit further includes:
  • the control terminal of the auxiliary transistor is electrically connected to the scanning signal terminal, the first terminal of the auxiliary transistor is electrically connected to the second terminal of the third transistor, and the second terminal of the auxiliary transistor is electrically connected to the The control terminal of the driving transistor is electrically connected.
  • the lighting control circuit includes:
  • control terminal of the fourth transistor is electrically connected to the light-emitting control signal terminal, the first terminal of the fourth transistor is electrically connected to the first power supply terminal, and the second terminal of the fourth transistor is electrically connected electrically connected to the first end of the driving transistor;
  • control terminal of the fifth transistor is electrically connected to the light-emitting control signal terminal
  • first terminal of the fifth transistor is electrically connected to the second terminal of the driving transistor
  • first terminal of the fifth transistor is electrically connected to the second terminal of the driving transistor.
  • the two ends are electrically connected to the light emitting device.
  • the data writing circuit includes:
  • the control terminal of the sixth transistor is electrically connected to the scan signal terminal
  • the first terminal of the sixth transistor is electrically connected to the data signal terminal
  • the second terminal of the sixth transistor is electrically connected to the data signal terminal
  • the first end of the driving transistor is electrically connected.
  • the second reset circuit initializes the control terminal of the driving transistor according to the signal of the initialization signal terminal;
  • the data writing circuit under the control of the signal at the scanning signal end, the data writing circuit provides the signal at the data signal end to the first end of the drive transistor, and stores it through the compensation capacitor; Under the control of the signal at the control signal end, the control end and the second end of the driving transistor are turned on to perform threshold compensation;
  • the threshold compensation circuit turns on the control end and the second end of the driving transistor under the control of the signal at the first control signal end to perform threshold compensation
  • the light-emitting control circuit under the control of the signal at the light-emitting control signal terminal, conducts the first power supply terminal with the first terminal of the driving transistor, and connects the second terminal of the driving transistor with the first terminal of the driving transistor.
  • the light-emitting device is turned on, and the light-emitting device is driven to emit light.
  • the second control signal terminal and the first control signal terminal are the same signal terminal
  • the driving method further includes:
  • the first reset circuit provides the signal of the initialization signal terminal to the light-emitting device under the control of the signal of the second control signal terminal;
  • the first reset circuit provides the signal of the initialization signal terminal to the light-emitting device under the control of the signal of the second control signal terminal.
  • the second control signal terminal and the reset signal terminal are the same signal terminal
  • the driving method further includes:
  • the first reset circuit provides the signal from the initialization signal terminal to the light-emitting device under the control of the signal from the second control signal terminal.
  • the second control signal terminal and the scan signal terminal are the same signal terminal
  • the driving method further includes:
  • the first reset circuit provides the signal from the initialization signal terminal to the light emitting device under the control of the signal from the second control signal terminal.
  • the driving method further includes:
  • the first reset circuit provides the signal from the initialization signal terminal to the light-emitting device under the control of the signal from the second control signal terminal;
  • the first reset circuit provides the signal of the initialization signal terminal to the light-emitting device under the control of the signal of the second control signal terminal;
  • the first reset circuit provides the signal of the initialization signal terminal to the light-emitting device under the control of the signal of the second control signal terminal.
  • the driving method further includes:
  • the first reset circuit provides the signal of the initialization signal terminal to the light-emitting device under the control of the signal of the second control signal terminal.
  • the driving method prior to the reset phase, the driving method further includes:
  • the first reset circuit provides the signal of the initialization signal terminal to the light-emitting device under the control of the signal of the second control signal terminal.
  • the driving method further includes:
  • the first reset circuit provides the signal of the initialization signal terminal to the light-emitting device under the control of the signal of the second control signal terminal.
  • the pixel circuit further includes: a first reset circuit; before the reset stage, the driving method further includes: an anode reset stage; wherein, in the anode reset stage, the first reset circuit Under the control of the signal of the second control signal terminal, the signal of the initialization signal terminal is provided to the light-emitting device, and the light-emitting device is initialized;
  • the driving method further includes: in the reset stage, the first reset circuit, under the control of the signal of the second control signal terminal, provides the signal of the initialization signal terminal to the light-emitting device, and initializes the light-emitting device;
  • the data writing circuit provides the signal of the data signal end to the first end of the driving transistor under the control of the signal of the scan signal end.
  • the display device provided by the embodiment of the present disclosure includes the above-mentioned pixel circuit.
  • FIG. 1 is a schematic structural diagram of a pixel circuit in an embodiment of the disclosure
  • FIG. 2 is a schematic diagram of a specific structure of some pixel circuits in an embodiment of the disclosure
  • 3 is a timing diagram of some signals in an embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of a specific structure of further pixel circuits in an embodiment of the disclosure.
  • FIG. 5 is a timing diagram of further signals in an embodiment of the present disclosure.
  • FIG. 6 is a timing diagram of further signals in an embodiment of the present disclosure.
  • FIG. 7 is a timing diagram of some further signals in an embodiment of the present disclosure.
  • FIG. 8 is a timing diagram of further signals in an embodiment of the present disclosure.
  • FIG. 9 is a timing diagram of further signals in an embodiment of the present disclosure.
  • FIG. 10 is a timing diagram of further signals in the embodiments of the present disclosure.
  • FIG. 11 is a timing diagram of further signals in an embodiment of the present disclosure.
  • FIG. 12 is a schematic diagram of a specific structure of further pixel circuits in an embodiment of the disclosure.
  • FIG. 13 is a schematic diagram of the specific structure of further pixel circuits in an embodiment of the disclosure.
  • FIG. 14 is a schematic diagram of a specific structure of further pixel circuits in an embodiment of the disclosure.
  • 15 is a schematic diagram of the specific structure of further pixel circuits in an embodiment of the disclosure.
  • FIG. 16 is a timing diagram of further signals in an embodiment of the present disclosure.
  • Some pixel circuits provided by the embodiments of the present disclosure, as shown in FIG. 1 may include:
  • the data writing circuit 10 is electrically connected to the first end of the drive transistor M0, and is configured to provide the signal of the data signal end DA to the first end of the drive transistor M0 under the control of the signal of the scan signal end GA;
  • the first end of the compensation capacitor CF is electrically connected to the first power supply terminal ELVDD, and the second end of the compensation capacitor CF is electrically connected to the first end of the driving transistor M0;
  • the storage circuit 21 is respectively electrically connected to the control terminal of the driving transistor M0 and the first power terminal ELVDD;
  • the second reset circuit 22 is electrically connected to the control terminal of the driving transistor M0, and is configured to initialize the control terminal of the driving transistor M0 according to the signal of the initialization signal terminal VINIT; Under the control, the signal of the initialization signal terminal VINIT is provided to the control terminal of the driving transistor M0;
  • the light-emitting control circuit 23 is electrically connected to the first power supply terminal ELVDD, the first and second terminals of the driving transistor M0 and the light-emitting device L, and is configured to connect the first power supply to the light-emitting control signal terminal EM under the control of the signal.
  • the terminal ELVDD is connected to the first terminal of the driving transistor M0, and the second terminal of the driving transistor M0 is connected to the light emitting device L, and the light emitting device L is driven to emit light.
  • the control terminal of the driving transistor can be initialized according to the signal of the initialization signal terminal through the second reset circuit.
  • the signal of the data signal end can be provided to the first end of the driving transistor through the data writing circuit under the control of the signal of the scan signal end.
  • the first power supply terminal is connected to the first terminal of the driving transistor, and the second terminal of the driving transistor is connected to the light-emitting device to drive the light-emitting device to emit light.
  • the compensation capacitor By setting the compensation capacitor, since the compensation capacitor is electrically connected to the first end of the driving transistor, the signal input to the first end of the driving transistor can be stored, so that the voltage input to the first end of the driving transistor can be stabilized. In this way, when the second end of the driving transistor is turned on with the light-emitting device, the light-emitting device can be stably driven to emit light, thereby improving display uniformity.
  • the pixel circuit may further include: a threshold compensation circuit 30; wherein, the threshold compensation circuit 30 is electrically connected to the control terminal and the second terminal of the driving transistor M0, respectively, and It is configured to turn on the control terminal and the second terminal of the driving transistor M0 under the control of the signal of the first control signal terminal CS1, so as to perform threshold compensation.
  • the threshold compensation circuit 30 is electrically connected to the control terminal and the second terminal of the driving transistor M0, respectively, and It is configured to turn on the control terminal and the second terminal of the driving transistor M0 under the control of the signal of the first control signal terminal CS1, so as to perform threshold compensation.
  • the first end of the light emitting device L is electrically connected to the light emitting control circuit 23
  • the second end of the light emitting device L is electrically connected to the second power supply end ELVSS.
  • the first end of the light emitting device L electrically connected to the light emitting control circuit 23 is its positive electrode
  • the second end connected to the second power supply end ELVSS is its negative electrode.
  • the light emitting device L may be at least one of an organic light emitting diode and a quantum dot light emitting diode.
  • the light emitting device L realizes light emission under the action of the current when the driving transistor M0 is in a saturated state.
  • the light-emitting device L has a turn-on voltage, and emits light when the voltage difference between the two ends of the light-emitting device L is greater than or equal to the turn-on voltage.
  • the voltage Vdd of the first power supply terminal ELVDD is generally positive
  • the voltage Vss of the second power supply terminal ELVSS is generally grounded or negative.
  • the voltage Vini of the initial signal terminal and the voltage Vss of the second power terminal ELVSS need to satisfy the formula: Vini-Vss ⁇ Vth(L); wherein Vth(L) is the turn-on voltage of the light emitting device L.
  • the driving transistor M0 may be a P-type transistor; wherein, the control terminal N3 of the driving transistor M0 may be its gate, The first terminal N1 of the driving transistor M0 may be its source, and the second terminal N2 of the driving transistor M0 may be its drain.
  • the driving transistor M0 may also be an N-type transistor; wherein, the control terminal N3 of the driving transistor M0 may be its gate, the first terminal N1 of the driving transistor M0 may be its drain, and the second terminal N2 of the driving transistor M0 may be its source.
  • the type of the driving transistor M0 can be specifically designed and determined according to the requirements of the practical application, which is not limited here.
  • the threshold compensation circuit 30 may include: a first transistor M1; wherein a control terminal of the first transistor M1 and a first control signal terminal CS1 is electrically connected, the first terminal of the first transistor M1 is electrically connected to the control terminal of the driving transistor M0, and the second terminal of the first transistor M1 is electrically connected to the second terminal of the driving transistor M0.
  • the storage circuit 21 may include: a storage capacitor CST; wherein the first end of the storage capacitor CST is electrically connected to the first power supply terminal ELVDD , the second terminal of the storage capacitor CST is electrically connected to the control terminal of the driving transistor M0.
  • the second reset circuit 22 may include: a third transistor M3; wherein, the control terminal of the third transistor M3 and the reset signal terminal RST Electrical connection, the first terminal of the third transistor M3 is electrically connected to the initialization signal terminal VINIT, and the second terminal of the third transistor M3 is electrically connected to the control terminal of the driving transistor M0.
  • the light-emitting control circuit 23 includes: a fourth transistor M4 and a fifth transistor M5; wherein, the control terminal of the fourth transistor M4 is connected to the light-emitting
  • the control signal terminal EM is electrically connected, the first terminal of the fourth transistor M4 is electrically connected to the first power supply terminal ELVDD, and the second terminal of the fourth transistor M4 is electrically connected to the first terminal of the driving transistor M0.
  • the control terminal of the fifth transistor M5 is electrically connected to the light emission control signal terminal EM, the first terminal of the fifth transistor M5 is electrically connected to the second terminal of the driving transistor M0, and the second terminal of the fifth transistor M5 is electrically connected to the light emitting device L.
  • the data writing circuit 10 includes: a sixth transistor M6; wherein the control terminal of the sixth transistor M6 is electrically connected to the scan signal terminal GA.
  • the first terminal of the sixth transistor M6 is electrically connected to the data signal terminal DA, and the second terminal of the sixth transistor M6 is electrically connected to the first terminal of the driving transistor M0.
  • all transistors may be P-type transistors.
  • all transistors may be N-type transistors, which are not limited here.
  • the P-type transistor is turned off under the action of a high level, and is turned on under the action of a low level; the N-type transistor is turned on under the action of a high level, and the Cut off under the action of low level.
  • the above-mentioned transistor may be a thin film transistor (TFT, Thin Film Transistor), or a metal oxide semiconductor field effect transistor (MOS, Metal Oxide Semiconductor).
  • TFT Thin Film Transistor
  • MOS Metal Oxide Semiconductor
  • the control terminal of the transistor can be used as its gate, and according to the type of the transistor and the signal of the control terminal, the first terminal of the transistor can be used as its source, and the second terminal can be used as its drain.
  • the first end of the transistor is used as its drain, and the second end is used as its source, which is not limited herein.
  • the second reset circuit initializes the control terminal of the driving transistor according to the signal of the initialization signal terminal;
  • the data writing circuit under the control of the signal at the scanning signal end, the data writing circuit provides the signal at the data signal end to the first end of the drive transistor, and stores it through the compensation capacitor; the threshold compensation circuit controls the signal at the first control signal end Next, the control terminal and the second terminal of the driving transistor are turned on to perform threshold compensation;
  • the threshold compensation circuit turns on the control end and the second end of the driving transistor under the control of the signal at the first control signal end to perform threshold compensation
  • the light-emitting control circuit under the control of the light-emitting control signal terminal, conducts the first power supply terminal and the first terminal of the driving transistor, and conducts the second terminal of the driving transistor and the light-emitting device to drive the light-emitting device to emit light.
  • em represents the signal loaded on the light-emitting control signal terminal EM
  • rst represents the signal loaded on the reset signal terminal RST
  • ga represents the signal loaded on the scanning signal terminal GA
  • cs1 represents the signal loaded on the first control signal terminal CS1 Signal.
  • the working process of a pixel circuit in one display frame may include: a reset phase T1, a threshold compensation phase T2, a compensation hold phase T3, and a light-emitting phase T4.
  • the third transistor M3 is turned on under the control of the low level of the signal rst, so as to provide the signal of the initialization signal terminal VINIT to the control terminal N3 of the driving transistor M0, so that the control terminal N3 of the driving transistor M0 is turned on.
  • the voltage is Vini, and the control of the drive transistor M0 is initialized.
  • the first transistor M1 is turned off under the control of the high level of the signal cs1.
  • the sixth transistor M6 is turned off under the control of the high level of the signal ga.
  • the fourth transistor M4 and the fifth transistor M5 are turned off under the control of the high level of the signal em.
  • the sixth transistor M6 is turned on under the control of the low level of the signal ga, so as to provide the signal of the data signal terminal DA to the first terminal N1 of the driving transistor M0, so that the first terminal N1 of the driving transistor M0 can be turned on.
  • the voltage of the terminal N1 is the voltage Vda of the signal of the data signal terminal DA.
  • the voltage Vda is stored through the compensation capacitor CF.
  • the first transistor M1 is turned on under the control of the low level of the signal cs1, so as to turn on the control terminal N3 and the second terminal N2 of the driving transistor M0, so that the driving transistor M0 forms a diode connection mode, thereby making the driving transistor M0
  • the voltage Vda of the first terminal N1 charges the control terminal N3 of the driving transistor M0.
  • the third transistor M3 is turned off under the control of the high level of the signal rst.
  • the fourth transistor M4 and the fifth transistor M5 are turned off under the control of the high level of the signal em.
  • the voltage Vda is stored due to the compensation capacitor CF.
  • the first transistor M1 is turned on under the control of the low level of the signal cs1, so as to turn on the control terminal N3 and the second terminal N2 of the driving transistor M0, so that the driving transistor M0 forms a diode connection, and then the driving transistor M0 is connected.
  • the voltage Vda of the first terminal N1 of M0 continues to charge the control terminal N3 of the driving transistor M0, so that the voltage of the control terminal N3 of the driving transistor M0 can be charged to Vda-
  • the sixth transistor M6 is turned off under the control of the high level of the signal ga.
  • the third transistor M3 is turned off under the control of the high level of the signal rst.
  • the fourth transistor M4 and the fifth transistor M5 are turned off under the control of the high level of the signal em.
  • the fourth transistor M4 and the fifth transistor M5 are both turned on under the control of the low level of the signal em.
  • the turned-on fourth transistor M4 may provide the voltage Vdd of the first power supply terminal ELVDD to the first terminal N1 of the driving transistor M0, so that the voltage of the first terminal N1 of the driving transistor M0 is Vdd.
  • the turned-on fifth transistor M5 can conduct the second end N2 of the driving transistor M0 with the light emitting device L, so that the working current Ids flows into the light emitting device L to drive the light emitting device L to emit light.
  • K is a structural constant related to process and design.
  • the first transistor M1 is turned off under the control of the high level of the signal cs1.
  • the sixth transistor M6 is turned off under the control of the high level of the signal ga.
  • the third transistor M3 is turned off under the control of the high level of the signal rst.
  • the signal ga controls the conduction period of the sixth transistor M6 to become shorter and shorter, which leads to In the threshold compensation stage T2 , the amount of charge written into the storage capacitor CST by the signal of the data signal terminal DA through the driving transistor M0 is insufficient, thereby causing insufficient compensation of the threshold voltage of the driving transistor M0 .
  • the signal cs1 of the first control signal terminal CS1 different from the signal ga of the scan signal terminal GA, the on and off of the first transistor M1 and the sixth transistor M6 can be controlled respectively.
  • the storage capacitor CST can be charged by controlling both the first transistor M1 and the sixth transistor M6 to be turned on in the threshold compensation stage T2.
  • the storage capacitor CST can continue to be charged, so that the voltage of the control terminal N3 of the driving transistor M0 can finally reach Vda-
  • the buffering stage T5 there may also be a buffer phase T5 between the compensation holding phase T3 and the light-emitting phase T4.
  • the first transistor M1, the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 can be controlled to be turned off, so that the characteristics of the transistors in the pixel circuit can be stabilized, so that the After stabilization, it enters the next working stage, thereby improving the stability of the pixel circuit.
  • Embodiments of the present disclosure further provide some pixel circuits, and a schematic structural diagram is shown in FIG. 5 , which is modified from the implementations in the foregoing embodiments. Only the differences between this embodiment and the above-mentioned embodiments will be described below, and the similarities will not be repeated here.
  • the pixel circuit may further include: a first reset circuit 40 ; wherein, the first reset circuit 40 is electrically connected to the light-emitting device L, and the first reset circuit 40 It is configured to supply the signal of the initialization signal terminal VINIT to the light emitting device L under the control of the signal of the second control signal terminal CS2. In this way, the light emitting device L can be initialized.
  • the first reset circuit may include: a second transistor M2; wherein the control terminal of the second transistor M2 is electrically connected to the second control signal terminal CS2, and the first reset circuit The first terminal of the second transistor M2 is electrically connected to the initialization signal terminal VINIT, and the second terminal of the second transistor M2 is electrically connected to the light emitting device L.
  • the driving method may further include:
  • the first reset circuit provides the signal from the initialization signal terminal to the light-emitting device under the control of the signal from the second control signal terminal;
  • the first reset circuit provides the signal of the initialization signal terminal to the light-emitting device under the control of the signal of the second control signal terminal;
  • the first reset circuit provides the signal of the initialization signal terminal to the light-emitting device under the control of the signal of the second control signal terminal.
  • the driving method may further include: in the compensation holding stage, the first reset circuit provides the signal of the initialization signal terminal to the light emitting device under the control of the signal of the second control signal terminal.
  • the driving method may further include: in the initialization stage, the first reset circuit, under the control of the signal of the second control signal terminal, provides the signal of the initialization signal terminal to light-emitting device.
  • the driving method may further include: an initialization phase, the first reset circuit is controlled by the signal at the second control signal terminal, The signal of the initialization signal terminal is supplied to the light emitting device.
  • em represents the signal loaded on the light-emitting control signal terminal EM
  • rst represents the signal loaded on the reset signal terminal RST
  • ga represents the signal loaded on the scanning signal terminal GA
  • cs1 represents the signal loaded on the first control signal terminal CS1 signal
  • cs2 represents the signal loaded to the second control signal terminal.
  • the working process of a pixel circuit in one display frame may include: a reset phase T1, a threshold compensation phase T2, a compensation hold phase T3, and a light-emitting phase T4.
  • the second transistor M2 is turned off under the control of the high level of the signal cs2.
  • the rest of the working process in this stage may refer to the above-mentioned embodiment, and will not be repeated here.
  • the second transistor M2 is turned on under the control of the low level of the signal cs2, and the signal of the initialization signal terminal VINIT can be provided to the light-emitting device L, so as to initialize the light-emitting device L and eliminate the light-emitting device L. the interface charge of the light-emitting layer.
  • the second transistor M2 continues to be turned on under the control of the low level of the signal cs2, and further provides the signal of the initialization signal terminal VINIT to the light-emitting device L to initialize the light-emitting device L and further eliminate the light-emitting device The interface charge of the light-emitting layer in L.
  • the second transistor M2 is turned off under the control of the high level of the signal cs2.
  • the pixel circuit shown in FIG. 4 is taken as an example, and the operation process of the pixel circuit provided by the embodiments of the present disclosure is described in conjunction with the circuit timing diagram shown in FIG. 6 .
  • em represents the signal loaded on the light-emitting control signal terminal EM
  • rst represents the signal loaded on the reset signal terminal RST
  • ga represents the signal loaded on the scanning signal terminal GA
  • cs1 represents the signal loaded on the first control signal terminal CS1 signal
  • cs2 represents the signal loaded to the second control signal terminal.
  • the working process of a pixel circuit in one display frame may include: a reset phase T1, a threshold compensation phase T2, a compensation hold phase T3, and a light-emitting phase T4.
  • the second transistor M2 is turned on under the control of the low level of the signal cs2, and the signal of the initialization signal terminal VINIT can be provided to the light-emitting device L to initialize the light-emitting device L and eliminate the The interface charge of the light-emitting layer.
  • the second transistor M2 is turned off under the control of the high level of the signal cs2.
  • the second transistor M2 is turned off under the control of the high level of the signal cs2.
  • the second transistor M2 is turned off under the control of the high level of the signal cs2.
  • the rest of the working process in this stage may refer to the above-mentioned embodiment, and will not be repeated here.
  • em represents the signal loaded to the light-emitting control signal terminal EM
  • rst represents the signal loaded to the reset signal terminal RST
  • ga represents the signal loaded to the scan signal terminal GA
  • cs1 represents the signal loaded to the first control signal terminal CS1 signal
  • cs2 represents the signal loaded to the second control signal terminal.
  • the working process of a pixel circuit in one display frame may include: a reset phase T1, a threshold compensation phase T2, a compensation hold phase T3, and a light-emitting phase T4.
  • the second transistor M2 is turned off under the control of the high level of the signal cs2.
  • the second transistor M2 is turned on under the control of the low level of the signal cs2, and the signal of the initialization signal terminal VINIT can be provided to the light-emitting device L, so as to initialize the light-emitting device L and eliminate the light-emitting device L. the interface charge of the light-emitting layer.
  • the second transistor M2 is turned off under the control of the high level of the signal cs2.
  • the second transistor M2 is turned off under the control of the high level of the signal cs2.
  • em represents the signal loaded on the light-emitting control signal terminal EM
  • rst represents the signal loaded on the reset signal terminal RST
  • ga represents the signal loaded on the scanning signal terminal GA
  • cs1 represents the signal loaded on the first control signal terminal CS1 signal
  • cs2 represents the signal loaded to the second control signal terminal.
  • the working process of a pixel circuit in one display frame may include: a reset phase T1, a threshold compensation phase T2, a compensation hold phase T3, and a light-emitting phase T4.
  • the second transistor M2 is turned on under the control of the low level of the signal cs2, and the signal of the initialization signal terminal VINIT can be provided to the light-emitting device L to initialize the light-emitting device L and eliminate the The interface charge of the light-emitting layer.
  • the second transistor M2 continues to be turned on under the control of the low level of the signal cs2, and the signal of the initialization signal terminal VINIT can be provided to the light-emitting device L to initialize the light-emitting device L and further eliminate the light-emitting device The interface charge of the light-emitting layer in L.
  • the second transistor M2 continues to be turned on under the control of the low level of the signal cs2, and the signal of the initialization signal terminal VINIT can be provided to the light-emitting device L to initialize the light-emitting device L and further eliminate the light-emitting device The interface charge of the light-emitting layer in L.
  • the second transistor M2 is turned off under the control of the high level of the signal cs2.
  • em represents the signal loaded to the light-emitting control signal terminal EM
  • rst represents the signal loaded to the reset signal terminal RST
  • ga represents the signal loaded to the scan signal terminal GA
  • cs1 represents the signal loaded to the first control signal terminal CS1 signal
  • cs2 represents the signal loaded to the second control signal terminal.
  • the working process of a pixel circuit in one display frame may include: an initialization phase T6, a reset phase T1, a threshold compensation phase T2, a compensation holding phase T3, and a light-emitting phase T4.
  • the second transistor M2 is turned on under the control of the low level of the signal cs2, and the signal of the initialization signal terminal VINIT can be provided to the light-emitting device L to initialize the light-emitting device L and eliminate the The interface charge of the light-emitting layer.
  • the sixth transistor M6 is turned off under the control of the high level of the signal ga.
  • the third transistor M3 is turned off under the control of the high level of the signal rst.
  • the fourth transistor M4 and the fifth transistor M5 are turned off under the control of the high level of the signal em.
  • the second transistor M2 is turned off under the control of the high level of the signal cs2.
  • the second transistor M2 is turned off under the control of the high level of the signal cs2.
  • the second transistor M2 is turned off under the control of the high level of the signal cs2.
  • the second transistor M2 is turned off under the control of the high level of the signal cs2.
  • em represents the signal loaded on the light-emitting control signal terminal EM
  • rst represents the signal loaded on the reset signal terminal RST
  • ga represents the signal loaded on the scanning signal terminal GA
  • cs1 represents the signal loaded on the first control signal terminal CS1 signal
  • cs2 represents the signal loaded to the second control signal terminal.
  • the working process of a pixel circuit in one display frame may include: a reset phase T1, an initialization phase T6, a threshold compensation phase T2, a compensation hold phase T3, and a light-emitting phase T4.
  • the second transistor M2 is turned off under the control of the high level of the signal cs2.
  • the second transistor M2 is turned on under the control of the low level of the signal cs2, and the signal of the initialization signal terminal VINIT can be provided to the light-emitting device L to initialize the light-emitting device L and eliminate the The interface charge of the light-emitting layer.
  • the sixth transistor M6 is turned off under the control of the high level of the signal ga.
  • the third transistor M3 is turned off under the control of the high level of the signal rst.
  • the fourth transistor M4 and the fifth transistor M5 are turned off under the control of the high level of the signal em.
  • the second transistor M2 is turned off under the control of the high level of the signal cs2.
  • the second transistor M2 is turned off under the control of the high level of the signal cs2.
  • the second transistor M2 is turned off under the control of the high level of the signal cs2.
  • em represents the signal loaded on the light-emitting control signal terminal EM
  • rst represents the signal loaded on the reset signal terminal RST
  • ga represents the signal loaded on the scanning signal terminal GA
  • cs1 represents the signal loaded on the first control signal terminal CS1 signal
  • cs2 represents the signal loaded to the second control signal terminal.
  • the working process of a pixel circuit in one display frame may include: a reset phase T1, a threshold compensation phase T2, a compensation hold phase T3, and a light-emitting phase T4.
  • the second transistor M2 is turned off under the control of the high level of the signal cs2.
  • the second transistor M2 is turned off under the control of the high level of the signal cs2.
  • the second transistor M2 continues to be turned on under the control of the low level of the signal cs2, and the signal of the initialization signal terminal VINIT can be provided to the light-emitting device L to initialize the light-emitting device L and further eliminate the light-emitting device The interface charge of the light-emitting layer in L.
  • the second transistor M2 is turned off under the control of the high level of the signal cs2.
  • the embodiments of the present disclosure further provide some pixel circuits, and a schematic structural diagram is shown in FIG. 12 , which is modified from the implementation in the above-mentioned embodiments. Only the differences between this embodiment and the above-mentioned embodiments will be described below, and the similarities will not be repeated here.
  • the first control signal terminal CS1 and the second control signal terminal may be the same signal terminal.
  • both the control terminal of the first transistor M1 and the control terminal of the second transistor M2 are electrically connected to the first control signal terminal CS1.
  • the driving method may further include:
  • the first reset circuit provides the signal of the initialization signal terminal to the light-emitting device under the control of the signal of the second control signal terminal;
  • the first reset circuit provides the signal of the initialization signal terminal to the light-emitting device under the control of the signal of the second control signal terminal.
  • the signal timing diagram corresponding to the pixel circuit shown in FIG. 12 is shown in FIG. 5 , and its working process can refer to the working process of the pixel circuit shown in FIG. 4 under the control of the signal timing diagram shown in FIG. 5 . , which will not be repeated here.
  • the embodiments of the present disclosure further provide some pixel circuits, the schematic diagram of which is shown in FIG. 13 , which is modified from the implementation in the above-mentioned embodiments. Only the differences between this embodiment and the above-mentioned embodiments will be described below, and the similarities will not be repeated here.
  • the second control signal terminal and the reset signal terminal RST may be the same signal terminal.
  • both the control terminal of the first transistor M1 and the control terminal of the second transistor M2 are electrically connected to the reset signal terminal RST.
  • the driving method may further include: in the reset stage, the first reset circuit provides the signal of the initialization signal terminal to the light emitting device under the control of the signal of the second control signal terminal.
  • the signal timing diagram corresponding to the pixel circuit shown in FIG. 13 is shown in FIG. 6 , and its working process can refer to the working process of the pixel circuit shown in FIG. 4 under the control of the signal timing diagram shown in FIG. 6 . , which will not be repeated here.
  • Embodiments of the present disclosure further provide some pixel circuits, and a schematic structural diagram is shown in FIG. 14 , which is modified from the implementation in the above-mentioned embodiments. Only the differences between this embodiment and the above-mentioned embodiments will be described below, and the similarities will not be repeated here.
  • the second control signal terminal and the scan signal terminal GA may be the same signal terminal.
  • the control terminal of the first transistor M1 and the control terminal of the second transistor M2 are both electrically connected to the scan signal terminal GA.
  • the driving method may further include: in the threshold compensation stage, the first reset circuit provides the signal of the initialization signal terminal to the light emitting device under the control of the signal of the second control signal terminal.
  • the signal timing diagram corresponding to the pixel circuit shown in FIG. 14 is shown in FIG. 7 , and its working process can refer to the working process of the pixel circuit shown in FIG. 4 under the control of the signal timing diagram shown in FIG. 7 . , which will not be repeated here.
  • the embodiments of the present disclosure further provide some pixel circuits, and a schematic structural diagram is shown in FIG. 15 , which is a modification of the implementation in the above-mentioned embodiments. Only the differences between this embodiment and the above-mentioned embodiments will be described below, and the similarities will not be repeated here.
  • the second reset circuit 22 may further include: an auxiliary transistor MF; wherein the control terminal of the auxiliary transistor MF is electrically connected to the scan signal terminal GA, and the auxiliary transistor MF is electrically connected to the scanning signal terminal GA.
  • the first terminal of MF is electrically connected to the second terminal of the third transistor M3, and the second terminal of the auxiliary transistor MF is electrically connected to the control terminal of the driving transistor M0.
  • the pixel circuit further includes: a first reset circuit; before the reset stage, the driving method further includes: an anode reset stage; wherein, in the anode reset stage, the first reset circuit is controlled by a signal at the second control signal terminal , the signal of the initialization signal terminal is provided to the light-emitting device, and the light-emitting device is initialized.
  • the driving method further includes: in the reset stage, the first reset circuit, under the control of the signal of the second control signal terminal, provides the signal of the initialization signal terminal to the light-emitting device to initialize the light-emitting device; the data writing circuit is in the scanning signal terminal. Under the control of the signal, the signal of the data signal terminal is provided to the first terminal of the driving transistor.
  • em represents the signal loaded on the light-emitting control signal terminal EM
  • rst represents the signal loaded on the reset signal terminal RST
  • ga represents the signal loaded on the scanning signal terminal GA
  • cs1 represents the signal loaded on the first control signal terminal CS1 Signal.
  • the working process of a pixel circuit in one display frame may include: anode reset phase T0, reset phase T1, threshold compensation phase T2, compensation hold phase T3, buffer phase T5, and light-emitting phase T4.
  • the third transistor M3 is turned on under the control of the low level of the signal rst to provide the signal of the initialization signal terminal VINIT to the first terminal of the auxiliary transistor MF.
  • the second transistor M2 is turned on under the control of the low level of the signal rst to provide the signal of the initialization signal terminal VINIT to the light emitting device L, thereby initializing the light emitting device L.
  • the first transistor M1 is turned off under the control of the high level of the signal cs1.
  • the sixth transistor M6 and the auxiliary transistor MF are turned off under the control of the high level of the signal ga.
  • the fourth transistor M4 and the fifth transistor M5 are turned off under the control of the high level of the signal em.
  • the auxiliary transistor MF is turned off under the control of the high level of the signal ga.
  • the third transistor M3 is turned on under the control of the low level of the signal rst, and the auxiliary transistor MF is turned on under the control of the low level of the signal ga to provide the signal of the initialization signal terminal VINIT to the driver
  • the control terminal N3 of the transistor M0 so that the voltage of the control terminal N3 of the driving transistor M0 is Vini, and then the control of the driving transistor M0 is initialized.
  • the second transistor M2 is turned on under the control of the low level of the signal rst to provide the signal of the initialization signal terminal VINIT to the light emitting device L, thereby initializing the light emitting device L.
  • the sixth transistor M6 is controlled by the low level of the signal ga to provide the signal of the data signal terminal DA to the first terminal of the driving transistor M0.
  • the first transistor M1 is turned off under the control of the high level of the signal cs1.
  • the fourth transistor M4 and the fifth transistor M5 are turned off under the control of the high level of the signal em.
  • the sixth transistor M6 is controlled by the low level of the signal ga to provide the signal of the data signal terminal DA to the first terminal N1 of the driving transistor M0, so that the first terminal N1 of the driving transistor M0 can be
  • the voltage of is the voltage Vda of the signal of the data signal terminal DA.
  • the first transistor M1 is turned on under the control of the low level of the signal cs1, so as to turn on the control terminal N3 and the second terminal N2 of the driving transistor M0, so that the driving transistor M0 forms a diode connection mode, thereby making the driving transistor M0
  • the voltage Vda of the first terminal N1 charges the control terminal N3 of the driving transistor M0.
  • the third transistor M3 and the second transistor M2 are turned off under the control of the high level of the signal rst.
  • the fourth transistor M4 and the fifth transistor M5 are turned off under the control of the high level of the signal em.
  • each transistor is turned off. Therefore, the characteristics of the transistors in the pixel circuit can be stabilized, so as to enter the light-emitting stage after stabilization, thereby improving the stability of the pixel circuit.
  • the fourth transistor M4 and the fifth transistor M5 are both turned on under the control of the low level of the signal em.
  • the turned-on fourth transistor M4 may provide the voltage Vdd of the first power supply terminal ELVDD to the first terminal N1 of the driving transistor M0, so that the voltage of the first terminal N1 of the driving transistor M0 is Vdd.
  • the turned-on fifth transistor M5 can conduct the second end N2 of the driving transistor M0 with the light emitting device L, so that the working current Ids flows into the light emitting device L to drive the light emitting device L to emit light.
  • K is a structural constant related to process and design.
  • the first transistor M1 is turned off under the control of the high level of the signal cs1.
  • the sixth transistor M6 and the auxiliary transistor MF are turned off under the control of the high level of the signal ga.
  • the third transistor M3 and the second transistor M2 are turned off under the control of the high level of the signal rst.
  • an embodiment of the present disclosure further provides a display device, including the above-mentioned pixel circuit provided by an embodiment of the present disclosure.
  • the principle of solving the problem of the display device is similar to that of the aforementioned pixel circuit. Therefore, the implementation of the display device can refer to the implementation of the aforementioned pixel circuit, and repeated details are not repeated here.
  • the display device may be any product or component with display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • a mobile phone such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • Other essential components of the display device should be understood by those of ordinary skill in the art, and will not be repeated here, nor should it be regarded as a limitation of the present disclosure.
  • the above-mentioned pixel circuit, the driving method thereof, and the display device provided by the embodiments of the present disclosure can initialize the control terminal of the driving transistor through the control circuit.
  • the signal of the data signal end can be provided to the first end of the driving transistor through the data writing circuit under the control of the signal of the scan signal end.
  • the compensation capacitor since the compensation capacitor is electrically connected to the first end of the driving transistor, the signal input to the first end of the driving transistor can be stored, so that the voltage input to the first end of the driving transistor can be stabilized. In this way, when the control circuit makes the second end of the driving transistor conduct with the light-emitting device, the light-emitting device can be stably driven to emit light, thereby improving display uniformity.

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Abstract

本公开实施例提供的像素电路、其驱动方法及显示装置，通过数据写入电路在扫描信号端的信号的控制下，可以将数据信号端的信号提供给驱动晶体管的第一端。通过第二复位电路根据初始化信号端的信号对驱动晶体管的控制端进行初始化；通过发光控制电路在发光控制信号端的信号的控制下，将第一电源端与驱动晶体管的第一端导通，以及将驱动晶体管的第二端和发光器件导通，驱动发光器件发光。通过设置补偿电容，由于补偿电容与驱动晶体管的第一端电连接，将输入到驱动晶体管的第一端的信号进行存储，使输入到驱动晶体管的第一端的电压进行稳定。这样在控制电路使驱动晶体管的第二端与发光器件导通时，稳定的驱动发光器件发光，提高显示均一性。

Description

像素电路、其驱动方法及显示装置
相关申请的交叉引用
本申请要求在2020年07月21日提交中国专利局、申请号为202010707046.2、申请名称为“一种显示装置及其驱动方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，特别涉及像素电路、其驱动方法及显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)是当今平板显示器研究领域的热点之一。基于OLED显示器的低能耗、生产成本低、自发光、宽视角及响应速度快等优点，在手机、平板电脑、数码相机等显示领域，OLED显示器已经开始广泛应用。通常，OLED属于电流驱动，需要稳定的电流来控制其发光。
发明内容
本公开实施例提供的像素电路，包括：
数据写入电路，与驱动晶体管的第一端电连接，且被配置为在扫描信号端的信号的控制下，将数据信号端的信号提供给所述驱动晶体管的第一端；
补偿电容，所述补偿电容的第一端与第一电源端电连接，所述补偿电容的第二端与所述驱动晶体管的第一端电连接；
存储电路，分别与所述驱动晶体管的控制端和所述第一电源端电连接；
第二复位电路，与所述驱动晶体管的控制端电连接，且被配置为根据初始化信号端的信号对所述驱动晶体管的控制端进行初始化；
发光控制电路，与所述第一电源端、所述驱动晶体管的第一端和第二端 以及所述发光器件电连接，且被配置为在发光控制信号端的信号的控制下，将所述第一电源端与所述驱动晶体管的第一端导通，以及将所述驱动晶体管的第二端和所述发光器件导通，驱动所述发光器件发光。
在一些示例中，所述像素电路还包括：
阈值补偿电路，分别与所述驱动晶体管的控制端和第二端电连接，且被配置为在第一控制信号端的信号的控制下，将所述驱动晶体管的控制端和第二端导通，以进行阈值补偿。
在一些示例中，所述阈值补偿电路包括：
第一晶体管，所述第一晶体管的控制端与所述第一控制信号端电连接，所述第一晶体管的第一端与所述驱动晶体管的控制端电连接，所述第一晶体管的第二端与所述驱动晶体管的第二端电连接。
在一些示例中，所述像素电路还包括：
第一复位电路，与所述发光器件电连接，且被配置为在第二控制信号端的信号的控制下，将初始化信号端的信号提供给所述发光器件。
在一些示例中，所述第一复位电路包括：
第二晶体管，所述第二晶体管的控制端与所述第二控制信号端电连接，所述第二晶体管的第一端与所述初始化信号端电连接，所述第二晶体管的第二端与所述发光器件电连接。
在一些示例中，所述存储电路包括：
存储电容，所述存储电容的第一端与所述第一电源端电连接，所述存储电容的第二端与所述驱动晶体管的控制端电连接。
在一些示例中，所述第二复位电路包括：
第三晶体管，所述第三晶体管的控制端与所述复位信号端电连接，所述第三晶体管的第一端与所述初始化信号端电连接，所述第三晶体管的第二端与所述驱动晶体管的控制端电连接。
在一些示例中，所述第二复位电路还包括：
辅助晶体管，所述辅助晶体管的控制端与所述扫描信号端电连接，所述 辅助晶体管的第一端与所述第三晶体管的第二端电连接，所述辅助晶体管的第二端与所述驱动晶体管的控制端电连接。
在一些示例中，所述发光控制电路包括：
第四晶体管，所述第四晶体管的控制端与所述发光控制信号端电连接，所述第四晶体管的第一端与所述第一电源端电连接，所述第四晶体管的第二端与所述驱动晶体管的第一端电连接；
第五晶体管，所述第五晶体管的控制端与所述发光控制信号端电连接，所述第五晶体管的第一端与所述驱动晶体管的第二端电连接，所述第五晶体管的第二端与所述发光器件电连接。
在一些示例中，所述数据写入电路包括：
第六晶体管，所述第六晶体管的控制端与所述扫描信号端电连接，所述第六晶体管的第一端与所述数据信号端电连接，所述第六晶体管的第二端与所述驱动晶体管的第一端电连接。
本公开实施例提供的像素电路的驱动方法，包括：
复位阶段，所述第二复位电路根据初始化信号端的信号对所述驱动晶体管的控制端进行初始化；
阈值补偿阶段，所述数据写入电路在扫描信号端的信号的控制下，将数据信号端的信号提供给所述驱动晶体管的第一端，并通过所述补偿电容进行存储；阈值补偿电路在第一控制信号端的信号的控制下，将所述驱动晶体管的控制端和第二端导通，以进行阈值补偿；
补偿保持阶段，所述阈值补偿电路在第一控制信号端的信号的控制下，将所述驱动晶体管的控制端和第二端导通，以进行阈值补偿；
发光阶段，所述发光控制电路在发光控制信号端的信号的控制下，将所述第一电源端与所述驱动晶体管的第一端导通，以及将所述驱动晶体管的第二端和所述发光器件导通，驱动所述发光器件发光。
在一些示例中，所述第二控制信号端与所述第一控制信号端为同一信号端；
所述驱动方法还包括：
在所述阈值补偿阶段，所述第一复位电路在第二控制信号端的信号的控制下，将初始化信号端的信号提供给所述发光器件；
在所述补偿保持阶段，所述第一复位电路在第二控制信号端的信号的控制下，将初始化信号端的信号提供给所述发光器件。
在一些示例中，所述第二控制信号端与所述复位信号端为同一信号端；
所述驱动方法还包括：
在所述复位阶段，所述第一复位电路在第二控制信号端的信号的控制下，将初始化信号端的信号提供给所述发光器件。
在一些示例中，所述第二控制信号端与所述扫描信号端为同一信号端；
所述驱动方法还包括：
在所述阈值补偿阶段，所述第一复位电路在第二控制信号端的信号的控制下，将初始化信号端的信号提供给所述发光器件。
在一些示例中，所述驱动方法还包括：
在所述复位阶段，所述第一复位电路在第二控制信号端的信号的控制下，将初始化信号端的信号提供给所述发光器件；
在所述阈值补偿阶段，所述第一复位电路在第二控制信号端的信号的控制下，将初始化信号端的信号提供给所述发光器件；
在所述补偿保持阶段，所述第一复位电路在第二控制信号端的信号的控制下，将初始化信号端的信号提供给所述发光器件。
在一些示例中，所述驱动方法还包括：
在所述补偿保持阶段，所述第一复位电路在第二控制信号端的信号的控制下，将初始化信号端的信号提供给所述发光器件。
在一些示例中，在所述复位阶段之前，所述驱动方法还包括：
初始化阶段，所述第一复位电路在第二控制信号端的信号的控制下，将初始化信号端的信号提供给所述发光器件。
在一些示例中，在所述复位阶段之后，且在所述阈值补偿阶段之前，所 述驱动方法还包括：
初始化阶段，所述第一复位电路在第二控制信号端的信号的控制下，将初始化信号端的信号提供给所述发光器件。
在一些示例中，所述像素电路还包括：第一复位电路；在所述复位阶段之前，所述驱动方法还包括：阳极复位阶段；其中，在所述阳极复位阶段，所述第一复位电路在第二控制信号端的信号的控制下，将初始化信号端的信号提供给所述发光器件，对所述发光器件进行初始化；
所述驱动方法还包括：在所述复位阶段，所述第一复位电路在第二控制信号端的信号的控制下，将初始化信号端的信号提供给所述发光器件，对所述发光器件进行初始化；所述数据写入电路在扫描信号端的信号的控制下，将数据信号端的信号提供给所述驱动晶体管的第一端。
本公开实施例提供的显示装置，包括上述像素电路。
附图说明
图1为本公开实施例中的像素电路的结构示意图；
图2为本公开实施例中的一些像素电路的具体结构示意图；
图3为本公开实施例中的一些信号时序图；
图4为本公开实施例中的又一些像素电路的具体结构示意图；
图5为本公开实施例中的又一些信号时序图；
图6为本公开实施例中的又一些信号时序图；
图7为本公开实施例中的又一些信号时序图；
图8为本公开实施例中的又一些信号时序图；
图9为本公开实施例中的又一些信号时序图；
图10为本公开实施例中的又一些信号时序图；
图11为本公开实施例中的又一些信号时序图；
图12为本公开实施例中的又一些像素电路的具体结构示意图；
图13为本公开实施例中的又一些像素电路的具体结构示意图；
图14为本公开实施例中的又一些像素电路的具体结构示意图；
图15为本公开实施例中的又一些像素电路的具体结构示意图；
图16为本公开实施例中的又一些信号时序图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。
本公开实施例提供的一些像素电路，如图1所示，可以包括：
数据写入电路10，与驱动晶体管M0的第一端电连接，且被配置为在扫描信号端GA的信号的控制下，将数据信号端DA的信号提供给驱动晶体管M0的第一端；
补偿电容CF，补偿电容CF的第一端与第一电源端ELVDD电连接，补偿电容CF的第二端与驱动晶体管M0的第一端电连接；
存储电路21，分别与驱动晶体管M0的控制端和第一电源端ELVDD电连接；
第二复位电路22，与驱动晶体管M0的控制端电连接，且被配置为根据初始化信号端VINIT的信号对驱动晶体管M0的控制端进行初始化；例如，被配置为在复位信号端RST的信号的控制下，将初始化信号端VINIT的信号提供给驱动晶体管M0的控制端；
发光控制电路23，与第一电源端ELVDD、驱动晶体管M0的第一端和第二端以及发光器件L电连接，且被配置为在发光控制信号端EM的信号的控制下，将第一电源端ELVDD与驱动晶体管M0的第一端导通，以及将驱动晶体管M0的第二端和发光器件L导通，驱动发光器件L发光。
本公开实施例提供的上述像素电路，通过第二复位电路可以根据初始化信号端的信号对驱动晶体管的控制端进行初始化。通过数据写入电路在扫描信号端的信号的控制下，可以将数据信号端的信号提供给驱动晶体管的第一端。通过发光控制电路可以在发光控制信号端的信号的控制下，将第一电源端与驱动晶体管的第一端导通，以及将驱动晶体管的第二端和发光器件导通，驱动发光器件发光。通过设置补偿电容，由于补偿电容与驱动晶体管的第一端电连接，可以将输入到驱动晶体管的第一端的信号进行存储，从而可以使输入到驱动晶体管的第一端的电压进行稳定。这样在驱动晶体管的第二端与发光器件导通时，可以稳定的驱动发光器件发光，进而可以提高显示均一性。
由于工艺制程和器件老化等原因，驱动晶体管M0的阈值电压Vth会发生偏移，从而导致显示装置中的不同区域的发光器件L的发光亮度不均一，进而影响显示效果。有鉴于此，在本公开实施例中，如图1所示，像素电路还可以包括：阈值补偿电路30；其中，阈值补偿电路30分别与驱动晶体管M0的控制端和第二端电连接，且被配置为在第一控制信号端CS1的信号的控制下，将驱动晶体管M0的控制端和第二端导通，以进行阈值补偿。这样一来，通过设置阈值补偿电路30，可以实现补偿驱动晶体管M0的阈值电压的功能。
下面结合具体实施例，对本公开进行详细说明。需要说明的是，本实施 例中是为了更好的解释本公开，但不限制本公开。
在具体实施时，在本公开实施例提供的上述像素电路中，发光器件L的第一端与发光控制电路23电连接，发光器件L的第二端与第二电源端ELVSS电连接。示例性地，发光器件L与发光控制电路23电连接的第一端为其正极，与第二电源端ELVSS连接的第二端为其负极。例如，发光器件L可以为有机发光二极管和量子点发光二极管中的至少一个。并且，发光器件L在驱动晶体管M0处于饱和状态时的电流的作用下实现发光。另外，一般发光器件L具有开启电压，在发光器件L两端的电压差大于或等于开启电压时进行发光。
在具体实施时，在本公开实施例提供的上述像素电路中，第一电源端ELVDD的电压Vdd一般为正值，第二电源端ELVSS的电压Vss一般接地或为负值。并且初始信号端的电压Vini与第二电源端ELVSS的电压Vss需要满足公式：Vini-Vss<Vth(L)；其中，Vth(L)为发光器件L的开启电压。
在具体实施时，在本公开实施例提供的上述像素电路中，如图1与图2所示，驱动晶体管M0可以为P型晶体管；其中，驱动晶体管M0的控制端N3可以为其栅极，驱动晶体管M0的第一端N1可以为其源极，驱动晶体管M0的第二端N2可以为其漏极。或者，驱动晶体管M0也可以为N型晶体管；其中，驱动晶体管M0的控制端N3可以为其栅极，驱动晶体管M0的第一端N1可以为其漏极，驱动晶体管M0的第二端N2可以为其源极。在实际应用中，驱动晶体管M0的类型具体可以根据实际应用的需求进行设计确定，在此不作限定。
在具体实施时，在本公开实施例提供的上述像素电路中，如图2所示，阈值补偿电路30可以包括：第一晶体管M1；其中，第一晶体管M1的控制端与第一控制信号端CS1电连接，第一晶体管M1的第一端与驱动晶体管M0的控制端电连接，第一晶体管M1的第二端与驱动晶体管M0的第二端电连接。
在具体实施时，在本公开实施例提供的上述像素电路中，如图2所示，存储电路21可以包括：存储电容CST；其中，存储电容CST的第一端与第一电源端ELVDD电连接，存储电容CST的第二端与驱动晶体管M0的控制 端电连接。
在具体实施时，在本公开实施例提供的上述像素电路中，如图2所示，第二复位电路22可以包括：第三晶体管M3；其中，第三晶体管M3的控制端与复位信号端RST电连接，第三晶体管M3的第一端与初始化信号端VINIT电连接，第三晶体管M3的第二端与驱动晶体管M0的控制端电连接。
在具体实施时，在本公开实施例提供的上述像素电路中，如图2所示，发光控制电路23包括：第四晶体管M4和第五晶体管M5；其中，第四晶体管M4的控制端与发光控制信号端EM电连接，第四晶体管M4的第一端与第一电源端ELVDD电连接，第四晶体管M4的第二端与驱动晶体管M0的第一端电连接。第五晶体管M5的控制端与发光控制信号端EM电连接，第五晶体管M5的第一端与驱动晶体管M0的第二端电连接，第五晶体管M5的第二端与发光器件L电连接。
在具体实施时，在本公开实施例提供的上述像素电路中，如图2所示，数据写入电路10包括：第六晶体管M6；其中，第六晶体管M6的控制端与扫描信号端GA电连接，第六晶体管M6的第一端与数据信号端DA电连接，第六晶体管M6的第二端与驱动晶体管M0的第一端电连接。
进一步地，为了简化像素电路的制作工艺流程，在具体实施时，在本公开实施例提供的上述像素电路中，如图2所示，可以使所有的晶体管均为P型晶体管。或者，也可以使所有的晶体管均为N型晶体管，在此不作限定。
在具体实施时，在本公开实施例提供的上述像素电路中，P型晶体管在高电平作用下截止，在低电平作用下导通；N型晶体管在高电平作用下导通，在低电平作用下截止。
需要说明的是，在本公开实施例提供的上述像素电路中，上述晶体管可以是薄膜晶体管(TFT，Thin Film Transistor)，也可以是金属氧化物半导体场效应管(MOS，Metal Oxide Semiconductor)，在此不作限定。在具体实施时，上述晶体管的控制端可以作为其栅极，并且可以根据晶体管类型以及控制端的信号的不同，可以将上述晶体管的第一端作为其源极，第二端作为其漏极。 或者，将上述晶体管的第一端作为其漏极，第二端作为其源极，在此不作限定。
本公开实施例提供的上述像素电路的驱动方法，包括如下步骤：
复位阶段，第二复位电路根据初始化信号端的信号对驱动晶体管的控制端进行初始化；
阈值补偿阶段，数据写入电路在扫描信号端的信号的控制下，将数据信号端的信号提供给驱动晶体管的第一端，并通过补偿电容进行存储；阈值补偿电路在第一控制信号端的信号的控制下，将驱动晶体管的控制端和第二端导通，以进行阈值补偿；
补偿保持阶段，阈值补偿电路在第一控制信号端的信号的控制下，将驱动晶体管的控制端和第二端导通，以进行阈值补偿；
发光阶段，发光控制电路在发光控制信号端的信号的控制下，将第一电源端与驱动晶体管的第一端导通，以及将驱动晶体管的第二端和发光器件导通，驱动发光器件发光。
下面以图2所示的像素电路为例，结合图3所示的电路时序图，对本公开实施例提供的上述像素电路的工作过程作以描述。如图3所示，em代表加载到发光控制信号端EM信号，rst代表加载到复位信号端RST的信号，ga代表加载到扫描信号端GA的信号，cs1代表加载到第一控制信号端CS1的信号。并且，一个像素电路在一个显示帧中的工作过程，可以包括：复位阶段T1、阈值补偿阶段T2、补偿保持阶段T3、发光阶段T4。
在复位阶段T1，第三晶体管M3在信号rst的低电平的控制下导通，以将初始化信号端VINIT的信号提供给驱动晶体管M0的控制端N3，从而使驱动晶体管M0的控制端N3的电压为Vini，进而对驱动晶体管M0的控制进行初始化。并且，第一晶体管M1在信号cs1的高电平的控制下截止。第六晶体管M6在信号ga的高电平的控制下截止。第四晶体管M4和第五晶体管M5在信号em的高电平的控制下截止。
在阈值补偿阶段T2，第六晶体管M6在信号ga的低电平的控制下导通， 以将数据信号端DA的信号提供给驱动晶体管M0的第一端N1，可以使驱动晶体管M0的第一端N1的电压为数据信号端DA的信号的电压Vda。并通过补偿电容CF将电压Vda进行存储。第一晶体管M1在信号cs1的低电平的控制下导通，以将驱动晶体管M0的控制端N3和第二端N2导通，从而使驱动晶体管M0形成二极管连接方式，进而使驱动晶体管M0的第一端N1的电压Vda对驱动晶体管M0的控制端N3进行充电。并且，第三晶体管M3在信号rst的高电平的控制下截止。第四晶体管M4和第五晶体管M5在信号em的高电平的控制下截止。
在补偿保持阶段T3，由于补偿电容CF将电压Vda进行存储。并且，第一晶体管M1在信号cs1的低电平的控制下导通，以将驱动晶体管M0的控制端N3和第二端N2导通，从而使驱动晶体管M0形成二极管连接方式，进而使驱动晶体管M0的第一端N1的电压Vda对驱动晶体管M0的控制端N3继续进行充电，以使驱动晶体管M0的控制端N3的电压可以充电为Vda-|Vth|。并且，第六晶体管M6在信号ga的高电平的控制下截止。第三晶体管M3在信号rst的高电平的控制下截止。第四晶体管M4和第五晶体管M5在信号em的高电平的控制下截止。
在发光阶段T4，第四晶体管M4和第五晶体管M5在信号em的低电平的控制下均导通。导通的第四晶体管M4可以将第一电源端ELVDD的电压Vdd提供给驱动晶体管M0的第一端N1，以使驱动晶体管M0的第一端N1的电压为Vdd。这样可以使驱动晶体管M0处于饱和状态，从而使驱动晶体管M0产生工作电流Ids：Ids＝K(Vdd-Vda) 2。导通的第五晶体管M5可以将驱动晶体管M0的第二端N2与发光器件L导通，从而使工作电流Ids流入发光器件L，以驱动发光器件L发光。其中，K为与工艺和设计有关的结构常数。并且，第一晶体管M1在信号cs1的高电平的控制下截止。第六晶体管M6在信号ga的高电平的控制下截止。第三晶体管M3在信号rst的高电平的控制下截止。
需要说明的是，随着显示装置的刷新频率越来越高，例如，由60Hz上升 为120Hz，240Hz等，这样使得信号ga控制第六晶体管M6导通的时长会越来越短，从而导致在阈值补偿阶段T2中，数据信号端DA的信号通过驱动晶体管M0写入存储电容CST的电荷量不足，进而导致驱动晶体管M0的阈值电压补偿不充分。本公开实施例中，通过使第一控制信号端CS1的信号cs1与扫描信号端GA的信号ga不同，可以分别控制第一晶体管M1和第六晶体管M6的导通和截止。这样在本公开实施例提供的像素电路应用于高刷新频率的显示装置时，通过在阈值补偿阶段T2均控制第一晶体管M1和第六晶体管M6导通，可以对存储电容CST进行充电。并且，通过在补偿保持阶段T3继续控制第一晶体管M1导通，由于补偿电容CF存储有电压Vda，从而可以继续对存储电容CST进行充电，以使驱动晶体管M0的控制端N3的电压最终可以达到Vda-|Vth|。
需要说明的是，在补偿保持阶段T3与发光阶段T4之间还可以具有缓冲阶段T5。在缓冲阶段T5中，可以控制第一晶体管M1、第三晶体管M3、第四晶体管M4、第五晶体管M5以及第六晶体管M6均截止，从而可以使像素电路中的晶体管的特性进行稳定，以在稳定后进入下一个工作阶段，进而可以提高像素电路的稳定性。
需要说明的是，在实际应用中，上述各信号的具体电压值可以根据实际应用环境来设计确定，在此不作限定。
本公开实施例又提供了一些像素电路，结构示意图如图5所示，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
在具体实施时，在本公开实施例中，如图4所示，像素电路还可以包括：第一复位电路40；其中，第一复位电路40与发光器件L电连接，且第一复位电路40被配置为在第二控制信号端CS2的信号的控制下，将初始化信号端VINIT的信号提供给发光器件L。这样一来，可以发光器件L进行初始化。
在具体实施时，在本公开实施例中，如图4所示，第一复位电路可以包括：第二晶体管M2；其中，第二晶体管M2的控制端与第二控制信号端CS2 电连接，第二晶体管M2的第一端与初始化信号端VINIT电连接，第二晶体管M2的第二端与发光器件L电连接。
在具体实施时，在本公开实施例中，驱动方法还可以包括：
在复位阶段，第一复位电路在第二控制信号端的信号的控制下，将初始化信号端的信号提供给发光器件；
在阈值补偿阶段，第一复位电路在第二控制信号端的信号的控制下，将初始化信号端的信号提供给发光器件；
在补偿保持阶段，第一复位电路在第二控制信号端的信号的控制下，将初始化信号端的信号提供给发光器件。
或者，在具体实施时，在本公开实施例中，驱动方法还可以包括：在补偿保持阶段，第一复位电路在第二控制信号端的信号的控制下，将初始化信号端的信号提供给发光器件。
或者，在具体实施时，在本公开实施例中，在复位阶段之前，驱动方法还可以包括：初始化阶段，第一复位电路在第二控制信号端的信号的控制下，将初始化信号端的信号提供给发光器件。
或者，在具体实施时，在本公开实施例中，在复位阶段之后，且在阈值补偿阶段之前，驱动方法还可以包括：初始化阶段，第一复位电路在第二控制信号端的信号的控制下，将初始化信号端的信号提供给发光器件。
下面结合具体实施例进行说明。
在一些示例中，以图4所示的像素电路为例，结合图5所示的电路时序图，对本公开实施例提供的上述像素电路的工作过程作以描述。如图5所示，em代表加载到发光控制信号端EM信号，rst代表加载到复位信号端RST的信号，ga代表加载到扫描信号端GA的信号，cs1代表加载到第一控制信号端CS1的信号，cs2代表加载到第二控制信号端的信号。并且，一个像素电路在一个显示帧中的工作过程，可以包括：复位阶段T1、阈值补偿阶段T2、补偿保持阶段T3、发光阶段T4。
在复位阶段T1，第二晶体管M2在信号cs2的高电平的控制下截止。本 阶段中的其余工作过程可以参照上述实施例，在此不作赘述。
在阈值补偿阶段T2，第二晶体管M2在信号cs2的低电平的控制下导通，可以将初始化信号端VINIT的信号提供给发光器件L，以对发光器件L进行初始化，消除发光器件L中的发光层的界面电荷。本阶段中的其余工作过程可以参照上述实施例，在此不作赘述。
在补偿保持阶段T3，第二晶体管M2在信号cs2的低电平的控制下继续导通，进一步将初始化信号端VINIT的信号提供给发光器件L，以对发光器件L进行初始化，进一步消除发光器件L中的发光层的界面电荷。本阶段中的其余工作过程可以参照上述实施例，在此不作赘述。
在发光阶段T4，第二晶体管M2在信号cs2的高电平的控制下截止。本阶段中的其余工作过程可以参照上述实施例，在此不作赘述。
在另一些示例中，以图4所示的像素电路为例，结合图6所示的电路时序图，对本公开实施例提供的上述像素电路的工作过程作以描述。如图6所示，em代表加载到发光控制信号端EM信号，rst代表加载到复位信号端RST的信号，ga代表加载到扫描信号端GA的信号，cs1代表加载到第一控制信号端CS1的信号，cs2代表加载到第二控制信号端的信号。并且，一个像素电路在一个显示帧中的工作过程，可以包括：复位阶段T1、阈值补偿阶段T2、补偿保持阶段T3、发光阶段T4。
在复位阶段T1，第二晶体管M2在信号cs2的低电平的控制下导通，可以将初始化信号端VINIT的信号提供给发光器件L，以对发光器件L进行初始化，消除发光器件L中的发光层的界面电荷。本阶段中的其余工作过程可以参照上述实施例，在此不作赘述。
在阈值补偿阶段T2，第二晶体管M2在信号cs2的高电平的控制下截止。本阶段中的其余工作过程可以参照上述实施例，在此不作赘述。
在补偿保持阶段T3，第二晶体管M2在信号cs2的高电平的控制下截止。本阶段中的其余工作过程可以参照上述实施例，在此不作赘述。
在发光阶段T4，第二晶体管M2在信号cs2的高电平的控制下截止。本 阶段中的其余工作过程可以参照上述实施例，在此不作赘述。
在又一些示例中，以图4所示的像素电路为例，结合图7所示的电路时序图，对本公开实施例提供的上述像素电路的工作过程作以描述。如图7所示，em代表加载到发光控制信号端EM信号，rst代表加载到复位信号端RST的信号，ga代表加载到扫描信号端GA的信号，cs1代表加载到第一控制信号端CS1的信号，cs2代表加载到第二控制信号端的信号。并且，一个像素电路在一个显示帧中的工作过程，可以包括：复位阶段T1、阈值补偿阶段T2、补偿保持阶段T3、发光阶段T4。
在复位阶段T1，第二晶体管M2在信号cs2的高电平的控制下截止。本阶段中的其余工作过程可以参照上述实施例，在此不作赘述。
在阈值补偿阶段T2，第二晶体管M2在信号cs2的低电平的控制下导通，可以将初始化信号端VINIT的信号提供给发光器件L，以对发光器件L进行初始化，消除发光器件L中的发光层的界面电荷。本阶段中的其余工作过程可以参照上述实施例，在此不作赘述。
在补偿保持阶段T3，第二晶体管M2在信号cs2的高电平的控制下截止。本阶段中的其余工作过程可以参照上述实施例，在此不作赘述。
在发光阶段T4，第二晶体管M2在信号cs2的高电平的控制下截止。本阶段中的其余工作过程可以参照上述实施例，在此不作赘述。
在又一些示例中，以图4所示的像素电路为例，结合图8所示的电路时序图，对本公开实施例提供的上述像素电路的工作过程作以描述。如图8所示，em代表加载到发光控制信号端EM信号，rst代表加载到复位信号端RST的信号，ga代表加载到扫描信号端GA的信号，cs1代表加载到第一控制信号端CS1的信号，cs2代表加载到第二控制信号端的信号。并且，一个像素电路在一个显示帧中的工作过程，可以包括：复位阶段T1、阈值补偿阶段T2、补偿保持阶段T3、发光阶段T4。
在复位阶段T1，第二晶体管M2在信号cs2的低电平的控制下导通，可以将初始化信号端VINIT的信号提供给发光器件L，以对发光器件L进行初 始化，消除发光器件L中的发光层的界面电荷。本阶段中的其余工作过程可以参照上述实施例，在此不作赘述。
在阈值补偿阶段T2，第二晶体管M2在信号cs2的低电平的控制下继续导通，可以将初始化信号端VINIT的信号提供给发光器件L，以对发光器件L进行初始化，进一步消除发光器件L中的发光层的界面电荷。本阶段中的其余工作过程可以参照上述实施例，在此不作赘述。
在补偿保持阶段T3，第二晶体管M2在信号cs2的低电平的控制下继续导通，可以将初始化信号端VINIT的信号提供给发光器件L，以对发光器件L进行初始化，进一步消除发光器件L中的发光层的界面电荷。本阶段中的其余工作过程可以参照上述实施例，在此不作赘述。
在发光阶段T4，第二晶体管M2在信号cs2的高电平的控制下截止。本阶段中的其余工作过程可以参照上述实施例，在此不作赘述。
在又一些示例中，以图4所示的像素电路为例，结合图9所示的电路时序图，对本公开实施例提供的上述像素电路的工作过程作以描述。如图9所示，em代表加载到发光控制信号端EM信号，rst代表加载到复位信号端RST的信号，ga代表加载到扫描信号端GA的信号，cs1代表加载到第一控制信号端CS1的信号，cs2代表加载到第二控制信号端的信号。并且，一个像素电路在一个显示帧中的工作过程，可以包括：初始化阶段T6、复位阶段T1、阈值补偿阶段T2、补偿保持阶段T3、发光阶段T4。
在初始化阶段T6，第二晶体管M2在信号cs2的低电平的控制下导通，可以将初始化信号端VINIT的信号提供给发光器件L，以对发光器件L进行初始化，消除发光器件L中的发光层的界面电荷。并且，第六晶体管M6在信号ga的高电平的控制下截止。第三晶体管M3在信号rst的高电平的控制下截止。第四晶体管M4和第五晶体管M5在信号em的高电平的控制下截止。
在复位阶段T1，第二晶体管M2在信号cs2的高电平的控制下截止。本阶段中的其余工作过程可以参照上述实施例，在此不作赘述。
在阈值补偿阶段T2，第二晶体管M2在信号cs2的高电平的控制下截止。 本阶段中的其余工作过程可以参照上述实施例，在此不作赘述。
在补偿保持阶段T3，第二晶体管M2在信号cs2的高电平的控制下截止。本阶段中的其余工作过程可以参照上述实施例，在此不作赘述。
在发光阶段T4，第二晶体管M2在信号cs2的高电平的控制下截止。本阶段中的其余工作过程可以参照上述实施例，在此不作赘述。
在又一些示例中，以图4所示的像素电路为例，结合图10所示的电路时序图，对本公开实施例提供的上述像素电路的工作过程作以描述。如图10所示，em代表加载到发光控制信号端EM信号，rst代表加载到复位信号端RST的信号，ga代表加载到扫描信号端GA的信号，cs1代表加载到第一控制信号端CS1的信号，cs2代表加载到第二控制信号端的信号。并且，一个像素电路在一个显示帧中的工作过程，可以包括：复位阶段T1、初始化阶段T6、阈值补偿阶段T2、补偿保持阶段T3、发光阶段T4。
在复位阶段T1，第二晶体管M2在信号cs2的高电平的控制下截止。本阶段中的其余工作过程可以参照上述实施例，在此不作赘述。
在初始化阶段T6，第二晶体管M2在信号cs2的低电平的控制下导通，可以将初始化信号端VINIT的信号提供给发光器件L，以对发光器件L进行初始化，消除发光器件L中的发光层的界面电荷。并且，第六晶体管M6在信号ga的高电平的控制下截止。第三晶体管M3在信号rst的高电平的控制下截止。第四晶体管M4和第五晶体管M5在信号em的高电平的控制下截止。
在阈值补偿阶段T2，第二晶体管M2在信号cs2的高电平的控制下截止。本阶段中的其余工作过程可以参照上述实施例，在此不作赘述。
在补偿保持阶段T3，第二晶体管M2在信号cs2的高电平的控制下截止。本阶段中的其余工作过程可以参照上述实施例，在此不作赘述。
在发光阶段T4，第二晶体管M2在信号cs2的高电平的控制下截止。本阶段中的其余工作过程可以参照上述实施例，在此不作赘述。
在又一些示例中，以图4所示的像素电路为例，结合图11所示的电路时序图，对本公开实施例提供的上述像素电路的工作过程作以描述。如图11所 示，em代表加载到发光控制信号端EM信号，rst代表加载到复位信号端RST的信号，ga代表加载到扫描信号端GA的信号，cs1代表加载到第一控制信号端CS1的信号，cs2代表加载到第二控制信号端的信号。并且，一个像素电路在一个显示帧中的工作过程，可以包括：复位阶段T1、阈值补偿阶段T2、补偿保持阶段T3、发光阶段T4。
在复位阶段T1，第二晶体管M2在信号cs2的高电平的控制下截止。本阶段中的其余工作过程可以参照上述实施例，在此不作赘述。
在阈值补偿阶段T2，第二晶体管M2在信号cs2的高电平的控制下截止。本阶段中的其余工作过程可以参照上述实施例，在此不作赘述。
在补偿保持阶段T3，第二晶体管M2在信号cs2的低电平的控制下继续导通，可以将初始化信号端VINIT的信号提供给发光器件L，以对发光器件L进行初始化，进一步消除发光器件L中的发光层的界面电荷。本阶段中的其余工作过程可以参照上述实施例，在此不作赘述。
在发光阶段T4，第二晶体管M2在信号cs2的高电平的控制下截止。本阶段中的其余工作过程可以参照上述实施例，在此不作赘述。
本公开实施例又提供了一些像素电路，结构示意图如图12所示，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
在具体实施时，在本公开实施例中，可以使第一控制信号端CS1和第二控制信号端为同一信号端。示例性地，如图12所示，第一晶体管M1的控制端和第二晶体管M2的控制端均与第一控制信号端CS1电连接。
在具体实施时，在本公开实施例中，驱动方法还可以包括：
在阈值补偿阶段，第一复位电路在第二控制信号端的信号的控制下，将初始化信号端的信号提供给发光器件；
在补偿保持阶段，第一复位电路在第二控制信号端的信号的控制下，将初始化信号端的信号提供给发光器件。
需要说明的是，图12所示的像素电路对应的信号时序图，如图5所示， 其工作过程可以参照图4所示的像素电路在图5所示的信号时序图控制下的工作过程，在此不作赘述。
本公开实施例又提供了一些像素电路，结构示意图如图13所示，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
在具体实施时，在本公开实施例中，可以使第二控制信号端和复位信号端RST为同一信号端。示例性地，如图13所示，第一晶体管M1的控制端和第二晶体管M2的控制端均与复位信号端RST电连接。
在具体实施时，在本公开实施例中，驱动方法还可以包括：在复位阶段，第一复位电路在第二控制信号端的信号的控制下，将初始化信号端的信号提供给所述发光器件。
需要说明的是，图13所示的像素电路对应的信号时序图，如图6所示，其工作过程可以参照图4所示的像素电路在图6所示的信号时序图控制下的工作过程，在此不作赘述。
本公开实施例又提供了一些像素电路，结构示意图如图14所示，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
在具体实施时，在本公开实施例中，可以使第二控制信号端和扫描信号端GA为同一信号端。示例性地，如图14所示，第一晶体管M1的控制端和第二晶体管M2的控制端均与扫描信号端GA电连接。
在具体实施时，在本公开实施例中，驱动方法还可以包括：在阈值补偿阶段，第一复位电路在第二控制信号端的信号的控制下，将初始化信号端的信号提供给所述发光器件。
需要说明的是，图14所示的像素电路对应的信号时序图，如图7所示，其工作过程可以参照图4所示的像素电路在图7所示的信号时序图控制下的工作过程，在此不作赘述。
本公开实施例又提供了一些像素电路，结构示意图如图15所示，其针对 上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
在具体实施时，在本公开实施例中，如图15所示，第二复位电路22还可以包括：辅助晶体管MF；其中，辅助晶体管MF的控制端与扫描信号端GA电连接，辅助晶体管MF的第一端与第三晶体管M3的第二端电连接，辅助晶体管MF的第二端与驱动晶体管M0的控制端电连接。
在一些示例中，像素电路还包括：第一复位电路；在复位阶段之前，驱动方法还包括：阳极复位阶段；其中，在阳极复位阶段，第一复位电路在第二控制信号端的信号的控制下，将初始化信号端的信号提供给发光器件，对发光器件进行初始化。并且，驱动方法还包括：在复位阶段，第一复位电路在第二控制信号端的信号的控制下，将初始化信号端的信号提供给发光器件，对发光器件进行初始化；数据写入电路在扫描信号端的信号的控制下，将数据信号端的信号提供给驱动晶体管的第一端。
下面以图15所示的像素电路为例，结合图16所示的电路时序图，对本公开实施例提供的上述像素电路的工作过程作以描述。如图16所示，em代表加载到发光控制信号端EM信号，rst代表加载到复位信号端RST的信号，ga代表加载到扫描信号端GA的信号，cs1代表加载到第一控制信号端CS1的信号。并且，一个像素电路在一个显示帧中的工作过程，可以包括：阳极复位阶段T0、复位阶段T1、阈值补偿阶段T2、补偿保持阶段T3、缓冲阶段T5、发光阶段T4。
在阳极复位阶段T0，第三晶体管M3在信号rst的低电平的控制下导通，以将初始化信号端VINIT的信号提供给辅助晶体管MF的第一端。并且，第二晶体管M2在信号rst的低电平的控制下导通，以将初始化信号端VINIT的信号提供给发光器件L，从而对发光器件L进行初始化。第一晶体管M1在信号cs1的高电平的控制下截止。第六晶体管M6和辅助晶体管MF在信号ga的高电平的控制下截止。第四晶体管M4和第五晶体管M5在信号em的高电平的控制下截止。辅助晶体管MF在信号ga的高电平的控制下截止。
在复位阶段T1，第三晶体管M3在信号rst的低电平的控制下导通，并且辅助晶体管MF在信号ga的低电平的控制下导通，以将初始化信号端VINIT的信号提供给驱动晶体管M0的控制端N3，从而使驱动晶体管M0的控制端N3的电压为Vini，进而对驱动晶体管M0的控制进行初始化。并且，第二晶体管M2在信号rst的低电平的控制下导通，以将初始化信号端VINIT的信号提供给发光器件L，从而对发光器件L进行初始化。第六晶体管M6在信号ga的低电平的控制下，以将数据信号端DA的信号提供给驱动晶体管M0的第一端。第一晶体管M1在信号cs1的高电平的控制下截止。第四晶体管M4和第五晶体管M5在信号em的高电平的控制下截止。
在阈值补偿阶段T2，第六晶体管M6在信号ga的低电平的控制下，以将数据信号端DA的信号提供给驱动晶体管M0的第一端N1，可以使驱动晶体管M0的第一端N1的电压为数据信号端DA的信号的电压Vda。第一晶体管M1在信号cs1的低电平的控制下导通，以将驱动晶体管M0的控制端N3和第二端N2导通，从而使驱动晶体管M0形成二极管连接方式，进而使驱动晶体管M0的第一端N1的电压Vda对驱动晶体管M0的控制端N3进行充电。并且，第三晶体管M3和第二晶体管M2在信号rst的高电平的控制下截止。第四晶体管M4和第五晶体管M5在信号em的高电平的控制下截止。
在缓存阶段T5，各晶体管均截止。从而可以使像素电路中的晶体管的特性进行稳定，以在稳定后进入发光阶段，进而可以提高像素电路的稳定性。
在发光阶段T4，第四晶体管M4和第五晶体管M5在信号em的低电平的控制下均导通。导通的第四晶体管M4可以将第一电源端ELVDD的电压Vdd提供给驱动晶体管M0的第一端N1，以使驱动晶体管M0的第一端N1的电压为Vdd。这样可以使驱动晶体管M0处于饱和状态，从而使驱动晶体管M0产生工作电流Ids：Ids＝K(Vdd-Vda) 2。导通的第五晶体管M5可以将驱动晶体管M0的第二端N2与发光器件L导通，从而使工作电流Ids流入发光器件L，以驱动发光器件L发光。其中，K为与工艺和设计有关的结构常数。并且，第一晶体管M1在信号cs1的高电平的控制下截止。第六晶体管M6和 辅助晶体管MF在信号ga的高电平的控制下截止。第三晶体管M3和第二晶体管M2在信号rst的高电平的控制下截止。
基于同一发明构思，本公开实施例还提供了显示装置，包括本公开实施例提供的上述像素电路。该显示装置解决问题的原理与前述像素电路相似，因此该显示装置的实施可以参见前述像素电路的实施，重复之处在此不再赘述。
在具体实施时，在本公开实施例中，显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
本公开实施例提供的上述像素电路、其驱动方法及显示装置，通过控制电路可以使驱动晶体管的控制端进行初始化。通过数据写入电路在扫描信号端的信号的控制下，可以将数据信号端的信号提供给驱动晶体管的第一端。通过设置补偿电容，由于补偿电容与驱动晶体管的第一端电连接，可以将输入到驱动晶体管的第一端的信号进行存储，从而可以使输入到驱动晶体管的第一端的电压进行稳定。这样在控制电路使驱动晶体管的第二端与发光器件导通时，可以稳定的驱动发光器件发光，进而可以提高显示均一性。
尽管已描述了本发明的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本发明范围的所有变更和修改。
显然，本领域的技术人员可以对本发明实施例进行各种改动和变型而不脱离本发明实施例的精神和范围。这样，倘若本发明实施例的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (20)

  1. 一种像素电路，其中，包括：
    数据写入电路，与驱动晶体管的第一端电连接，且被配置为在扫描信号端的信号的控制下，将数据信号端的信号提供给所述驱动晶体管的第一端；
    补偿电容，所述补偿电容的第一端与第一电源端电连接，所述补偿电容的第二端与所述驱动晶体管的第一端电连接；
    存储电路，分别与所述驱动晶体管的控制端和所述第一电源端电连接；
    第二复位电路，与所述驱动晶体管的控制端电连接，且被配置为根据初始化信号端的信号对所述驱动晶体管的控制端进行初始化；
    发光控制电路，与所述第一电源端、所述驱动晶体管的第一端和第二端以及所述发光器件电连接，且被配置为在发光控制信号端的信号的控制下，将所述第一电源端与所述驱动晶体管的第一端导通，以及将所述驱动晶体管的第二端和所述发光器件导通，驱动所述发光器件发光。
  2. 如权利要求1所述的像素电路，其中，所述像素电路还包括：
    阈值补偿电路，分别与所述驱动晶体管的控制端和第二端电连接，且被配置为在第一控制信号端的信号的控制下，将所述驱动晶体管的控制端和第二端导通，以进行阈值补偿。
  3. 如权利要求2所述的像素电路，其中，所述阈值补偿电路包括：
    第一晶体管，所述第一晶体管的控制端与所述第一控制信号端电连接，所述第一晶体管的第一端与所述驱动晶体管的控制端电连接，所述第一晶体管的第二端与所述驱动晶体管的第二端电连接。
  4. 如权利要求1-3任一项所述的像素电路，其中，所述像素电路还包括：
    第一复位电路，与所述发光器件电连接，且被配置为在第二控制信号端的信号的控制下，将初始化信号端的信号提供给所述发光器件。
  5. 如权利要求4所述的像素电路，其中，所述第一复位电路包括：
    第二晶体管，所述第二晶体管的控制端与所述第二控制信号端电连接， 所述第二晶体管的第一端与所述初始化信号端电连接，所述第二晶体管的第二端与所述发光器件电连接。
  6. 如权利要求1-3任一项所述的像素电路，其中，所述存储电路包括：
    存储电容，所述存储电容的第一端与所述第一电源端电连接，所述存储电容的第二端与所述驱动晶体管的控制端电连接。
  7. 如权利要求1-3任一项所述的像素电路，其中，所述第二复位电路包括：
    第三晶体管，所述第三晶体管的控制端与所述复位信号端电连接，所述第三晶体管的第一端与所述初始化信号端电连接，所述第三晶体管的第二端与所述驱动晶体管的控制端电连接。
  8. 如权利要求7所述的像素电路，其中，所述第二复位电路还包括：
    辅助晶体管，所述辅助晶体管的控制端与所述扫描信号端电连接，所述辅助晶体管的第一端与所述第三晶体管的第二端电连接，所述辅助晶体管的第二端与所述驱动晶体管的控制端电连接。
  9. 如权利要求1-3任一项所述的像素电路，其中，所述发光控制电路包括：
    第四晶体管，所述第四晶体管的控制端与所述发光控制信号端电连接，所述第四晶体管的第一端与所述第一电源端电连接，所述第四晶体管的第二端与所述驱动晶体管的第一端电连接；
    第五晶体管，所述第五晶体管的控制端与所述发光控制信号端电连接，所述第五晶体管的第一端与所述驱动晶体管的第二端电连接，所述第五晶体管的第二端与所述发光器件电连接。
  10. 如权利要求1-5任一项所述的像素电路，其中，所述数据写入电路包括：
    第六晶体管，所述第六晶体管的控制端与所述扫描信号端电连接，所述第六晶体管的第一端与所述数据信号端电连接，所述第六晶体管的第二端与所述驱动晶体管的第一端电连接。
  11. 一种如权利要求1-10任一项所述的像素电路的驱动方法，其中，包括：
    复位阶段，所述第二复位电路根据初始化信号端的信号对所述驱动晶体管的控制端进行初始化；
    阈值补偿阶段，所述数据写入电路在扫描信号端的信号的控制下，将数据信号端的信号提供给所述驱动晶体管的第一端，并通过所述补偿电容进行存储；阈值补偿电路在第一控制信号端的信号的控制下，将所述驱动晶体管的控制端和第二端导通，以进行阈值补偿；
    补偿保持阶段，所述阈值补偿电路在第一控制信号端的信号的控制下，将所述驱动晶体管的控制端和第二端导通，以进行阈值补偿；
    发光阶段，所述发光控制电路在发光控制信号端的信号的控制下，将所述第一电源端与所述驱动晶体管的第一端导通，以及将所述驱动晶体管的第二端和所述发光器件导通，驱动所述发光器件发光。
  12. 如权利要求11所述的驱动方法，其中，所述第二控制信号端与所述第一控制信号端为同一信号端；
    所述驱动方法还包括：
    在所述阈值补偿阶段，所述第一复位电路在第二控制信号端的信号的控制下，将初始化信号端的信号提供给所述发光器件；
    在所述补偿保持阶段，所述第一复位电路在第二控制信号端的信号的控制下，将初始化信号端的信号提供给所述发光器件。
  13. 如权利要求11所述的驱动方法，其中，所述第二控制信号端与所述复位信号端为同一信号端；
    所述驱动方法还包括：
    在所述复位阶段，所述第一复位电路在第二控制信号端的信号的控制下，将初始化信号端的信号提供给所述发光器件。
  14. 如权利要求11所述的驱动方法，其中，所述第二控制信号端与所述扫描信号端为同一信号端；
    所述驱动方法还包括：
    在所述阈值补偿阶段，所述第一复位电路在第二控制信号端的信号的控制下，将初始化信号端的信号提供给所述发光器件。
  15. 如权利要求11所述的驱动方法，其中，所述驱动方法还包括：
    在所述复位阶段，所述第一复位电路在第二控制信号端的信号的控制下，将初始化信号端的信号提供给所述发光器件；
    在所述阈值补偿阶段，所述第一复位电路在第二控制信号端的信号的控制下，将初始化信号端的信号提供给所述发光器件；
    在所述补偿保持阶段，所述第一复位电路在第二控制信号端的信号的控制下，将初始化信号端的信号提供给所述发光器件。
  16. 如权利要求11所述的驱动方法，其中，所述驱动方法还包括：
    在所述补偿保持阶段，所述第一复位电路在第二控制信号端的信号的控制下，将初始化信号端的信号提供给所述发光器件。
  17. 如权利要求11所述的驱动方法，其中，在所述复位阶段之前，所述驱动方法还包括：
    初始化阶段，所述第一复位电路在第二控制信号端的信号的控制下，将初始化信号端的信号提供给所述发光器件。
  18. 如权利要求11所述的驱动方法，其中，在所述复位阶段之后，且在所述阈值补偿阶段之前，所述驱动方法还包括：
    初始化阶段，所述第一复位电路在第二控制信号端的信号的控制下，将初始化信号端的信号提供给所述发光器件。
  19. 如权利要求11所述的驱动方法，其中，所述像素电路还包括：第一复位电路；在所述复位阶段之前，所述驱动方法还包括：阳极复位阶段；其中，在所述阳极复位阶段，所述第一复位电路在第二控制信号端的信号的控制下，将初始化信号端的信号提供给所述发光器件，对所述发光器件进行初始化；
    所述驱动方法还包括：在所述复位阶段，所述第一复位电路在第二控制 信号端的信号的控制下，将初始化信号端的信号提供给所述发光器件，对所述发光器件进行初始化；所述数据写入电路在扫描信号端的信号的控制下，将数据信号端的信号提供给所述驱动晶体管的第一端。
  20. 一种显示装置，其中，包括如权利要求1-10任一项所述的像素电路。
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