WO2022012251A1 - 薄膜晶体管及其制备方法和显示装置 - Google Patents

薄膜晶体管及其制备方法和显示装置 Download PDF

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Publication number
WO2022012251A1
WO2022012251A1 PCT/CN2021/100143 CN2021100143W WO2022012251A1 WO 2022012251 A1 WO2022012251 A1 WO 2022012251A1 CN 2021100143 W CN2021100143 W CN 2021100143W WO 2022012251 A1 WO2022012251 A1 WO 2022012251A1
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hole
electrode
active layer
pattern
thin film
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PCT/CN2021/100143
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English (en)
French (fr)
Inventor
强朝辉
李超
张惠勤
强力
关峰
梁志伟
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京东方科技集团股份有限公司
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Priority to US17/776,923 priority Critical patent/US20220416091A1/en
Publication of WO2022012251A1 publication Critical patent/WO2022012251A1/zh

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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
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    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
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    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • H—ELECTRICITY
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • H01L29/78624—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile the source and the drain regions being asymmetrical
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    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
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    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
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    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a thin film transistor, a preparation method thereof, and a display device.
  • the most used device is the thin film transistor (Thin Film Transistor, TFT), and the thin film transistor is a field effect transistor.
  • TFT Thin Film Transistor
  • the function of the TFT is a three-terminal switch, with three terminals such as gate, source and drain. When the gate is turned on, the signal can be transmitted from the source to the drain.
  • a thin film transistor in one aspect, includes: an active layer, a first electrode, a second electrode and a third doping pattern.
  • the material of the active layer is polysilicon, and the active layer has a channel region and a first electrode region and a second electrode region located on opposite sides of the channel region, wherein the first electrode region and the The second electrode region is an ion doping region, the first electrode region has a first ion doping concentration, and the second electrode region has a second ion doping concentration.
  • the first electrode and the second electrode are arranged on one side in the thickness direction of the active layer and are of the same layer and the same material, the first electrode is coupled to the first electrode region, and the second electrode is coupled to the second electrode region.
  • the third doping pattern is disposed between the first electrode and the first electrode region, and is in direct contact with the first electrode and the first electrode region, respectively, wherein the third doping pattern having a third ion doping concentration, the third ion doping concentration being different from the first ion doping concentration.
  • the thin film transistor further includes: a fourth doping pattern disposed between the second electrode and the second electrode region, respectively connected to the second electrode and the second electrode region direct contact; the fourth doping pattern has a fourth ion doping concentration, the fourth ion doping concentration is different from the second ion doping concentration.
  • the thin film transistor further includes: a gate insulating layer and a gate electrode stacked along a thickness direction of the active layer, and the gate insulating layer and the gate electrode are disposed between the active layer and the gate electrode. between the first electrode and the second electrode.
  • the gate insulating layer is located between the active layer and the gate; a first through hole is provided on the gate insulating layer, and the orthographic projection of the first through hole on the active layer falls within the overlapping range of the orthographic projection of the first electrode region and the first electrode on the active layer.
  • the third doping pattern is located in the first through hole.
  • a second through hole is further provided on the gate insulating layer, and the second through hole is located on the active layer.
  • the orthographic projection falls within the overlapping range of the second electrode region and the orthographic projection of the second electrode on the active layer.
  • the fourth doping pattern is located in the second through hole.
  • the first ion doping concentration is equal to or approximately equal to the second ion doping concentration; the third ion doping concentration is equal to or approximately equal to the fourth ion doping concentration; and The first ion doping concentration is greater than the third ion doping concentration.
  • the height of the third doping pattern is less than or equal to the depth of the first through hole, and the height of the fourth doping pattern is less than or equal to the depth of the second through hole.
  • the thin film transistor further includes: an interlayer insulating layer disposed on a side of the gate away from the active layer, and a third through hole and a fourth through hole are disposed on the interlayer insulating layer a through hole, wherein the third through hole communicates with the first through hole, and the fourth through hole communicates with the second through hole; the orthographic projection of the third through hole on the active layer and the orthographic projection of the first through hole on the active layer falls within the range of the first electrode region; the orthographic projection of the fourth through hole on the active layer and the second The orthographic projection of the through hole on the active layer falls within the range of the second electrode region.
  • the diameter of the third through hole is larger than the diameter of the first through hole, and the diameter of the fourth through hole is larger than the diameter of the second through hole.
  • the third doping pattern is also located in the third through hole, and the fourth doping pattern is also located in the fourth through hole.
  • the thickness of the third doping pattern is equal to or approximately equal to the thickness of the fourth doping pattern.
  • materials of the third doping pattern and the fourth doping pattern are semiconductor materials including N+ ions.
  • a display device including the thin film transistor described in any of the above embodiments.
  • a method for preparing a thin film transistor comprising:
  • the material of the active layer is polysilicon
  • the active layer has a channel region and a first electrode region and a second electrode region located on opposite sides of the channel region, the first electrode region An electrode region and the second electrode region are ion doping regions, the first electrode region has a first ion doping concentration, and the second electrode region has a second ion doping concentration.
  • a third doping pattern is formed on one side of the active layer, the third doping pattern has a third ion doping concentration, and the third ion doping concentration is different from the first ion doping concentration.
  • a first electrode is formed on the side of the third doping pattern away from the active layer, and a second electrode is formed on the active layer; the first electrode and the second electrode are of the same layer and the same material, The first electrode is coupled to the first electrode region through the third doping pattern, and the second electrode is coupled to the second electrode region.
  • a fourth doping pattern is also formed, the fourth doping pattern is coupled to the second electrode region, and the fourth doping pattern is also formed.
  • the four-doping pattern has a fourth ion doping concentration that is different from the second ion doping concentration.
  • Forming the second electrode on the active layer further includes: forming the second electrode on a side of the fourth doping pattern away from the active layer; wherein the fourth doping pattern is the same as the The second electrode is coupled.
  • forming the active layer further includes:
  • Ion doping is performed on a portion of the semiconductor pattern where the first electrode region and the second electrode region are to be formed to form the active layer.
  • forming a third doping pattern on one side of the active layer further includes:
  • a doped thin film is formed on a side of the gate insulating layer and the gate away from the active layer, and a third doped pattern is formed in the first through hole by patterning the doped thin film.
  • a second through hole is also formed, and the orthographic projection of the second through hole on the active layer falls on the second through hole within the range of the electrode area.
  • the doped film is formed on the side of the gate insulating layer and the gate away from the active layer, and the doped film is patterned to form the third doped film in the first through hole At the same time as the impurity pattern is formed, a fourth impurity pattern is also formed in the second through hole.
  • forming a third doping pattern on one side of the active layer further includes:
  • An interlayer insulating layer is formed on a side of the gate insulating layer and the gate away from the active layer.
  • a third through hole and a first through hole that communicate with each other are formed on the interlayer insulating layer and the gate insulating layer.
  • the third through hole is located on the interlayer insulating layer
  • the first through hole is located on the gate insulating layer
  • the orthographic projection of the third through hole on the active layer and the The orthographic projection of the first through hole on the active layer falls within the range of the first electrode region.
  • a doped thin film is formed on a side of the interlayer insulating layer away from the active layer, and the doped thin film is patterned to form a third doped film in the third through hole and the first through hole pattern.
  • the interlayer insulating layer and the first through hole are also formed.
  • a fourth through hole and a second through hole are formed on the gate insulating layer; wherein, the fourth through hole is located on the interlayer insulating layer, the second through hole is located on the gate insulating layer, and the The orthographic projection of the fourth through hole on the active layer and the orthographic projection of the second through hole on the active layer fall within the range of the second electrode region.
  • the doped thin film is formed on a side of the interlayer insulating layer away from the active layer, and the doped thin film is patterned to form the third through hole and the first through hole. At the same time as the third doping pattern, a fourth doping pattern is also formed in the fourth through hole and the second through hole.
  • FIG. 1A is a structural diagram of a display device provided according to some disclosed embodiments.
  • FIG. 1B is a structural diagram of a pixel circuit provided according to some disclosed embodiments.
  • 2A-2D are structural diagrams of a thin film transistor provided according to some embodiments of the disclosure.
  • 3A is a structural diagram of a thin film transistor in the related art
  • 3B is a diagram showing the relationship between the drain voltage, gate voltage, and drain current of a thin film transistor in the related art
  • FIGS. 4A-4D are structural diagrams of another thin film transistor provided according to some embodiments of the disclosure.
  • Figure 4E is an enlarged view at A in Figure 4D;
  • FIGS. 5A-5C are structural diagrams of another thin film transistor provided according to some embodiments of the disclosure.
  • 6A-6C are structural diagrams of another thin film transistor provided according to some embodiments of the disclosure.
  • FIGS. 7A-7B are structural diagrams of another thin film transistor provided according to some embodiments of the disclosure.
  • FIG. 8 is a flowchart of a method for fabricating a thin film transistor provided according to some disclosed embodiments.
  • 9A is a flow chart of a preparation process of an active layer provided according to some disclosed embodiments.
  • 9B-9C are diagrams of a preparation process of an active layer provided according to some disclosed embodiments.
  • FIG. 10A is a flow chart of a preparation process of a third doping pattern provided according to some disclosed embodiments.
  • FIG. 10B is a diagram of a preparation process of a third doping pattern and a fourth doping pattern provided according to some disclosed embodiments;
  • Figure 10C is a top view of Figure 10B
  • FIG. 10D is a diagram of a preparation process of a third doping pattern and a fourth doping provided according to some disclosed embodiments.
  • 11A is a flow chart of another preparation process of a third doping pattern provided according to some embodiments of the disclosure.
  • FIGS. 11B to 11E are process diagrams of another third doping pattern and a fourth doping pattern provided according to some disclosed embodiments.
  • FIG. 12A is a structural diagram of another display device provided according to some disclosed embodiments.
  • 12B is a structural diagram of a light emitting functional layer provided in accordance with some disclosed embodiments.
  • first and second are only used for descriptive purposes, and should not be construed as indicating or implying relative first importance or implicitly indicating the number of indicated technical features.
  • a feature defined as “first” or “second” may expressly or implicitly include one or more of that feature.
  • plural means two or more.
  • the expressions “coupled” and “connected” and their derivatives may be used.
  • the term “connected” may be used in describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other.
  • the term “coupled” may be used in describing some embodiments to indicate that two or more components are in direct physical or electrical contact.
  • the terms “coupled” or “communicatively coupled” may also mean that two or more components are not in direct contact with each other, yet still co-operate or interact with each other.
  • the embodiments disclosed herein are not necessarily limited by the content herein.
  • At least one of A, B, and C has the same meaning as “at least one of A, B, or C”, and both include the following combinations of A, B, and C: A only, B only, C only, A and B , A and C, B and C, and A, B, and C.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • the term “if” is optionally construed to mean “when” or “at” or “in response to determining” or “in response to detecting,” depending on the context.
  • the phrases “if it is determined that" or “if a [statement or event] is detected” are optionally interpreted to mean “in determining" or “in response to determining" or “on the detection of [the stated condition or event]” or “in response to the detection of the [ stated condition or event]”.
  • “same layer” refers to a layer structure in which a film layer for forming a specific pattern is formed by the same film forming process, and then formed by one patterning process using the same mask.
  • the same patterning process may include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights Or have different thicknesses.
  • Exemplary embodiments are described herein with reference to cross-sectional and/or plan views that are idealized exemplary drawings.
  • the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes of the drawings due to, for example, manufacturing techniques and/or tolerances, are contemplated.
  • example embodiments should not be construed as limited to the shapes of the regions shown herein, but to include deviations in shapes due, for example, to manufacturing. For example, an etched area shown as a rectangle will typically have curved features.
  • the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.
  • Embodiments of the present disclosure provide a display device, which may be, for example, an LCD (Liquid Crystal Display, liquid crystal display), an OLED (Organic Light-Emitting Diode, organic light-emitting diode) display device, and a QLED (Quantum Dot Light Emitting Diodes, Quantum dot light-emitting diode) any of the display devices.
  • a display device which may be, for example, an LCD (Liquid Crystal Display, liquid crystal display), an OLED (Organic Light-Emitting Diode, organic light-emitting diode) display device, and a QLED (Quantum Dot Light Emitting Diodes, Quantum dot light-emitting diode) any of the display devices.
  • LCD Liquid Crystal Display, liquid crystal display
  • OLED Organic Light-Emitting Diode, organic light-emitting diode
  • QLED Quantum Dot Light Emitting Diodes, Quantum dot light-e
  • the display device 1 includes a display area 10 and a peripheral area 11 at least partially surrounding the display area 10 .
  • the display area 10 is provided with sub-pixels p of multiple colors, for example, the multiple colors are three primary colors, and the three primary colors are, for example, red, green, and blue.
  • a drive circuit is provided in the above-mentioned display device 1, and the drive circuit includes, for example, a plurality of thin film transistors coupled and some other devices.
  • the driving circuit includes, for example, a pixel driving circuit and a GOA (Gate Driver On Array, array substrate row driving) circuit; wherein, the pixel driving circuit is arranged in the sub-pixel p; some other devices are, for example, capacitors, and the capacitors are, for example, storage capacitors .
  • the pixel driving circuit 122 is disposed in each sub-pixel p, and the GOA circuit 121 is disposed in the peripheral area 11 .
  • a plurality of gate lines 13 and data lines 14 are also provided in the display device 1 , the pixel driving circuits 122 in the same row of sub-pixels p are electrically connected to the same gate line 13 , and the pixel driving circuits 122 in the same column of sub-pixels p are electrically connected to the same gate line 13 .
  • the same data line 14 is electrically connected, and the end of a gate line 13 is coupled to an output end of the GOA circuit 121, so that the signal provided by the GOA circuit 121 can be transmitted to the pixel driving circuit 122 in the same row through the gate line 13, turning on the same row of pixel driving circuits 122. row the pixel driving circuit 122, and then all the data lines 14 start to write corresponding data signals to the pixel driving circuit 122, thereby driving the light emitting device D coupled to the pixel driving circuit 122 to emit light.
  • the above-mentioned pixel driving circuit 122 is, for example, a 2T1C type, a 7T1C type, or the like.
  • the GOA circuit 121 is, for example, a 3T1C type, an 8T2C type, etc.
  • the GOA circuit 121 may be a Gate GOA circuit (gate drive circuit) or an EM GOA circuit (light emission control circuit).
  • T represents a thin film transistor
  • C represents a capacitor.
  • 2T1C is the pixel driving circuit 122 including two thin film transistors and one capacitor.
  • the 2T1C type pixel driving circuit 122 includes a first transistor T1 , a second transistor T2 and a capacitor C, wherein the second transistor T2 is a driving transistor.
  • the gate of the first transistor T1 is electrically connected to the gate driving signal terminal Gate
  • the first pole of the first transistor T1 is electrically connected to the data signal terminal Data
  • the second pole of the first transistor T1 is electrically connected to the node N.
  • the gate of the second transistor T2 is electrically connected to the node N
  • the first electrode of the second transistor T2 is electrically connected to the power supply voltage signal terminal VDD
  • the second electrode of the second transistor T2 is electrically connected to the anode of the light emitting device D.
  • One end of the capacitor C is electrically connected to the node N, and the other end is electrically connected to the power supply voltage signal terminal VDD.
  • the cathode of the light emitting device D is electrically connected to the cathode signal terminal VSS.
  • the above-mentioned Gate GOA circuit can provide the gate driving signal to the gate line 13, the gate line 13 can transmit the gate driving signal to the gate driving signal terminal Gate, and the data line 14 can provide the data signal to the data signal terminal Data.
  • the number of thin film transistors and capacitors in the pixel driving circuit 122 and the GOA circuit 121 can be selected according to the actual needs of the driving circuit. The number is not limited, and only the pixel driving circuit 122 and the GOA circuit 121 listed above are used to illustrate that these driving circuits need to be formed by using thin film transistors.
  • an embodiment of the present disclosure provides a thin film transistor 2 , including:
  • the material of the active layer 21 is, for example, polysilicon (p-si).
  • the active layer 21 has a channel region 200 and a first electrode region 211 and a second electrode region 212 located on opposite sides of the channel region 200; wherein the first electrode region 211 and the second electrode region 212 are ion-doped regions,
  • the first electrode region 211 has a first ion doping concentration
  • the second electrode region 212 has a second ion doping concentration.
  • the first ion doping concentration of the first electrode region 211 may be the same as or different from the second ion doping concentration of the second electrode region 212 .
  • the first electrode region 211 is, for example, a source region
  • the second electrode region 212 is, for example, a drain region, and vice versa.
  • the first ion doping concentration and the second ion doping concentration are the same.
  • the first ion doping concentration and the second ion doping concentration are different.
  • the first electrode 24 and the second electrode 25 are arranged on one side in the thickness direction of the active layer 21 and are of the same layer and the same material.
  • the first electrode 24 is coupled to the first electrode area 211
  • the second electrode 25 is connected to the second electrode area. 212 Coupling.
  • the first electrode 24 is, for example, a source
  • the second electrode 25 is, for example, a drain.
  • the first electrode 24 is a source
  • the first electrode region 211 is a source region
  • the second electrode 25 is a drain
  • the first electrode region 211 is a source region
  • the second electrode region 212 is the drain region, and vice versa.
  • the third doping pattern 22 is disposed between the first electrode 24 and the first electrode region 211, and is in direct contact with the first electrode 24 and the first electrode region 211 respectively, wherein the third doping pattern 22 has a third ion doping pattern impurity concentration, the third ion doping concentration is different from the first ion doping concentration.
  • the third doping pattern 22 is disposed perpendicular to the first electrode region 211, is in direct contact with the first electrode 24 to form an ohmic contact, and is used to form an LDD (Lightly Doped Drain, lightly doped drain) region or an HDD (Highly Doped Drain, heavily doped drain) region.
  • LDD Lightly Doped Drain, lightly doped drain
  • HDD Highly Doped Drain, heavily doped drain
  • the ion doping concentration of the HDD region is greater than that of the LDD region.
  • the LDD region is used to alleviate the strong electric field of the drain of the thin film transistor 2, which can be equivalent to a resistance to reduce the light leakage current (off-state current of the thin film transistor 2); the LDD region can also be used to An ohmic contact and coupling function are formed between the first electrode 24 and the second electrode 25 ; the HDD region can also be used to form an ohmic contact and a coupling function with the first electrode 24 and the second electrode 25 .
  • the above-mentioned LDD region achieves the purpose of reducing the leakage current of the thin film transistor 2 by reducing the drain voltage Vd of the thin film transistor 2. Therefore, when the area of the LDD region is larger, it reduces the drain voltage Vd of the thin film transistor 2. The more obvious the effect of the voltage Vd is, the greater the magnitude of the reduction of the leakage current. Meanwhile, when the drain voltage Vd decreases, the threshold voltage of the thin film transistor 2 will increase.
  • the first electrode region 211 and the second electrode region 212 play a coupling role, wherein the first electrode region 211 enables the first electrode 24 to be coupled with the active layer 21 , and the second electrode region 212 The coupling between the second electrode 25 and the active layer 21 is achieved.
  • An ohmic contact is formed between the third doping pattern 22 and the first electrode 24 , and the third doping pattern 22 also has a coupling function for coupling the first electrode 24 and the active layer 21 .
  • One end of the second electrode 25 close to the active layer 21 is in contact with the second electrode region 212 , that is, the second electrode 25 is directly coupled with the second electrode region 212 . Ohmic contact.
  • the first ion doping concentration is equal to or approximately equal to the second ion doping concentration, and the first ion doping concentration is less than the third ion doping concentration.
  • the first electrode region 211 and the second electrode region 212 are LDD regions for reducing leakage current and drain voltage Vd.
  • the first ion doping concentration is equal to or approximately equal to the second ion doping concentration, and the first ion doping concentration is greater than the third ion doping concentration.
  • the third doping pattern 22 is an LDD region for reducing leakage current and drain voltage Vd.
  • the active layer 21 may further include a third doping region 23 ′, the third doping region 23 ′ is located in the first Between an electrode region 211 and the second electrode region 212, and adjacent to the second electrode region 212, the ion doping concentration of the third doping region 23' is, for example, a fifth doping concentration, and the fifth doping concentration
  • the third doped region 23' can be made an LDD region for reducing leakage current and drain voltage Vd.
  • the first ion doping concentration is equal to or approximately equal to the second ion doping concentration
  • the third ion doping concentration is equal to or approximately equal to the fifth doping concentration
  • the first ion doping concentration is greater than the third ion doping concentration doping concentration.
  • the third doping pattern 22 and the third doping region 23' are LDD regions for reducing leakage current and drain voltage Vd.
  • the first ion doping concentration is equal to or approximately equal to the fifth doping concentration
  • the second ion doping concentration is equal to or approximately equal to the third ion doping concentration
  • the first ion doping concentration is less than the second ion doping concentration concentration.
  • the first electrode region 211 and the third doping region 23' are LDD regions for reducing the leakage current and the drain voltage Vd.
  • the part of the active layer 21 that is located between the first electrode region 211 and the second electrode region 212 and does not belong to the third doping region 23 ′ is the channel region 200 of the thin film transistor 2 .
  • the length of the track area 200 is L, for example.
  • the short-channel effect of the thin film transistor 2 will become very obvious.
  • the short channel effect mainly means that the threshold voltage of the thin film transistor is related to the length of the channel region 200 to a very serious extent.
  • the short channel effect causes the threshold voltage of the thin film transistor 2 to decrease as the channel length decreases.
  • DIBL Drain Induced Barrier Lowering
  • the threshold voltage of the thin film transistor 2 decreases with the increase of the drain voltage Vd.
  • the threshold voltage will be different, and the smaller the threshold voltage, the easier it is to turn on the thin film transistor 2, which makes it difficult for the display device 1 to accurately control the turning on of the thin film transistor 2, resulting in a higher probability of the thin film transistor 2 being turned on by mistake, and when the threshold voltage After decreasing, the leakage current of the thin film transistor 2 will also increase. Therefore, the short channel effect makes it difficult to precisely control the turn-on of the thin film transistor 2 under different drain voltages, and there is a large leakage current, and the overall performance is poor.
  • the thin film transistor 2' in the related art includes an active layer 21', the active layer 21' includes a source region 211', a drain region 212', and a region between the source region 211' and the drain region 212'
  • An ohmic contact is formed between the source electrode 24' and the source region 211', and an ohmic contact is formed between the drain electrode 25' and the drain region 212'; the two third doped regions 23' are equivalent to resistance, and are used to reduce the The leakage current and the drain voltage Vd of the thin film transistor 2'.
  • the two third doping regions 23 ′ are located at the source electrode
  • the length L 0 of the channel region 200 ′ is smaller between the region 211 ′ and the drain region 212 ′, so that the short channel effect is still significant, and the overall performance of the thin film transistor 2 ′ is poor.
  • the abscissa in the figure is the gate voltage of the thin film transistor 2' in the related art, and the ordinate is the drain current of the thin film transistor 2'. From this figure, it can be clearly seen that when the gate voltage is The same, for example, both are 1.5V, and when the source voltage is set to 0, with the increase of the drain voltage Vd (Vd 1 ⁇ Vd 2 ⁇ Vd 3 ), the drain current is increasing, and the three curves cannot overlap. , the reason why the three curves cannot overlap is that the short-channel effect reduces the drain-induced potential barrier, which causes the threshold voltage of the thin film transistor 2' to drift, and as the drain voltage Vd increases, the threshold voltage decreases. Therefore, the drain voltage Vd has a great influence on the threshold voltage, and when the threshold voltage of the thin film transistor 2' is smaller, the probability of the thin film transistor 2 being turned on by mistake is greater, so the stability of the thin film transistor 2' is poor.
  • the length of the channel region 200 in the embodiment of the present disclosure is L; referring to FIG. 3A , the length L 0 of the channel region 200 ′ in the related art , it can be clearly seen that the length L of the channel region 200 in the present disclosure is greater than the length L 0 of the channel region 200 ′ in the related art.
  • the length of the third doped region 23 ′ shown in FIG. 3A in the related art is also larger, so the leakage current can be reduced and drain voltage Vd capability is also stronger. Therefore, the overall performance of the thin film transistor 2 in the embodiment of the present disclosure is superior to the performance of the thin film transistor 2' in the related art.
  • the thin film transistor 2 includes the third doping pattern 22 , and the third doping pattern 22 is disposed between the first electrode 24 and the first electrode region 211 , that is, the third doping pattern 22 is not located in in the active layer 21 . Due to the change of the position of the third doping pattern 22, on the one hand, the length of the channel region 200 in the active layer 21 can be set larger, and the short channel effect can be improved. On the other hand, the volume of the third doping pattern 22 can also be set larger. When the third doping pattern 22 is an LDD region, the equivalent resistance of the third doping pattern 22 is relatively large, which can reduce leakage current and leakage. The ability of the pole voltage Vd is stronger.
  • the first electrode region 211 and the second electrode region 212 are LDD regions, their lengths are longer than that of the third doping pattern 23' in the related art, which can reduce the leakage current and the drain voltage Vd. more capable.
  • the third doping pattern 22 or the first electrode region 211 and the second electrode region 212 are more capable of reducing the drain voltage Vd, for the same thin film transistor 2, the threshold voltages corresponding to different drain voltages Vd are all larger , the thin film transistor 2 is not easy to be turned on, so the probability of being turned on by mistake is low, the influence of the drain voltage Vd on its threshold voltage is reduced, and the influence of the short channel effect on the thin film transistor 2 can be further improved. Therefore, this The overall performance of the thin film transistor 2 in the disclosure is better.
  • the thin film transistor 2 further includes: a fourth doping pattern 23 disposed between the second electrode 25 and the second electrode region 212 , respectively connected to the second electrode 25 and the second doping pattern 23 .
  • the electrode regions 212 are in direct contact.
  • the fourth doping pattern 23 has a fourth ion doping concentration, and the fourth ion doping concentration is different from the second ion doping concentration.
  • the fourth doping pattern 23 is used to form an ohmic contact with the second electrode 25 , and when the fourth ion doping concentration is smaller than the second ion doping concentration, the fourth doping pattern 23 is used to reduce the leakage of the thin film transistor 2 Current magnitude and drain voltage Vd; when the fourth ion doping concentration is greater than the second ion doping concentration, the fourth doping pattern 23 acts as a coupling.
  • the first ion doping concentration is equal to or approximately equal to the second ion doping concentration
  • the third ion doping concentration is equal to or approximately equal to the fourth ion doping concentration
  • the first ion doping concentration is greater than the third ion doping concentration.
  • the third doping pattern 22 and the fourth doping pattern 23 are LDD regions for reducing the leakage current and the drain voltage Vd of the thin film transistor 2 .
  • the first ion doping concentration is equal to or approximately equal to the fourth ion doping concentration
  • the second ion doping concentration is equal to or approximately equal to the third ion doping concentration
  • the first ion doping concentration is greater than the second ion doping concentration. impurity concentration.
  • the third doping pattern 22 and the second electrode region 212 are LDD regions for reducing the leakage current and the drain voltage Vd of the thin film transistor 2 .
  • the first ion doping concentration is equal to or approximately equal to the fourth ion doping concentration
  • the second ion doping concentration is equal to or approximately equal to the third ion doping concentration
  • the first ion doping concentration is less than the third ion doping concentration. impurity concentration.
  • the first electrode region 211 and the fourth doping pattern 23 are LDD regions for reducing the leakage current and the drain voltage Vd of the thin film transistor 2 .
  • the first ion doping concentration is equal to or approximately equal to the second ion doping concentration
  • the third ion doping concentration is equal to or approximately equal to the fourth ion doping concentration
  • the first ion doping concentration is less than the third ion doping concentration. impurity concentration.
  • the first electrode region 211 and the second electrode region 212 are LDD regions for reducing the leakage current and the drain voltage Vd of the thin film transistor 2 .
  • the fourth doping pattern 23 is located between the first electrode 24 and the first electrode region 211 , so that the third doping region can no longer be provided in the active layer 21 23', and the length of the fourth doping pattern 23 can be set to be greater than the length of the third doping region 23', so the fourth doping pattern 23 can not only further increase the length of the channel region 200 of the thin film transistor 2, but also improve the Short channel effect, when the fourth ion doping concentration is lower than the second ion doping concentration, the area of the LDD region in the thin film transistor 2 can be increased to further improve the short channel effect and reduce the drain voltage Vd.
  • the thin film transistor 2 further includes: a gate insulating layer 26 and a gate electrode 28 stacked along the thickness direction of the active layer 21 , and the gate insulating layer 26 and The gate electrode 28 is disposed between the active layer 21 and the first electrode 24 and the second electrode 25 .
  • the gate insulating layer 26 is located between the active layer 21 and the gate electrode 28; the gate insulating layer 26 is provided with a first through hole 261, and the orthographic projection of the first through hole 261 on the active layer 21 falls on the first electrode The region 211 and the first electrode 24 are within the overlapping range of the orthographic projections on the active layer 21 ; the third doping pattern 22 is located in the first through hole 261 .
  • the thin film transistor 2 is a top-gate thin film transistor 2 .
  • the gate 28 in the top-gate thin film transistor 2 can play a role of self-alignment in the process of ion doping the first electrode region 211 and the second electrode region 212, so as to avoid using a mask in the process of ion doping board, thereby reducing production costs.
  • the orthographic projection of the first through hole 261 on the active layer 21 is a circle.
  • the length of the orthographic projection of the first electrode 24 on the active layer 21 and the overlapping portion of the first electrode region 211 is S
  • the length of the orthographic projection of the first through hole 261 on the active layer 21 is a circle diameter, which is smaller than S.
  • the third doping pattern 22 is located in the first through hole 261 , wherein referring to FIGS. 2A to 2D and FIGS. 4A to 4D , the thickness of the third doping pattern 22 may be equal to or approximately equal to the depth of the first through hole 261 . Referring to FIG. 5A , the thickness of the third doping pattern 22 may also be smaller than the depth of the first through hole 261 . Referring to FIGS. 5B and 5C , the thickness of the third doping pattern 22 may also be greater than the depth of the first through hole 261 .
  • the first through hole 261 on the active layer 21 falls within the overlapping range of the orthographic projection of the first electrode region 211 and the first electrode 24 on the active layer 21, on the one hand, the first through hole 261
  • the gate insulating layer 26 is prepared, the first through hole 261 can be formed on the gate insulating layer 26, and then the third doping pattern 22 is prepared, wherein for the third doping
  • the prepared thickness of the miscellaneous pattern 22 can be set according to the actual performance requirements of the thin film transistor 2 .
  • the gate insulating layer 26 is further provided with a second through hole 262 .
  • the orthographic projection of the second through hole 262 on the active layer 21 falls within the overlapping range of the orthographic projection of the second electrode region 212 and the second electrode 25 on the active layer 21; the fourth doping pattern 23 is located in the second through hole 262.
  • the fourth doping pattern 23 is located in the second through hole 262 , wherein referring to FIGS. 4A to 4D , the thickness of the fourth doping pattern 23 is equal to or approximately equal to the depth of the second through hole 262 . Referring to FIG. 5A , the thickness of the fourth doping pattern 23 is smaller than the depth of the second via hole 262 . Referring to FIGS. 5B and 5C , the thickness of the fourth doping pattern 23 is greater than the depth of the second through hole 262 .
  • the beneficial effect of the fourth doping pattern 23 disposed in the second through hole 262 is the same as the beneficial effect of the third doping pattern 22 disposed in the first through hole 261 , and thus will not be repeated.
  • the first ion doping concentration is equal to or approximately equal to the second ion doping concentration; the third ion doping concentration is equal to or approximately equal to the fourth ion doping concentration; And the first ion doping concentration is greater than the third ion doping concentration.
  • the third doping pattern 22 and the fourth doping pattern 23 are LDD regions, and the equivalent resistance of the third doping pattern 22 and the fourth doping pattern 23 is relatively large, which can reduce the drain voltage to the greatest extent. Vd and leakage current.
  • the third doping pattern when the first ion doping concentration is lower than the third ion doping concentration and/or the second ion doping concentration is lower than the fourth ion doping concentration, the third doping pattern
  • the edge of the orthographic projection of 22 on the active layer 21 coincides with the edge of the first electrode region 211 on the side away from the second electrode region 212, and/or the orthographic projection of the fourth doping pattern 23 on the active layer 21.
  • the edge coincides with the edge of the second electrode region 212 on the side away from the first electrode region 211 .
  • the first ion doping concentration is equal to or approximately equal to the fourth ion doping concentration
  • the second ion doping concentration is equal to or approximately equal to the third ion doping concentration
  • the first ion doping concentration is greater than the second ion doping concentration Ion doping concentration
  • the first ion doping concentration is equal to or approximately equal to the fourth ion doping concentration
  • the second ion doping concentration is equal to or approximately equal to the third ion doping concentration
  • the first ion doping concentration is less than the second ion doping concentration. impurity concentration; at this time, the side of the third doping pattern 22 away from the fourth doping pattern 23 is aligned with the side of the first electrode region 211 away from the second electrode region 212 .
  • the first ion doping concentration is equal to or approximately equal to the second ion doping concentration
  • the third ion doping concentration is equal to or approximately equal to the fourth ion doping concentration
  • the first ion doping concentration is less than the third ion doping concentration.
  • the first electrode region 211 and/or the second electrode region 212 are LDD regions, when the side of the third doping pattern 22 away from the fourth doping pattern 23 and the side of the first electrode region 211 away from the second electrode region 212 and/or when the side of the fourth doping pattern 23 away from the third doping pattern 22 is aligned with the side of the second electrode region 212 away from the first electrode region 211, the third doping pattern 22 and the The carriers transported by the four-doped pattern 23 pass through all of the first electrode region 211 and the second electrode region 212 , and the area of the first electrode region 211 and the second electrode region 212 is larger, so that the first electrode region 211 has a larger area.
  • the equivalent resistance with the second electrode region 212 is larger, which can further reduce the drain voltage Vd.
  • the carriers transported by the third doping pattern 22 pass through the first electrode region 211 and the third doping pattern 22 In the part in contact with and close to the second electrode region 212 , the carriers transmitted by the fourth doping pattern 23 pass through the side of the second electrode region 212 that is in contact with the fourth doping pattern 23 and is close to the first electrode region 211 part, that is, the carriers do not pass through all the first electrode region 211 and the second electrode region 212, and the equivalent resistance of the first electrode region 211 and the second electrode region 212 is calculated according to the part that the carriers pass through of. Therefore, in FIGS. 4D and 6C , the equivalent resistances of the first electrode region 211 and the second electrode region 212 are not the same.
  • the height of the third doping pattern 22 is less than or equal to the depth of the first through hole 261
  • the height of the fourth doping pattern 23 is less than or equal to the depth of the second through hole 262 . It is convenient to prepare the third doping pattern 22 in the first through hole 261 and the fourth doping pattern 23 in the second through hole 262 after the gate insulating layer 26 is formed.
  • the thin film transistor 2 further includes: an interlayer insulating layer 27 disposed on the gate 28 away from the On one side of the source layer 21, the interlayer insulating layer 27 is provided with a third through hole 271 and a fourth through hole 272, wherein the third through hole 271 communicates with the first through hole 261, and the fourth through hole 272 communicates with the second through hole 271.
  • the holes 262 communicate.
  • the orthographic projection of the third through hole 271 on the active layer 21 and the orthographic projection of the first through hole 261 on the active layer 21 fall within the range of the first electrode region 211 ; the fourth through hole 272 is in the active layer 21 The orthographic projection of the second through hole 262 on the active layer 21 falls within the range of the second electrode region 212 .
  • the third through hole 271 and the first through hole 261 have the same or approximately the same size
  • the fourth through hole 272 and the second through hole have the same or approximately the same size.
  • 262 is the same or about the same size.
  • the size of the first through hole 261 and the size of the second through hole 262 are the same or approximately the same.
  • the longitudinal cross-sections of the first through holes 261 to the fourth through holes 272 are rectangular, and the dimensions are all the same or approximately the same.
  • the size of the first through hole 261 and the size of the second through hole 262 are the same or approximately the same, and the size of the third through hole 271 and the fourth through hole 272 are the same or approximately the same.
  • the longitudinal sections of the first through holes 261 to the fourth through holes 272 are all inverted trapezoids, and in the longitudinal section view, the length of the top side of the first through hole 261 is equal to or approximately equal to the length of the bottom side of the third through hole 271 , the length of the top side of the second through hole 262 is equal to or approximately equal to the length of the bottom side of the fourth through hole 272 .
  • the size of the first through hole 261 and the size of the second through hole 262 are the same or approximately the same, and the size of the third through hole 271 and the fourth through hole 272 are the same or approximately the same.
  • the diameter of the third through hole 271 is larger than the diameter of the first through hole 261, for example, and the diameter of the fourth through hole 272 is larger than the diameter of the second through hole 262, for example.
  • the longitudinal sections of the first to fourth through holes 261 to 272 are rectangular, the diameters of the upper and lower ends of any one of the first to fourth through holes 261 to 272 are the same or approximately the same.
  • the diameters of the upper end and the lower end of any one of the first through hole 261 to the fourth through hole 272 are not equal, wherein , for any through hole, the diameter of the upper end is greater than the diameter of the lower end, that is, there is a maximum diameter and a minimum diameter.
  • the diameter of the third through hole 271 is larger than the diameter of the first through hole 261, for example, it can be understood that the minimum diameter of the third through hole 271 is larger than the maximum diameter of the first through hole 261; the diameter of the fourth through hole 272 is larger than, for example, the second through hole.
  • the diameter of the hole 262 can be understood as the minimum diameter of the fourth through hole 272 is greater than the maximum diameter of the second through hole.
  • the longitudinal sections of the first through holes 261 to the fourth through holes 272 are all inverted trapezoids, and in the longitudinal section view, the length of the top side of the first through hole 261 (corresponding to the first through hole 261
  • the maximum diameter of the second through hole 271 is smaller than the length of the bottom edge of the third through hole 271 (corresponding to the minimum diameter of the third through hole 271 ), and the length of the top edge of the second through hole 262 (corresponding to the maximum diameter of the second through hole 262 ) is smaller than that of the fourth through hole 262
  • the length of the bottom edge of the hole 272 (corresponding to the minimum diameter of the fourth through hole 272 ).
  • This structure can ensure the contact area between the side of the first electrode 24 close to the active layer 21 and the side of the third doping pattern 22 away from the active layer 21 , the side of the second electrode 25 close to the active layer 21 and the side of the third doping pattern 22 away from the active layer 21 .
  • the contact area of the side of the four-doped pattern 23 away from the active layer 21 is larger, thereby ensuring the coupling between the first electrode 24 and the third doping pattern 22 and between the second electrode 25 and the fourth doping pattern 23 Better connection stability.
  • the third doping pattern 22 is also located in the third through hole 271
  • the fourth doping pattern 23 is also located in the fourth through hole 272 .
  • the first through hole 261 to the fourth through hole 272 can be prepared after the interlayer insulating layer 27 is prepared, and when the first through hole 261 and the fourth through hole 272 are prepared
  • the three through holes 271 are prepared at the same time, and the punching process can be saved when the second through holes 262 and the fourth through holes 272 are prepared at the same time.
  • the thicknesses of the third doping pattern 22 and the fourth doping pattern 23 can be set larger, especially when the third doping pattern 22 and the fourth doping pattern 23 are LDD regions, the thickness of the third doping pattern 22 and the fourth doping pattern 23 can be further increased.
  • the equivalent resistances of the third doping pattern 22 and the fourth doping pattern 23 further reduce the drain voltage Vd and reduce the short channel effect.
  • the thickness of the third doping pattern 22 is equal to or approximately equal to the thickness of the fourth doping pattern 23 .
  • the thickness of the third doping pattern 22 is equal to or approximately equal to the fourth doping pattern 23
  • the thickness is 100 ⁇ , it is convenient for subsequent fabrication of other film layers (such as the interlayer insulating layer 27 , the first electrode 24 and the second electrode 25 ) on the third doping pattern 22 and the fourth doping pattern 23 .
  • the thin film transistor 2 in the embodiment of the present disclosure may be an N-type transistor or a P-type transistor.
  • an N-type transistor is used as an example for description.
  • the materials of the third doping pattern 22 and the fourth doping pattern 23 include, for example, a semiconductor material of N+ ions, such as N+a-si.
  • the doping ions of the first electrode region 211 and the second electrode region 212 are also N+ ions, for example.
  • the N+ ions are, for example, P (phosphorus) ions
  • the doping doses corresponding to the first ion doping concentration and the second ion doping concentration are, for example, 5 ⁇ 10 14 /cm 2 to 1 ⁇ 10 15 /cm 2 .
  • Doping doses corresponding to the triple ion doping concentration and the fourth ion doping concentration are, for example, 5 ⁇ 10 13 cm 2 to 1 ⁇ 10 14 cm 2 .
  • the third doping region 23' and the fourth doping pattern 23 can be used as LDD regions, those skilled in the art can understand that the third doping region 23' and the fourth doping pattern 23 can be used as LDD regions.
  • the doping region 23' and the fourth doping pattern 23 cannot coexist in the thin film transistor 2, and the fifth doping concentration may be equal to or approximately equal to the fourth ion doping concentration.
  • an embodiment of the present disclosure further provides a method for fabricating a thin film transistor 2 , including:
  • an active layer 21 is formed.
  • the active layer 21 has a channel region 200 and a first electrode region 211 and a second electrode region 212 located on opposite sides of the channel region 200, and the first electrode region 211 and the second electrode region 212 are ion-doped regions,
  • the first electrode region 211 has a first ion doping concentration
  • the second electrode region 212 has a second ion doping concentration.
  • the material of the active layer 21 is polysilicon.
  • the active layer 21 may further include a third doping region 23 ′, the ion doping concentration of the third doping region 23 ′ is a fifth doping concentration, and the fifth doping concentration is the same as that of the second ion doping concentration.
  • the doping concentration is different, and the third doping region 23' is used to form the LDD region.
  • the third doping pattern 22 has a third ion doping concentration, and the third ion doping concentration is different from the first ion doping concentration.
  • a first electrode 24 is formed on the side of the third doping pattern 22 away from the active layer 21, and a second electrode 25 is formed on the active layer 21.
  • the first electrode 24 and the second electrode 25 are of the same layer and the same material, and the An electrode 24 is coupled to the first electrode region 211 through the third doping pattern 22 , and the second electrode 25 is coupled to the second electrode region 212 .
  • a fourth doping pattern 23 while the third doping pattern 22 is formed on the active layer 21 , a fourth doping pattern 23 , the fourth doping pattern 23 and the second electrode region 212 are also formed at the same time. Coupling, the fourth doping pattern 23 has a fourth ion doping concentration, and the fourth ion doping concentration is different from the second ion doping concentration.
  • Forming the second electrode 25 on the active layer 21 further includes: forming the second electrode 25 on the side of the fourth doping pattern 23 away from the active layer 21 ; wherein the fourth doping pattern 23 is coupled to the second electrode 25 .
  • the first electrode 24 and the second electrode 25 are made of the same layer and the same material, and the material of the first electrode 24 and the second electrode 25 is at least one of conductive metals such as silver (Ag), aluminum (Al), and titanium (Ti).
  • forming the active layer 21 includes:
  • a polysilicon thin film is formed, and a semiconductor pattern is formed by a patterning process.
  • the thickness of the polysilicon film is, for example,
  • a gate insulating layer 26 is formed on one side of the semiconductor pattern 210 .
  • the thickness of the gate insulating layer 26 is, for example,
  • the gate insulating layer 26 can be a single-layer structure, and the material of the single-layer structure is, for example, silicon oxide (SiO); it can also be a stack structure stacked along the thickness direction of the thin film transistor 2, such as a double-layer stack structure, wherein
  • the material of one layer structure close to one side of the semiconductor pattern 210 is, for example, silicon oxide, and the material of the other layer structure is, for example, silicon nitride (SiN).
  • a gate electrode 28 is formed on a side of the gate insulating layer 26 away from the semiconductor pattern 210 .
  • the material of the gate electrode 28 is, for example, molybdenum (Mo), and the thickness thereof is, for example, 200 nm to 350 nm.
  • ion doping is performed on the portion of the semiconductor pattern 210 where the first electrode region and the second electrode region are to be formed, so as to form the active layer 21 .
  • the gate 28 has been formed on the gate insulating layer 26, when the semiconductor pattern 210 is ion-doped, the gate can play a role of self-alignment, so that a mask is not required for the ion-doping, That is, the doping ions 2100 can be made to enter the part of the semiconductor pattern 210 where the first electrode region and the second electrode region are to be formed, and finally the first electrode region 211 and the second electrode region 212 are formed.
  • the first ion doping concentration and the second ion doping concentration are equal or approximately equal.
  • the doping dose on each side is, for example, 51 ⁇ 10 14 /cm 2 -1 ⁇ 10 15 /cm 2 , so that the first ion doping concentration and the second ion doping concentration are large, so that the first electrode region 211 and the second electrode region 212 become HDD regions.
  • forming the polysilicon film includes, for example:
  • An amorphous silicon film is deposited, and the amorphous silicon (a-si) in the amorphous silicon film is converted into polysilicon by laser irradiation to form a polysilicon film, or polysilicon is directly deposited to form a polysilicon film.
  • laser annealing can be performed by an excimer laser annealing device to convert amorphous silicon in the amorphous silicon film into polycrystalline silicon, so as to form a polycrystalline silicon film.
  • the thin film transistor 2 needs a substrate as a carrier for each film layer in the process of preparing the thin film transistor 2, so the above polysilicon thin film needs to be fabricated on the substrate.
  • a buffer layer may be formed on the substrate before the polysilicon thin film is formed.
  • the buffer layer is, for example, a stacked structure of a silicon nitride layer and a silicon oxide layer, wherein the thickness of the silicon nitride layer is, for example, The thickness of the silicon oxide layer is, for example, And the silicon nitride layer is closer to the substrate than the silicon oxide layer.
  • forming the third doping pattern 22 on one side of the active layer 21 further includes:
  • a first through hole 261 is formed on the gate insulating layer 26 , and the orthographic projection of the first through hole 261 on the active layer 21 falls within the range of the first electrode region 211 .
  • the first through hole 261 penetrates the gate insulating layer 26 , and the longitudinal section of the first through hole 261 is, for example, an inverted trapezoid.
  • a doped film 220 is formed on the side of the gate insulating layer 26 and the gate 28 away from the active layer 21, and a third through hole 261 is formed by patterning the doped film 220. Doping pattern 22 .
  • the third doping pattern 22 is an LDD region.
  • the size of the second through hole 262 is, for example, the same or approximately the same as the size of the first through hole 261 .
  • a doped film 220 is formed on the side of the gate insulating layer 26 and the gate 28 away from the active layer 21 , and the doped film 220 is patterned to form a third dopant in the first through hole 261 At the same time as the pattern 22 , the fourth doped pattern 23 is also formed in the second through hole 262 .
  • forming the third doping pattern 22 on one side of the active layer 21 may further include:
  • an interlayer insulating layer 27 is formed on the side of the gate insulating layer 26 and the gate electrode 28 away from the active layer 21 .
  • the thickness of the interlayer insulating layer 27 is, for example, 500 nm.
  • the interlayer insulating layer 27 can be a single-layer structure, and the material of the single-layer structure is, for example, silicon oxide (SiO); it can also be a laminated structure, such as a double-layer laminated structure, wherein a layer close to the side of the gate insulating layer 26
  • the material of the structure is, for example, silicon oxide, and the thickness is, for example, 200 nm; the material of the other layer structure is, for example, silicon nitride, and the thickness is, for example, 300 nm.
  • a third through hole 271 and a first through hole 261 are formed on the interlayer insulating layer 27 and the gate insulating layer 26 .
  • the third through hole 271 is located on the interlayer insulating layer 27, the first through hole 261 is located on the gate insulating layer 26, the orthographic projection of the third through hole 271 on the active layer 21 and the first through hole 261 on the active layer 21
  • the orthographic projection on the layer 21 falls within the range of the first electrode region 211 .
  • the longitudinal sections of the first through hole 261 and the third through hole 271 are both inverted trapezoids.
  • a doped film 220 is formed on the side of the interlayer insulating layer 27 away from the active layer 21 , and the doped film 220 is patterned to form the third through hole 271 and the first through hole 261 A third doping pattern 22 is formed there.
  • the interlayer insulating layer 27 and the gate insulating layer are also formed at the same time.
  • a fourth through hole 272 and a second through hole 262 are formed on the 26 .
  • the fourth through hole 272 is located on the interlayer insulating layer 27, the second through hole 262 is located on the gate insulating layer 26, the orthographic projection of the fourth through hole 272 on the active layer 21 and the second through hole 262 on the active layer 21
  • the orthographic projection on the layer 21 falls within the range of the second electrode region 212 .
  • a doped film 220 is formed on the side of the interlayer insulating layer 27 away from the active layer 21, and the doped film 220 is patterned to form the third through hole 271 and the first through hole 261. Simultaneously with the three doping patterns 22 , the fourth doping patterns 23 are also formed in the fourth through holes 272 and the second through holes 262 .
  • the thickness of the third doping pattern 22 and the thickness of the fourth doping pattern 23 are the same or approximately the same, and are smaller than the sum of the depths of the first through hole and the third A portion of the first electrode 24 is formed in the remaining portion, and a portion of the second electrode 25 is formed in the remaining portion of the fourth through hole 212, so as to increase the distance between the first electrode 24 and the third doping pattern 22, the second electrode 25 Coupling stability with the fourth doping pattern 23 .
  • the material of the doped thin film 220 is, for example, N+a-si.
  • forming the doped film 220 made of N+a-si includes:
  • N+a-si particles are deposited to form doped thin film 220 .
  • the amorphous silicon thin film is formed first, and then N+ ions are doped on the amorphous silicon thin film to form the doped thin film 220 .
  • the purpose of doping N+ ions can be achieved by doping PH 3 (phosphine) into the amorphous silicon film.
  • the doping dose of PH 3 is, for example, 5 ⁇ 10 13 /cm 2 to 1 ⁇ 10 14 /cm 2 , so that lightly doped third doping patterns 22 and fourth doping patterns 23 can be obtained.
  • a metal thin film is deposited on the interlayer insulating layer 27, and the metal thin film is patterned to form a first electrode 24 and a second electrode 25, wherein the first electrode 24 and the third doping The pattern 22 is coupled, and the second electrode 25 is coupled with the fourth doping pattern 23 .
  • the metal thin film is, for example, a laminated structure, such as a three-layer laminated structure of Ti/Al/Ti, the aluminum layer is located in the middle, and the thickness is, for example, 650 nm; the thickness of each Ti layer is, for example, 50 nm.
  • the above-mentioned preparation method of the thin film transistor 2 has the same beneficial effects as the above-mentioned thin film transistor 2, and thus will not be repeated.
  • the first electrode 24 and the second electrode 25 can also be formed on the side away from the active layer 21
  • the material of the anode 214 is, for example, indium tin oxide (ITO), and the anode 214 is, for example, coupled to the second electrode 25 of the thin film transistor 2 .
  • ITO indium tin oxide
  • the material of the flat layer 213 is an organic material, such as polyimide (PI).
  • the material of the pixel defining layer 215 is an organic material, such as photosensitive polyimide.
  • the light-emitting functional layer 216 is used to form the light-emitting device D in the pixel driving circuit 122 .
  • the light-emitting functional layer 216 may also include an electron transport layer (Election Transporting Layer, ETL) 2162, an electron injection layer (Election Injection Layer, EIL) 2163, and a hole transport layer (Hole Transporting Layer, HTL) 2164 And a hole injection layer (Hole Injection Layer, HIL) 2165.
  • ETL electron transport layer
  • EIL electron injection layer
  • HTL hole transport layer
  • HIL Hole Injection Layer
  • the encapsulation layer 217 includes a first inorganic encapsulation sub-layer 2171 , an organic encapsulation sub-layer 2173 and a second inorganic encapsulation sub-layer 2172 stacked along the thickness direction of the thin film transistor 2 .
  • the materials of the first inorganic encapsulation sub-layer 2171 and the second inorganic encapsulation sub-layer 2172 are, for example, at least one of silicon nitride and silicon oxide.
  • the first inorganic encapsulation sub-layer 2171 and the second inorganic encapsulation sub-layer 2172 may be formed by, for example, magnetron sputtering.
  • the organic encapsulation sub-layer 2173 can be formed by, for example, ink jet printing (Ink jet printing, IJP).
  • the above-mentioned OLED display device has the same beneficial effects as the above-mentioned thin film transistor 2 , so it is not repeated here.
  • approximately equal, approximately the same, approximately equal means the same, that is, although two numerical values are not actually equal, the difference between the two numerical values is within the allowable range of error, so the influence of its difference can be ignored.
  • the first ion doping concentration is approximately equal to the second ion doping concentration, that is, although the first ion doping concentration and the second ion doping concentration are not the same, the first ion doping concentration and the second ion doping concentration are not the same.
  • the difference between the concentrations is within an allowable range of error, and the difference does not affect the characteristics of the first electrode region 211 and the second electrode region 212 .
  • the allowable error range can be determined according to the characteristics of the actual product, such as ⁇ 0.1%, ⁇ 1%, etc., which is not limited in the present disclosure.
  • the first ion doping concentration to the fifth doping concentration all refer to the average value of each doping concentration, and the average value is an arithmetic average value; for example, the third ion doping concentration
  • the impurity concentration is the average concentration of ion doping in the third doping pattern 22 , and actually in the third doping pattern 22 , the ion doping concentration at each position may have a certain difference, for example, because the third doping pattern 22 needs to simultaneously
  • An ohmic contact is formed between the third doping pattern 22 and the first electrode 24, so the ion doping concentration of the part of the third doping pattern 22 in contact with the first electrode 24 can be set higher to achieve ohmic contact, and the ion doping concentration of the remaining area It can be set smaller to achieve the effect of reducing the drain voltage Vd and leakage current of the thin film transistor.

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Abstract

一种薄膜晶体管，包括：有源层，有源层的材料为多晶硅，有源层具有沟道区和位于沟道区相对两侧的第一电极区和第二电极区，其中，第一电极区和第二电极区为离子掺杂区域，第一电极区具有第一离子掺杂浓度，第二电极区具有第二离子掺杂浓度；第一电极和第二电极，设置于有源层厚度方向上的一侧且同层同材料，第一电极与第一电极区耦接、第二电极与第二电极区耦接；第三掺杂图案，设置于第一电极和第一电极区之间，分别与第一电极和第一电极区直接接触，其中，第三掺杂图案具有第三离子掺杂浓度，第三离子掺杂浓度与第一离子掺杂浓度不同。

Description

薄膜晶体管及其制备方法和显示装置
本申请要求于2020年7月17日提交的、申请号为202010693348.9的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种薄膜晶体管及其制备方法和显示装置。
背景技术
在显示面板的驱动电路中，使用的最多的器件是薄膜晶体管(Thin Film Transistor，TFT)，薄膜晶体管是一种场效应晶体管。在驱动电路中，TFT的功能是一个三端开关管，三端例如栅极、源极和漏极，当栅极开启时，信号可以从源极传输至漏极。
发明内容
一方面，提供一种薄膜晶体管。所述薄膜晶体管包括：有源层、第一电极、第二电极和第三掺杂图案。所述有源层的材料为多晶硅，所述有源层具有沟道区和位于所述沟道区相对两侧的第一电极区和第二电极区，其中，所述第一电极区和所述第二电极区为离子掺杂区域，所述第一电极区具有第一离子掺杂浓度，所述第二电极区具有第二离子掺杂浓度。所述第一电极和所述第二电极设置于所述有源层厚度方向上的一侧且同层同材料，所述第一电极与所述第一电极区耦接、所述第二电极与所述第二电极区耦接。所述第三掺杂图案设置于所述第一电极和所述第一电极区之间，分别与所述第一电极和所述第一电极区直接接触，其中，所述第三掺杂图案具有第三离子掺杂浓度，所述第三离子掺杂浓度与所述第一离子掺杂浓度不同。
在一些实施例中，所述薄膜晶体管还包括：第四掺杂图案，设置于所述第二电极和所述第二电极区之间，分别与所述第二电极和所述第二电极区直接接触；所述第四掺杂图案具有第四离子掺杂浓度，所述第四离子掺杂浓度与所述第二离子掺杂浓度不同。
在一些实施例中，所述薄膜晶体管还包括：沿所述有源层的厚度方向层叠的栅绝缘层和栅极，且所述栅绝缘层和所述栅极设置于所述有源层与所述第一电极和所述第二电极之间。
其中，所述栅绝缘层位于所述有源层和所述栅极之间；所述栅绝缘层上设置有第一通孔，所述第一通孔在所述有源层上的正投影落在所述第一电极区和所述第一电极在所述有源层上的正投影重叠的范围以内。
所述第三掺杂图案位于所述第一通孔中。
在一些实施例中，在所述薄膜晶体管还包括第四掺杂图案的情况下，所述栅绝缘层上还设置有第二通孔，所述第二通孔在所述有源层上的正投影落在所述第二电极区和所述第二电极在所述有源层上的正投影重叠的范围以内。
所述第四掺杂图案位于所述第二通孔中。
在一些实施例中，所述第一离子掺杂浓度等于或者大致等于所述第二离子掺杂浓度；所述第三离子掺杂浓度等于或者大致等于所述第四离子掺杂浓度；且所述第一离子掺杂浓度大于所述第三离子掺杂浓度。
在一些实施例中，所述第三掺杂图案的高度小于等于所述第一通孔的深度，所述第四掺杂图案的高度小于等于所述第二通孔的深度。
在一些实施例中，所述薄膜晶体管还包括：层间绝缘层，设置于所述栅极远离所述有源层的一侧，所述层间绝缘层上设置有第三通孔和第四通孔，其中所述第三通孔与所述第一通孔连通，所述第四通孔与所述第二通孔连通；所述第三通孔在所述有源层上的正投影和所述第一通孔在所述有源层上的正投影落在所述第一电极区的范围以内；所述第四通孔在所述有源层上的正投影和所述第二通孔在所述有源层上的正投影落在所述第二电极区的范围以内。
在一些实施例中，所述第三通孔的直径大于所述第一通孔的直径，所述第四通孔的直径大于所述第二通孔的直径。
在一些实施例中，所述第三掺杂图案还位于所述第三通孔中，所述第四掺杂图案还位于所述第四通孔中。
在一些实施例中，所述第三掺杂图案的厚度等于或大致等于所述第四掺杂图案的厚度。
在一些实施例中，所述第三掺杂图案和所述第四掺杂图案的材料为包括N+离子的半导体材料。
另一方面，提供一种显示装置，包括如上任一实施例所述的薄膜晶体管。
又一方面，提供一种薄膜晶体管的制备方法，包括：
形成有源层；其中，所述有源层的材料为多晶硅，所述有源层具有沟道区和位于所述沟道区相对两侧的第一电极区和第二电极区，所述第一电极区和所述第二电极区为离子掺杂区域，所述第一电极区具有第一离子掺杂浓度，所述第二电极区具有第二离子掺杂浓度。
在所述有源层的一侧形成第三掺杂图案，所述第三掺杂图案具有第三离 子掺杂浓度，所述第三离子掺杂浓度与所述第一离子掺杂浓度不同。
在所述第三掺杂图案远离所述有源层的一侧形成第一电极，在所述有源层上形成第二电极；所述第一电极和所述第二电极同层同材料，所述第一电极通过所述第三掺杂图案与所述第一电极区耦接，所述第二电极与所述第二电极区耦接。
在一些实施例中，在所述有源层上形成第三掺杂图案的同时，还形成第四掺杂图案，所述第四掺杂图案与所述第二电极区耦接，所述第四掺杂图案具有第四离子掺杂浓度，所述第四离子掺杂浓度与所述第二离子掺杂浓度不同。
在所述有源层上形成所述第二电极进一步包括：在所述第四掺杂图案远离所述有源层的一侧形成所述第二电极；其中，所述第四掺杂图案与所述第二电极耦接。
在一些实施例中，形成有源层进一步包括：
形成多晶硅薄膜，通过图案化工艺形成半导体图案；
在所述半导体图案的一侧形成栅绝缘层；
在所述栅绝缘层远离半导体图案的一侧形成栅极；
对所述半导体图案中待形成第一电极区和第二电极区的部分进行离子掺杂，以形成所述有源层。
在一些实施例中，在所述有源层的一侧形成第三掺杂图案进一步包括：
在所述栅绝缘层上形成第一通孔，所述第一通孔在所述有源层上的正投影落在所述第一电极区的范围以内；
在所述栅绝缘层和所述栅极远离所述有源层的一侧形成掺杂薄膜，通过图案化所述掺杂薄膜，在所述第一通孔中形成第三掺杂图案。
在一些实施例中，在所述栅绝缘层上形成第一通孔的同时，还形成第二通孔，所述第二通孔在所述有源层上的正投影落在所述第二电极区的范围以内。
在所述栅绝缘层和所述栅极远离所述有源层的一侧形成所述掺杂薄膜，图案化所述掺杂薄膜，以在所述第一通孔中形成所述第三掺杂图案的同时，还在所述第二通孔中形成第四掺杂图案。
在一些实施例中，在所述有源层的一侧形成第三掺杂图案进一步包括：
在所述栅绝缘层和所述栅极远离所述有源层的一侧形成层间绝缘层。
在所述层间绝缘层和所述栅绝缘层上形成连通的第三通孔和第一通孔。其中，所述第三通孔位于所述层间绝缘层上，所述第一通孔位于所述栅绝缘 层上，所述第三通孔在所述有源层上的正投影和所述第一通孔在所述有源层上的正投影落在所述第一电极区的范围以内。
在所述层间绝缘层远离所述有源层的一侧形成掺杂薄膜，图案化所述掺杂薄膜，以在所述第三通孔和所述第一通孔中形成第三掺杂图案。
在一些实施例中，在所述层间绝缘层和所述栅绝缘层上形成连通的所述第三通孔和所述第一通孔的同时，还在所述层间绝缘层和所述栅绝缘层上形成连通的第四通孔和第二通孔；其中，所述第四通孔位于所述层间绝缘层上，所述第二通孔位于所述栅绝缘层上，所述第四通孔在所述有源层上的正投影和所述第二通孔在所述有源层上的正投影落在所述第二电极区的范围以内。
在所述层间绝缘层远离所述有源层的一侧形成所述掺杂薄膜，图案化所述掺杂薄膜，以在所述第三通孔和所述第一通孔中形成所述第三掺杂图案的同时，还在所述第四通孔和所述第二通孔中形成第四掺杂图案。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1A为根据公开的一些实施例提供的一种显示装置的结构图；
图1B为根据公开的一些实施例提供的一种像素电路的结构图；
图2A～图2D为根据公开的一些实施例提供的一种薄膜晶体管的结构图；
图3A为相关技术中的一种薄膜晶体管的结构图；
图3B为相关技术中的一种薄膜晶体管的漏极电压与栅极电压、漏极电流之间的关系图；
图4A～图4D为根据公开的一些实施例提供的另一种薄膜晶体管的结构图；
图4E为图4D中A处的放大图；
图5A～图5C为根据公开的一些实施例提供的另一种薄膜晶体管的结构图；
图6A～图6C为根据公开的一些实施例提供的另一种薄膜晶体管的结构图；
图7A～图7B为根据公开的一些实施例提供的另一种薄膜晶体管的结构图；
图8为根据公开的一些实施例提供的一种薄膜晶体管的制备方法的流程图；
图9A为根据公开的一些实施例提供的一种有源层的制备过程的流程图；
图9B～图9C为根据公开的一些实施例提供的一种有源层的制备过程图；
图10A为根据公开的一些实施例提供的一种第三掺杂图案的制备过程的流程图；
图10B为根据公开的一些实施例提供的一种第三掺杂图案和第四掺杂图案的制备过程图；
图10C为图10B的俯视图；
图10D为根据公开的一些实施例提供的一种第三掺杂图案和第四掺杂的制备过程图；
图11A为根据公开的一些实施例提供的另一种第三掺杂图案的制备过程的流程图；
图11B～图11E为根据公开的一些实施例提供的另一种第三掺杂图案和第四掺杂图案的制备过程图；
图12A为根据公开的一些实施例提供的另一种显示装置的结构图；
图12B为根据公开的一些实施例提供的发光功能层的结构图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定 特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对第一要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“耦接”或“通信耦合(communicatively coupled)”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
如本文中所使用，根据上下文，术语“如果”任选地被解释为意思是“当……时”或“在……时”或“响应于确定”或“响应于检测到”。类似地，根据上下文，短语“如果确定……”或“如果检测到[所陈述的条件或事件]”任选地被解释为是指“在确定……时”或“响应于确定……”或“在检测到[所陈述的条件或事件]时”或“响应于检测到[所陈述的条件或事件]”。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
如本文所使用的那样，“约”或“近似”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。
如本文所使用的那样，“同层”指的是采用同一成膜工艺形成用于形成 特定图形的膜层，然后利用同一掩模板通过一次构图工艺形成的层结构。根据特定图形的不同，同一构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续的，这些特定图形还可能处于不同的高度或者具有不同的厚度。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
本公开的实施例提供一种显示装置，该显示装置例如可以是LCD(Liquid Crystal Display，液晶显示器)、OLED(Organic Light-Emitting Diode，有机发光二极管)显示装置和QLED(Quantum Dot Light Emitting Diodes，量子点发光二极管)显示装置中的任一种。
如图1A所示，显示装置1包括显示区10和至少部分围绕显示区10的周边区11。在显示区10设置有多种颜色的亚像素p，多种颜色例如为三基色，三基色又例如为红色、绿色和蓝色。
在上述的显示装置1中设置有驱动电路，驱动电路例如包括：耦接的多个薄膜晶体管和一些其它器件。其中，驱动电路例如包括像素驱动电路和GOA(Gate Driver On Array，阵列基板行驱动)电路；其中，像素驱动电路设置于亚像素p中；一些其它器件例如为电容，该电容又例如为存储电容。
参考图1A，以显示装置1为OLED显示装置为例，像素驱动电路122设置于每个亚像素p中，GOA电路121设置于周边区11。在显示装置1中还设置有多条栅线13和数据线14，同一行亚像素p中的像素驱动电路122与同一条栅线13电连接，同一列亚像素p中的像素驱动电路122与同一条数据线14电连接，一条栅线13的端部与GOA电路121的一个输出端耦接，从而GOA电路121提供的信号可以通过栅线13传输至同一行像素驱动电路122中，打开同一行像素驱动电路122，然后所有的数据线14开始向像素驱动电路122写入对应的数据信号，从而驱动与像素驱动电路122耦接的发光器件D发光。
示例的，上述的像素驱动电路122例如为2T1C型、7T1C型等。GOA电路121例如为3T1C型、8T2C型等，GOA电路121可以是Gate GOA电路(栅极驱动电路)，也可以是EM GOA电路(发光控制电路)。其中，T代表薄 膜晶体管、C代表电容，例如2T1C即为包括2个薄膜晶体管和1个电容的像素驱动电路122。
示例的，参考图1B，2T1C型的像素驱动电路122包括第一晶体管T1、第二晶体管T2和电容C，其中第二晶体管T2为驱动晶体管。第一晶体管T1的栅极与栅极驱动信号端Gate电连接，第一晶体管T1的第一极与数据信号端Data电连接，第一晶体管T1的第二极与节点N电连接。第二晶体管T2的栅极与节点N电连接，第二晶体管T2的第一极与电源电压信号端VDD电连接，第二晶体管T2的第二极与发光器件D的阳极电连接。电容C的一端与节点N电连接，另一端与电源电压信号端VDD电连接。发光器件D的阴极与阴极信号端VSS电连接。
上述的Gate GOA电路可以向栅线13提供栅极驱动信号，栅线13则可以将栅极驱动信号传输至栅极驱动信号端Gate，数据线14可以向数据信号端Data提供数据信号。
像素驱动电路122和GOA电路121中的薄膜晶体管和电容的数量，均可根据驱动电路的实际需求而进行选择，因此，本公开中对像素驱动电路122和GOA电路121中的薄膜晶体管和电容的数量均不做限制，仅以上述列举的像素驱动电路122和GOA电路121，以说明该些驱动电路需要使用薄膜晶体管构成而已。
基于上述，参考图2A～图2D，本公开的实施例提供一种薄膜晶体管2，包括：
有源层21，有源层21的材料例如为多晶硅(p-si)。
有源层21具有沟道区200和位于沟道区200相对两侧的第一电极区211和第二电极区212；其中，第一电极区211和第二电极区212为离子掺杂区域，第一电极区211具有第一离子掺杂浓度，第二电极区212具有第二离子掺杂浓度。
第一电极区211的第一离子掺杂浓度可以和第二电极区212的第二离子掺杂浓度相同，也可以不同。
第一电极区211例如是源极区，第二电极区212例如是漏极区，反之亦然。
示例的，参考图2A～图2C，第一离子掺杂浓度和第二离子掺杂浓度相同。
又示例的，参考图2D，第一离子掺杂浓度和第二离子掺杂浓度不同。
第一电极24和第二电极25；设置于有源层21厚度方向上的一侧且同层同材料，第一电极24与第一电极区211耦接，第二电极25与第二电极区212 耦接。
第一电极24例如是源极，第二电极25例如是漏极，且当第一电极24是源极时，第一电极区211为源极区；当第二电极25为漏极时，第二电极区212为漏极区，反之亦然。
第三掺杂图案22；设置于第一电极24和第一电极区211之间，分别与第一电极24和第一电极区211直接接触，其中，第三掺杂图案22具有第三离子掺杂浓度，第三离子掺杂浓度与第一离子掺杂浓度不同。
第三掺杂图案22垂直于第一电极区211设置，与第一电极24直接接触以形成欧姆接触，以及用于形成LDD(Lightly Doped Drain，轻掺杂漏)区域或HDD(Highly Doped Drain，重掺杂漏)区域。
HDD区域的离子掺杂浓度大于LDD区域的离子掺杂浓度。其中，LDD区域用于缓和薄膜晶体管2中漏极的强电场，其可等效为电阻，用于减小光照漏电流(薄膜晶体管2的关态电流)的大小；LDD区域还可以用于与第一电极24和第二电极25之间形成欧姆接触和起耦接作用；HDD区域也可以用于与第一电极24和第二电极25形成欧姆接触和起耦接作用。
本领域技术人员可以理解的是，上述的LDD区域是通过降低薄膜晶体管2的漏极电压Vd来实现降低薄膜晶体管2的漏电流的目的，因此当LDD区域的面积越大时，其降低漏极电压Vd的效果越明显，漏电流减小的幅度越大。同时，当漏极电压Vd减小时，薄膜晶体管2的阈值电压将增大。
参考图2A～图2D，第一电极区211和第二电极区212起耦接作用，其中，第一电极区211使得第一电极24与有源层21实现了耦接，第二电极区212使得第二电极25与有源层21之间实现了耦接。第三掺杂图案22与第一电极24之间形成了欧姆接触，且第三掺杂图案22还具有耦接作用，用于耦接第一电极24和有源层21。第二电极25靠近有源层21的一端与第二电极区212接触，即第二电极25与第二电极区212直接耦接，此时第二电极25与第二电极区212之间形成了欧姆接触。
在此基础上，受第一离子掺杂浓度、第二离子掺杂浓度和第三离子掺杂浓度之间大小关系的影响，第一电极区211、第二电极区212和第三掺杂图案22还具有以下作用。
示例的，参考图2A，第一离子掺杂浓度等于或大致等于第二离子掺杂浓度，且第一离子掺杂浓度小于第三离子掺杂浓度。此时，第一电极区211和第二电极区212为LDD区域，用于降低漏电流和漏极电压Vd。
参考图2B，第一离子掺杂浓度等于或大致等于第二离子掺杂浓度，且第 一离子掺杂浓度大于第三离子掺杂浓度。此时，第三掺杂图案22为LDD区域，用于降低漏电流和漏极电压Vd。
参考图2C和图2D，当第二离子掺杂浓度使得第二电极区212成为HDD区域时，有源层21还可以包括第三掺杂区23′，该第三掺杂区23′位于第一电极区211和第二电极区212之间，且与第二电极区212紧挨，该第三掺杂区23′的离子掺杂浓度例如为第五掺杂浓度，该第五掺杂浓度可以使得该第三掺杂区23′成为LDD区域，用于降低漏电流和漏极电压Vd。
其中，参考图2C，第一离子掺杂浓度等于或大致等于第二离子掺杂浓度，第三离子掺杂浓度等于或大致等于第五掺杂浓度，且第一离子掺杂浓度大于第三离子掺杂浓度。此时，第三掺杂图案22和第三掺杂区23′为LDD区域，用于降低漏电流和漏极电压Vd。
参考图2D，第一离子掺杂浓度等于或大致等于第五掺杂浓度，第二离子掺杂浓度等于或大致等于第三离子掺杂浓度，且第一离子掺杂浓度小于第二离子掺杂浓度。此时，第一电极区211和第三掺杂区23′为LDD区域，用于降低漏电流和漏极电压Vd。
参考图2A～图2D，有源层21中位于第一电极区211和第二电极区212之间，且不属于第三掺杂区23′的部分为薄膜晶体管2的沟道区200，沟道区200的长度例如为L。
在显示装置1的像素密度较高的情况下，薄膜晶体管2的整体尺寸均较小，而沟道区200的长度也将随着薄膜晶体管2的尺寸的减小而减小，但是当沟道区200的长度减小到一定程度时，例如减小至2μm(微米)以下时，此时薄膜晶体管2的短沟道效应将变的十分明显。短沟道效应主要是指薄膜晶体管的阈值电压与沟道区200的长度相关到非常严重的程度，例如短沟道效应导致薄膜晶体管2的阈值电压随着沟道长度的减小而减小。漏致势垒降低(Drain Induced Barrier Lowering，DIBL)是短沟道效应的一种体现。在DIBL效应中，在沟道长度较小的情况下，薄膜晶体管2阈值电压随着漏极电压Vd的增大而减小，若针对同一薄膜晶体管2而言，当其漏极电压不同时，其阈值电压将不同，而阈值电压越小，薄膜晶体管2越容易被开启，从而致使显示装置1难以精确控制薄膜晶体管2的开启，致使薄膜晶体管2被误开启的概率更高，且当阈值电压减小后，薄膜晶体管2的漏电流也将增大。因此，短沟道效应使得薄膜晶体管2在不同的漏极电压下难以精确控制其开启，且存在较大的漏电流，整体性能较差。
参考图3A，相关技术中的薄膜晶体管2′包括有源层21′，有源层21′包括 源极区211′、漏极区212′和位于源极区211′和漏极区212′之间的两个第三掺杂区23′，其中，源极区211′和漏极区212′为HDD区域，两个第三掺杂区23′为LDD区域。源极24′与源极区211′之间形成了欧姆接触，漏极25′和漏极区212′之间形成了欧姆接触；两个第三掺杂区23′相当于电阻，用于降低薄膜晶体管2′的漏电流和漏极电压Vd的大小。虽然在该相关技术中，设置了两个第三掺杂区23′用于降低漏极电压Vd，以改善薄膜晶体管2′的整体性能，但是，两个第三掺杂区23′位于源极区211′和漏极区212′之间，使得沟道区200′的长度L 0较小，从而导致短沟道效应依然显著，薄膜晶体管2′的整体性能较差。
示例的，参考图3B，图中横坐标为相关技术中的薄膜晶体管2′的栅极电压，纵坐标为薄膜晶体管2′的漏极电流，从该图中，明显可以看出当栅极电压相同，例如均为1.5V，且设定源极电压等于0时，随着漏极电压Vd(Vd 1＜Vd 2＜Vd 3)的增大，漏极电流在增大，三条曲线并不能重合，三条曲线不能重合的原因是短沟道效应致使漏致势垒降低，从而引起了薄膜晶体管2′的阈值电压发生了漂移，且随着漏极电压Vd的增大，阈值电压在减小。因此，漏极电压Vd的对阈值电压的影响较大，而当薄膜晶体管2′的阈值电压越小时，薄膜晶体管2被误开启的概率则越大，所以薄膜晶体管2′的稳定性较差。
在有源层21长度相同的前提下，参考图2A～图2D，本公开实施例中的沟道区200的长度为L；参考图3A，相关技术中的沟道区200′的长度L 0，可以明显看出，本公开中的沟道区200的长度L大于相关技术中的沟道区200′的长度L 0。参考图2A，在第一电极区211和第二电极区212均为LDD区域时，相对于相关技术中图3A所示的第三掺杂区域23′的长度也更大，所以能够降低漏电流和漏极电压Vd的能力也更强。从而，本公开实施例中的薄膜晶体管2的整体性能优于相关技术中的薄膜晶体管2′的性能。
在本公开的实施例中，薄膜晶体管2包括第三掺杂图案22，第三掺杂图案22设置于第一电极24与第一电极区211之间，即第三掺杂图案22并不位于有源层21中。由于第三掺杂图案22位置的改变，一方面可以使得有源层21中沟道区200的长度设置的较大，改善短沟道效应。另一方面，第三掺杂图案22的体积也可以设置的较大，当第三掺杂图案22为LDD区域时，第三掺杂图案22的等效电阻较大，可以降低漏电流和漏极电压Vd的能力更强。又一方面，当第一电极区211和第二电极区212为LDD区域时，其长度相对相关技术中的第三掺杂图案23′的长度更大，能够降低漏电流和漏极电压Vd的能力更强。当第三掺杂图案22或者第一电极区211和第二电极区212能够降低漏极电压Vd的能力更强时，针对同一薄膜晶体管2，不同的漏极电压 Vd对应的阈值电压均较大，薄膜晶体管2不易被开启，从而被误开启的概率较低，减小了漏极电压Vd对其阈值电压的影响，还可以再进一步改善短沟道效应对薄膜晶体管2的影响，因此，本公开中薄膜晶体管2的整体性能较好。
在一些实施例中，参考图4A～图4D，薄膜晶体管2还包括：第四掺杂图案23，设置于第二电极25和第二电极区212之间，分别与第二电极25和第二电极区212直接接触。第四掺杂图案23具有为第四离子掺杂浓度，第四离子掺杂浓度与第二离子掺杂浓度不同。
第四掺杂图案23用于与第二电极25之间形成欧姆接触，以及当第四离子掺杂浓度小于第二离子掺杂浓度时，第四掺杂图案23用于降低薄膜晶体管2的漏电流大小和漏极电压Vd；当第四离子掺杂浓度大于第二离子掺杂浓度时，第四掺杂图案23起耦接作用。
示例的，参考图4A，第一离子掺杂浓度等于或大致等于第二离子掺杂浓度，第三离子掺杂浓度等于或大致等于第四离子掺杂浓度，且第一离子掺杂浓度大于第三离子掺杂浓度。此时，第三掺杂图案22和第四掺杂图案23为LDD区域，用于降低薄膜晶体管2的漏电流大小和漏极电压Vd。
参考图4B，第一离子掺杂浓度等于或大致等于第四离子掺杂浓度，第二离子掺杂浓度等于或大致等于第三离子掺杂浓度，且第一离子掺杂浓度大于第二离子掺杂浓度。此时，第三掺杂图案22和第二电极区212为LDD区域，用于降低薄膜晶体管2的漏电流大小和漏极电压Vd。
参考图4C，第一离子掺杂浓度等于或大致等于第四离子掺杂浓度，第二离子掺杂浓度等于或大致等于第三离子掺杂浓度，且第一离子掺杂浓度小于第三离子掺杂浓度。此时，第一电极区211和第四掺杂图案23为LDD区域，用于降低薄膜晶体管2的漏电流大小和漏极电压Vd。
参考图4D，第一离子掺杂浓度等于或大致等于第二离子掺杂浓度，第三离子掺杂浓度等于或大致等于第四离子掺杂浓度，且第一离子掺杂浓度小于第三离子掺杂浓度。此时，第一电极区211和第二电极区212为LDD区域，用于降低薄膜晶体管2的漏电流大小和漏极电压Vd。
当薄膜晶体管2还包括第四掺杂图案23时，第四掺杂图案23位于第一电极24和第一电极区211之间，从而使得有源层21中可以不再设置第三掺杂区23′，且第四掺杂图案23的长度可以设置的大于第三掺杂区23′的长度，因此第四掺杂图案23不仅可以进一步增大薄膜晶体管2的沟道区200的长度，改善短沟道效应，还可以在第四离子掺杂浓度小于第二离子掺杂浓度时，增大薄膜晶体管2中LDD区域的面积，进一步改善短沟道效应和降低漏极电压 Vd。
在一些实施例中，参考图2A～图2D，图4A～图4D，薄膜晶体管2还包括：沿有源层21的厚度方向层叠的栅绝缘层26和栅极28，且栅绝缘层26和栅极28设置于有源层21与第一电极24和第二电极25之间。
其中，栅绝缘层26位于有源层21和栅极28之间；栅绝缘层26上设置有第一通孔261，第一通孔261在有源层21上的正投影落在第一电极区211和第一电极24在有源层21上的正投影重叠的范围以内；第三掺杂图案22位于第一通孔261中。
由于栅极28位于有源层21之上，因此该薄膜晶体管2为顶栅型薄膜晶体管2。顶栅型薄膜晶体管2中的栅极28可以在对第一电极区211和第二电极区212进行离子掺杂的过程中起自对准的作用，避免在进行离子掺杂的过程使用掩膜板，从而降低生产成本。
示例的，以第一通孔261在有源层21上的正投影为圆形为例。参考图4E，第一电极24在有源层21上的正投影和第一电极区211重叠的部分的长度为S，第一通孔261在有源层21上的正投影的长度为圆形的直径，该直径小于S。
第三掺杂图案22位于第一通孔261中，其中参考图2A～图2D，图4A～图4D，第三掺杂图案22的厚度可以等于或大致等于第一通孔261的深度。参考图5A，第三掺杂图案22的厚度也可以小于第一通孔261的深度。参考图5B和图5C，第三掺杂图案22的厚度还可以大于第一通孔261的深度。
当第一通孔261在有源层21上的正投影落在第一电极区211和第一电极24在有源层21上的正投影重叠的范围以内时，一方面，第一通孔261可以垂直设置，设置较为简单；另一方面，当栅绝缘层26制备完成后，即可在栅绝缘层26上形成第一通孔261，然后制备第三掺杂图案22，其中对于第三掺杂图案22的制备厚度可根据薄膜晶体管2的实际性能需求进行设置。
在一些实施例中，参考图4A～图4D、图5A～图5C，在薄膜晶体管2还包括第四掺杂图案23的情况下，栅绝缘层26上还设置有第二通孔262，第二通孔262在有源层21上的正投影落在第二电极区212和第二电极25在有源层21上的正投影重叠的范围以内；第四掺杂图案23位于第二通孔262中。
第四掺杂图案23位于第二通孔262中，其中参考图4A～图4D，第四掺杂图案23的厚度等于或者大致等于第二通孔262的深度。参考图5A，第四掺杂图案23的厚度小于第二通孔262的深度。参考图5B和图5C，第四掺杂图案23的厚度大于第二通孔262的深度。
第四掺杂图案23的设置在第二通孔262中的有益效果与第三掺杂图案22 设置在第一通孔261中的有益效果相同，因此不再赘述。
在一些实施例中，参考图4A，图5A～图5C，第一离子掺杂浓度等于或者大致等于第二离子掺杂浓度；第三离子掺杂浓度等于或者大致等于第四离子掺杂浓度；且第一离子掺杂浓度大于第三离子掺杂浓度。
在该种结构中，第三掺杂图案22和第四掺杂图案23为LDD区域，第三掺杂图案22和第四掺杂图案23的等效电阻较大，能够最大程度降低漏极电压Vd以及漏电流。
在另一些实施例中，参考图6A～图6C，第一离子掺杂浓度小于第三离子掺杂浓度和/或第二离子掺杂浓度小于第四离子掺杂浓度时，第三掺杂图案22在有源层21上的正投影的边缘与第一电极区211远离第二电极区212一侧的边缘重合，和/或，第四掺杂图案23在有源层21上的正投影的边缘与第二电极区212远离第一电极区211一侧的边缘重合。其中，参考图6A，第一离子掺杂浓度等于或大致等于第四离子掺杂浓度，第二离子掺杂浓度等于或者大致等于第三离子掺杂浓度，且第一离子掺杂浓度大于第二离子掺杂浓度；此时，第四掺杂图案23远离第三掺杂图案22的一侧与第二电极区212远离第一电极区211的一侧对齐设置。
参考图6B，第一离子掺杂浓度等于或大致等于第四离子掺杂浓度，第二离子掺杂浓度等于或者大致等于第三离子掺杂浓度，且第一离子掺杂浓度小于第二离子掺杂浓度；此时，第三掺杂图案22远离第四掺杂图案23的一侧与第一电极区211远离第二电极区212的一侧对齐设置。
参考图6C，第一离子掺杂浓度等于或大致等于第二离子掺杂浓度，第三离子掺杂浓度等于或者大致等于第四离子掺杂浓度，且第一离子掺杂浓度小于第三离子掺杂浓度；此时，第三掺杂图案22远离第四掺杂图案23的一侧与第一电极区211远离第二电极区212的一侧对齐设置，第四掺杂图案23远离第三掺杂图案22的一侧与第二电极区212远离第一电极区211的一侧对齐设置。
由于第一电极区211和/或第二电极区212为LDD区域，当第三掺杂图案22远离第四掺杂图案23的一侧与第一电极区211远离第二电极区212的一侧对齐设置，和/或，第四掺杂图案23远离第三掺杂图案22的一侧与第二电极区212远离第一电极区211的一侧对齐设置时，第三掺杂图案22和第四掺杂图案23所传输的载流子经过了第一电极区211和第二电极区212的全部，通过第一电极区211和第二电极区212的面积较大，从而第一电极区211和第二电极区212的等效电阻较大，可以进一步降低漏极电压Vd。
本领域技术人员可以理解的是，参考图4D，在该种结构的薄膜晶体管2中，第三掺杂图案22所传输的载流子经过了第一电极区211中与第三掺杂图案22接触以及靠近第二电极区212一侧的部分，第四掺杂图案23所传输的载流子经过了第二电极区212中与第四掺杂图案23接触且靠近第一电极区211一侧的部分，即载流子并未经过全部的第一电极区211和第二电极区212，而第一电极区211和第二电极区212的等效电阻是根据载流子所经过的部分计算的。因此，在图4D和图6C中，第一电极区211和第二电极区212的等效电阻并不相同。
在一些实施例中，参考图4A和图5A，第三掺杂图案22的高度小于等于第一通孔261的深度，第四掺杂图案23的高度小于等于第二通孔262的深度。便于在形成栅绝缘层26后，在第一通孔261中制备第三掺杂图案22和在第二通孔262中制备第四掺杂图案23。
在一些实施例中，参考图4A～图4D、图5A～图5C、图6A～图6C和图7A～图7B，薄膜晶体管2还包括：层间绝缘层27，设置于栅极28远离有源层21的一侧，层间绝缘层27上设置有第三通孔271和第四通孔272，其中第三通孔271与第一通孔261连通，第四通孔272与第二通孔262连通。第三通孔271在有源层21上的正投影和第一通孔261在有源层21上的正投影落在第一电极区211的范围以内；第四通孔272在有源层21上的正投影和第二通孔262在有源层21上的正投影落在第二电极区212的范围以内。
示例的，参考图4A～图4D、图5A～图5C和图6A～图6C，第三通孔271和第一通孔261的尺寸相同或大致相同，第四通孔272和第二通孔262的尺寸相同或大致相同。在此基础上，在另一些实施例中，第一通孔261的尺寸和第二通孔262的尺寸相同或大致相同。在此基础上，例如，第一通孔261至第四通孔272的纵截面为矩形，且尺寸均相同或大致相同，此时便于同时制作第一通孔261和第三通孔271、第二通孔262和第四通孔272。
又示例的，参考图7A，第一通孔261的尺寸和第二通孔262的尺寸相同或大致相同，第三通孔271和第四通孔272的尺寸相同或大致相同。例如，第一通孔261至第四通孔272的纵截面均为倒梯形，且在纵截面图中，第一通孔261的顶边长度等于或大致等于第三通孔271的底边长度，第二通孔262的顶边长度等于或大致等于第四通孔272的底边长度。此时也便于同时制作第一通孔261和第三通孔271、第二通孔262和第四通孔272。
再示例的，参考图7B，第一通孔261的尺寸和第二通孔262的尺寸相同或大致相同，第三通孔271和第四通孔272的尺寸相同或大致相同。在此基 础上，第三通孔271的直径例如大于第一通孔261的直径，第四通孔272的直径例如大于第二通孔262的直径。当第一通孔261至第四通孔272的纵截面为矩形时，第一通孔261至第四通孔272中的任一个通孔的上端和下端的直径是相同的或大致相同的。而当第一通孔261至第四通孔272的纵截面为倒梯形时，第一通孔261至第四通孔272中的任一个通孔的上端和下端的直径是不相等的，其中，针对任一个通孔，其上端的直径大于其下端的直径，即存在最大直径和最小直径。此时第三通孔271的直径例如大于第一通孔261的直径可以理解为第三通孔271最小直径大于第一通孔261的最大直径；第四通孔272的直径例如大于第二通孔262的直径可以理解为第四通孔272的最小直径大于第二通孔的最大直径。
在此基础上，示例的，第一通孔261至第四通孔272的纵截面均为倒梯形，且在纵截面图中，第一通孔261的顶边长度(对应第一通孔261的最大直径)小于第三通孔271的底边长度(对应第三通孔271的最小直径)，第二通孔262的顶边长度(对应第二通孔262的最大直径)小于第四通孔272的底边长度(对应第四通孔272的最小直径)。该种结构可以保证第一电极24靠近有源层21的一侧与第三掺杂图案22远离有源层21的一侧的接触面积、第二电极25靠近有源层21的一侧与第四掺杂图案23远离有源层21的一侧的接触面积较大，从而保证第一电极24和第三掺杂图案22之间、第二电极25和第四掺杂图案23之间的耦接稳定性更好。
在一些实施例中，参考图5C，第三掺杂图案22还位于第三通孔271中，第四掺杂图案23还位于第四通孔272中。一方面，该种结构的薄膜晶体管2在制备的过程中，可以在层间绝缘层27制备完成后，再制备第一通孔261至第四通孔272，且当第一通孔261和第三通孔271同时制备，第二通孔262和第四通孔272同时制备时，可以节省打孔工序。另一方面，第三掺杂图案22和第四掺杂图案23的厚度可以设置的较大，尤其在第三掺杂图案22和第四掺杂图案23为LDD区域时，可以进一步增大第三掺杂图案22和第四掺杂图案23的等效电阻，从而进一步降低漏极电压Vd，降低短沟道效应。
在一些实施例中，第三掺杂图案22的厚度等于或大致等于第四掺杂图案23的厚度。一方面，可以便于后续同时在第三掺杂图案22的上侧制备第一电极24，在第四掺杂图案23的上侧制备第二电极25；另一方面，在第三掺杂图案22厚度等于或大于第一通孔261的深度，第四掺杂图案23的厚度等于或大于第二通孔262的深度时，第三掺杂图案22的厚度等于或大致等于第四掺杂图案23的厚度时，便于后续制作位于第三掺杂图案22和第四掺杂图案 23上的其它膜层(比如层间绝缘层27、第一电极24和第二电极25)。
本公开的实施例中的薄膜晶体管2可以为N型晶体管，也可以为P型晶体管。在本公开的实施例中，以N型晶体管为例进行说明。
在此基础上，在一些实施例中，第三掺杂图案22和第四掺杂图案23的材料例如包括N+离子的半导体材料，例如N+a-si。第一电极区211和第二电极区212的掺杂离子例如也为N+离子。进一步的，N+离子例如为P(磷)离子，第一离子掺杂浓度和第二离子掺杂浓度对应的掺杂剂量例如为5×10 14/cm 2～1×10 15/cm 2，第三离子掺杂浓度和第四离子掺杂浓度对应的掺杂剂量例如为5×10 13cm 2～1×10 14cm 2。
本领域技术人员可以理解的是，虽然掺杂剂量和掺杂浓度的计算方式不同，但掺杂剂量和掺杂浓度之间存在对应关系，掺杂剂量越大则掺杂浓度也越高，因此可以用掺杂剂量之间的关系来衡量掺杂浓度之间的关系。
结合图2C、图2D、图4A、图4C、图5A～图5C，由于第三掺杂区23′和第四掺杂图案23均可以做LDD区域，因此本领域技术人员可以理解，第三掺杂区23′和第四掺杂图案23不能并存于薄膜晶体管2中，且第五掺杂浓度可以等于或者大致等于第四离子掺杂浓度。
参考图8，本公开的实施例还提供一种薄膜晶体管2的制备方法，包括：
S1、参考图2A～图2D，形成有源层21。
其中，有源层21具有沟道区200和位于沟道区200相对两侧的第一电极区211和第二电极区212，第一电极区211和第二电极区212为离子掺杂区域，第一电极区211具有第一离子掺杂浓度，第二电极区212具有第二离子掺杂浓度。有源层21的材料为多晶硅。
参考图2C和图2D，有源层21还可以包括第三掺杂区23′，第三掺杂区23′的离子掺杂浓度为第五掺杂浓度，第五掺杂浓度与第二离子掺杂浓度不同，第三掺杂区23′用于形成LDD区域。
S2、在有源层21的一侧形成第三掺杂图案22，第三掺杂图案22具有第三离子掺杂浓度，第三离子掺杂浓度与第一离子掺杂浓度不同。
S3、在第三掺杂图案22远离有源层21的一侧形成第一电极24，在有源层21上形成第二电极25，第一电极24和第二电极25同层同材料，第一电极24通过第三掺杂图案22与第一电极区211耦接，第二电极25与第二电极区212耦接。
在一些实施例中，参考图4A～图4D，在有源层21上形成第三掺杂图案22的同时，还形成第四掺杂图案23，第四掺杂图案23与第二电极区212耦 接，第四掺杂图案23具有第四离子掺杂浓度，第四离子掺杂浓度与第二离子掺杂浓度不同。
在有源层21上形成第二电极25进一步包括：在第四掺杂图案23远离有源层21的一侧形成第二电极25；其中，第四掺杂图案23与第二电极25耦接。
第一电极24和第二电极25同层同材料，第一电极24和第二电极25的材料例如为银(Ag)、铝(Al)、钛(Ti)等导电金属中的至少一种。
在一些实施例中，参考图9A，形成有源层21包括：
S10、参考图9B，形成多晶硅薄膜，通过图案化工艺形成半导体图案。
多晶硅薄膜的厚度例如为
Figure PCTCN2021100143-appb-000001
S11、参考图9B，在半导体图案210的一侧形成栅绝缘层26。
栅绝缘层26的厚度例如为
Figure PCTCN2021100143-appb-000002
栅绝缘层26可以为单层结构，该单层结构的材料例如为氧化硅(SiO)；也可以为沿薄膜晶体管2的厚度方向层叠的叠层结构，例如为双层的叠层结构，其中靠近半导体图案210一侧的一层结构的材料例如为氧化硅，另一层结构的材料例如为氮化硅(SiN)。
S12、参考图9B，在栅绝缘层26远离半导体图案210的一侧形成栅极28。
栅极28的材料例如为钼(Mo)，厚度例如为200nm～350nm。
S13、参考图9C，对半导体图案210中待形成第一电极区和第二电极区的部分进行离子掺杂，以形成有源层21。
由于已在栅绝缘层26上形成了栅极28，因此在对半导体图案210做离子掺杂时，栅极可起到自对准的作用，从而在进行离子掺杂时无需使用掩膜板，即可使掺杂离子2100进入半导体图案210中待形成第一电极区和第二电极区的部分，最终形成第一电极区211和第二电极区212。
在一些实施例中，第一离子掺杂浓度和第二离子掺杂浓度相等或者大致相等。
示例的，在向半导体图案210中待形成第一电极区和第二电极区的部分进行P(磷)离子重掺杂时，每侧的掺杂剂量例如为51×10 14/cm 2～1×10 15/cm 2，以使得第一离子掺杂浓度和第二离子掺杂浓度较大，使得第一电极区211和第二电极区212成为HDD区域。
在一些实施例中，形成多晶硅薄膜例如包括：
沉积非晶硅薄膜，通过激光照射以使非晶硅薄膜中的非晶硅(a-si)转化为多晶硅以形成多晶硅薄膜，或者直接沉积多晶硅以形成多晶硅薄膜。
示例的，可通过准分子激光退火设备进行激光退火以使得非晶硅薄膜中 的非晶硅转换为多晶硅，以形成多晶硅薄膜。
本领域技术人员可以理解的是，薄膜晶体管2在制备的过程中是需要衬底作为制作各膜层的承载的，因此上述的多晶硅薄膜是需要制作在衬底上的。
在另一些实施例中，为了避免衬底中的H(氢)离子对有源层21的影响，在制作多晶硅薄膜之前，在衬底上还可以制作一层缓冲层。沿衬底厚度方向，缓冲层例如为氮化硅层和氧化硅层的层叠结构，其中，氮化硅层的厚度例如为
Figure PCTCN2021100143-appb-000003
氧化硅层的厚度例如为
Figure PCTCN2021100143-appb-000004
且相对于氧化硅层，氮化硅层更靠近衬底。
在此基础上，参考图10A，在有源层21的一侧形成第三掺杂图案22进一步包括：
S20、参考图10B和图10C，在栅绝缘层26上形成第一通孔261，第一通孔261在有源层21上的正投影落在第一电极区211的范围以内。
第一通孔261贯穿了栅绝缘层26，第一通孔261的纵截面例如为倒梯形。
S21、结合图10D和图7A，在栅绝缘层26和栅极28远离有源层21的一侧形成掺杂薄膜220，通过图案化掺杂薄膜220，在第一通孔261中形成第三掺杂图案22。
示例的，第三掺杂图案22的第三离子掺杂浓度小于第一电极区211的掺杂浓度，则第三掺杂图案22为LDD区域。
在此基础上，在另一些实施例中，参考图10B和图10C，在栅绝缘层26上形成第一通孔261的同时，还形成第二通孔262，第二通孔262在有源层21上的正投影落在第二电极区212的范围以内。
第二通孔262的尺寸例如和第一通孔261的尺寸相同或大致相同。
结合图10D和图7A，在栅绝缘层26和栅极28远离有源层21的一侧形成掺杂薄膜220，图案化掺杂薄膜220，以在第一通孔261中形成第三掺杂图案22的同时，还在第二通孔262中形成第四掺杂图案23。
在另一些实施例中，参考图11A，在有源层21的一侧形成第三掺杂图案22还可以包括：
S20′、参考图11B，在栅绝缘层26和栅极28远离有源层21的一侧形成层间绝缘层27。
层间绝缘层27的厚度例如为500nm。
层间绝缘层27可以为单层结构，该单层结构的材料例如为氧化硅(SiO)；也可以为层叠结构，例如为双层的层叠结构，其中靠近栅绝缘层26一侧的一层结构的材料例如为氧化硅，厚度例如为200nm；另一层结构的材料例如为 氮化硅，厚度例如为300nm。
S21′、参考图11C，在层间绝缘层27和栅绝缘层26上形成连通的第三通孔271和第一通孔261。
其中，第三通孔271位于层间绝缘层27上，第一通孔261位于栅绝缘层26上，第三通孔271在有源层21上的正投影和第一通孔261在有源层21上的正投影落在第一电极区211的范围以内。
示例的，第一通孔261和第三通孔271的纵截面均为倒梯形。
S22′、结合图11D和图7A，在层间绝缘层27远离有源层21的一侧形成掺杂薄膜220，图案化掺杂薄膜220，以在第三通孔271和第一通孔261中形成第三掺杂图案22。
在一些实施例中，参考图11C，在层间绝缘层27和栅绝缘层26上形成连通的第三通孔271和第一通孔261的同时，还在层间绝缘层27和栅绝缘层26上形成连通的第四通孔272和第二通孔262。其中，第四通孔272位于层间绝缘层27上，第二通孔262位于栅绝缘层26上，第四通孔272在有源层21上的正投影和第二通孔262在有源层21上的正投影落在第二电极区212的范围以内。
结合图11D和图11E，在层间绝缘层27远离有源层21的一侧形成掺杂薄膜220，图案化掺杂薄膜220，以在第三通孔271和第一通孔261中形成第三掺杂图案22的同时，还在第四通孔272和第二通孔262中形成第四掺杂图案23。
示例的，第三掺杂图案22的厚度和第四掺杂图案23厚度相同或大致相同，且小于第一通孔和第三通孔的深度之和，以便于后续在第三通孔217的剩余部分中形成第一电极24的部分，在第四通孔212的剩余部分中形成第二电极25的部分，从而以增加第一电极24与第三掺杂图案22之间、第二电极25与第四掺杂图案23的耦接稳定性。
在上述的实施例中，掺杂薄膜220的材料例如为N+a-si。
在一些实施例中，形成材料为N+a-si的掺杂薄膜220包括：
沉积N+a-si粒子以形成掺杂薄膜220。
或者，先形成非晶硅薄膜，再对非晶硅薄膜进行N+离子掺杂，以形成掺杂薄膜220。
在对非晶硅薄膜进行N+离子掺杂时，例如可通过向非晶硅薄膜中掺杂PH 3(磷烷)来实现掺杂N+离子的目的。掺杂时，PH 3的掺杂剂量例如为5×10 13/cm 2～1×10 14/cm 2，从而可以得到轻掺杂的第三掺杂图案22和第四掺杂 图案23。
在一些实施例中，参考图7A，在层间绝缘层27上沉积金属薄膜，图案化该金属薄膜，以形成第一电极24和第二电极25，其中，第一电极24与第三掺杂图案22耦接，第二电极25与第四掺杂图案23耦接。
金属薄膜例如为层叠结构，例如为Ti/Al/Ti的三层层叠结构，铝层位于中间，厚度例如为650nm；每层Ti层的厚度例如为50nm。
上述薄膜晶体管2的制备方法具有和上述的薄膜晶体管2相同的有益效果，因此不再赘述。
参考图12A，当显示装置1为OLED显示装置时，在衬底3上形成缓冲层29和薄膜晶体管2中之后，还可以第一电极24和第二电极25远离有源层21的一侧形成平坦层213、阳极214、像素界定层215、发光功能层216和封装层217等膜层。
其中，阳极214的材料例如为氧化铟锡(Indium tin oxide，ITO)，阳极214例如与薄膜晶体管2的第二电极25耦接。
平坦层213的材料为有机材料，例如聚酰亚胺(Polyimide，PI)。
像素界定层215的材料为有机材料，例如为感光型的聚酰亚胺。
参考图12B，发光功能层216用于形成像素驱动电路122中的发光器件D。发光功能层216除包括发光层2161外，还可以包括电子传输层(Election Transporting Layer，ETL)2162、电子注入层(Election Injection Layer，EIL)2163、空穴传输层(Hole Transporting Layer，HTL)2164以及空穴注入层(Hole Injection Layer，HIL)2165。需要说明的是，发光功能层216并不限于仅包括发光层2161和ETL2162、EIL2163、HTL2164、HIL2165的组合，其还可以包括其它功能层别。
封装层217包括沿薄膜晶体管2的厚度方向层叠的第一无机封装子层2171、有机封装子层2173和第二无机封装子层2172。
第一无机封装子层2171和第二无机封装子层2172的材料例如为氮化硅、氧化硅中的至少一种。形成第一无机封装子层2171和第二无机封装子层2172例如可采用磁控溅射的方式。形成有机封装子层2173例如可以通过喷墨打印(Ink jet printing，IJP)的方式。
上述的OLED显示装置具有与上述的薄膜晶体管2相同的有益效果，因此不再赘述。
本领域技术人员可以理解的是，本公开中的大致等于、大致相同、大致相等所表达的意思是相同的，即虽然两个数值虽然实际上并不相等，但该两 个数值之间的差异是在误差允许范围内，从而可以忽略因其差异所带来的影响。例如，第一离子掺杂浓度大致等于第二离子掺杂浓度，即第一离子掺杂浓度和第二离子掺杂浓度虽然并不相同，但该第一离子掺杂浓度和第二离子掺杂浓度之间的差异是在误差允许的范围内的，且该差异并不会影响第一电极区211和第二电极区212的特性。误差允许范围可以根据实际产品的特性进行确定，例如±0.1％、±1％等，本公开对此不做限定。
需要说明的是，在本公开的实施例中，第一离子掺杂浓度至第五掺杂浓度均指的是各个掺杂浓度的平均值，该平均值为算术平均值；例如第三离子掺杂浓度为第三掺杂图案22中离子掺杂的平均浓度，而实际在第三掺杂图案22中，各个位置的离子掺杂浓度可能具有一定差异，例如由于第三掺杂图案22同时需要和第一电极24之间形成欧姆接触，因此第三掺杂图案22中与第一电极24接触的部分的离子掺杂浓度可以设置的较大，以实现欧姆接触，剩余区域的离子掺杂浓度可以设置的较小，以实现降低薄膜晶体管的漏极电压Vd和漏电流的作用。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (19)

  1. 一种薄膜晶体管，包括：
    有源层，所述有源层的材料为多晶硅，所述有源层具有沟道区和位于所述沟道区相对两侧的第一电极区和第二电极区，其中，所述第一电极区和所述第二电极区为离子掺杂区域，所述第一电极区具有第一离子掺杂浓度，所述第二电极区具有第二离子掺杂浓度；
    第一电极和第二电极，设置于所述有源层厚度方向上的一侧且同层同材料，所述第一电极与所述第一电极区耦接、所述第二电极与所述第二电极区耦接；
    第三掺杂图案；设置于所述第一电极和所述第一电极区之间，分别与所述第一电极和所述第一电极区直接接触，其中，所述第三掺杂图案具有第三离子掺杂浓度，所述第三离子掺杂浓度与所述第一离子掺杂浓度不同。
  2. 根据权利要求1所述的薄膜晶体管，还包括：第四掺杂图案，设置于所述第二电极和所述第二电极区之间，分别与所述第二电极和所述第二电极区直接接触；所述第四掺杂图案具有第四离子掺杂浓度，所述第四离子掺杂浓度与所述第二离子掺杂浓度不同。
  3. 根据权利要求1或2所述的薄膜晶体管，还包括：沿所述有源层的厚度方向层叠的栅绝缘层和栅极，且所述栅绝缘层和所述栅极设置于所述有源层与所述第一电极和所述第二电极之间；
    其中，所述栅绝缘层位于所述有源层和所述栅极之间；所述栅绝缘层上设置有第一通孔，所述第一通孔在所述有源层上的正投影落在所述第一电极区和所述第一电极在所述有源层上的正投影重叠的范围以内；
    所述第三掺杂图案位于所述第一通孔中。
  4. 根据权利要求3所述的薄膜晶体管，其中，在所述薄膜晶体管还包括第四掺杂图案的情况下，所述栅绝缘层上还设置有第二通孔，所述第二通孔在所述有源层上的正投影落在所述第二电极区和所述第二电极在所述有源层上的正投影重叠的范围以内；
    所述第四掺杂图案位于所述第二通孔中。
  5. 根据权利要求4所述的薄膜晶体管，其中，所述第一离子掺杂浓度等于或者大致等于所述第二离子掺杂浓度；所述第三离子掺杂浓度等于或者大致等于所述第四离子掺杂浓度；且所述第一离子掺杂浓度大于所述第三离子掺杂浓度。
  6. 根据权利要求4或5所述的薄膜晶体管，其中，所述第三掺杂图案的 高度小于等于所述第一通孔的深度，所述第四掺杂图案的高度小于等于所述第二通孔的深度。
  7. 根据权利要求4或5所述的薄膜晶体管，还包括：层间绝缘层，设置于所述栅极远离所述有源层的一侧，所述层间绝缘层上设置有第三通孔和第四通孔，其中所述第三通孔与所述第一通孔连通，所述第四通孔与所述第二通孔连通；所述第三通孔在所述有源层上的正投影和所述第一通孔在所述有源层上的正投影落在所述第一电极区的范围以内；所述第四通孔在所述有源层上的正投影和所述第二通孔在所述有源层上的正投影落在所述第二电极区的范围以内。
  8. 根据权利要求7所述的薄膜晶体管，其中，所述第三通孔的直径大于所述第一通孔的直径，所述第四通孔的直径大于所述第二通孔的直径。
  9. 根据权利要求7或8所述的薄膜晶体管，其中，所述第三掺杂图案还位于所述第三通孔中，所述第四掺杂图案还位于所述第四通孔中。
  10. 根据权利要求6或9所述的薄膜晶体管，其中，所述第三掺杂图案的厚度等于或大致等于所述第四掺杂图案的厚度。
  11. 根据权利要求2所述的薄膜晶体管，其中，所述第三掺杂图案和所述第四掺杂图案的材料为包括N+离子的半导体材料。
  12. 一种显示装置，包括如权利要求1～11任一项所述的薄膜晶体管。
  13. 一种薄膜晶体管的制备方法，包括：
    形成有源层；其中，所述有源层的材料为多晶硅，所述有源层具有沟道区和位于所述沟道区相对两侧的第一电极区和第二电极区，所述第一电极区和所述第二电极区为离子掺杂区域，所述第一电极区具有第一离子掺杂浓度，所述第二电极区具有第二离子掺杂浓度；
    在所述有源层的一侧形成第三掺杂图案，所述第三掺杂图案具有第三离子掺杂浓度，所述第三离子掺杂浓度与所述第一离子掺杂浓度不同；
    在所述第三掺杂图案远离所述有源层的一侧形成第一电极，在所述有源层上形成第二电极；所述第一电极和所述第二电极同层同材料，所述第一电极通过所述第三掺杂图案与所述第一电极区耦接，所述第二电极与所述第二电极区耦接。
  14. 根据权利要求13所述的薄膜晶体管的制备方法，其中，在所述有源层上形成第三掺杂图案的同时，还形成第四掺杂图案，所述第四掺杂图案与所述第二电极区耦接，所述第四掺杂图案具有第四离子掺杂浓度，所述第四离子掺杂浓度与所述第二离子掺杂浓度不同；
    在所述有源层上形成所述第二电极进一步包括：在所述第四掺杂图案远离所述有源层的一侧形成所述第二电极；其中，所述第四掺杂图案与所述第二电极耦接。
  15. 根据权利要求13或14所述的薄膜晶体管的制备方法，其中，形成有源层进一步包括：
    形成多晶硅薄膜，通过图案化工艺形成半导体图案；
    在所述半导体图案的一侧形成栅绝缘层；
    在所述栅绝缘层远离半导体图案的一侧形成栅极；
    对所述半导体图案中待形成第一电极区和第二电极区的部分进行离子掺杂，以形成所述有源层。
  16. 根据权利要求15所述的薄膜晶体管的制备方法，其中，
    在所述有源层的一侧形成第三掺杂图案进一步包括：
    在所述栅绝缘层上形成第一通孔，所述第一通孔在所述有源层上的正投影落在所述第一电极区的范围以内；
    在所述栅绝缘层和所述栅极远离所述有源层的一侧形成掺杂薄膜，通过图案化所述掺杂薄膜，在所述第一通孔中形成第三掺杂图案。
  17. 根据权利要求16所述的薄膜晶体管的制备方法，其中，在所述栅绝缘层上形成第一通孔的同时，还形成第二通孔，所述第二通孔在所述有源层上的正投影落在所述第二电极区的范围以内；
    在所述栅绝缘层和所述栅极远离所述有源层的一侧形成所述掺杂薄膜，图案化所述掺杂薄膜，以在所述第一通孔中形成所述第三掺杂图案的同时，还在所述第二通孔中形成第四掺杂图案。
  18. 根据权利要求15所述的薄膜晶体管的制备方法，其中，
    在所述有源层的一侧形成第三掺杂图案进一步包括：
    在所述栅绝缘层和所述栅极远离所述有源层的一侧形成层间绝缘层；
    在所述层间绝缘层和所述栅绝缘层上形成连通的第三通孔和第一通孔；其中，所述第三通孔位于所述层间绝缘层上，所述第一通孔位于所述栅绝缘层上，所述第三通孔在所述有源层上的正投影和所述第一通孔在所述有源层上的正投影落在所述第一电极区的范围以内；
    在所述层间绝缘层远离所述有源层的一侧形成掺杂薄膜，图案化所述掺杂薄膜，以在所述第三通孔和所述第一通孔中形成第三掺杂图案。
  19. 根据权利要求18所述的薄膜晶体管的制备方法，其中，
    在所述层间绝缘层和所述栅绝缘层上形成连通的所述第三通孔和所述第 一通孔的同时，还在所述层间绝缘层和所述栅绝缘层上形成连通的第四通孔和第二通孔；其中，所述第四通孔位于所述层间绝缘层上，所述第二通孔位于所述栅绝缘层上，所述第四通孔在所述有源层上的正投影和所述第二通孔在所述有源层上的正投影落在所述第二电极区的范围以内；
    在所述层间绝缘层远离所述有源层的一侧形成所述掺杂薄膜，图案化所述掺杂薄膜，以在所述第三通孔和所述第一通孔中形成所述第三掺杂图案的同时，还在所述第四通孔和所述第二通孔中形成第四掺杂图案。
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