WO2022012225A1 - 改善沟槽表面结构缺陷的方法及半导体结构的制备方法 - Google Patents

改善沟槽表面结构缺陷的方法及半导体结构的制备方法 Download PDF

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WO2022012225A1
WO2022012225A1 PCT/CN2021/098948 CN2021098948W WO2022012225A1 WO 2022012225 A1 WO2022012225 A1 WO 2022012225A1 CN 2021098948 W CN2021098948 W CN 2021098948W WO 2022012225 A1 WO2022012225 A1 WO 2022012225A1
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flushing
cleaning solution
substrate
semiconductor structure
water
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PCT/CN2021/098948
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English (en)
French (fr)
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陈涛
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长鑫存储技术有限公司
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Priority to US17/599,459 priority Critical patent/US20230055868A1/en
Publication of WO2022012225A1 publication Critical patent/WO2022012225A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02082—Cleaning product to be cleaned
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment

Definitions

  • the present disclosure relates to the technical field of semiconductor fabrication processes, and in particular, to a method for improving surface structural defects of trenches and a method for fabricating a semiconductor structure.
  • a main purpose of the present disclosure is to overcome at least one of the above-mentioned defects of the prior art, and to provide a method that can effectively improve the granular defects of the trench surface structure.
  • the grooves of the substrate are rinsed with a cleaning solution, the cleaning solution being water.
  • the cleaning solution is water at 50°C to 70°C.
  • the cleaning solution is water at 60°C.
  • the cleaning solution is deionized water.
  • the cleaning solution when the substrate is rinsed, the cleaning solution is used for multiple rinses.
  • the method for improving the surface structure defects of the grooves proposed by the present disclosure is to use water as a cleaning solution to rinse the grooves of the substrate after forming the grooves on the substrate.
  • the present disclosure can effectively improve the granular defects of the surface structure of trenches such as word line structures.
  • Another main purpose of the present disclosure is to overcome at least one of the above-mentioned defects of the prior art, and to provide a method for fabricating a semiconductor structure using the above-mentioned method for improving the defects of the trench surface structure.
  • a method for preparing a semiconductor structure is provided; wherein, the following steps are included:
  • the substrate is ashed.
  • the cleaning solution is water at 50°C to 70°C.
  • the cleaning solution is water at 60°C.
  • the cleaning solution is deionized water.
  • the cleaning solution when the substrate is rinsed, the cleaning solution is used for multiple rinses.
  • the method for preparing the semiconductor structure proposed in the present disclosure can optimize the etching effect of tungsten on the word line structure by adopting the above-mentioned method for improving the defects of the trench surface structure, and significantly improve the poor crossing of the word line.
  • FIG. 1 is a top view of an array in a first step of a method for fabricating a semiconductor structure proposed by the present disclosure
  • Fig. 2 is the sectional view made along line A-A in Fig. 1;
  • FIG. 3 is a cross-sectional view in another step of the method for fabricating the semiconductor structure proposed by the present disclosure
  • FIG. 5 is a top view of the array in another step of the method for fabricating the semiconductor structure proposed by the present disclosure
  • Figure 6 is a sectional view taken along line D-D in Figure 5;
  • FIG. 7 is a top view of an array in a first step of a method for preparing a conventional semiconductor structure
  • FIG. 8 is a cross-sectional view taken along line E-E in FIG. 7 .
  • trench isolation region
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments can be embodied in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.
  • FIG. 1 to FIG. 3 the schematic diagrams of the structure of the semiconductor structure in the main steps of the method for improving the defects of the trench surface structure proposed by the present disclosure are representatively shown.
  • the method for improving the surface structure defect of the trench proposed by the present disclosure is exemplified by being applied to a dynamic random access memory (DRAM).
  • DRAM dynamic random access memory
  • FIG. 1 specifically shows the top view of the array when the trenches 120 are formed on the substrate 110;
  • FIG. 2 specifically shows the cross-sectional view taken along the line AA in FIG.
  • the cross-sectional structure when the oxide particles 130 are adhered on the trench 120 is shown; another cross-sectional view taken along the line AA in FIG. 1 is specifically shown in FIG.
  • the method for improving the surface structure defect of the trench 120 is a cross-sectional structure after the oxide particles 130 adhering to the trench 120 are removed.
  • the method for improving the surface structural defects of the trench 120 proposed by the present disclosure includes the following steps:
  • the grooves 120 of the substrate 110 are rinsed with a cleaning solution, and the cleaning solution is water.
  • the method for improving the surface structure defects of the trenches 120 proposed in the present disclosure uses water as a cleaning solution to rinse the trenches 120 of the substrate 110 , thereby effectively improving the surface structure of the trenches 120 of the word line structure 140 , for example. granular defects, so that the etching of tungsten on the word line structure 140 in the subsequent process can be optimized. Furthermore, it has no influence on the structure of the word line structure 140 itself. Compared with the existing semiconductor preparation methods, it does not have the step of rinsing the trenches of the substrate after etching, thus causing the problem of residual by-products such as oxide particles, and forming large particles after tungsten deposition shape defect. The phenomenon of insufficient word line tungsten etching caused by the etching of the blocking channel causes poor coupling between the bit line and the short circuit of the word line, thereby causing poor crossover in the final reliability test.
  • the cleaning liquid may preferably be water at 50°C to 70°C, such as 50°C, 55°C, 62°C, 70°C, and the like. Accordingly, since hot water has better solubility, by-products such as oxide particles 130 can be removed better. At the same time, different from the acid-base rinsing liquid used in other types of semiconductor fabrication processes, if such rinsing liquid is applied to the cleaning steps involved in the present disclosure, this liquid will corrode the word line structure and cause damage to the word line structure. Due to the difference in electrical properties, the present disclosure can effectively avoid the above problems by using hot water as the cleaning solution. In other embodiments, the cleaning solution can also select water of other temperature, that is, it may be lower than 50°C, or may be higher than 70°C, such as 48°C, 75°C, etc., which is not limited to this embodiment.
  • the cleaning solution may preferably be water at 60°C.
  • the cleaning liquid may preferably be deionized water.
  • the cleaning solution may be further preferably deionized water at 60°C.
  • a process of rinsing the substrate 110 with a rinsing liquid for multiple times may preferably be used.
  • the duration and flow rate of each rinsing can be the same, so that each rinsing can achieve the same rinsing effect, and repeated rinsing is more efficient. until the oxide particles 130 on the trenches 120 are completely removed or a predetermined removal effect is achieved.
  • the duration of each flushing may not be exactly the same, and the flow rate of each flushing may not be exactly the same.
  • multiple flushings may be performed in an equidistant sequence, or multiple flushings may be performed in other manners. Flushing can be flexibly selected and adjusted according to different process requirements against multiple flushing methods, and is not limited to this embodiment.
  • the rinsing time when multiple rinsing is performed in an equidistant sequence, can be designed to decrease successively until the oxide particles 130 are completely removed or a predetermined removal effect is achieved.
  • the flow rate of flushing can also be designed to gradually decrease.
  • the decreasing trend of flushing time and the decreasing trend of flushing flow may preferably be the same.
  • the flushing time when multiple flushing is performed by means of an iso-difference sequence, the flushing time can also be designed to increase successively, and the flushing flow rate can be the same as the flushing time.
  • the flushing time is designed to increase one by one and the other to decrease successively, which is not limited to this embodiment.
  • the time and flow of each flush can be designed according to the process needs. For example, assuming that multiple flushes supply and demand flushing X (X ⁇ 3) times, the first Y (1 ⁇ 3) times before the flushing can be started. Y ⁇ X) times and the last Z (1 ⁇ Z ⁇ X, and Y+Z ⁇ X) times after finishing the flushing time, it is designed to be less than the flushing time of the other times.
  • the flushing time of the second flush is designed to be greater than the flushing time of the other flushes, and the flushing flow rate can also adopt the above design ideas, which will not be repeated here.
  • the flushing flow rate in the sequence with the shorter flushing time may also be greater than or equal to the flushing in the sequence with the longer flushing time.
  • the flow rate is not limited to this embodiment.
  • the method for improving the surface structure defects of the trenches 120 proposed by the present disclosure is to use water as a cleaning solution to rinse the trenches 120 of the substrate 110 after the trenches 120 are formed on the substrate 110 .
  • the present disclosure can effectively improve granular defects such as the surface structure of the trench 120 of the word line structure 140 .
  • FIG. 1 to FIG. 6 which typically show the schematic structural diagrams of the semiconductor structure in the main steps of the method for fabricating the semiconductor structure proposed by the present disclosure.
  • the method for fabricating the semiconductor structure proposed in the present disclosure is described by taking the application to a dynamic random access memory (DRAM) as an example.
  • DRAM dynamic random access memory
  • FIG. 4 specifically shows a cross-sectional view of the cleaned semiconductor structure after ashing treatment (ASH) and deposition of silicon dioxide gate (DEP gate OX);
  • FIG. 5 specifically shows Figure 6 is a cross-sectional view taken along the line DD in Figure 5 .
  • the method for fabricating the semiconductor structure proposed by the present disclosure includes the following steps:
  • the substrate 110 is subjected to an ashing process, a silicon dioxide layer gate electrode, a tungsten deposition etching process, and the like.
  • the method for fabricating the semiconductor structure proposed in the present disclosure can optimize the etching effect of tungsten (W) on the word line structure 140 and significantly improve word line cross fail.
  • W tungsten
  • the present disclosure uses water, especially hot water at 50° C. to 70° C., as a cleaning solution to wash the substrate 110 and then perform ashing treatment, which can prevent other by-products from being oxidized to form unnecessary impurity products and Silicon damage, etc.
  • the substrate 110 may preferably include a substrate and a mask layer 113 .
  • the substrate may be a silicon substrate, a germanium substrate, or a silicon germanium substrate.
  • the trench isolation region 112 divides the substrate into an active region 111, and the trench isolation region is filled with silicon dioxide (SiO 2 ).
  • the mask layer 113 is formed on the trench isolation region 112, for example, silicon nitride (SiN), and the above-mentioned silicon dioxide and silicon nitride can be collectively regarded as a mask layer.
  • a photomask layer 114 is formed on the mask layer 113 . On this basis, the above-mentioned ashing process on the substrate 100 is used to remove the photomask layer.
  • the cleaning liquid may preferably be water at 50°C to 70°C, such as 50°C, 55°C, 62°C, 70°C, and the like.
  • the cleaning solution can also select water of other temperature, that is, it may be lower than 50°C, or may be higher than 70°C, such as 48°C, 75°C, etc., which is not limited to this embodiment.
  • the cleaning solution may preferably be water at 60°C.
  • the cleaning liquid may preferably be deionized water.
  • the cleaning solution may be further preferably deionized water at 60°C.
  • a process of rinsing the substrate 110 with a rinsing liquid for multiple times may preferably be used.
  • the duration and flow rate of each rinsing can be the same, so that each rinsing can achieve the same rinsing effect, and repeated rinsing is more efficient. until the oxide particles 130 on the trenches 120 are completely removed or a predetermined removal effect is achieved.
  • FIG. 7 specifically shows a top view of the array after the semiconductor structure is etched by tungsten in an existing method for preparing a semiconductor structure; Sectional view of line EE.
  • the existing semiconductor structure is limited by the traditional preparation method and the traditional cleaning method, which will lead to the obvious phenomenon of insufficient word line tungsten etching, that is, the word line structure 210 in the trench of the substrate has etching residues Section 240.
  • the semiconductor structure fabricated by the method can greatly reduce the short-circuit defect of the word line.
  • the method for fabricating a semiconductor structure proposed in the present disclosure can optimize the etching effect of tungsten on the word line structure by adopting the above-mentioned method for improving the defects of the trench surface structure, and significantly improve the poor word line crossing.
  • the phenomenon of insufficient word line tungsten etching can be greatly reduced, thereby greatly reducing word line short circuit defects, reducing cross defects, and improving final yield.

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Abstract

一种改善沟槽表面结构缺陷的方法及半导体结构的制备方法，所述改善沟槽表面结构缺陷的方法包含以下步骤：在基底（110）上形成沟槽（120）之后，利用清洗液冲洗所述基底（110）的所述沟槽（120），所述清洗液为水。通过利用水作为清洗液冲洗基底（110）的沟槽（120），能够有效改善例如字线结构（140）的沟槽的表面结构的颗粒状缺陷，从而能够优化后续工艺中对字线结构（140）钨的刻蚀，而且对字线结构（140）本身的结构没有任何影响。

Description

改善沟槽表面结构缺陷的方法及半导体结构的制备方法
相关申请的交叉引用
本公开要求基于2020年7月16日提交的申请号为202010686770.1的中国申请的优先权，通过援引将其全部内容并入本文中。
技术领域
本公开涉及半导体制备工艺技术领域，尤其涉及一种改善沟槽表面结构缺陷的方法及半导体结构的制备方法。
背景技术
在现有的半导体制备工艺技术中，例如字线结构(Word Line，WL)的沟槽，在蚀刻之后是通过灰化(ASH)的方法去除副产物残留，这样会生成部分氧化物颗粒粘附在字线沟槽的表面，如无法去除干净就会在钨沉积(W DEP)之后形成大颗粒状缺陷。
当形成上述大颗粒状缺陷时，且这些大颗粒刚好位于字线结构等沟槽上方时，在之后进行的钨刻蚀的工艺中，这些大颗粒会阻挡沟道的刻蚀而造成字线钨刻蚀不足(WL W Under-ETCH)的现象引起位线耦合与字线短路不良(BLC-WL short)，这样会在最终可靠性测试的时候造成交叉不良(cross fail)的发生，从而导致低良品率(low yield)。
发明内容
本公开的一个主要目的在于克服上述现有技术的至少一种缺陷，提供一种能够有效改善沟槽表面结构的颗粒状缺陷的方法。
为实现上述目的，本公开采用如下技术方案：
根据本公开的一个方面，提供一种改善沟槽表面结构缺陷的方法；其中，包含以下步骤：
在基底上形成沟槽之后，利用清洗液冲洗所述基底的所述沟槽，所述清洗液为水。
根据本公开的其中一个实施方式，所述清洗液为50℃～70℃的水。
根据本公开的其中一个实施方式，所述清洗液为60℃的水。
根据本公开的其中一个实施方式，所述清洗液为去离子水。
根据本公开的其中一个实施方式，冲洗所述基底时，是利用所述清洗液多次冲洗。
由上述技术方案可知，本公开提出的改善沟槽表面结构缺陷的方法的优点和积极效果在于：
本公开提出的改善沟槽表面结构缺陷的方法，是在基底上形成沟槽之后，利用水作为清洗液冲洗基底的沟槽。通过上述设计，本公开能够有效改善例如字线结构的沟槽的表面结构的颗粒状缺陷。
本公开的另一个主要目的在于克服上述现有技术的至少一种缺陷，提供一种采用上述改善沟槽表面结构缺陷的方法的半导体结构的制备方法。
为实现上述目的，本公开采用如下技术方案：
根据本公开的另一个方面，提供一种半导体结构的制备方法；其中，包含以下步骤：
制备基底；
在所述基底上形成沟槽；
利用清洗液冲洗所述基底的所述沟槽，所述清洗液为水；以及
对所述基底进行灰化处理。
根据本公开的其中一个实施方式，所述清洗液为50℃～70℃的水。
根据本公开的其中一个实施方式，所述清洗液为60℃的水。
根据本公开的其中一个实施方式，所述清洗液为去离子水。
根据本公开的其中一个实施方式，冲洗所述基底时，是利用所述清洗液多次冲洗。
由上述技术方案可知，本公开提出的半导体结构的制备方法的优点和积极效果在于：
本公开提出的半导体结构的制备方法，通过采用上述的改善沟槽表面结构缺陷的方法，能够优化字线结构上的钨的刻蚀效果，显著改善字线交叉不良。
附图说明
图1是本公开提出的半导体结构的制备方法一步骤中的阵列俯视图；
图2是沿图1中直线A-A所作的剖视图；
图3是本公开提出的半导体结构的制备方法另一步骤中的剖视图；
图4是本公开提出的半导体结构的制备方法又一步骤中的剖视图；
图5是本公开提出的半导体结构的制备方法再一步骤中的阵列俯视图；
图6是沿图5中直线D-D所作的剖视图；
图7是一种现有半导体结构的制备方法一步骤中的阵列俯视图；
图8是沿图7中直线E-E所作的剖视图。
附图标记说明如下：
110.基底；
111.有源区；
112.沟槽隔离区；
113.掩膜层；
114.光掩膜层；
120.沟槽；
130.氧化物颗粒；
140.字线结构；
210.基底；
240.字线结构；
241.刻蚀残留部分。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
参阅图1至图3所示，其代表性地示出了本公开提出的改善沟槽表面结构缺陷的方法的主要步骤中半导体结构的结构示意图。在该示例性实施方式中，本公开提出的改善沟槽表面结构缺陷的方法是以应用于动态随机存储器(DRAM)为例进行说明的。本领域技术人员容易理解的是，为将本公开的相关设计应用于其他类型的半导体器件的清洗制程或其他工艺中，而对下述的具体实施方式做出多种改型、添加、替代、删除或其他变化，这些变化仍在本公开提出的改善沟槽表面结构缺陷的方法的原理的范围内。
如图1至图3所示，图1中具体示出了在基底110上形成沟槽120时的阵列俯视图；图2中具体示出了沿图1中直线A-A所作的剖视图，且该图中示出了沟槽120上粘附氧化物颗粒130时的剖视结构；图3中具体示出了沿图1中直线A-A所作的另一剖视图，且该图中示出了经由本公开提出的改善沟槽120表面结构缺陷的方法，将沟槽120上粘附的氧化物颗粒130去除后的剖视结构。以下将结合上述附图，对本公开提出的改善沟槽120表面结构缺陷的方法的各主要步骤的工艺、功效进行详细说明。
如图1至图3所示，在本实施方式中，本公开提出的改善沟槽120表面结构缺陷的方法包含以下步骤：
在基底110上形成沟槽120之后，利用清洗液冲洗基底110的沟槽120，清洗液为水。
通过上述工艺设计，本公开提出的改善沟槽120表面结构缺陷的方法，利用水作为清洗液冲洗基底110的沟槽120，据此能够有效改善例如字线结构140的沟槽120的表面结构的颗粒状缺陷，从而能够优化后续工艺中对字线结构140钨的刻蚀。而且对字线结构140本身的结构没有任何影响。相比于现有的半导体的制备方法，其不具有在刻蚀后对基底的沟槽进行冲洗的步骤，因此会导致例如氧化物颗粒等副产物残留的问题，并在钨沉积后形成大颗粒状缺陷。阻挡沟道的刻蚀而造成字线钨刻蚀不足的现象引起位线耦合与字线短路不良，进而在最终可靠性测试中造成交叉不良。
较佳地，在本实施方式中，清洗液可以优选为50℃～70℃的水，例如50℃、55℃、62℃、70℃等。据此，由于热水具有更好的溶解性，因此能够更好的去除氧化物颗粒130等副产物。同时，区别于现有的其他类型的半导体制备工艺中所采用的酸碱类冲洗液，如将此种冲洗液应用到本公开涉及的清洗步骤中，此种液体会对字线结构造成腐蚀而产生电性差异，本公开采用热水作为清洗液能够有效避免上述问题。在其他实施方式中，清洗液亦可选择其他温度的水，即可以小于50℃，或可大于70℃，例如48℃、75℃等，并不以本实施方式为限。
进一步地，基于清洗液为50℃～70℃的水的工艺设计，在本实施方式中，清洗液可以进一步优选为60℃的水。
较佳地，在本实施方式中，清洗液可以优选为去离子水。
进一步地，基于清洗液的上述温度和种类的工艺设计，在本实施方式中，清洗液可以进一步优选为60℃的去离子水。
较佳地，在本实施方式中，对于利用冲洗液冲洗基底110的步骤而言，可以优选地采用利用冲洗液多次冲洗基底110的工艺。
进一步地，基于利用冲洗液多次出现基底110的工艺设计，在本实施方式中，每次冲洗时的持续时间和流量等均可相同，使得每次冲洗能够完成相同的冲洗效果，重复冲洗多次直至沟槽120上的氧化物颗粒130完全去除或者达到预定的去除效果。在其他实施方式中，每次冲洗时的持续时间亦可不完全相同，且每次冲洗的流量亦可不完全相同，例如可以采用等差序列的方式进行多次冲洗，或可采用其他方式进行多次冲洗，可以根据不同的工艺需要对抗多次冲洗的方式进行灵活选择和调整，并不以本实施方式为限。
例如，在另一实施方式中，当采用等差序列的方式进行多次冲洗时，冲洗的时间可以设计为逐次递减，直至氧化物颗粒130完全去除或者达到预定的去除效果。并且，在上述过程中，冲洗的流量亦可设计为逐次递减。在此基础上，冲洗时间的递减趋势与冲洗流量的递减趋势可以优选为相同。另外，当采用等差序列的方式进行多次冲洗时，冲洗的时间亦可设计为逐次递增，且冲洗的流量可以与冲洗的时间同为逐次递减或者同为逐次递增，亦可将冲洗的流量与冲洗的时间设计为一者逐次递增另一者逐次递减，均不以本实施方式为限。
又如，在另一实施方式中，可以根据工艺需要分别设计各次冲洗的时间和流量，例如，假设多次冲洗供需冲洗X(X≥3)次，可以将开始冲洗的前Y(1≤Y＜X)次和结束冲洗的后Z(1≤Z＜X，且Y+Z＜X)次时的冲洗时间，设计为小于其余次冲洗的冲洗时间，亦可将前Y次和后Z次时的冲洗时间设计为大于其余次冲洗的冲洗时间，冲洗流量亦可采用上述设计思路，在此不予赘述。
再如，在另一实施方式中，当多次冲洗的冲洗时间采用不完全相同的设计时，冲洗时间较短的次序中的冲洗流量，亦可大于或者等于冲洗时间较长的次序中的冲洗流量，均不以本实施方式为限。
在此应注意，附图中示出而且在本说明书中描述的改善沟槽120表面结构缺陷的方法仅仅是能够采用本公开原理的许多种方法中的几个示例。应当清楚地理解，本公开的原理绝非仅限于附图中示出或本说明书中描述的改善沟槽120表面结构缺陷的方法的任何细节或任何步骤。
综上所述，本公开提出的改善沟槽120表面结构缺陷的方法，是在基底110上形成沟槽120之后，利用水作为清洗液冲洗基底110的沟槽120。通过上述设计，本公开能够有效改善例如字线结构140的沟槽120的表面结构的颗粒状缺陷。
基于上述对本公开提出的改善沟槽120表面结构缺陷的方法的一示例性实施方式的详细说明，以下将对本公开提出的半导体结构的制备方法的一示例性实施方式进行说明。
如图1至图6所示，其代表性地示出了本公开提出的半导体结构的制备方法的主要步骤中，半导体结构的结构示意图。在该示例性实施方式中，本公开提出的半导体结构的制备方法是以应用于动态随机存储器(DRAM)为例进行说明的。本领域技术人员容易理解的是，为将本公开的相关设计应用于其他类型的半导体器件的制程或其他工艺中，而对下述的具体实施方式做出多种改型、添加、替代、删除或其他变化，这些变化仍在本公开提出的改善沟槽120表面结构缺陷的方法的原理的范围内。
配合参阅图4至图6所示，图4中具体示出了清洗后的半导体结构经灰化处理(ASH)和沉积二氧化硅栅极(DEP gate OX)后的剖视图；图5中具体示出了上述半导体结构再经由钨刻蚀完成后的阵列俯视图；图6是沿图5中直线D-D所作的剖视图。以下将结合上述附图，对本公开提出的半导体结构的制备方法的各主要步骤的工艺、功效进行详细说明。
如图1至图6所示，在本实施方式中，本公开提出的半导体结构的制备方法包含以下步骤：
制备基底110；
在基底110上形成沟槽120；
利用清洗液冲洗基底110的沟槽120，清洗液为水；以及
对基底110进行灰化处理、沉积二氧化硅层栅极、钨沉积刻蚀工艺等。
通过上述工艺设计，本公开提出的半导体结构的制备方法，能够优化字线结构140上的钨(W)的刻蚀效果，显著改善字线交叉不良(cross fail)。其中，相比于现有的其他类型的半导体制备工艺中所采用的酸碱类冲洗液，如将此种冲洗液应用到本公开涉及的清洗步骤中，此种液体会对字线结构造成腐蚀而产生电性差异，本公开利用水，特别是例如50℃～70℃的热水作为清洗液对基底110冲洗后在进行灰化处理，能够防止其他副产物被氧化形成不必要的杂质产物和硅损伤等问题。
较佳地，如图1至图6所示，在本实施方式中，基底110可以优选地包含衬底和掩膜层113。其中，衬底可以为硅衬底、锗衬底、锗化硅衬底。沟槽隔离区112将衬底分为有源区111，沟槽隔离区使用二氧化硅(SiO 2)填充。掩膜层113形成于沟槽隔离区112上，例如为氮化硅(SiN)，且上述二氧化硅与氮化硅可共同视为掩膜层。掩膜层113上面形成有光掩膜层114。在此基础上，上述对基底100进行的灰化处理，即用于去除该光掩膜层。
较佳地，在本实施方式中，清洗液可以优选为50℃～70℃的水，例如50℃、55℃、62℃、70℃等。在其他实施方式中，清洗液亦可选择其他温度的水，即可以小于50℃，或可大于70℃，例如48℃、75℃等，并不以本实施方式为限。
进一步地，基于清洗液为50℃～70℃的水的工艺设计，在本实施方式中，清洗液可以进一步优选为60℃的水。
较佳地，在本实施方式中，清洗液可以优选为去离子水。
进一步地，基于清洗液的上述温度和种类的工艺设计，在本实施方式中，清洗液可以 进一步优选为60℃的去离子水。
较佳地，在本实施方式中，对于利用冲洗液冲洗基底110的步骤而言，可以优选地采用利用冲洗液多次冲洗基底110的工艺。
进一步地，基于利用冲洗液多次出现基底110的工艺设计，在本实施方式中，每次冲洗时的持续时间和流量等均可相同，使得每次冲洗能够完成相同的冲洗效果，重复冲洗多次直至沟槽120上的氧化物颗粒130完全去除或者达到预定的去除效果。
在此应注意，附图中示出而且在本说明书中描述的半导体结构的制备方法仅仅是能够采用本公开原理的许多种方法中的几个示例。应当清楚地理解，本公开的原理绝非仅限于附图中示出或本说明书中描述的半导体结构的制备方法的任何细节或任何步骤。
如图7和图8所示，图7中具体示出了一种现有半导体结构的制备方法中，半导体结构经由钨刻蚀完成后的阵列俯视图；图8中具体示出了沿图7中直线E-E所作的剖视图。其中，可以看出，现有半导体结构受传统制备方法及其传统清洗方法的限制，会产生明显的字线钨刻蚀不足的现象，即基底的沟槽内的字线结构210存在刻蚀残留部分240。反观本公开提出的半导体结构的制备方法，经其制备的半导体结构能够大量减少字线短路不良。
综上所述，本公开提出的半导体结构的制备方法，通过采用上述的改善沟槽表面结构缺陷的方法，能够优化字线结构上的钨的刻蚀效果，显著改善字线交叉不良。相比于现有工艺，能够大量减少字线钨刻蚀不足的现象发生，从而大量减少字线短路不良，减少交叉不良发生，改善最终良率。
虽然已参照几个典型实施例描述了本公开，但应当理解，所用的术语是说明和示例性、而非限制性的术语。由于本公开能够以多种形式具体实施而不脱离公开的精神或实质，所以应当理解，上述实施例不限于任何前述的细节，而应在随附权利要求所限定的精神和范围内广泛地解释，因此落入权利要求或其等效范围内的全部变化和改型都应为随附权利要求所涵盖。

Claims (20)

  1. 一种改善沟槽表面结构缺陷的方法，其特征在于，包含以下步骤：
    在基底上形成沟槽之后，利用清洗液冲洗所述基底的所述沟槽，所述清洗液为水。
  2. 根据权利要求1所述的改善沟槽表面结构缺陷的方法，其特征在于，所述清洗液为50℃～70℃的水。
  3. 根据权利要求2所述的改善沟槽表面结构缺陷的方法，其特征在于，所述清洗液为60℃的水。
  4. 根据权利要求1所述的改善沟槽表面结构缺陷的方法，其特征在于，所述清洗液为去离子水。
  5. 根据权利要求1所述的改善沟槽表面结构缺陷的方法，其特征在于，冲洗所述基底时，是利用所述清洗液多次冲洗。
  6. 根据权利要求5所述的改善沟槽表面结构缺陷的方法，其特征在于，每次冲洗的持续时间相等。
  7. 根据权利要求5所述的改善沟槽表面结构缺陷的方法，其特征在于，每次冲洗的清洗液的流量相等。
  8. 根据权利要求5所述的改善沟槽表面结构缺陷的方法，其特征在于，每次冲洗的持续时间以等差序列的方式递增或者递减。
  9. 根据权利要求5所述的改善沟槽表面结构缺陷的方法，其特征在于，每次冲洗的清洗液的流量以等差序列的方式递增或者递减。
  10. 根据权利要求5所述的改善沟槽表面结构缺陷的方法，其特征在于，定义冲洗次 数为X次，其中X≥3，开始冲洗的前Y次和结束冲洗的后Z次的冲洗时间，小于其余次冲洗的冲洗时间，其中1≤Y＜X，1≤Z＜X，且Y+Z＜X。
  11. 根据权利要求5所述的改善沟槽表面结构缺陷的方法，其特征在于，定义冲洗次数为X次，其中X≥3，开始冲洗的前Y次和结束冲洗的后Z次的冲洗时间，大于其余次冲洗的冲洗时间，其中1≤Y＜X，1≤Z＜X，且Y+Z＜X。
  12. 根据权利要求5所述的改善沟槽表面结构缺陷的方法，其特征在于，多次冲洗的冲洗时间不完全相同，任意两次冲洗中，冲洗时间较短的冲洗的清洗液的流量，大于冲洗时间较短的冲洗的清洗液的流量。
  13. 一种半导体结构的制备方法，其特征在于，包含以下步骤：
    制备基底；
    在所述基底上形成沟槽；
    利用清洗液冲洗所述基底的所述沟槽，所述清洗液为水；以及
    对所述基底进行灰化处理。
  14. 根据权利要求13所述的半导体结构的制备方法，其特征在于，所述清洗液为50℃～70℃的水。
  15. 根据权利要求14所述的半导体结构的制备方法，其特征在于，所述清洗液为60℃的水。
  16. 根据权利要求13所述的半导体结构的制备方法，其特征在于，所述清洗液为去离子水。
  17. 根据权利要求13所述的半导体结构的制备方法，其特征在于，冲洗所述基底时，是利用所述清洗液多次冲洗。
  18. 根据权利要求17所述的半导体结构的制备方法，其特征在于，每次冲洗的持续时 间相等。
  19. 根据权利要求17所述的半导体结构的制备方法，其特征在于，每次冲洗的清洗液的流量相等。
  20. 根据权利要求17所述的半导体结构的制备方法，其特征在于，每次冲洗的持续时间以等差序列的方式递增或者递减。
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