WO2022007600A1 - 半导体结构及其制作方法 - Google Patents

半导体结构及其制作方法 Download PDF

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Publication number
WO2022007600A1
WO2022007600A1 PCT/CN2021/100239 CN2021100239W WO2022007600A1 WO 2022007600 A1 WO2022007600 A1 WO 2022007600A1 CN 2021100239 W CN2021100239 W CN 2021100239W WO 2022007600 A1 WO2022007600 A1 WO 2022007600A1
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Prior art keywords
conductive structure
conductive
spacer
forming
trench
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French (fr)
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刘志拯
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to US17/451,341 priority Critical patent/US12027456B2/en
Publication of WO2022007600A1 publication Critical patent/WO2022007600A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/66—Conductive materials thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/063—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0147—Manufacturing their gate sidewall spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/063—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material
    • H10W20/0636—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material the conductive members being on sidewalls
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/076—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/43—Layouts of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/435—Cross-sectional shapes or dispositions of interconnections

Definitions

  • the present invention relates to the technical field of integrated circuits, in particular to a semiconductor structure and a manufacturing method thereof.
  • the integration of the device structure is getting higher and higher, especially in the manufacturing process of DRAM (Dynamic Random Access Memory) with smaller key dimensions, etching
  • the margin of the process is also reduced.
  • the peripheral circuit structure M0 such as the sense amplifier (SA) and the sub word line driver (SWD)
  • SA sense amplifier
  • SWD sub word line driver
  • a semiconductor structure and a method of fabricating the same are provided.
  • a method of fabricating a semiconductor structure comprising:
  • first spacer structure in the trench, the first spacer structure covering at least sidewalls of the trench
  • the second conductive structure covers the sidewall of the first spacer structure away from the first conductive structure;
  • a third conductive structure is formed, and the third conductive structure covers the sidewall of the second spacer structure away from the second conductive structure.
  • the first conductive structure is a pad
  • both the second conductive structure and the third conductive structure are conductive leads.
  • the trench includes a first region and a second region, wherein the width of the first region is greater than the width of the second region, and the first conductive structure is formed in the first region Inside.
  • the step of forming the first spacer structure includes:
  • first isolation material layer by a deposition process, the first isolation material layer covering the sidewall and bottom of the trench and the top of the sacrificial layer, and filling the second region of the trench;
  • the first isolation material layer is etched, the first isolation material layer covering the bottom of the trench and the top of the sacrificial layer is removed, and the first isolation material covering the sidewall of the trench is retained. a layer of isolation material to form the first spacer structure.
  • the step of forming the first conductive structure includes:
  • first conductive material layer filling the first region of the trench and covering the sacrificial layer and the top of the first spacer structure
  • the step of forming the second conductive structure includes:
  • the line widths of the second conductive structure and the third conductive structure are both in the range of 10-50 nm.
  • the first conductive structure, the second conductive structure and the third conductive structure are all made of metal conductive materials.
  • the method for fabricating the semiconductor structure further includes:
  • An insulating layer is formed, the insulating layer fills the area to be filled and covers the tops of the first conductive structure, the second conductive structure and the third conductive structure.
  • a semiconductor structure formed by using the method for fabricating a semiconductor structure described in any of the above embodiments comprising: a substrate, a first conductive structure, a second conductive structure and a third conductive structure ;
  • first conductive structure, the second conductive structure and the third conductive structure are disposed on the surface of the substrate at intervals, and the second conductive structure is located on the first conductive structure and the third conductive structure between the three conductive structures.
  • the semiconductor structure further includes an insulating layer, and the insulating layer fills a region between the first conductive structure, the second conductive structure, and the third conductive structure, and covers all the conductive structures. the top of the first conductive structure, the second conductive structure and the third conductive structure.
  • the first conductive structure is a pad
  • the second conductive structure and the third conductive structure are leads.
  • the line widths of the second conductive structure and the third conductive structure are both in the range of 10-50 nm.
  • the size of the mask used in the photolithography process is increased to the size of the first conductive structure.
  • the sum of the width of the structure and twice the width of the first spacer structure reduces the restrictions on the lithography process, thereby solving the problem of difficult metal wiring in the peripheral circuit structure caused by the reduction of critical dimensions, and improving product quality at the same time .
  • FIG. 1 is a flowchart of a method for fabricating a semiconductor structure provided by an embodiment
  • 2-8 are schematic cross-sectional structural diagrams of a structure obtained in a method for fabricating a semiconductor structure provided in an embodiment
  • FIG. 9 is a top view of a semiconductor structure provided by an embodiment.
  • a method for fabricating a semiconductor structure including the following steps:
  • Step S110 providing the substrate 100
  • Step S120 forming a sacrificial layer 200 on the substrate 100;
  • Step S130 forming trenches 210 in the sacrificial layer 200;
  • Step S140 forming a first spacer structure 300 in the trench 210 , and the first spacer structure 300 at least covers the sidewall of the trench 210 ;
  • Step S150 forming a first conductive structure 400 in the trench 210;
  • Step S160 forming a second conductive structure 500, the second conductive structure 500 covers the sidewall of the first spacer structure 300 away from the first conductive structure 400;
  • Step S170 forming a second spacer structure 600 , and the second spacer structure 600 covers the sidewall of the second conductive structure 500 away from the first spacer structure 300 ;
  • step S180 a third conductive structure 700 is formed, and the third conductive structure 700 covers the sidewall of the second spacer structure 600 away from the second conductive structure 500 .
  • the layout of the core area is limited by the word line/bit line spacing.
  • the patterning process is also limited when forming the metal wiring corresponding to the core area.
  • the traditional use of reverse self-aligned double Patterning technology has not been able to realize wiring very well.
  • the trenches 210 are formed in the sacrificial layer 200 first, and then the first spacer structure 300 and the first conductive structure 400 are formed in the trenches in sequence, so that the size of the mask used in the photolithography process is reduced.
  • the width of the first conductive structure 400 is increased to the sum of the width of the first spacer structure 300, which reduces the limitation of the photolithography process, thereby solving the metal wiring in the peripheral circuit structure caused by the reduction of the critical dimension. difficult problems while improving product quality.
  • the substrate 100 includes a semiconductor base and a word line structure, a bit line structure and a capacitor structure sequentially formed on the semiconductor base.
  • the semiconductor substrate may be, but not limited to, a silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, a silicon carbide substrate or a silicon-on-insulator substrate.
  • the first conductive structure 400 is a pad
  • the second conductive structure 500 and the third conductive structure 700 are both conductive leads.
  • both the second conductive structure 500 and the third conductive structure 700 are connected to the pad, and provide data received by the pad to the corresponding word line or bit line structure.
  • FIG. 2 Please refer to FIG. 2 , wherein (a) in FIG. 2 is a schematic top view of the structure after the trench 210 is formed, and (b) in FIG. 2 is a schematic cross-sectional structure along the dotted line AB in FIG. 2 (a).
  • the trench 210 includes a first region 211 and a second region 212, wherein the width of the first region 211 is greater than the width of the second region 212, and the first conductive structure 400 is formed in the first region 211 .
  • the specific steps of forming the trench 210 in this embodiment include:
  • a sacrificial material is deposited on the substrate 100 using a deposition process to form the sacrificial layer 200 .
  • the thickness of the sacrificial layer 200 is determined by the height of the first conductive structure 400 to be formed.
  • the sacrificial layer 200 can be made of materials such as silicon oxide, silicon nitride, etc., wherein the deposition process can include chemical vapor deposition (CVD), low pressure CVD (LPCVD), plasma enhanced CVD (PECVD), atomic layer deposition ( ALD) and plasma enhanced ALD (PEALD).
  • CVD chemical vapor deposition
  • LPCVD low pressure CVD
  • PECVD plasma enhanced CVD
  • ALD atomic layer deposition
  • PEALD plasma enhanced ALD
  • a patterned mask layer is formed on the sacrificial layer 200 .
  • the patterned mask layer has openings exposing the sacrificial layer 200 , and the openings define the shape and position of the trenches 210 .
  • the patterned mask layer may include a patterned photoresist layer or a patterned hard mask layer.
  • the step of forming the patterned mask layer specifically includes:
  • the sacrificial layer 200 is coated with photoresist to form a photoresist layer, and then a laser is used to irradiate the photoresist layer through a mask to cause a chemical reaction of the photoresist in the exposed area;
  • the photoresist in the exposed area (the former is called positive photoresist, the latter is called negative photoresist), and the pattern on the photomask is transferred to the photoresist layer to form a patterned mask layer.
  • a hard mask layer can be formed on the sacrificial layer 200 first, a photoresist layer can be formed on the hard mask layer next, and then an exposure The developing process exposes and develops the photoresist layer to obtain a patterned photoresist layer; and then etches the hard mask layer based on the patterned photoresist layer to form the patterned hard mask film layer.
  • the sacrificial layer 200 is etched based on the patterned mask layer to form the trench 210 , and the substrate 100 is exposed at the bottom of the trench 210 .
  • the step of removing the patterned mask layer is further included; specifically, when the patterned mask layer is a patterned hard mask layer, a chemical mechanical polishing process, an etching process or a chemical mechanical polishing process can be used.
  • the patterned mask layer is removed by a combination of etching processes; when the patterned mask layer is a patterned photoresist layer, an ashing process can be used to remove the patterned mask layer.
  • the step of forming the first spacer structure 300 includes:
  • a first isolation material layer is formed by a deposition process, the first isolation material layer covers the sidewall and bottom of the trench 210 and the top of the sacrificial layer 200 , and fills the second region 212 of the trench 210 ;
  • Chemical mechanical polishing or etching is performed on the first isolation material layer, the first isolation material layer covering the bottom of the trench 210 and the top of the sacrificial layer 200 is removed, and the first isolation material layer covering the trench 210 is retained.
  • the first isolation material layer on the sidewall forms the first spacer structure 300 .
  • the first conductive structure 400 is a pad
  • the second conductive structure 500 and the third conductive structure 700 are both conductive leads.
  • the length of the pad is smaller than the length of the conductive lead, so it is only necessary to increase the width of the trench 210 in the area where the pad is arranged.
  • a silicon nitride material can be deposited through a deposition process to form the first isolation material layer, and the first isolation material layer covers the sidewall of the trench 210 and the bottom and the top of the sacrificial layer 200, and fill the second region 212 of the trench 210; then, use an etch-back or chemical mechanical polishing process to remove the bottom and the sacrificial layer covering the trench 210
  • the first isolation material layer on the top of the trench 200 remains to cover the first isolation material layer on the sidewall of the trench 210 to form the first spacer structure 300 .
  • the width of the first spacer structure 300 formed by the deposition process in the first region 211 is greater than or equal to that in the second region 212 . Therefore, in the direction perpendicular to the extending direction of the trench 210 , the difference between the width of the trench 210 in the first region 211 and the width in the second region 212 is greater than or equal to the width of the first conductive structure 400 to be formed.
  • the step of forming the first conductive structure 400 includes:
  • the first conductive material layer fills the first region 211 of the trench 210 and covers the top of the sacrificial layer 200 and the first spacer structure;
  • the first conductive material layer covering the sacrificial layer 200 and the top of the first spacer structure is removed to form the first conductive structure 400, the top of the first conductive structure 400 and the first spacer structure
  • the top of the 300 is flush.
  • the specific process of forming the first conductive structure 400 in the embodiment of the present invention includes: using a deposition process to deposit conductive materials, such as metal materials such as tungsten and nickel, on the substrate 100 on which the first spacer structures 300 are formed to form a first conductive material layer, the first conductive material layer fills the first region 211 of the trench 210 and covers the sacrificial layer 200 and the top of the first spacer structure; then, use an etch back or The chemical mechanical polishing process removes the first conductive material layer covering the sacrificial layer 200 and the top of the first spacer structure to form the first conductive structure 400, the top of the first conductive structure 400 is connected to the The top of the first spacer structure 300 is flush.
  • conductive materials such as metal materials such as tungsten and nickel
  • the step of forming the second conductive structure 500 includes:
  • the second conductive material layer covering the substrate 100 , the tops of the first spacer structures 300 and the first conductive structures 400 and the outer sidewalls of the first spacer structures 300 ;
  • the sacrificial layer 200 is first removed.
  • the sacrificial layer 200 is made of silicon oxide material, and the first isolation structure is made of silicon nitride material, so oxidation can be used
  • the sacrificial layer 200 is removed by the etching selectivity ratio of the silicon material and the silicon nitride material; then, a conductive material, such as metal materials such as tungsten and nickel, is deposited by a deposition process to form a second conductive material layer, the second conductive material layer covering the substrate 100, the top of the first spacer structure 300 and the first conductive structure 400 and the outer sidewall of the first spacer structure 300; finally, the second conductive material layer is etched back, removing the second conductive material layer covering the substrate 100 , the first spacer structure 300 and the top of the first conductive structure 400 , leaving the second layer covering the outer sidewalls of the first spacer structure 300 A conductive material layer to form the second
  • the process of forming the second spacer structure 600 specifically includes:
  • a silicon nitride material is deposited by a deposition process to form a second isolation material layer, and the second isolation material layer covers the substrate 100 and the first conductive structure 400 , the tops of the first spacer structure 300 and the second conductive structure 500 , and cover the sidewalls of the second conductive structure 500 away from the first spacer structure 300 .
  • the process of forming the third conductive structure 700 specifically includes: first, depositing conductive materials, such as metal materials such as tungsten, nickel, etc. by a deposition process, to form a third conductive material layer, the A third conductive material layer covers the substrate 100 , the first spacer structure 300 , the first conductive structure 400 , the second conductive structure 500 , the top of the second spacer structure 600 and the second the sidewall of the spacer structure 600 away from the first spacer structure 300; finally, chemical mechanical polishing or etchback is performed on the third conductive material layer to remove the cover substrate 100, the first spacer structure 300, all the The third conductive material layer on top of the first conductive structure 400 , the second conductive structure 500 , and the second spacer structure 600 remains the first spacer structure 300 covering the outer sidewalls of the first spacer structure 300 . Three conductive material layers to form the third conductive structure 700 .
  • conductive materials such as metal materials such as tungsten, nickel, etc.
  • the line widths of the second conductive structure and the third conductive structure are both in the range of 10 to 50 nm; specifically, the line widths of the second conductive structure and the third conductive structure may be 10 nm and 20 nm. , 30nm, 40nm or 50nm.
  • the line widths of the second conductive structure and the third conductive structure can be controlled within the range of 10-50 nm, the internal resistance on the conductive leads can be reduced, and the word line/bit line can be satisfied at the same time. spacing restrictions. The spacing distance between the conductive leads is specifically determined by the thickness of the spacing structure therebetween.
  • the first conductive structure 400 , the second conductive structure 500 and the third conductive structure 700 are all made of metal conductive materials. It can be understood that the use of metal conductive materials to make the first conductive structure 400 , the second conductive structure 500 and the third conductive structure 700 can reduce the internal resistance on the conductive leads, and maintain a good timing of transmission signals. Consistency, and help reduce the difficulty of material management, thereby reducing production costs.
  • the method for fabricating the semiconductor structure further includes:
  • An insulating layer 800 is formed, the insulating layer 800 fills the area to be filled, and covers the tops of the first conductive structure 400 , the second conductive structure 500 and the third conductive structure 700 .
  • the first spacer structure 300 and the second spacer structure 600 in order to facilitate the manufacture, it is possible to use materials with poor insulation and/or low dielectric coefficients. Therefore, for example, the first spacer structure 300 is used.
  • the second spacer structure 600 as an insulating structure may cause dark current and/or parasitic capacitance, so the insulating layer 800 needs to be re-formed.
  • the materials for making the first spacer structure 300 and the second spacer structure 600 have good insulation and high dielectric constant, the first spacer structure 300 and the second spacer structure can also be retained 600.
  • an embodiment further provides a semiconductor structure formed by using the method for fabricating a semiconductor structure described in any of the foregoing embodiments, please refer to FIG. 9 , the semiconductor structure includes: a substrate 100 , a first conductive Structure 400 , second conductive structure 500 and third conductive structure 700 .
  • the first conductive structure 400 , the second conductive structure 500 and the third conductive structure 700 are disposed on the surface of the substrate 100 at intervals, and the second conductive structure 500 is located on the first conductive structure 400 and the third conductive structure 700 .
  • the substrate 100 includes a semiconductor base and a word line structure, a bit line structure and a capacitor structure sequentially formed on the semiconductor base.
  • the semiconductor substrate may be a silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, a silicon carbide substrate or a silicon-on-insulator substrate, but not limited thereto.
  • the semiconductor structure further includes an insulating layer 800 filling the space between the first conductive structure 400 , the second conductive structure 500 and the third conductive structure 700 . area, and cover the tops of the first conductive structure 400 , the second conductive structure 500 and the third conductive structure 700 .
  • the first conductive structure 400 , the second conductive structure 500 and the third conductive structure 700 are insulated by the insulating layer 800 to prevent dark current and/or parasitic capacitance from being generated;
  • the insulating layer 800 also supports the first conductive structure 400, the second conductive structure 500 and the third conductive structure 700, preventing the first conductive structure 400, the second conductive structure 500 and the third conductive structure
  • the three-conductive structure 700 collapses or collapses due to external force.
  • the first conductive structure 400 is a pad
  • the second conductive structure 500 and the third conductive structure 700 are both conductive leads.
  • both the second conductive structure 500 and the third conductive structure 700 are connected to the pad, and provide data received by the pad to the corresponding word line or bit line structure.
  • the line widths of the second conductive structure and the third conductive structure are both in the range of 10 to 50 nm;
  • the line widths can all be 10 nm, 20 nm, 30 nm, 40 nm, or 50 nm, and so on.
  • the line widths of the second conductive structure and the third conductive structure can be controlled within the range of 10-50 nm, the internal resistance on the conductive leads can be reduced, and the word line/bit line can be satisfied at the same time. spacing restrictions.
  • the spacing distance between the conductive leads is specifically determined by the thickness of the spacing structure therebetween.
  • the present embodiment provides a semiconductor structure and a manufacturing method thereof, wherein the manufacturing method includes: providing a substrate 100 ; forming a sacrificial layer 200 on the substrate 100 ; forming a trench in the sacrificial layer 200 groove 210; forming a first spacer structure 300 in the trench 210, the first spacer structure 300 covering at least the sidewall of the trench 210; forming a first conductive structure 400 in the trench 210; forming A second conductive structure 500, the second conductive structure 500 covers the sidewall of the first spacer structure 300 away from the first conductive structure 400; a second spacer structure 600 is formed, the second spacer structure 600 covers the The second conductive structure 500 is away from the sidewall of the first spacer structure 300 ; a third conductive structure 700 is formed, and the third conductive structure 700 covers the sidewall of the second spacer structure 600 away from the second conductive structure 500 .
  • the size of the mask used in the photolithography process is increased to The sum of the width of the first conductive structure 400 and twice the width of the first spacer structure 300 reduces the limitation on the photolithography process, thereby solving the problem of difficult metal wiring in the peripheral circuit structure caused by the reduced critical dimension , while improving product quality.

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

一种半导体结构的制作方法包括：在衬底上形成牺牲层；在牺牲层内形成沟槽；在沟槽内形成第一间隔结构，第一间隔结构至少覆盖沟槽的侧壁；在沟槽以形成第一导电结构；形成覆盖第一间隔结构外侧侧壁的第二导电结构；形成覆盖第二导电结构的外侧侧壁的第二间隔结构；形成覆盖第二间隔结构外侧侧壁的第三导电结构。

Description

半导体结构及其制作方法
相关申请的交叉引用
本申请要求于2020年7月8日提交中国专利局、申请号为2020106498800、发明名称为“半导体结构及其制作方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及集成电路技术领域，特别是涉及一种半导体结构及其制作方法。
背景技术
随着半导体存储器关键尺寸在不断的缩小，器件结构的集成度随之越来越高，尤其在关键尺寸较小的DRAM(Dynamic Random Access Memory，即动态随机存取存储器)制造过程中，刻蚀工艺的余量也随之减小，例如在形成了诸如传感放大器(SA)和子字线驱动器(SWD)的外围电路结构M0中，布线图案的间距迅速变小，使得利用图案化工艺进行金属布线变得困难。
发明内容
根据各个实施例，提供一种半导体结构及其制作方法。
一种半导体结构的制作方法，包括：
提供衬底；
在所述衬底上形成牺牲层；
在所述牺牲层内形成沟槽；
在所述沟槽内形成第一间隔结构，所述第一间隔结构至少覆盖所述沟槽的侧壁；
在所述沟槽以形成第一导电结构；
形成第二导电结构，所述第二导电结构覆盖所述第一间隔结构远离所述第一导电结构的侧壁；
形成第二间隔结构，所述第二间隔结构覆盖所述第二导电结构远离所述第一间隔结构的侧壁；
形成第三导电结构，所述第三导电结构覆盖所述第二间隔结构远离所述第二导电结构的侧壁。
在其中一个实施例中，所述第一导电结构为焊盘，所述第二导电结构和所述第三导电结构均为导电引线。
在其中一个实施例中，所述沟槽包括第一区域和第二区域，其中所述第一区域的宽度大于所述第二区域的宽度，所述第一导电结构形成于所述第一区域内。
在其中一个实施例中，形成所述第一间隔结构步骤包括：
通过沉积工艺形成第一隔离材料层，所述第一隔离材料层覆盖所述沟槽的侧壁和底部以及所述牺牲层的顶部，且填满所述沟槽的第二区域；
对所述第一隔离材料层进行刻蚀，去除覆盖所述沟槽的底部以及所述牺牲层的顶部的所述第一隔离材料层，保留覆盖所述沟槽的侧壁上的所述第一隔离材料层以形成所述第一间隔结构。
在其中一个实施例中，形成所述第一导电结构的步骤包括：
形成第一导电材料层，所述第一导电材料层填满所述沟槽的第一区域， 且覆盖所述牺牲层和所述第一间隔结构的顶部；
去除覆盖所述牺牲层和所述第一间隔结构的顶部的所述第一导电材料层以形成所述第一导电结构，所述第一导电结构的顶部与所述第一间隔结构的顶部齐平。
在其中一个实施例中，形成所述第二导电结构的步骤包括：
去除所述牺牲层；
沉积形成第二导电材料层，所述第二导电材料层覆盖所述衬底、所述第一间隔结构和第一导电结构的顶部以及所述第一间隔结构的外侧侧壁；
去除覆盖所述衬底、所述第一间隔结构和第一导电结构的顶部的所述第二导电材料层，保留覆盖所述第一间隔结构的外侧侧壁的所述第二导电材料层以形成所述第二导电结构。
在其中一个实施例中，所述第二导电结构和所述第三导电结构的线宽范围均为10～50nm。
在其中一个实施例中，所述第一导电结构、所述第二导电结构和所述第三导电结构均采用金属导电材料制作。
在其中一个实施例中，所述半导体结构的制作方法还包括：
去除所述第一间隔结构和所述第二间隔结构，以形成待填充区域；
形成绝缘层，所述绝缘层填充所述待填充区域，且覆盖所述第一导电结构、所述第二导电结构以及第三导电结构的顶部。
基于同一发明构思，还提供了采用上述任一实施例所述的半导体结构的制作方法形成的半导体结构，所述半导体结构包括：衬底、第一导电结构、第二导电结构和第三导电结构；
其中，所述第一导电结构、所述第二导电结构和所述第三导电结构间隔 的设置在所述衬底表面，且所述第二导电结构位于所述第一导电结构和所述第三导电结构之间。
在其中一个实施例中，所述半导体结构还包括绝缘层，所述绝缘层填充在所述第一导电结构、所述第二导电结构和所述第三导电结构之间的区域，且覆盖所述第一导电结构、所述第二导电结构以及所述第三导电结构的顶部。
在其中一个实施例中，所述第一导电结构为焊盘，所述第二导电结构和所述第三导电结构为引线。
在其中一个实施例中，所述第二导电结构和所述第三导电结构的线宽范围均为10～50nm。
在上述方法中，通过先在牺牲层内形成沟槽，然后再在沟槽内依次形成第一间隔结构以及第一导电结构，使得光刻过程中使用的掩膜的尺寸增大至第一导电结构的宽度与2倍的第一间隔结构的宽度之和，降低了对光刻工艺的限制，从而解决了因关键尺寸变小所导致的外围电路结构中金属布线困难的问题，同时提高产品品质。
附图说明
为了更清楚地说明本发明实施例或传统技术中的技术方案，下面将对实施例或传统技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为一实施例提供的半导体结构的制作方法的流程图；
图2-8为一实施例中提供的半导体结构的制作方法中所得结构的截面结构示意图；
图9为一实施例提供的半导体结构的俯视图。
具体实施方式
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使本发明的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可以用于描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语还包括使用和操作中的器件的不同取向。此外，这里参考作为本发明的理想实施例(和中间结构)的示意图的横截面图来描述发明的实施例，这样可以预期由于例如制造技术和/或容差导致的所示形状的变化。因此，本发明的实施例不应当局限于在此所示的区的特定形状，而是包括由于例如制造技术导致的形状偏差。
请参阅图1，根据一实施例，提供一种半导体结构的制作方法，包括如下步骤：
步骤S110，提供衬底100；
步骤S120，在所述衬底100上形成牺牲层200；
步骤S130，在所述牺牲层200内形成沟槽210；
步骤S140，在所述沟槽210内形成第一间隔结构300，所述第一间隔结构300至少覆盖所述沟槽210的侧壁；
步骤S150，在所述沟槽210以形成第一导电结构400；
步骤S160，形成第二导电结构500，所述第二导电结构500覆盖所述第一间隔结构300远离所述第一导电结构400的侧壁；
步骤S170，形成第二间隔结构600，所述第二间隔结构600覆盖所述第二导电结构500远离所述第一间隔结构300的侧壁；
步骤S180，形成第三导电结构700，所述第三导电结构700覆盖所述第二间隔结构600远离所述第二导电结构500的侧壁。
可以理解，核心区域布局受限于字线/位线间距的限制，随着关键尺寸的减小，形成核心区域对应的金属布线时图案化工艺也受到限制，传统的利用反向自对准双重图案技术已无法很好实现布线。为此，本实施例中通过先在牺牲层200内形成沟槽210，然后再在沟槽内依次形成第一间隔结构300以及第一导电结构400，使得光刻过程中使用的掩膜的尺寸增大至第一导电结构400的宽度与2倍的第一间隔结构300的宽度之和，降低了对光刻工艺的限制，从而解决了因关键尺寸变小所导致的外围电路结构中金属布线困难的问题，同时提高产品品质。
本实施例中，所述衬底100包括半导基底以及在所述半导体基底上依次形成的字线结构、位线结构和电容结构。半导基底可以为硅基底、外延硅基底、硅锗基底、碳化硅基底或硅覆绝缘基底，但不以此为限。
在其中一个实施例中，所述第一导电结构400为焊盘，所述第二导电结构500和所述第三导电结构700均为导电引线。本实施例中，所述第二导电结构500和所述第三导电结构700均与所述焊盘连接，将焊盘接收到的数据 提供给相应的字线或位线结构。
请参见图2，其中，图2中的(a)图为形成沟槽210后的俯视结构示意图,图2中的(b)图为沿图(a)中虚线AB处的截面结构示意图。在其中一个实施例中，所述沟槽210包括第一区域211和第二区域212，其中所述第一区域211的宽度大于所述第二区域212的宽度，所述第一导电结构400形成于所述第一区域211内。
具体的，本实施例中形成沟槽210的具体步骤包括：
首先，利用沉积工艺在衬底100上沉积牺牲材料以形成牺牲层200。本实施例中，所述牺牲层200的厚度由所需要形成的第一导电结构400的高度来决定。具体的，可采用氧化硅、氮化硅等材料制作所述牺牲层200，其中沉积工艺可以包括化学气相沉积(CVD)、低压CVD(LPCVD)、等离子体增强CVD(PECVD)、原子层沉积(ALD)以及等离子体增强ALD(PEALD)。
其次，于所述牺牲层200上形成图形化掩膜层，所述图形化掩膜层内具有暴露出所述牺牲层200的开口，所述开口定义出所述沟槽210的形状及位置。该图形化掩膜层可以包括图形光刻胶层或图形化硬掩膜层，当所述图形化掩膜层为图形化光刻胶层时，形成图形化掩膜层的步骤具体包括：于所述牺牲层200上涂覆光刻胶，形成光刻胶层，然后利用激光器通过光罩照射光刻胶层引起曝光区域的光刻胶发生化学反应；再通过显影技术溶解去除曝光区域或未曝光区域的光刻胶(前者称正性光刻胶，后者称负性光刻胶)，将光罩上的图案转移到所述光刻胶层，形成图形化掩膜层。当所述图形化掩膜层为图形化硬掩膜层时，可以先于所述牺牲层200上形成硬掩膜层，其次于所述硬掩膜层上形成光刻胶层，然后采用曝光显影工艺对所述光刻胶层进行曝光显影以得到图形化光刻胶层；接着再基于所述图形化光刻胶层对所述硬掩 膜层进行刻蚀以形成所述图形化硬掩膜层。
最后，基于所述图形化掩膜层刻蚀所述牺牲层200以形成所述沟槽210，所述沟槽210的底部露出所述衬底100。
形成沟槽210之后还包括去除图形化掩膜层的步骤；具体的，当图形化掩膜层为图形化硬掩膜层时，可以采用化学机械研磨工艺、刻蚀工艺或化学机械研磨工艺与刻蚀工艺相结合的工艺来去除图形化掩膜层；当图形化掩膜层为图形化光刻胶层时，可以采用灰化工艺去除图形化掩膜层。
在其中一个实施例中，形成所述第一间隔结构300步骤包括：
通过沉积工艺形成第一隔离材料层，所述第一隔离材料层覆盖所述沟槽210的侧壁和底部以及所述牺牲层200的顶部，且填满所述沟槽210的第二区域212；
对所述第一隔离材料层进行化学机械研磨或刻蚀，去除覆盖所述沟槽210的底部以及所述牺牲层200的顶部的所述第一隔离材料层，保留覆盖所述沟槽210的侧壁上的所述第一隔离材料层，形成所述第一间隔结构300。
请参见图3，本实施例中，所述第一导电结构400为焊盘，所述第二导电结构500和所述第三导电结构700均为导电引线。焊盘的长度小于导电引线的长度，因此只需要在设置焊盘的区域加大所述沟槽210的宽度。具体的，当所述牺牲层200采用氧化硅制作时，可通过沉积工艺沉积氮化硅材料，形成所述第一隔离材料层，所述第一隔离材料层覆盖所述沟槽210的侧壁和底部以及所述牺牲层200的顶部，且填满所述沟槽210的第二区域212；然后，利用回刻蚀或化学机械研磨工艺去除覆盖所述沟槽210的底部以及所述牺牲层200的顶部的所述第一隔离材料层，保留覆盖所述沟槽210的侧壁上的所述第一隔离材料层，形成所述第一间隔结构300。
需注意的是，为了填满所述第二区域212，因此利用沉积工艺形成的第一间隔结构300在第一区域211内宽度大于或等于其在第二区域212内宽度。因此在沿垂直于沟槽210延伸的方向上，沟槽210在第一区域211内的宽度与其在第二区域212内的宽度差大于或等于需要形成的第一导电结构400的宽度。
在其中一个实施例中，形成所述第一导电结构400的步骤包括：
形成第一导电材料层，所述第一导电材料层填满所述沟槽210的第一区域211，且覆盖所述牺牲层200和所述第一间隔结构的顶部；
去除覆盖所述牺牲层200和所述第一间隔结构的顶部的所述第一导电材料层以形成所述第一导电结构400，所述第一导电结构400的顶部与所述第一间隔结构300的顶部齐平。
请参见图4，本发明实施例中形成第一导电结构400的具体过程包括：利用沉积工艺在形成第一间隔结构300的衬底100上沉积导电材料，例如钨、镍等金属材料，以形成第一导电材料层，所述第一导电材料层填满所述沟槽210的第一区域211，且覆盖所述牺牲层200和所述第一间隔结构的顶部；然后，利用回刻蚀或化学机械研磨工艺去除覆盖所述牺牲层200和所述第一间隔结构的顶部的所述第一导电材料层以形成所述第一导电结构400，所述第一导电结构400的顶部与所述第一间隔结构300的顶部齐平。
在其中一个实施例中，形成所述第二导电结构500的步骤包括：
去除所述牺牲层200；
沉积形成第二导电材料层，所述第二导电材料层覆盖所述衬底100、所述第一间隔结构300和第一导电结构400的顶部以及所述第一间隔结构300的外侧侧壁；
去除覆盖所述衬底100、所述第一间隔结构300和第一导电结构400的顶部的所述第二导电材料层，保留覆盖所述第一间隔结构300的外侧侧壁的所述第二导电材料层以形成所述第二导电结构500。
请参见图5，在形成第一导电结构400后，首先去除所述牺牲层200，由于本实施例中牺牲层200采用氧化硅材料，而第一隔离结构采用氮化硅材料，因此可利用氧化硅材料与氮化硅材料的刻蚀选择比去除所述牺牲层200；然后，利用沉积工艺沉积导电材料，例如钨、镍等金属材料，形成第二导电材料层，所述第二导电材料层覆盖所述衬底100、所述第一间隔结构300和第一导电结构400的顶部以及所述第一间隔结构300的外侧侧壁；最后，对所述第二导电材料层进行回刻蚀，去除覆盖所述衬底100、所述第一间隔结构300和第一导电结构400的顶部的所述第二导电材料层，保留覆盖所述第一间隔结构300的外侧侧壁的所述第二导电材料层，形成所述第二导电结构500。
请参见图6，在其中一个实施例中，形成第二间隔结构600的过程具体包括：
首先，在形成所述第二导电结构500的衬底100上，利用沉积工艺沉积氮化硅材料以形成第二隔离材料层，所述第二隔离材料层覆盖衬底100、第一导电结构400、第一间隔结构300和第二导电结构500的顶部，且覆盖所述第二导电结构500远离所述第一间隔结构300的侧壁。
然后，对所述第二隔离材料层进行化学机械研磨或回刻蚀，去除覆盖衬底100、第一导电结构400、第一间隔结构300和第二导电结构500的顶部的第二隔离材料层，保留覆盖所述第二导电结构500远离所述第一间隔结构300的侧壁的第二隔离材料层，形成所述第二间隔结构600。
请参见图7，在其中一个实施例中，形成第三导电结构700的过程具体包括：首先，沉积利用沉积工艺沉积导电材料，例如钨、镍等金属材料，形成第三导电材料层，所述第三导电材料层覆盖所述衬底100、所述第一间隔结构300、所述第一导电结构400、所述第二导电结构500、所述第二间隔结构600的顶部以及所述第二间隔结构600的远离所述第一间隔结构300的侧壁；最后，对所述第三导电材料层进行化学机械研磨或回刻蚀，去除覆盖衬底100、所述第一间隔结构300、所述第一导电结构400、所述第二导电结构500、所述第二间隔结构600的顶部的所述第三导电材料层，保留覆盖所述第一间隔结构300的外侧侧壁的所述第三导电材料层，形成所述第三导电结构700。
在其中一个实施例中，所述第二导电结构和所述第三导电结构的线宽范围均为10～50nm；具体的，第二导电结构和第三导电结构的线宽可以为10nm、20nm、30nm、40nm或50nm。利用本发明提供的制作方法，可将所述第二导电结构和所述第三导电结构的线宽范围控制在10～50nm范围内，降低导电引线上的内阻，同时满足字线/位线的间距的限制。导电引线的之间的间隔距离具体由二者之间的间隔结构的厚度来决定。
在其中一个实施例中，所述第一导电结构400、所述第二导电结构500和所述第三导电结构700均采用金属导电材料制作。可以理解，采用金属导电材料制所述第一导电结构400、所述第二导电结构500和所述第三导电结构700，可减小导电引线上的内阻，保持传输信号的时序具有良好的一致性，且有利于降低物料管理难度，进而降低生产成本。
请参见图8，在其中一个实施例中，所述半导体结构的制作方法还包括：
去除所述第一间隔结构和所述第二间隔结构，以形成待填充区域；
形成绝缘层800，所述绝缘层800填充所述待填充区域，且覆盖所述第一导电结构400、所述第二导电结构500以及第三导电结构700的顶部。
可以理解，在第一间隔结构300和第二间隔结构600的过程中，为了便于制作，有可能采用的绝缘性较差和/或介电系数较低的材料，因此如采用第一间隔结构300和第二间隔结构600作为绝缘结构则可能会导致产生暗电流和/或寄生电容，因此需要重新形成绝缘层800。在其它一些实施例中，如果制作第一间隔结构300和第二间隔结构600的材料具有良好的绝缘性和较高的介电系数，也可保留所述第一间隔结构300和第二间隔结构600。
基于同一发明构思，一实施例还提供了一种采用上述任一实施例所述的半导体结构的制作方法形成的半导体结构，请参见图9，所述半导体结构包括：衬底100、第一导电结构400、第二导电结构500和第三导电结构700。
所述第一导电结构400、所述第二导电结构500和所述第三导电结构700间隔的设置在所述衬底100表面，且所述第二导电结构500位于所述第一导电结构400和所述第三导电结构700之间。
本实施例中，所述衬底100包括半导体基底以及在所述半导体基底上依次形成的字线结构、位线结构和电容结构。半导体基底可以为硅基底、外延硅基底、硅锗基底、碳化硅基底或硅覆绝缘基底，但不以此为限。
在其中一个实施例中，所述半导体结构还包括绝缘层800，所述绝缘层800填充在所述第一导电结构400、所述第二导电结构500和所述第三导电结构700之间的区域，且覆盖所述第一导电结构400、所述第二导电结构500以及所述第三导电结构700的顶部。本实施例中，通过绝缘层800将所述第一导电结构400、所述第二导电结构500和所述第三导电结构700进行绝缘，以防止产生暗电流和/或寄生电容；此外，所述绝缘层800还对第一导电结构 400、所述第二导电结构500和所述第三导电结构700起到了支撑作用，防止第一导电结构400、所述第二导电结构500和所述第三导电结构700因受到外力作用而发生倒伏或坍塌。
在其中一个实施例中，所述第一导电结构400为焊盘，所述第二导电结构500和所述第三导电结构700均为导电引线。本实施例中，所述第二导电结构500和所述第三导电结构700均与所述焊盘连接，将焊盘接收到的数据提供给相应的字线或位线结构。
在其中一个实施例中，在其中一个实施例中，所述第二导电结构和所述第三导电结构的线宽范围均为10～50nm；具体的，第二导电结构和第三导电结构的线宽均可以为10nm、20nm、30nm、40nm或50nm等等。利用本发明提供的制作方法，可将所述第二导电结构和所述第三导电结构的线宽范围控制在10～50nm范围内，降低导电引线上的内阻，同时满足字线/位线的间距的限制。导电引线的之间的间隔距离具体由二者之间的间隔结构的厚度来决定。
综上，本实施例提供了一种半导体结构及其制作方法，其中所述制作方法包括：提供衬底100；在所述衬底100上形成牺牲层200；在所述牺牲层200内形成沟槽210；在所述沟槽210内形成第一间隔结构300，所述第一间隔结构300至少覆盖所述沟槽210的侧壁；在所述沟槽210以形成第一导电结构400；形成第二导电结构500，所述第二导电结构500覆盖所述第一间隔结构300远离所述第一导电结构400的侧壁；形成第二间隔结构600，所述第二间隔结构600覆盖所述第二导电结构500远离所述第一间隔结构300的侧壁；形成第三导电结构700，所述第三导电结构700覆盖所述第二间隔结构600远离所述第二导电结构500的侧壁。上述方法中，通过先在牺牲层200内形成沟槽210，然后再在沟槽内依次形成第一间隔结构300以及第一导电 结构400，使得光刻过程中使用的掩膜的尺寸增大至第一导电结构400的宽度与2倍的第一间隔结构300的宽度之和，降低了对光刻工艺的限制，从而解决了因关键尺寸变小所导致的外围电路结构中金属布线困难的问题，同时提高产品品质。
在本说明书的描述中，参考术语“其中一个实施例”、“其他一些实施例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特征包含于本发明的至少一个实施例或示例中。在本说明书中，对上述术语的示意性描述不一定指的是相同的实施例或示例。
上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (13)

  1. 一种半导体结构的制作方法，包括：
    提供衬底；
    在所述衬底上形成牺牲层；
    在所述牺牲层内形成沟槽；
    在所述沟槽内形成第一间隔结构，所述第一间隔结构至少覆盖所述沟槽的侧壁；
    在所述沟槽以形成第一导电结构；
    形成第二导电结构，所述第二导电结构覆盖所述第一间隔结构远离所述第一导电结构的侧壁；
    形成第二间隔结构，所述第二间隔结构覆盖所述第二导电结构远离所述第一间隔结构的侧壁；及
    形成第三导电结构，所述第三导电结构覆盖所述第二间隔结构远离所述第二导电结构的侧壁。
  2. 如权利要求1所述的方法，其中所述第一导电结构为焊盘，所述第二导电结构和所述第三导电结构均为导电引线。
  3. 如权利要求1所述的方法，其中所述沟槽包括第一区域和第二区域，其中所述第一区域的宽度大于所述第二区域的宽度，所述第一导电结构形成于所述第一区域内。
  4. 如权利要求3所述的方法，其中形成所述第一间隔结构包括：
    通过沉积工艺形成第一隔离材料层，所述第一隔离材料层覆盖所述沟槽的侧壁和底部以及所述牺牲层的顶部，且填满所述沟槽的第二区域；
    对所述第一隔离材料层进行刻蚀，去除覆盖所述沟槽的底部以及所述牺 牲层的顶部的所述第一隔离材料层，保留覆盖所述沟槽的侧壁上的所述第一隔离材料层以形成所述第一间隔结构。
  5. 如权利要求3所述的方法，其中形成所述第一导电结构包括：
    形成第一导电材料层，所述第一导电材料层填满所述沟槽的第一区域，且覆盖所述牺牲层和所述第一间隔结构的顶部；
    去除覆盖所述牺牲层和所述第一间隔结构的顶部的所述第一导电材料层以形成所述第一导电结构，所述第一导电结构的顶部与所述第一间隔结构的顶部齐平。
  6. 如权利要求1所述的方法，其中形成所述第二导电结构包括：
    去除所述牺牲层；
    沉积形成第二导电材料层，所述第二导电材料层覆盖所述衬底、所述第一间隔结构和第一导电结构的顶部以及所述第一间隔结构的外侧侧壁；
    去除覆盖所述衬底、所述第一间隔结构和第一导电结构的顶部的所述第二导电材料层，保留覆盖所述第一间隔结构的外侧侧壁的所述第二导电材料层以形成所述第二导电结构。
  7. 如权利要求1所述的方法，其中所述第二导电结构和所述第三导电结构的线宽范围均为10～50nm。
  8. 如权利要求1所述的方法，其中所述第一导电结构、所述第二导电结构和所述第三导电结构均采用金属导电材料制作。
  9. 如权利要求1所述的方法，还包括：
    去除所述第一间隔结构和所述第二间隔结构，以形成待填充区域；及
    形成绝缘层，所述绝缘层填充所述待填充区域，且覆盖所述第一导电结构、所述第二导电结构以及第三导电结构的顶部。
  10. 一种半导体结构，采用如权利要求1所述的方法形成，所述半导体结构包括：衬底、第一导电结构、第二导电结构和第三导电结构；
    其中，所述第一导电结构、所述第二导电结构和所述第三导电结构间隔的设置在所述衬底表面，且所述第二导电结构位于所述第一导电结构和所述第三导电结构之间。
  11. 如权利要求10所述的半导体结构，还包括绝缘层，所述绝缘层填充在所述第一导电结构、所述第二导电结构和所述第三导电结构之间的区域，且覆盖所述第一导电结构、所述第二导电结构以及所述第三导电结构的顶部。
  12. 如权利要求10所述的半导体结构，其中所述第一导电结构为焊盘，所述第二导电结构和所述第三导电结构为引线。
  13. 如权利要求10-12中任一项所述的半导体结构，其中所述第二导电结构和所述第三导电结构的线宽范围均为10～50nm。
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