WO2022000395A1 - 基于可调同质结场效应器件的单元电路及多功能逻辑电路 - Google Patents

基于可调同质结场效应器件的单元电路及多功能逻辑电路 Download PDF

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WO2022000395A1
WO2022000395A1 PCT/CN2020/099817 CN2020099817W WO2022000395A1 WO 2022000395 A1 WO2022000395 A1 WO 2022000395A1 CN 2020099817 W CN2020099817 W CN 2020099817W WO 2022000395 A1 WO2022000395 A1 WO 2022000395A1
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input terminal
input
signal
terminal
output
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PCT/CN2020/099817
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English (en)
French (fr)
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缪峰
梁世军
潘晨
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南京大学
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
    • H03K17/6872—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor using complementary field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17724—Structural details of logic blocks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/0948—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits

Definitions

  • the invention relates to the field of semiconductor materials and devices, in particular to a unit circuit based on a tunable homojunction field effect device, and a multifunctional logic circuit, an adder and a subtractor logic circuit obtained on the basis of the unit circuit.
  • the present invention provides a unit circuit based on a tunable homojunction field effect device, which solves the problem of a multi-functional logic circuit requiring many transistors and wasting resources.
  • the present invention discloses a unit circuit based on a tunable homojunction field effect device, and the unit circuit E includes:
  • the second input terminal V in2 is used for receiving the second input voltage signal
  • the third input terminal V in3 is used for receiving the third input voltage signal
  • the first tunable homojunction field effect transistor M1 For the first tunable homojunction field effect transistor M1, its source S1 is coupled to the first input terminal, the gate electrode 1a close to the source S1 is connected to the second input terminal, and its gate electrode close to the drain 1b is coupled to the third input terminal;
  • the second tunable homojunction field effect transistor M2 For the second tunable homojunction field effect transistor M2, its source S2 is coupled to the third input terminal, the gate electrode 2a close to the source S2 is connected to the second input terminal, and its gate electrode close to the drain 2b is coupled to the first input end;
  • the first tunable homogeneous junction field effect transistor is connected to the drain of the second tunable homogeneous junction field effect transistor, and the output of the connection point is used as the output terminal V out ;
  • the first tunable homojunction field effect transistor M1 and the second tunable homojunction field effect transistor M2 have the same structure, including a substrate insulating material, a channel material layer, an insulating layer and a metal electrode layer; the metal The electrode layer includes a drain electrode layer, a source electrode layer, a gate electrode layer A and a gate electrode layer B, the gate electrode layer A and the gate electrode layer B are prepared in parallel on the substrate insulating material, and the gate electrode layer A and the gate electrode layer B are prepared in parallel on the substrate insulating material.
  • a gap is left between the gate electrode layers B to ensure electrical insulation between the two, the insulating layer completely covers the gate electrode layer A and the gate electrode layer B, and the drain electrode layer is placed on the gate electrode layer A
  • the left edge of the channel material layer above, the source electrode layer is placed on the right edge of the channel material layer above the gate motor layer B, that is, the gate electrode layer A and the gate electrode 1b in M1
  • the gate electrode layer A corresponds to the gate electrode 2b in M2
  • the gate electrode layer B corresponds to the gate electrode 1a in M1
  • the gate electrode layer B corresponds to the gate electrode 2a in M2.
  • the second input terminal V in2 inputs a high level
  • the output terminal V out outputs an AND gate
  • the logical operation result is AB
  • the second input terminal V in2 inputs a low level
  • the output terminal V out outputs an OR gate
  • the logical operation result is A+B
  • the second input terminal V in2 inputs a signal C, and the output terminal V out outputs a subtraction and borrow operation, and the result of the logic operation is
  • the third input terminal V in3 is at high level, and the output terminal V out outputs the result of the logic operation
  • the third input terminal V in3 is at low level, and the output terminal V out outputs the result of the logic operation
  • the output terminal is the signal following, and the logical operation result is A;
  • the output signal is always at a high level. If the first input terminal V in1 is at a high level is low level, the second input terminal V in2 is high level, then the output signal is always low level;
  • the output terminal V out implements a NOT gate, and the result of the logic operation is
  • the present invention also discloses a multifunctional logic circuit, which includes two of the unit circuits, which are respectively denoted as logic circuit E1 and logic circuit E2, and the output end corresponding to the logic circuit E1 is the same as the second output end of the logic circuit E2.
  • input terminal, a second input terminal V in2, a third input V in3, fourth input terminal V in4, 5 having a fifth input terminal and an output logic circuit, are denoted as a first input terminal V in1, Input V in5 .
  • the present invention also discloses a multifunctional logic circuit, which includes two of the unit circuits, which are denoted as logic circuit E1 and logic circuit E2 respectively, and the output end corresponding to the logic circuit E1 is connected to the third unit circuit of the logic circuit E2. connected to the input terminal, a logic circuit is formed having five inputs and one output terminal V out are respectively referred to as a first input terminal V in1, a second input terminal V in2, a third input V in3, fourth input terminal V in4 , the fifth input V in5 .
  • the present invention also discloses an adder and a subtractor logic circuit, which is formed by connecting three above-mentioned unit circuits in series, which are respectively denoted as a first unit, a second unit and a third unit.
  • the specific connection method is as follows: :
  • the first input terminal of the first unit is connected to the first input terminal of the second unit, and serves as the first input terminal of the logic circuit of the adder and the subtractor, and inputs the signal B;
  • the second input terminal of the first unit is connected to the third input terminal of the third unit, and is used as the second input terminal of the logic circuit of the adder and the subtractor to input signal A;
  • the third input terminal of the first unit is connected to the third input terminal of the second unit, and serves as the third input terminal of the logic circuit of the adder and the subtractor, and the input signal C;
  • the output end of the first unit is connected to the second input end of the second unit and the first input end of the third unit, as the first output end of the logic circuit of the adder and the subtractor, denoted as output signal B out ;
  • the output end of the second unit is connected with the second input end of the third unit, as the second output end of the logic circuit of the adder and the subtractor, denoted as the output signal C out ;
  • the output terminal of the third unit is used as the adder signal output terminal output signal Sum of the adder and the subtractor logic circuit or the signal output terminal output terminal of the subtractor outputting the signal Diff.
  • the input signal and output signal satisfy the Boolean logic operation:
  • the output signals B out and Diff respectively represent the result of the borrow operation and the difference operation result of the subtractor
  • the output signals C out and Sum respectively represent the result of the carry operation and the sum operation result of the adder.
  • the present invention discloses a design scheme of a multi-functional logic circuit based on a tunable homojunction field effect device. Through the operation of voltage biasing of two discrete gate electrodes, homojunctions with different device channels can be realized. state, and further apply source-drain voltages of different polarities to make the homojunction in a forward or reverse biased working state, so that the device exhibits a variety of switching functions, and a variety of functions can be realized through one device, saving cost and 2.
  • the logic unit circuit designed by the present invention has the ability to perform reconfigurable logic functions, and the logic circuit constructed by cascading unit circuits can not only perform full adder and subtractor, etc.
  • the required transistor resources and occupied area are greatly reduced, so the structure proposed by the present invention is simpler, and the circuit design scheme with reconfigurable logic function can meet the requirements of low power consumption in the future. It has great competitiveness in terms of consumption application requirements.
  • Fig. 1 is the front view of the tunable homojunction field effect device of embodiment 1;
  • Embodiment 2 is a top view of the tunable homojunction field effect device described in Embodiment 1;
  • Embodiment 3 is a right side view of the tunable homojunction field effect device described in Embodiment 1;
  • FIG. 5 is a schematic diagram of the unit circuit described in Embodiment 1, wherein FIG. 5 a is a circuit structure diagram, and FIG. 5 b is a multi-function circuit function table;
  • FIG. 6 is a schematic diagram of a logic circuit composed of the unit circuit described in Embodiment 1, wherein FIG. 6a is a circuit structure diagram, and FIG. 6b is a multi-function circuit function table;
  • FIG. 7 is a schematic diagram of another logic circuit composed of the unit circuit described in Embodiment 1, wherein FIG. 7a is a circuit structure diagram, and FIG. 7b is a multi-function circuit function table;
  • FIG. 8 is a schematic circuit diagram of the adder and the subtractor according to Embodiment 1, wherein FIG. 8a is a circuit structure diagram, and FIG. 8b is a truth table of input and output signals of a multifunctional circuit.
  • the present invention first introduces a tunable homojunction field effect device, which includes an insulating layer 3, a metal electrode layer, a channel material layer 2 and a substrate insulating material 1; a metal electrode
  • the layers include a drain electrode layer 41, a source electrode layer 42, a gate electrode layer A43, and a gate electrode layer B44.
  • the gate electrode layer A43 and the gate electrode layer B42 are prepared side by side on the substrate insulating material 1, and a gap is left therebetween to ensure that the gate electrode layer A43 and the gate electrode layer B44 cannot conduct.
  • the insulating layer 3 is laid on the gate electrode layer A43 and the gate electrode layer B42.
  • the channel material layer 2 is laid on the overlapping area of the gate electrode layer A43 and the gate electrode layer B44 and the insulating layer 3, to ensure that the insulating layer between the channel material layer 2 and the gate electrode layer A43 and the gate electrode layer B44 is ensured. 3 completely isolated.
  • the drain electrode layer 41 and the source electrode layer 42 are prepared directly above the channel material layer 2, and are placed directly above the left and right edges of the gate electrode layer A43 and the gate electrode layer B42, respectively, while ensuring that the drain electrode layer 41 And the source electrode layer 42 is completely isolated from the gate electrode layer A43 and the gate electrode layer B44 by the insulating layer 3 .
  • the channel material layer 2 is an intrinsic semiconductor, the band gap is in the range of 0.5-1.5 eV, and the material thickness is less than 30 nm, which can exhibit bipolar field effect characteristics.
  • the channel material layer 2 can be selected from low-dimensional semiconductor materials such as silicon nanowires, carbon nanotubes, two-dimensional layered materials, or organic semiconductor thin film materials.
  • the metal work function of the drain electrode layer 41 and the source electrode layer 42 is the middle energy value of the band gap of the channel material layer.
  • the gate insulating layer can be selected from insulating material layers such as a silicon dioxide layer, an aluminum oxide layer, a hafnium oxide layer, a hexagonal boron nitride layer, and a zirconium oxide layer.
  • a bias voltage V ds is applied to the drain electrode layer 41 , the source electrode layer 42 is grounded, the gate electrode layer A43 is applied with a gate voltage V gA , and the gate electrode layer B44 is applied with a gate voltage V gB .
  • the device channel material layer can be adjusted to be NN-type homojunction, PP-type homojunction, PN-type homojunction and NP-type homojunction under gate voltage bias.
  • V ds source-drain voltage
  • the forward bias or reverse bias state of the homojunction is further realized, so as to determine whether the current state of the device is on or off.
  • the specific regulation method is as follows:
  • the device scans V gB to realize the function of an N-type FET device.
  • V gB >0 the channel homojunction state is NN junction, the current state is on, when V gB ⁇ 0, the channel homojunction state is NP junction, and the current state is off.
  • V ds ⁇ 0 and V gA ⁇ 0 the device scans V gB to realize the function of a P-type FET device.
  • V gB >0 the channel homojunction state is PN junction, and the current state is off.
  • V gB ⁇ 0 the channel homojunction state is PP junction, and the current state is turned on.
  • the state of the channel homojunction is regulated as a PN junction, and the V ds is scanned to realize the function of a forward diode device, which is a forward diode.
  • V ds >0 the channel homojunction state is a forward-biased PN junction, and the current state is turned on.
  • V ds ⁇ 0 the channel homojunction state is a reverse-biased PN junction, and the current state is turned off.
  • the state of the channel homojunction is controlled to be an NP junction, which is embodied as a reverse diode, and the function of a forward diode device is realized by scanning V ds, When V ds >0, the channel homojunction state is a forward -biased NP junction, and the current state is turned off. When V ds ⁇ 0, the channel homojunction state is a reverse-biased NP junction, and the current state is turned on.
  • N-type FET N-type FET
  • P-type FET forward diode
  • reverse diode reverse diode
  • a multifunctional unit circuit structure E is constructed, and the structure includes:
  • the second input terminal V in2 is used for receiving the second input voltage signal
  • the third input terminal V in3 is used for receiving the third input voltage signal
  • the source S1 of the first tunable homojunction field effect transistor M1 is coupled to the first input terminal, the gate electrode 1a close to the source S1 is connected to the second input terminal, and the gate electrode 1b close to the drain is coupled to connected to the third input terminal;
  • the source S2 of the second tunable homojunction field effect transistor M2 is coupled to the third input terminal, the gate electrode 2a close to the source S2 is connected to the second input terminal, and the gate electrode 2b close to the drain is coupled to connected to the first input terminal;
  • the drain D of the first tunable homojunction field effect transistor is connected to the drain D of the second tunable homojunction field effect transistor, and the output of the connection point is used as the output terminal V out ;
  • the input signal V in2 and the input signal V in3 determine the type of the device channel homojunction, ie NN junction, PN junction, PP junction or NP junction, the input signal V in1 and the input signal
  • the relative potential of V in2 determines the source-drain voltage bias polarity of the device; for device M2, the input signal V in1 and the input signal V in2 determine the type of device channel homojunction, namely NN junction, PN junction, PP junction And the NP junction, the relative potential between the input signal Vin1 and the input signal Vin2 determines the source-drain voltage bias polarity of the device.
  • the circuit shown in FIG. 5a will sequentially exhibit 9 different logic operation functions according to the configuration scheme of the input signals V in1 , V in2 and V in3 shown in FIG. 5b , including 'AND gate', logic The operation result is AB; 'OR gate', the logical operation result is A+B; 'Not gate', the logical operation result is The signal follows, and the result of the logic operation is A; if the output is kept high, the result of the logic operation is 1; if the output is kept at a low level, the result of the logic operation is 0; 'essential implication', the result of the logic operation is The 'substantial implication' takes the 'not' operation, and the result of the logical operation is Subtraction and borrow operation, the result of the logical operation is
  • the circuit shown in FIG. 5a can be used to realize the three most basic logic functions, 'and', 'or' and 'not'.
  • the combination of these three logic functions can Implement arbitrary logic functions.
  • the circuit can perform 'substantial implication' logical operations, so it has a more diverse logic construction method. Therefore, taking the circuit of FIG. 1a as a basic unit, and by cascading and combining the basic units of the circuit, a logic circuit with an arbitrary computing function can be constructed with high efficiency.
  • the input signal V in1 and the input signal V in3 are input signal A and signal B respectively, the input signal V in2 is a fixed high level (logic 1), the output signal V out is an 'AND gate' respectively, and the result of the logic operation is AB;
  • the input signal V in2 is a fixed low level (logic 0)
  • the output signal V out is an 'OR gate'
  • the result of the logic operation is A+B.
  • Input signal V in1 is high level (logic 1)
  • input signal V in3 is low level (logic 0)
  • input signal V in1 is low level (logic 0)
  • input signal V in3 is high level (Logical 1)
  • the input signal V in2 is the input signal A
  • the output signal V out is a 'not gate'
  • the result of the logic operation is
  • the input signal V in1 and the input signal V in2 are both high level (logic 1), or the input signal V in1 and the input signal V in2 are both low level (logic 0), the input signal V in3 is the input signal A, Then the output signal V out is the result of the logic operation is A.
  • the input signal V in1 is high level (logic 1)
  • the input signal V in2 is low level (logic 0)
  • the input signal V in3 is input signal A, then the output signal is always high level (logic 1).
  • the input signal V in1 and the input signal V in2 respectively input the signal A and the signal B, the input signal V in3 is a fixed high level (logic 1), and the output signal V out is the result of the logic operation.
  • the input signal V in3 is a fixed low level (logic 0), and the output signal V out is a logic operation.
  • FIG. 6 in this embodiment, on the basis of the circuit structure E of the multifunctional unit, two basic circuit units as shown in FIG. 5 a are cascaded.
  • the circuit cascading method is shown in Figure 6a, the output terminal corresponding to the logic circuit E1 is connected to the second input terminal of the logic circuit E2 to form a logic circuit with five input terminals and one output terminal, which are respectively denoted as the first input terminal.
  • V in1 a second input terminal V in2, a third input V in3, fourth input terminal V in4, fifth input V in5.
  • FIG. 7 in this embodiment, two basic circuit units as shown in FIG. 5 a are cascaded.
  • the circuit cascading method is shown in Figure 7a, which are respectively denoted as logic circuit E1 and logic circuit E2.
  • the output terminal corresponding to logic circuit E1 is connected to the third input terminal of logic circuit E2, forming a circuit with five input terminals and one output terminal V out of the logic circuit, are denoted as a first input terminal V in1, a second input terminal V in2, a third input V in3, fourth input terminal V in4, fifth input V in5.
  • the 'AND gate' of three input signals can be realized in turn, and the logical operation result is ABC; 'AND OR gate', The result of logical operation is AB+C; 'OR gate', the result of logical operation is (A+B)C; 'Or gate', the result of logical operation is A+B+C.
  • the circuit structure implemented by the adder and the subtractor based on the tunable homogeneous junction field effect device in this embodiment includes three unit circuits, denoted as the first unit, the second unit and the The third unit, the specific connection method is:
  • the first input terminal of the first unit is connected to the first input terminal of the second unit, and serves as the first input terminal of the logic circuit of the adder and the subtractor, and inputs the signal B;
  • the second input terminal of the first unit is connected to the third input terminal of the third unit, and is used as the second input terminal of the logic circuit of the adder and the subtractor to input signal A;
  • the third input terminal of the first unit is connected to the third input terminal of the second unit, and serves as the third input terminal of the logic circuit of the adder and the subtractor, and the input signal C;
  • the output end of the first unit is connected to the second input end of the second unit and the first input end of the third unit, as the first output end of the logic circuit of the adder and the subtractor, denoted as output signal B out ;
  • the output end of the second unit is connected with the second input end of the third unit, as the second output end of the logic circuit of the adder and the subtractor, denoted as the output signal C out ;
  • the output terminal of the third unit is used as the adder signal output terminal of the adder and the subtractor logic circuit to output the signal Sum or the signal output terminal of the subtractor to output the signal Diff.
  • the input signal B is input to the source terminal (S) of the device M1, and the gate electrode (2b) near the drain terminal (D) of the device M2;
  • the input signal C is input to the source terminal (S) of the device M2, and Gate electrode (1b) near the drain (D) of device M1;
  • input signal A is input to the gate electrode (1a) near the source (S) of device M1, and gate electrode (1a) near the source (S) of device M2 (2a).
  • the output signal B out is output through the connection point of the drain terminal (D) of the device M1 and the device M2; the input signal and the output signal satisfy the Boolean logic operation:
  • the input signal B is input to the source terminal (S) of device M3, and to the gate electrode (4b) near the drain terminal (D) of device M4.
  • the input signal C is input to the source terminal (S) of device M4, and to the gate electrode (3b) near the drain terminal (D) of device M3.
  • the output signal Bout of the circuit of unit 1 is input to the gate electrode (3a) near the source terminal (S) of device M3, and the gate electrode (4a) near the source terminal (S) of device M4.
  • the output signal C out is output via the drain (D) connection point of the device M3 and the device M4.
  • the input signal and output signal satisfy the Boolean logic operation:
  • the output signal B out of the unit 1 circuit is input to the source terminal (S) of the device M5, and the gate electrode (6b) near the drain terminal (D) of the device M6.
  • the input signal A is input to the source terminal (S) of the device M6, and to the gate electrode (5b) near the drain terminal (D) of the device M5.
  • the output signal C out of the circuit of unit 2 is input to the gate electrode (5a) near the source terminal (S) of the device M5, and the gate electrode (6a) near the source terminal (S) of the device M6.
  • the output signal Sum or Diff is output via the drain (D) connection point of the device M5 and the device M6.
  • the input signal and output signal satisfy the Boolean logic operation:
  • the circuit input signals are A, B and C
  • the output signals are B out , C out and Sum (or Diff).
  • the output signals B out and Diff respectively represent the result of the borrow operation and the difference operation result of the subtractor
  • the output signals C out and Sum respectively represent the result of the carry operation and the sum operation result of the adder.
  • the logic unit circuit designed by the present invention has the ability to perform reconfigurable logic functions, and the logic circuit constructed by cascading unit circuits can not only perform logic functions such as full adder and subtractor, but also The required transistor resources and footprint are greatly reduced compared to conventional CMOS technology. Therefore, the structure proposed by the present invention is simpler, and the circuit design scheme with reconfigurable logic function has great competitiveness in meeting the requirements of low power consumption applications in the future.

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Abstract

本发明公开了基于可调同质结场效应器件的单元电路以及多功能逻辑电路，对应的设计方案包括四步：可调同质结器件的结构搭建、可调同质结器件的多功能电学操作实现、基本逻辑单元电路的设计以及级联单元逻辑电路实现复杂逻辑功能；本发明首先设计了基于双极性场效应特性材料的可调同质结器件；然后在该器件中引入源漏电压的极性作为额外的控制信号，进一步，通过对三个可重构逻辑单元进行级联，设计出了具有执行全加器和减法器逻辑功能的多功能逻辑电路，本发明所设计的逻辑单元电路具有执行可重构逻辑功能的能力。利用级联单元电路构建的逻辑电路不仅能够同时执行全加器和减法器等逻辑功能，而且所需要的晶体管资源和所占面积相比于传统CMOS技术得到极大地减少。

Description

基于可调同质结场效应器件的单元电路及多功能逻辑电路 技术领域
本发明涉及半导体材料和器件领域，具体涉及一种基于可调同质结场效应器件的单元电路，以及在该单元电路基础上得到的多功能逻辑电路、加法器和减法器的逻辑电路。
背景技术
随着诸如人工智能，物联网，可植入医疗等新型电子应用产业的兴起，具有低功耗、柔性、生物相容性等新兴需求的多功能逻辑电路逐渐成为研究热点。而传统硅基逻辑电路难以满足诸如此类的多样化的应用需求，一方面，硅基器件功能单一，构建多功能逻辑电路需要耗费大量晶体管资源，这会增加电路的功耗；另一方面，硅基器件难以满足柔性、生物相容性等需求，使得硅基逻辑电路难以应用于相关领域。
发明内容
发明目的：为了克服现有技术的不足，本发明提供一种基于可调同质结场效应器件的单元电路，其解决了多功能逻辑电路需要的晶体管多，资源浪费的问题。
技术方案：一方面，本发明公开基于可调同质结场效应器件的单元电路，所述单元电路E包括：
第一输入端V in1，用于接收第一输入电压信号；
第二输入端V in2，用于接收第二输入电压信号；
第三输入端V in3，用于接收第三输入电压信号；
第一可调同质结场效应晶体管M1，其源极S1耦接至第一输入端，所述靠近源极S1的栅极电极1a连接至第二输入端，其靠近漏极的栅极电极1b耦接至第三输入端；
第二可调同质结场效应晶体管M2，其源极S2耦接至第三输入端，所述靠近源极S2的栅极电极2a连接至第二输入端，其靠近漏极的栅极电极2b耦接至第一输入端；
所述第一可调同质结场效应晶体管与第二可调同质结场效应晶体管的漏极相连，并由其连接点的输出作为输出端V out；
所述第一可调同质结场效应晶体管M1和第二可调同质结场效应晶体管M2的结构相同，包括衬底绝缘材料、沟道材料层、绝缘层和金属电极层；所述金属电极层包括漏电极层、源电极层、栅电极层A和栅电极层B，所述栅极电极层A和栅电极层B并列制备于衬底绝缘材料之上，且栅极电极层A和栅电极层B之间留有间隙，保证二者之 间电绝缘，绝缘层完全覆盖于栅极电极层A和栅电极层B之上，所述漏电极层置于所述栅极电极层A上方的沟道材料层的左侧边缘，所述源电极层置于所述栅极电机层B上方的沟道材料层的右侧边缘，即栅极电极层A与M1中的栅极电极1b对应，栅极电极层A与M2中的栅极电极2b对应，栅极电极层B与M1中的栅极电极1a对应，栅极电极层B与M2中的栅极电极2a对应。
进一步的，包括：
若第一输入端V in1和第三输入端V in3分别输入信号A和信号B，第二输入端V in2输入高电平，输出端V out输出为与门，逻辑运算结果为AB，
第二输入端V in2输入低电平，输出端V out输出为或门，逻辑运算结果为A+B，
第二输入端V in2输入信号C，输出端V out输出为减法借位运算，逻辑运算结果为
Figure PCTCN2020099817-appb-000001
若第一输入端V in1和第二输入端V in2分别输入信号A和信号B，第三输入端V in3为高电平，输出端V out输出逻辑运算结果
Figure PCTCN2020099817-appb-000002
第三输入端V in3为低电平，输出端V out输出逻辑运算结果
Figure PCTCN2020099817-appb-000003
若第三输入端V in3为输入信号A，第一输入端V in1和第二输入端V in2为相同的电平，则输出端为信号跟随，逻辑运算结果为A；
若第三输入端V in3为输入信号A，第一输入端V in1为高电平，第二输入端V in2为低电平，则输出信号恒为高电平，若第一输入端V in1为低电平，第二输入端V in2为高电平，则输出信号恒为低电平；
若第一输入端V in1与所述第三输入端V in3为相反的电平，输入信号Vin2为输入信号A，则输出端V out实现非门，逻辑运算结果为
Figure PCTCN2020099817-appb-000004
本发明还公开一种多功能逻辑电路，其包括两个所述的单元电路，分别记为逻辑电路E1和逻辑电路E2，所述逻辑电路E1对应的输出端与所述逻辑电路E2的第二输入端相连，形成具有5个输入端和一个输出端逻辑电路，分别记为第一输入端V in1，第二输入端V in2，第三输入端V in3，第四输入端V in4，第五输入端V in5。
进一步的，包括：
若第一输入端V in1和第三输入端V in3分别输入信号A和B，第四输入端V in4和第五输入端V in5输入相反的电平，第二输入端V in2输入高电平，则实现与非门，逻辑运算结果为
Figure PCTCN2020099817-appb-000005
第二输入端V in2输入低电平，则实现或非门，逻辑运算结果为
Figure PCTCN2020099817-appb-000006
若第四输入端V in4和第五输入端V in5分别输入信号A和B，第二输入端V in2输入信号C，第一输入端V in1和第三输入端V in3输入相反的电平，则实现多数门，逻辑运算结果为AB+BC+AC。
本发明还公开一种多功能逻辑电路，其包括2个所述的单元电路，分别记为逻辑电路E1和逻辑电路E2，所述逻辑电路E1对应的输出端与所述逻辑电路E2的第三输入端相连，形成具有5个输入端和一个输出端V out的逻辑电路，分别记为第一输入端V in1，第二输入端V in2，第三输入端V in3，第四输入端V in4，第五输入端V in5。
进一步的，包括：
在第一输入端V in1、第三输入端V in3、第四输入端V in4分别输入信号A、B和C，若第二输入端V in2和第五输入端V in5均输入高电平，则实现与门，输出端V out输出ABC；
若第二输入端V in2和第五输入端V in5均输入低电平，则实现或门，输出端V out输出A+B+C；
若第二输入端V in2为高电平，第五输入端V in5输入低电平，则实现与或门，输出端V out输出AB+C；
若第二输入端V in2为低电平，第五输入端V in5输入高电平，则实现或与门，输出端V out输出(A+B)C。
另外的，本发明还公开一种加法器和减法器逻辑电路，其由三个上述所述的单元电路串联而成，分别记为第一单元、第二单元和第三单元，具体连接方式为：
第一单元的第一输入端与所述第二单元的第一输入端相连，作为所述加法器和减法器逻辑电路的第一个输入端，输入信号B；
第一单元的第二输入端与所述第三单元的第三输入端连接，作为所述加法器和减法器逻辑电路的第二个输入端，输入信号A；
第一单元的第三输入端与所述第二单元的第三输入端连接，作为所述加法器和减法器逻辑电路的第三个输入端，输入信号C；
第一单元的输出端与所述第二单元的第二输入端以及第三单元的第一输入端连接，作为所述加法器和减法器逻辑电路的第一个输出端，记为输出信号B out；
第二单元的输出端与所述第三单元的第二输入端连接，作为所述加法器和减法器逻辑电路的第二个输出端，记为输出信号C out；
所述第三单元的输出端作为所述加法器和减法器逻辑电路的加法器信号输出端输 出信号Sum或减法器的信号输出端输出信号Diff。
进一步的，包括：
输入信号和输出信号满足布尔逻辑运算：
Figure PCTCN2020099817-appb-000007
输入信号和输出信号满足布尔逻辑运算：
Figure PCTCN2020099817-appb-000008
输入信号和输出信号满足布尔逻辑运算：
Figure PCTCN2020099817-appb-000009
Figure PCTCN2020099817-appb-000010
其中，输出信号B out和Diff分别代表减法器的借位运算结果和差值运算结果，输出信号C out和Sum分别代表了加法器的进位运算结果和求和运算结果。
有益效果：1、本发明公开了基于可调同质结场效应器件的多功能逻辑电路的设计方案，通过两个分立栅极电极的电压偏置的操作可以实现器件沟道不同的同质结状态，进一步施加不同极性的源漏电压使得同质结处于正偏或反偏工作状态，从而让器件表现出多样化的开关功能，通过一种器件就可以实现多种功能，节省了成本和资源；2、通过对器件功能的充分利用，本发明所设计的逻辑单元电路具有执行可重构逻辑功能的能力，进一步通过级联单元电路构建的逻辑电路不仅能够执行全加器和减法器等逻辑功能，而且所需要的晶体管资源和所占面积相比于传统CMOS技术得到极大地减少，因此本发明所提出的结构更加简单，并且具有可重构逻辑功能的电路设计方案在未来满足低功耗应用需求方面具有很大的竞争力。
附图说明
图1为实施例1可调同质结场效应器件的正视图；
图2为实施例1所述的可调同质结场效应器件的俯视图；
图3为实施例1所述的可调同质结场效应器件的右视图；
图4为实施例1可调同质结场效应器件在不同电学操作下的器件功能表；
图5为实施例1所述的单元电路的原理图，其中图5a为电路结构图，图5b为多功能电路功能表；
图6为实施例1所述的单元电路组成的一种逻辑电路的原理图，其中图6a为电路结构图，图6b为多功能电路功能表；
图7为实施例1所述的单元电路组成的另一种逻辑电路的原理图，其中图7a为电路结构图，图7b为多功能电路功能表；
图8为实施例1所述的加法器和减法器的电路原理图，其中图8a为电路结构图，图8b为多功能电路输入输出信号真值表。
具体实施方式
实施例1
如图1、图2及图3所示，本发明首先介绍基于可调同质结场效应器件，其包括绝缘层3、金属电极层、沟道材料层2和衬底绝缘材料1；金属电极层包括漏电极层41、源电极层42、栅电极层A43和栅电极层B44。
栅极电极层A43和栅电极层B42并列制备于衬底绝缘材料1之上，其间留有间隙保证栅极电极层A43和栅极电极层B44不能导通。绝缘层3铺设于栅极电极层A43和栅极电极层B42之上。沟道材料层2铺设于栅极电极层A43和栅极电极层B44与绝缘层3重合区域之上，保证沟道材料层2和栅极电极层A43和栅极电极层B44之间被绝缘层3完全隔离。将漏电极层41和源电极层42制备于沟道材料层2正上方，分别置于栅极电极层A43和栅极电极层B42左侧边缘和右侧边缘正上方，同时保证漏电极层41和源电极层42与栅极电极层A43和栅极电极层B44被绝缘层3完全隔离。
在本实施例中，沟道材料层2为本征半导体，带隙范围在0.5～1.5eV，材料厚度<30nm，可以表现出双极性场效应特性。沟道材料层2可以选用硅纳米线，碳纳米管，二维层状材料，或有机半导体薄膜材料等低维半导体材料。漏电极层41和源电极层42的金属功函数大小为沟道材料层带隙的中间能量值。
在本实施例中，栅极绝缘层可选择二氧化硅层、氧化铝层、氧化铪层、六角氮化硼层、氧化锆层等绝缘性材料层。
如图1所示，漏电极层41施加偏置电压V ds，源电极层42接地，栅极电极层A43施加栅极电压V gA，栅极电极层B44施加栅极电压V gB。
在本实施例中，器件沟道材料层在栅极电压偏置下可被调控为NN型同质结，PP型同质结，PN型同质结和NP型同质结，在不同极性的源漏电压(V ds)的操作下进一步实现同质结的正偏或反偏状态，从而确定器件的电流状态是导通或截止，具体调控方式为：
如图4所示，在本实施例中，器件在V ds>0且V gA>0时，扫描V gB实现N型FET器件功能，当V gB>0，则沟道同质结状态为NN结，电流状态导通，当V gB<0，则沟道同质结状态为NP结，电流状态截止。
在本实施例中，器件在V ds<0且V gA<0时，扫描V gB实现P型FET器件功能，当V gB>0，则沟道同质结状态为PN结，电流状态截止，当V gB<0，则沟道同质结状态为 PP结，电流状态导通。
在本实施例中，器件在V gA<0且V gB>0的组合操作下，沟道同质结状态被调控为PN结，扫描V ds实现正向二极管器件功能，为正向二极管，当V ds>0，则沟道同质结状态为正偏PN结，电流状态导通，当V ds<0，则沟道同质结状态为反偏PN结，电流状态截止。
在本实施例中，器件在V gA>0且V gB<0的组合操作下，沟道同质结状态被调控为NP结，体现为反向二极管，扫描V ds实现正向二极管器件功能，当V ds>0，则沟道同质结状态为正偏NP结，电流状态截止，当V ds<0，则沟道同质结状态为反偏NP结，电流状态导通。
由此基于单一器件在不同电学操作下可实现N型FET，P型FET，正向二极管和反向二极管的器件功能。
如图5a所示，在上述可调同质结场效应器件的基础上，构建多功能单元电路结构E，该结构包括：
第一输入端V in1，用于接收第一输入电压信号；
第二输入端V in2，用于接收第二输入电压信号；
第三输入端V in3，用于接收第三输入电压信号；
第一可调同质结场效应晶体管M1，其源极S1耦接至第一输入端，靠近源极S1的栅极电极1a连接至第二输入端，其靠近漏极的栅极电极1b耦接至第三输入端；
第二可调同质结场效应晶体管M2，其源极S2耦接至第三输入端，靠近源极S2的栅极电极2a连接至第二输入端，其靠近漏极的栅极电极2b耦接至第一输入端；
第一可调同质结场效应晶体管的漏极D与第二可调同质结场效应晶体管的漏极D相连，并由其连接点的输出作为输出端V out；
在本实施例中，对于器件M1，输入信号V in2和输入信号V in3决定了器件沟道同质结的类型，即NN结，PN结，PP结或NP结，输入信号V in1和输入信号V in2的相对电势决定了器件的源漏电压偏置极性；对于器件M2，输入信号V in1和输入信号V in2决定了器件沟道同质结的类型，即NN结，PN结，PP结和NP结，输入信号V in1和输入信号V in2之间的相对电势决定了器件的源漏电压偏置极性。
本实施例中，图5a所示的电路根据如图5b所示的输入信号V in1，V in2和V in3配置方案，将依次表现出9种不同的逻辑运算功能，包括‘与门’，逻辑运算结果为AB； ‘或门’，逻辑运算结果为A+B；‘非门’，逻辑运算结果为
Figure PCTCN2020099817-appb-000011
信号跟随，逻辑运算结果为A；保持高电平输出，逻辑运算结果为1；保持低电平输出，逻辑运算结果为0；‘实质蕴涵’，逻辑运算结果为
Figure PCTCN2020099817-appb-000012
‘实质蕴涵’取‘非’运算，逻辑运算结果为
Figure PCTCN2020099817-appb-000013
减法借位运算，逻辑运算结果为
Figure PCTCN2020099817-appb-000014
本实施例中，如图5a所示的电路能够被用来实现最基本的三种逻辑功能，‘与’，‘或’和‘非’，从原理上讲，这三个逻辑功能的组合可以实现任意的逻辑功能。进一步，该电路能够执行‘实质蕴涵’逻辑运算，因而具备了更加多元的逻辑构建方式。因此，以图1a的电路为基本单元，通过对电路进行基本单元的级联组合，可以高效率的构建具有执行任意计算功能的逻辑电路。
具体的9中运算功能的实现方法为，如图5b所示：
1、输入信号V in1和输入信号V in3分别输入信号A和信号B，输入信号V in2为固定高电平(逻辑1)，输出信号V out分别为‘与门’，逻辑运算结果为AB；
输入信号V in2为固定低电平(逻辑0)，输出信号V out分别为‘或门’，逻辑运算结果为A+B。
2、输入信号V in1为高电平(逻辑1)，输入信号V in3为低电平(逻辑0)，或输入信号V in1为低电平(逻辑0)，输入信号V in3为高电平(逻辑1)，输入信号V in2为输入信号A，则输出信号V out为‘非门’，逻辑运算结果为
Figure PCTCN2020099817-appb-000015
3、输入信号V in1和输入信号V in2均为高电平(逻辑1)，或输入信号V in1和输入信号V in2均为低电平(逻辑0)，输入信号V in3为输入信号A，则输出信号V out为逻辑运算结果为A。
4、输入信号V in1为高电平(逻辑1)，输入信号V in2为低电平(逻辑0)，输入信号V in3为输入信号A，则输出信号恒为高电平(逻辑1)。
5、输入信号V in1为低电平(逻辑0)，输入信号V in2为高电平(逻辑1)，输入信号V in3为输入信号A，则输出信号恒为低电平(逻辑0)。
6、输入信号V in1和输入信号V in2分别输入信号A和信号B，输入信号V in3为固定高电平(逻辑1)，输出信号V out为逻辑运算结果为
Figure PCTCN2020099817-appb-000016
输入信号V in3为固定低电平(逻辑0)，输出信号V out为逻辑运算结果为
Figure PCTCN2020099817-appb-000017
7、输入信号V in1，输入信号V in2和输入信号V in3分别输入信号A，信号B和信号C,则输出信号
Figure PCTCN2020099817-appb-000018
本实施例只需采用两个元器件，就可实现多种逻辑功能，节省了资源。
进一步的，如图6所示，本实施例在上述多功能单元电路结构E的基础上，将两个如图5a所示的电路基本单元进行级联。电路级联方式如图6a所示，逻辑电路E1对应的输出端与所述逻辑电路E2的第二输入端相连，形成具有5个输入端和一个输出端逻辑电路，分别记为第一输入端V in1，第二输入端V in2，第三输入端V in3，第四输入端V in4，第五输入端V in5。
本实施例中，基于如图6a所示的电路结构，在如图6b所示的输入信号操作方式下，可以依次实现‘与非门’，逻辑运算结果为
Figure PCTCN2020099817-appb-000019
‘或非门’，逻辑运算结果为
Figure PCTCN2020099817-appb-000020
‘多数门’，逻辑运算结果为AB+BC+AC，具体实现方式为：
(1)若第一输入端V in1和第三输入端V in3分别输入信号A和B，第四输入端V in4和第五输入端V in5输入相反的电平，第二输入端V in2输入高电平，则实现与非门，逻辑运算结果为
Figure PCTCN2020099817-appb-000021
(2)第二输入端V in2输入低电平，则实现或非门，逻辑运算结果为
Figure PCTCN2020099817-appb-000022
(3)若第四输入端V in4和第五输入端V in5分别输入信号A和B，第二输入端V in2输入信号C，第一输入端V in1和第三输入端V in3输入相反的电平，则实现多数门，逻辑运算结果为AB+BC+AC。
进一步的，如图7所示，本实施例将两个如图5a所示的电路基本单元进行级联。电路级联方式如图7a所示，分别记为逻辑电路E1和逻辑电路E2，逻辑电路E1对应的输出端与逻辑电路E2的第三输入端相连，形成具有5个输入端和一个输出端V out的逻辑电路，分别记为第一输入端V in1，第二输入端V in2，第三输入端V in3，第四输入端V in4，第五输入端V in5。
本实施例中，基于如图7a所示的电路，根据如图7b所示的信号输入操作方式，可以依次实现三输入信号的‘与门’，逻辑运算结果为ABC；‘与或门’，逻辑运算结果为AB+C；‘或与门’，逻辑运算结果为(A+B)C；‘或门’，逻辑运算结果为A+B+C。
为了实现上述逻辑功能，具体实现方式为：
(1)在第一输入端V in1、第三输入端V in3、第四输入端V in4分别输入信号A、B和C，若第二输入端V in2和第五输入端V in5均输入高电平，则实现与门，输出端V out输出ABC；
(2)若第二输入端V in2和第五输入端V in5均输入低电平，则实现或门，输出端V out 输出A+B+C；
(3)若第二输入端V in2为高电平，第五输入端V in5输入低电平，则实现与或门，输出端V out输出AB+C；
(4)若第二输入端V in2为低电平，第五输入端V in5输入高电平，则实现或与门，输出端V out输出(A+B)C。
进一步的，如图8a所示，本实施例的基于可调同质结场效应器件的加法器和减法器实现的电路结构，包括三个单元电路，分别记为第一单元、第二单元和第三单元，具体连接方式为：
第一单元的第一输入端与所述第二单元的第一输入端相连，作为所述加法器和减法器逻辑电路的第一个输入端，输入信号B；
第一单元的第二输入端与所述第三单元的第三输入端连接，作为所述加法器和减法器逻辑电路的第二个输入端，输入信号A；
第一单元的第三输入端与所述第二单元的第三输入端连接，作为所述加法器和减法器逻辑电路的第三个输入端，输入信号C；
第一单元的输出端与所述第二单元的第二输入端以及第三单元的第一输入端连接，作为所述加法器和减法器逻辑电路的第一个输出端，记为输出信号B out；
第二单元的输出端与所述第三单元的第二输入端连接，作为所述加法器和减法器逻辑电路的第二个输出端，记为输出信号C out；
所述第三单元的输出端作为所述加法器和减法器逻辑电路的加法器信号输出端输出信号Sum或减法器的信号输出端输出信号Diff。
每个单元的具体结构以及各个单元之间的连接方式为：
对于第一单元电路，输入信号B输入器件M1的源端(S)，和器件M2漏端(D)附近的栅极电极(2b)；输入信号C输入器件M2的源端(S)，和器件M1漏端(D)附近的栅极电极(1b)；输入信号A输入器件M1的源端(S)附近的栅极电极(1a)，和器件M2源端(S)附近的栅极电极(2a)。输出信号B out经由器件M1和器件M2的漏端(D)连接点输出；输入信号和输出信号满足布尔逻辑运算：
Figure PCTCN2020099817-appb-000023
对于单元2电路，输入信号B输入器件M3的源端(S)，和器件M4漏端(D)附近的栅极电极(4b)。输入信号C输入器件M4的源端(S)，和器件M3漏端(D)附近的栅极电极(3b)。单元1电路的输出信号B out输入器件M3的源端(S)附近的栅 极电极(3a)，和器件M4源端(S)附近的栅极电极(4a)。输出信号C out经由器件M3和器件M4的漏端(D)连接点输出。输入信号和输出信号满足布尔逻辑运算：
Figure PCTCN2020099817-appb-000024
对于单元3电路，单元1电路的输出信号B out输入器件M5的源端(S)，和器件M6漏端(D)附近的栅极电极(6b)。输入信号A输入器件M6的源端(S)，和器件M5漏端(D)附近的栅极电极(5b)。单元2电路的输出信号C out输入器件M5的源端(S)附近的栅极电极(5a)，和器件M6源端(S)附近的栅极电极(6a)。输出信号Sum或Diff经由器件M5和器件M6的漏端(D)连接点输出。输入信号和输出信号满足布尔逻辑运算：
Figure PCTCN2020099817-appb-000025
本实施例中，电路输入信号为A、B和C，输出信号为B out、C out和Sum(或Diff)。其中，输出信号B out和Diff分别代表减法器的借位运算结果和差值运算结果，输出信号C out和Sum分别代表了加法器的进位运算结果和求和运算结果。由此，基于同一电路同时实现了加法器和减法器的逻辑运算。
如图8b所示，为图8a电路的输入输出真值表，
当A、B和C均为高电平，输出端B out为高电平，输出端C out为高电平，输出端Sum或Diff为高电平；
当A、B均为高电平，C为低电平，输出端B out为低电平，输出端C out为高电平，输出端Sum或Diff为低电平；
当A、C均为高电平，B为低电平，输出端B out为低电平，输出端C out为高电平，输出端Sum或Diff为低电平；
当B、C均为低电平，A为高电平，输出端B out为低电平，输出端C out为低电平，输出端Sum或Diff为高电平；
当B、C均为高电平，A为低电平，输出端B out为高电平，输出端C out为高电平，输出端Sum或Diff为低电平；
当A、C均为低电平，B为高电平，输出端B out为高电平，输出端C out为低电平，输出端Sum或Diff为高电平；
当B、A均为低电平，C为高电平，输出端B out为高电平，输出端C out为低电平，输出端Sum或Diff为高电平；
当A、B、C均为低电平，输出端B out为低电平，输出端C out为低电平，输出端Sum 或Diff为低电平。
通过对器件功能的充分利用，本发明所设计的逻辑单元电路具有执行可重构逻辑功能的能力，进一步通过级联单元电路构建的逻辑电路不仅能够执行全加器和减法器等逻辑功能，而且所需要的晶体管资源和所占面积相比于传统CMOS技术得到极大地减少。因此本发明所提出的结构更加简单，并且具有可重构逻辑功能的电路设计方案在未来满足低功耗应用需求方面具有很大的竞争力。

Claims (8)

  1. 一种基于可调同质结场效应器件的单元电路，其特征在于，所述单元电路E包括：
    第一输入端V in1，用于接收第一输入电压信号；
    第二输入端V in2，用于接收第二输入电压信号；
    第三输入端V in3，用于接收第三输入电压信号；
    第一可调同质结场效应晶体管M1，其源极S1耦接至第一输入端，所述靠近源极S1的栅极电极1a连接至第二输入端，其靠近漏极的栅极电极1b耦接至第三输入端；
    第二可调同质结场效应晶体管M2，其源极S2耦接至第三输入端，所述靠近源极S2的栅极电极2a连接至第二输入端，其靠近漏极的栅极电极2b耦接至第一输入端；
    所述第一可调同质结场效应晶体管的漏极与第二可调同质结场效应晶体管的漏极相连，并由其连接点的输出作为输出端V out；
    所述第一可调同质结场效应晶体管M1和第二可调同质结场效应晶体管M2的结构相同，包括衬底绝缘材料、沟道材料层、绝缘层和金属电极层；所述金属电极层包括漏电极层、源电极层、栅电极层A和栅电极层B，所述栅极电极层A和栅电极层B并列制备于衬底绝缘材料之上，且栅极电极层A和栅电极层B之间留有间隙，保证二者之间电绝缘，绝缘层完全覆盖于栅极电极层A和栅电极层B之上，所述漏电极层置于所述栅极电极层A上方的沟道材料层的左侧边缘，所述源电极层置于所述栅极电机层B上方的沟道材料层的右侧边缘，即栅极电极层A与M1中的栅极电极1b对应，栅极电极层A与M2中的栅极电极2b对应，栅极电极层B与M1中的栅极电极1a对应，栅极电极层B与M2中的栅极电极2a对应。
  2. 根据权利要求1所述的基于可调同质结场效应器件的单元电路，其特征在于，若第一输入端V in1和第三输入端V in3分别输入信号A和信号B，第二输入端V in2输入高电平，输出端V out输出为与门，逻辑运算结果为AB，
    第二输入端V in2输入低电平，输出端V out输出为或门，逻辑运算结果为A+B，
    第二输入端V in2输入信号C，输出端V out输出为减法借位运算，逻辑运算结果为
    Figure PCTCN2020099817-appb-100001
    若第一输入端V in1和第二输入端V in2分别输入信号A和信号B，第三输入端V in3为高电平，输出端V out输出逻辑运算结果
    Figure PCTCN2020099817-appb-100002
    第三输入端V in3为低电平，输出端V out输出逻辑运算结果
    Figure PCTCN2020099817-appb-100003
    若第三输入端V in3为输入信号A，第一输入端V in1和第二输入端V in2为相同的电平，则输出端为信号跟随，逻辑运算结果为A；
    若第三输入端V in3为输入信号A，第一输入端V in1为高电平，第二输入端V in2为低电平，则输出信号恒为高电平，若第一输入端V in1为低电平，第二输入端V in2为高电平，则输出信号恒为低电平；
    若第一输入端V in1与所述第三输入端V in3为相反的电平，输入信号V in2为输入信号A，则输出端V out实现非门，逻辑运算结果为
    Figure PCTCN2020099817-appb-100004
  3. 一种多功能逻辑电路，其特征在于，其包括两个权利要求1所述的单元电路，分别记为逻辑电路E1和逻辑电路E2，所述逻辑电路E1对应的输出端与所述逻辑电路E2的第二输入端相连，形成具有5个输入端和一个输出端逻辑电路，分别记为第一输入端V in1，第二输入端V in2，第三输入端V in3，第四输入端V in4，第五输入端V in5。
  4. 根据权利要求3所述的多功能逻辑电路，其特征在于，若第一输入端V in1和第三输入端V in3分别输入信号A和B，第四输入端V in4和第五输入端V in5输入相反的电平，第二输入端V in2输入高电平，则实现与非门，逻辑运算结果为
    Figure PCTCN2020099817-appb-100005
    第二输入端V in2输入低电平，则实现或非门，逻辑运算结果为
    Figure PCTCN2020099817-appb-100006
    若第四输入端V in4和第五输入端V in5分别输入信号A和B，第二输入端V in2输入信号C，第一输入端V in1和第三输入端V in3输入相反的电平，则实现多数门，逻辑运算结果为AB+BC+AC。
  5. 一种多功能逻辑电路，其特征在于，其包括2个权利要求1所述的单元电路，分别记为逻辑电路E1和逻辑电路E2，所述逻辑电路E1对应的输出端与所述逻辑电路E2的第三输入端相连，形成具有5个输入端和一个输出端V out的逻辑电路，分别记为第一输入端V in1，第二输入端V in2，第三输入端V in3，第四输入端V in4，第五输入端V in5。
  6. 根据权利要求5所述的多功能逻辑电路，其特征在于，在第一输入端V in1、第三输入端V in3、第四输入端V in4分别输入信号A、B和C，若第二输入端V in2和第五输入端V in5均输入高电平，则实现与门，输出端V out输出ABC；
    若第二输入端V in2和第五输入端V in5均输入低电平，则实现或门，输出端V out输出A+B+C；
    若第二输入端V in2为高电平，第五输入端V in5输入低电平，则实现与或门，输出端V out输出AB+C；
    若第二输入端V in2为低电平，第五输入端V in5输入高电平，则实现或与门，输出端V out输出(A+B)C。
  7. 一种加法器和减法器逻辑电路，其特征在于，其由三个权利要求1所述的单元电路级联而成，分别记为第一单元、第二单元和第三单元，具体连接方式为：
    第一单元的第一输入端与所述第二单元的第一输入端相连，作为所述加法器和减法器逻辑电路的第一个输入端，输入信号B；
    第一单元的第二输入端与所述第三单元的第三输入端连接，作为所述加法器和减法器逻辑电路的第二个输入端，输入信号A；
    第一单元的第三输入端与所述第二单元的第三输入端连接，作为所述加法器和减法器逻辑电路的第三个输入端，输入信号C；
    第一单元的输出端与所述第二单元的第二输入端以及第三单元的第一输入端连接，作为所述加法器和减法器逻辑电路的第一个输出端，记为输出信号B out；
    第二单元的输出端与所述第三单元的第二输入端连接，作为所述加法器和减法器逻辑电路的第二个输出端，记为输出信号C out；
    所述第三单元的输出端作为所述加法器和减法器逻辑电路的加法器信号输出端输出信号Sum或减法器的信号输出端输出信号Diff。
  8. 根据权利要求7所述的加法器和减法器逻辑电路，其特征在于，
    输入信号和输出信号满足布尔逻辑运算：
    Figure PCTCN2020099817-appb-100007
    输入信号和输出信号满足布尔逻辑运算：
    Figure PCTCN2020099817-appb-100008
    输入信号和输出信号满足布尔逻辑运算：
    Figure PCTCN2020099817-appb-100009
    C，其中，输出信号B out和Diff分别代表减法器的借位运算结果和差值运算结果，输出信号C out和Sum分别代表了加法器的进位运算结果和求和运算结果。
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