WO2024036509A1 - 图像传感运算单元及其操作方法、图像传感运算器和电子设备 - Google Patents

图像传感运算单元及其操作方法、图像传感运算器和电子设备 Download PDF

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WO2024036509A1
WO2024036509A1 PCT/CN2022/113040 CN2022113040W WO2024036509A1 WO 2024036509 A1 WO2024036509 A1 WO 2024036509A1 CN 2022113040 W CN2022113040 W CN 2022113040W WO 2024036509 A1 WO2024036509 A1 WO 2024036509A1
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unit
photosensitive unit
image sensing
photosensitive
control voltage
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PCT/CN2022/113040
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English (en)
French (fr)
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周正
于贵海
刘晓彦
康晋锋
黄鹏
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北京大学
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Priority to PCT/CN2022/113040 priority Critical patent/WO2024036509A1/zh
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith

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  • the present disclosure relates to the fields of semiconductor technology and integrated circuit technology, and in particular, to an image sensing computing unit and its operating method, image sensing computing unit and electronic equipment.
  • the image sensing computing system can effectively realize image sensing processing functions such as face recognition and fingerprint recognition, and is widely used in monitoring and security, human-computer interaction and other fields.
  • the traditional image sensing computing system consists of an image sensing module and a computing processing module.
  • the optical signal needs to be converted into an electrical signal in the image sensing module first, and then transmitted to the computing processing module for logical operations. This causes the image sensor module to
  • the sensory computing system is complex, with large amounts of redundant data and long transmission distances, which seriously affects the image sensing computing efficiency of the system.
  • One aspect of the present disclosure provides an image sensing computing unit, which includes a first photosensitive unit and a second photosensitive unit, and the second photosensitive unit is connected in series with the first photosensitive unit, wherein the first photosensitive unit is The changing direction of the first threshold voltage is opposite to the changing direction of the second threshold voltage of the second photosensitive unit when receiving light, so as to realize in-situ logical operations between light input signals.
  • the first photosensitive unit includes a first transistor, a first buried oxide layer and a first doped well layer.
  • the first buried oxide layer is located under the first transistor; the first doped well layer is located under the first buried oxide layer. under the oxygen layer.
  • the second photosensitive unit includes a second transistor, a second buried oxide layer and a second doped well layer.
  • the second buried oxide layer is located under the second transistor; the second doped well layer is located under the second buried oxide layer. under the oxygen layer.
  • the first transistor and the second transistor have different transistor types, and the first doped well layer and the second doped well layer have the same well doping type.
  • the source of the first transistor is connected to the power supply voltage
  • the drain of the first transistor is connected to the drain of the second transistor
  • the source of the second transistor is connected to ground
  • the gate of the first transistor is connected to the ground.
  • a gate control voltage, the gate of the second transistor is connected to the second gate control voltage
  • the first doped well layer is connected to the first well control voltage
  • the second doped well layer is connected to the second well control voltage.
  • Another aspect of the present disclosure provides an operating method for the above-mentioned image sensing computing unit, which includes: performing an exposure operation on the image sensing computing unit in an off state, so that the first photosensitive sensor of the image sensing computing unit The equivalent resistance of the unit and/or the second photosensitive unit changes; controlling the first gate control voltage of the first photosensitive unit and/or the second gate control voltage of the second photosensitive unit of the image sensing operation unit after the exposure operation, Generate an output voltage of the image sensing computing unit to implement a readout operation of the image sensing computing unit; and control the first gate control voltage and/or the second photosensitive unit of the image sensing computing unit that has undergone the readout operation.
  • the second gate control voltage of the photosensitive unit is used to turn off the first photosensitive unit and/or the second photosensitive unit; at the same time, the first well control voltage and/or the second well control voltage is controlled to reset the image sensing operation unit. operate.
  • performing an exposure operation on the image sensing arithmetic unit in an off state includes: controlling the first gate control voltage of the first photosensitive unit and/or the second photosensitive unit of the image sensing arithmetic unit.
  • the second gate control voltage causes the first photosensitive unit and/or the second photosensitive unit of the image sensing computing unit to be turned off, and the image sensing computing unit is in an off state; at the same time, the first well control voltage of the first photosensitive unit is controlled. and/or the second well control voltage of the second photosensitive unit to implement the exposure operation.
  • the image sensing operation unit after controlling the first gate control voltage of the first photosensitive unit and/or the second gate control voltage of the second photosensitive unit of the image sensing operation unit after the exposure operation, the image sensing operation unit generates The output voltage includes: controlling the first gate control voltage and/or the second gate control voltage when the first well control voltage of the first photosensitive unit and/or the second well control voltage of the second photosensitive unit remains unchanged, To turn on the first photosensitive unit and/or the second photosensitive unit; read the drain voltage between the first photosensitive unit and the second photosensitive unit as the output voltage.
  • Another aspect of the present disclosure provides an image sensor arithmetic unit, which includes an image sensor array composed of the above image sensor arithmetic unit.
  • Another aspect of the present disclosure provides an electronic device, which includes the above-mentioned image sensor arithmetic unit.
  • the present disclosure can directly perform photoelectric conversion and simultaneously realize the in-situ logic processing function, so that the image sensor operation unit directly outputs an electrical signal representing the corresponding logical operation result, thereby eliminating the need for traditional logic processing signals.
  • the processing module effectively reduces the complexity of the system and improves the efficiency of image information processing.
  • Figure 1 schematically shows a schematic circuit composition diagram of an image sensing arithmetic unit according to an embodiment of the present disclosure
  • Figure 2 schematically shows a structural diagram of an Np type photosensitive unit according to an embodiment of the present disclosure, its corresponding equivalent circuit diagram, and a diagram of the relationship between threshold voltage V th and light intensity;
  • Figure 3 schematically shows a structural diagram of an Nn-type photosensitive unit according to an embodiment of the present disclosure, its corresponding equivalent circuit diagram, and a diagram of the relationship between threshold voltage V th and light intensity;
  • Figure 4 schematically shows a structural diagram of a Pp type photosensitive unit according to an embodiment of the present disclosure, its corresponding equivalent circuit diagram, and a diagram of the relationship between threshold voltage V th and light intensity;
  • Figure 5 schematically shows a structural diagram of a Pn type photosensitive unit according to an embodiment of the present disclosure, its corresponding equivalent circuit diagram, and a diagram of the variation of threshold voltage V th with light intensity;
  • FIG. 6 schematically illustrates an image sensing arithmetic unit composed of a P-n type photosensitive unit and an N-n type photosensitive unit that can implement 'NOR'/'NAND' logic between optical signals according to an embodiment of the present disclosure.
  • Figure 7 schematically shows an equivalent circuit diagram of an image sensing arithmetic unit composed of a P-p type photosensitive unit and an N-p type photosensitive unit that can implement AND//OR logic between optical signals according to an embodiment of the present disclosure. And its corresponding 'and'/' or' operation output diagram;
  • FIG. 8 schematically illustrates a flow chart of an operating method of an image sensing computing unit according to an embodiment of the present disclosure.
  • FIG. 9 schematically shows an operation timing diagram of the above-mentioned image sensing operation unit that can implement logical operations between light inputs according to an embodiment of the present disclosure.
  • modules in the devices in the embodiment can be adaptively changed and arranged in one or more devices different from that in the embodiment.
  • the modules or units or components in the embodiments may be combined into one module or unit or component, and furthermore they may be divided into a plurality of sub-modules or sub-units or sub-components.
  • All features disclosed in this specification including accompanying claims, abstract and drawings) and any method so disclosed may be employed in any combination, except that at least some of such features and/or processes or units are mutually exclusive. All processes or units of the equipment are combined.
  • Each feature disclosed in this specification may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.
  • several of these means may be embodied by the same item of hardware.
  • the present disclosure provides a method that can directly realize the optical signal arithmetic processing.
  • one aspect of the present disclosure provides an image sensing computing unit 100 , which includes a first photosensitive unit 101 and a second photosensitive unit 102 , and the second photosensitive unit 102 is connected in series with the first photosensitive unit 101 .
  • the direction of change of the first threshold voltage V th1 of the first photosensitive unit 101 when receiving light is opposite to the direction of change of the second threshold voltage V th2 of the second photosensitive unit 102 when receiving light, so as to realize the original alignment between the light input signals. Bit logic operations.
  • the image sensing computing unit 100 may be a structural unit with a photoelectric conversion function, wherein both the first photosensitive unit 101 and the second photosensitive unit 102 may be transistor units with a photosensitive function.
  • the first photosensitive unit 101 and the second photosensitive unit 102 are connected in series with each other, so their respective equivalent resistances in the series-connected circuit directly affect the voltage dividing effect of the two in the circuit.
  • the one with the larger equivalent resistance has a lower voltage division.
  • their corresponding equivalent resistances will also have corresponding different changing directions. For example, when the first photosensitive unit 101 is illuminated, the first threshold voltage V th1 increases, and the equivalent resistance increases; correspondingly, when the second photosensitive unit 102 is illuminated, the second threshold voltage V th2 decreases, and the equivalent resistance increases.
  • the threshold voltages of the two photosensitive units in the above embodiments of the present disclosure change in opposite directions when illuminated, so that their corresponding equivalent resistances change in opposite directions when illuminated.
  • the voltage division relationship between the two will be different depending on the lighting conditions of the two.
  • the image sensing module can only be used for photoelectric signal conversion, and the output electrical signal requires further conversion processing by the signal processing module before the logical operation between the optical input signals can be finally realized.
  • the image sensing operation unit of the embodiment of the present disclosure can directly perform photoelectric conversion while realizing the in-situ logic processing function, so that the image sensing operation unit directly outputs an electrical signal representing the corresponding logical operation result, thereby eliminating the need for traditional logic processing
  • the functional signal processing module effectively reduces the complexity of the system and improves the efficiency of optical signal processing.
  • the image sensing operation unit of the present disclosure that can implement in-situ logical operations between optical signals can discuss the input of optical signals with illumination as a logical value "1" and no illumination as a logical value "0". Therefore, those skilled in the art should understand that if illumination is a logical value "0" and no illumination is a logical value "1", the image sensing computing unit of the embodiment of the present disclosure implements the same thing as the above-mentioned "illumination is Logical value '1', no light is logical value '0'". The opposite logical operation will not be discussed in detail later.
  • a first photosensitive unit includes a first transistor, a first buried oxide layer and a first doped well layer.
  • the first buried oxide layer is located under the first transistor
  • the first doped well layer is located under the first buried oxide layer.
  • the second photosensitive unit includes a second transistor, a second buried oxide layer, and a second doped well layer.
  • the second buried oxide layer is located under the second transistor
  • the second doped well layer is located under the second buried oxide layer.
  • the photosensitive unit of the embodiment of the present disclosure can be a semiconductor structure in which transistors and doped well layers are respectively provided above and below the buried oxide layer.
  • the semiconductor structure can form an ultra-thin body and buried oxide structure.
  • the photosensitive transistor unit is the UTBB photosensitive transistor unit.
  • the semiconductor structure also includes a supporting substrate layer disposed below the doped well layer, and isolation trenches located on both sides of the doped well layer. The isolation trenches are generally used as shallow trench isolation to enable corresponding photosensitivity. Cells are isolated from other adjacent device cells.
  • a buried oxide layer is formed on the surface of the doped well layer, and a transistor is formed on the upper surface of the buried oxide layer, thus forming the main structure of the photosensitive unit.
  • the two serially connected first photosensitive units and the second photosensitive unit have the same structural form, and may have differences in the structural materials and structural function types of certain structural layers. Therefore, it can be ensured that the two devices can present threshold voltages in different changing directions when exposed to light. Thereby, the in-situ logical processing effect between the optical signals of the image sensing arithmetic unit of the embodiment of the present disclosure can be ensured.
  • the first transistor and the second transistor have different transistor types, and the first doped well layer and the second doped well layer have the same well doping type.
  • the transistor type may be an N-type doped or P-type doped field effect transistor, such as NMOS and PMOS; the well doping type may be an n-type doped or p-type doped well structure.
  • the above-mentioned photosensitive units of the embodiments of the present disclosure can be divided into N-p photosensitive units 200 of NMOS transistors 201 + p-type doped well layers 203 (as shown in FIG.
  • a structural layer of buried oxide layer is spaced between each transistor and the corresponding doped well layer, such as buried oxide layers 202, 302, 402 and 502.
  • the buried oxide layer can be a support layer with high transmittance, such as a silicon dioxide layer, which can allow light to pass through and illuminate the doped well layer. Therefore, when setting up a transistor, it is necessary to provide The illumination window is reserved so that the transistors cannot completely cover the buried oxide layer.
  • each transistor can have a gate terminal G, a drain terminal D and a source terminal S, and the corresponding doped well layer has a lead terminal B.
  • each photosensitive unit is a circuit form in which the back gate of a transistor unit is connected to a photosensitive capacitor.
  • the capacitance value of its corresponding photosensitive capacitor can be reduced as the light effect increases. Or it can be enhanced as the effect of illumination increases.
  • the capacitance value of the photosensitive capacitor corresponding to each of the above photosensitive units can be reduced as the effect of illumination increases. This ensures that after the corresponding photosensitive units are connected in series, the threshold voltages of the corresponding photosensitive units change in opposite directions after being illuminated, so as to realize the image sensing computing unit of the above-mentioned in-situ light logic operation.
  • the well control voltage V B ⁇ 0 of the corresponding lead terminal B2 can be controlled, and a depletion region is generated in the well corresponding to the doped well layer 203 and collected. Photogenerated electrons thereby lower the potential of the depletion region.
  • its equivalent capacitance is reduced, and on the other hand, it will produce a backgate modulation effect on the NMOS transistor 201 above the buried oxide layer 202, causing the threshold voltage V of the NMOS transistor 201 to TH increases.
  • the well control voltage V B ⁇ 0 of the corresponding lead terminal B4 can be controlled, and a depletion region is generated in the well corresponding to the doped well layer 403 and collected. Photogenerated electrons thereby lower the potential of the depletion region.
  • its equivalent capacitance is reduced, and on the other hand, it will produce a back-gate modulation effect on the PMOS transistor above the buried oxide layer 402, so that the threshold voltage V TH of the PMOS transistor 401 decrease.
  • the well control voltage V B of its corresponding doped well layer 303 is controlled to be >0.
  • the depletion region of the doped well layer 303 collects photogenerated holes, and the response will be The potential of the depletion region is raised, its equivalent capacitance is reduced, and at the same time, the back gate modulation effect on the NMOS transistor 301 is opposite to that of the photosensitive unit of the P-type doped well layer, so that the threshold voltage V TH of the NMOS transistor 301 is reduced.
  • the well control voltage V B of its corresponding doped well layer 503 is controlled to be >0.
  • the depletion region of the doped well layer 503 collects photogenerated holes, and the response will be The potential of the depletion region is raised, its equivalent capacitance is reduced, and at the same time, a backgate modulation effect on the PMOS transistor 501 is opposite to that of the photosensitive unit of the P-type doped well layer, so that the threshold voltage V TH of the PMOS transistor 501 is increased.
  • the image sensing computing unit 600 that can implement the logic of 'OR' and '/' and NOT' between optical signals and the image sensing computing unit 700 that can implement the 'OR' and '/'AND' logic between the optical signals are operated.
  • the corresponding instructions are as follows:
  • the Pn photosensitive unit and the Nn photosensitive unit are connected in series to realize the image sensing operation unit 600 of 'NOR'/'NAND' logic between optical signals.
  • the threshold voltage V TH increases. , its equivalent resistance will increase; after the Nn photosensitive unit connected in series with the above-mentioned Pn photosensitive unit is exposed, the threshold voltage V TH will decrease, and its equivalent resistance will decrease.
  • the Pn photosensitive unit and the Nn photosensitive unit are connected in series to achieve voltage division.
  • the output voltage V out output value is the smallest; when only one of the two photosensitive units connected in series is illuminated, That is, when the light input is '1 0' and '0 1', the output voltage V out output value is second; when the above two photosensitive units connected in series have no light, that is, when the light input is '0 0', the output voltage V out output value is maximum.
  • the logic value represented by the output voltage V out of the corresponding image sensing operation unit can be further determined by setting two different voltage comparison values (comparison values 1 and 2 as shown in Figure 6). If it is greater than the comparison value, the output is '1', and is less than '0'. Two different comparison values can obtain two logical results of 'NOR' or 'NAND'. Among them, setting a larger comparison value 1 so that only the output voltage V out with an input of '1 1' is '1' achieves a 'NAND'operation; on the contrary, setting a smaller comparison value 2 is The 'or not' operation will not be described in detail here.
  • the Pp photosensitive unit and the Np photosensitive unit are connected in series to realize the image sensing operation unit 700 of the 'OR'/'AND' logic between the light signals.
  • the threshold voltage V TH decreases.
  • the equivalent resistance will decrease; after the Np photosensitive unit connected in series with the above-mentioned Pp photosensitive unit is exposed, the threshold voltage V TH will increase, and its equivalent resistance will increase.
  • the working principle of the image sensing computing unit 600 shown in Figure 6 is similar, but the functional performance is basically opposite.
  • the output voltage V out output value is the largest; when only one of the two photosensitive units connected in series is exposed to light, that is, when the light input is '1 0' and '0 1', the output voltage V out output value is the second; when the above two photosensitive units are connected in series, the output value is the second.
  • the output voltage V out output value is the minimum.
  • the above-mentioned image sensing arithmetic unit of the embodiment of the present disclosure can be composed of two ultra-thin body and buried oxide structure photosensitive transistor units (UTBB photosensitive transistor units) with different transistor types and the same well doping type connected in series. Since the threshold voltages of two photosensitive units with different transistor types and the same well doping type change in opposite directions when illuminated, their equivalent resistances change in opposite directions when illuminated. When the two are connected in series, the partial pressure relationship between the two will be different depending on the lighting conditions of the two. Therefore, by setting the voltage comparison value, the logic value corresponding to the output voltage value can be determined, that is, the in-situ logic operation between the optical input signals can be realized.
  • UTBB photosensitive transistor units ultra-thin body and buried oxide structure photosensitive transistor units
  • the source of the first transistor is connected to the power supply voltage
  • the drain of the first transistor is connected to the drain of the second transistor
  • the source of the second transistor is grounded
  • the gate of the first transistor is connected to the first gate control voltage, and the gate of the second transistor is connected to the second gate control voltage; and the first doped well layer is connected to the first well control voltage, and the second doped well layer is connected to the third gate control voltage. Two well controlled voltage.
  • the image sensing arithmetic unit 600 that can implement the 'NOR' or 'NAND' logical operation between input light signals can be composed of a Pn photosensitive unit and an Nn photosensitive unit connected in series.
  • the source of the Pn photosensitive unit is connected to the power supply voltage V DD
  • its drain is connected to the drain of the Nn photosensitive unit
  • the source of the Nn photosensitive unit is connected to ground.
  • the gate of the Pn photosensitive unit can be connected to the gate control signal V Gp
  • the gate of the Nn photosensitive unit can be connected to another gate control signal V Gn .
  • the respective well electrodes of the doped well layers of both are connected to the well control signal V B. . Therefore, when the input of the image sensing calculation unit 600 is the incident light of each of the two photosensitive units, the output is the drain terminal voltage corresponding to the Nn photosensitive unit.
  • the image sensing arithmetic unit 700 which can implement 'OR' or 'AND' logical operations between input optical signals, can be connected in series with a Pp photosensitive unit and an Np photosensitive unit, that is, the source of the Pp photosensitive unit is connected to V DD . Its drain is connected to the drain of the Np photosensitive unit, and the source of the Np photosensitive unit is grounded.
  • the gate of the Pp photosensitive unit can be connected to the gate control signal V Gp
  • the gate of the Np unit can be connected to another gate control signal V Gn .
  • the respective well electrodes of the doped well layers of the two are commonly connected to the well control signal V B . Therefore, when the input of the image sensing calculation unit 700 is the incident light of each of the two photosensitive units, the output is the drain terminal voltage corresponding to the Np photosensitive unit.
  • the logic value of the output voltage V out can be further determined by setting the voltage comparison value, and the 'NOR'/'AND' logic operation between optical signals and the 'OR'/'AND' logic operation between optical signals can be realized. , and does not require additional circuit components such as signal operation and processing modules, which simplifies the processing system, shortens the logic operation time, and improves the logic operation efficiency.
  • FIG. 8 another aspect of the present disclosure provides an operation method of the image sensing computing unit shown in FIGS. 1 to 7 , which includes operations S801 to S803.
  • an exposure operation is performed on the image sensing computing unit in the off state, so that the equivalent resistance of the first photosensitive unit and/or the second photosensitive unit of the image sensing computing unit changes;
  • the first gate control voltage of the first photosensitive unit and/or the second gate control voltage of the second photosensitive unit of the image sensing operation unit that has undergone the exposure operation is controlled to generate an output voltage of the image sensing operation unit, Implement the readout operation of the image sensing computing unit;
  • the first gate control voltage of the first photosensitive unit and/or the second gate control voltage of the second photosensitive unit of the image sensing operation unit that has undergone the readout operation is controlled to turn off the first photosensitive unit and/or or the second photosensitive unit; simultaneously controlling the first well control voltage and/or the second well control voltage to implement a reset operation of the image sensing arithmetic unit.
  • performing an exposure operation on the image sensing operation unit in the off state in operation S801 includes:
  • the well control voltage V B ⁇ 0 corresponding to the two doped well layers is controlled.
  • the first gate control voltage of the first photosensitive unit of the image sensing operation unit and/or the second photosensitive unit of the second photosensitive unit that has undergone the exposure operation is controlled.
  • the gate control voltage which generates the output voltage of the image sensing operation unit, includes:
  • the first gate control voltage and/or the second gate control voltage are controlled to turn on the first photosensitive unit. and/or the second photosensitive unit;
  • the drain terminal voltage between the first photosensitive unit and the second photosensitive unit is read as the output voltage.
  • the first gate control voltage of the first photosensitive unit of the image sensing operation unit and/or the second photosensitive unit of the image sensing operation unit that has undergone the readout operation is controlled.
  • the second gate control voltage realizes the reset operation of the image sensing operation unit, including:
  • the first well control voltage and/or the second well control voltage are controlled to implement a reset operation.
  • Reset of the unit or, in this open state, for the image sensing computing unit 700 composed of the Pp photosensitive unit and the Np photosensitive unit as shown in Figure 7, control the well control voltage V B ⁇ 0 of the corresponding two doped well layers , thereby realizing the reset of each photosensitive unit.
  • the first well control voltage and/or the second well control voltage need to be controlled to be inverted to a voltage value with a polarity opposite to the corresponding well control voltage during the exposure operation, so that reset can be ensured.
  • an image sensor arithmetic unit which includes an image sensor array composed of the above-mentioned image sensor arithmetic unit.
  • the image sensing array can have N ⁇ M of the above-mentioned image sensing computing units at the same time, that is, it has 2N ⁇ M of the above-mentioned photosensitive units, where the two photosensitive units in each image sensing computing unit are connected in series, And keep the respective threshold voltages changing in opposite directions when illuminated, thereby realizing in-situ logic operations between corresponding light signals, so that the image sensing array can be directly used as a logic voltage output device, without the need for additional operations. processing module.
  • the electronic device can be a device with at least one function of optical communication and optical imaging, such as an optical communication device such as an optical communication laser device, to realize image perception processing functions such as face recognition, fingerprint recognition, etc., or it can be a laptop, computer, Portable smart electronic devices such as IPADs and smartphones can be well used in monitoring and security, human-computer interaction and other fields without specific restrictions.
  • optical communication device such as an optical communication laser device
  • image perception processing functions such as face recognition, fingerprint recognition, etc.
  • portable smart electronic devices such as IPADs and smartphones can be well used in monitoring and security, human-computer interaction and other fields without specific restrictions.

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Abstract

本公开提供了一种图像传感运算单元及其操作方法、图像传感运算器和电子设备。其中，图像传感运算单元包括第一感光单元以及第二感光单元，第二感光单元与第一感光单元串联，其中，第一感光单元在接收光照时的第一阈值电压变化方向，与第二感光单元在接收光照时的第二阈值电压变化方向相反，以实现光输入信号间的原位逻辑运算。因此，相对于现有技术，本公开实施例的图像传感运算单元能够直接在进行光电转换的同时实现原位的逻辑处理功能，使得图像传感运算单元直接输出代表相应逻辑运算结果的电信号，从而可以省略传统起逻辑处理作用的信号处理模块，有效降低系统的复杂度，提高光信号处理效率。

Description

图像传感运算单元及其操作方法、图像传感运算器和电子设备 技术领域
本公开涉及半导体技术和集成电路技术领域，尤其涉及一种图像传感运算单元及其操作方法、图像传感运算器和电子设备。
背景技术
图像传感运算系统可以有效的实现如人脸识别、指纹识别等图像感知处理功能，在监控安保、人机交互等领域应用广泛。传统的图像传感运算系统由图像传感模块和运算处理模块构成，需要先在图像传感模块内将光信号转换成电信号，然后再传输至运算处理模块进行逻辑运算，这就造成图像传感运算系统复杂，冗余数据量大、传递距离长，严重影响系统的图像感知运算效率。
发明内容
本公开的一个方面提供了一种图像传感运算单元，其中，包括第一感光单元以及第二感光单元，第二感光单元与第一感光单元串联，其中，第一感光单元在接收光照时的第一阈值电压变化方向，与第二感光单元在接收光照时的第二阈值电压变化方向相反，以实现光输入信号间的原位逻辑运算。
根据本公开的实施例，第一感光单元包括第一晶体管、第一埋氧层和第一掺杂阱层，第一埋氧层位于第一晶体管下；第一掺杂阱层位于第一埋氧层下。
根据本公开的实施例，第二感光单元包括第二晶体管、第二埋氧层和第二掺杂阱层，第二埋氧层位于第二晶体管下；第二掺杂阱层位于第二埋氧层下。
根据本公开的实施例，第一晶体管与第二晶体管的晶体管类型不同，第一掺杂阱层和第二掺杂阱层的阱掺杂类型相同。根据本公开的实施例，第一晶体管的源极接电源电压，第一晶体管的漏极与第二晶体管的漏极连接，第二晶体管的源极接地；其中，第一晶体管的栅极接第一栅控电压，第二晶体管的栅极接第二栅控电压；并且第一掺杂阱层接第一阱控电压，第二掺杂阱层接第二阱控电压。
本公开的另一个方面提供了一种上述的图像传感运算单元的操作方法，其中，包括：对处于关断状态的图像传感运算单元执行曝光操作，使得图像传感运算单元的第一感光单元和/或第二感光单元的等效电阻发生变化；控制经过曝光操作的图像传感运算单元的第一感光单元的第一栅控电压和/或第二感光单元的第二栅控电压，生成图像传感运算单元的输出电压，实现对图像传感运算单元的读出操作；以及控制经过读出操作的图像传感运算单元的第一感光单元的第一栅控电压和/或第二感光单元的第二栅控电压，以关断第一感光单元和/或第二感光单元；同时控制第一阱控电压和/或第二阱控电压，以实现对图像传感运算单元的复位操作。
根据本公开的实施例，在对处于关断状态的图像传感运算单元执行曝光操作中，包括：控制图像传感运算单元的第一感光单元的第一栅控电压和/或第二感光单元的第二栅控电压，使得图像传感运算单元的第一感光单元和/或第二感光单元关断，图像传感运算单元处于关断状态；同时控制第一感光单元的第一阱控电压和/或第二感光单元的第二阱控电压，实现曝光操作。
根据本公开的实施例，在控制经过曝光操作的图像传感运算单元的第一感光单元的第一栅控电压和/或第二感光单元的第二栅控电压，生成图像传感运算单元的输出电压中，包括：在第一感光单元的第一阱控电压和/或第二感光单元的第二阱控电压保持不变时，控制第一栅控电压和/或第二栅控电压，以开启第一感光单元和/或第二感光单元；读取第一感光单元和第二感光单元之间的漏端电压作为输出电压。
本公开的又一个方面提供了一种图像传感运算器，其中，包括上述的图像传感运算单元所构成的图像传感阵列。
本公开的还一个方面提供了一种电子设备，其中，包括上述的图像传感运算器。
相对于现有技术中图像传感运算系统既需要图像传感模块完成光电信号转换，还需要信号运算处理模块作进一步的运算处理之后，才能最终实现光输入信号间的逻辑运算的情况，本公开实施例的图像传感运算单元能够直接在进行光电转换的同时实现原位的逻辑处理功能，使得图像传感运算单元直接输出代表相应逻辑运算结果的电信号，从而可以省略传统逻 辑处理作用的信号处理模块，有效降低系统的复杂度，提高图像信息处理效率。
附图说明
图1示意性示出了根据本公开实施例的图像传感运算单元的电路组成示意图；
图2示意性示出了根据本公开实施例的N-p类型的感光单元结构图及其对应的等效电路图、阈值电压V th随光强的变化关系图；
图3示意性示出了根据本公开实施例的N-n类型的感光单元结构图及其对应的等效电路图、阈值电压V th随光强的变化关系图；
图4示意性示出了根据本公开实施例的P-p类型的感光单元结构图及其对应的等效电路图、阈值电压V th随光强的变化关系图；
图5示意性示出了根据本公开实施例的P-n类型的感光单元结构图及其对应的等效电路图、阈值电压V th随光强的变化关系图；
图6示意性示出了根据本公开实施例的可实现光信号间‘或非’/‘与非’逻辑的P-n类型的感光单元与N-n类型的感光单元所构成的图像传感运算单元的等效电路图及其对应的‘或非’/‘与非’操作输出示意图；
图7示意性示出了根据本公开实施例的可实现光信号间‘与’/‘或’逻辑的P-p类型的感光单元与N-p类型的感光单元所构成的图像传感运算单元的等效电路图及其对应的‘与’/‘或’操作输出示意图；
图8示意性示出了根据本公开实施例的图像传感运算单元的操作方法的流程图；以及
图9示意性出了根据本公开实施例的可实现光输入间逻辑操作的上述图像传感运算单元的操作时序图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本发明进一步详细说明。
需要说明的是，在附图或说明书正文中，未绘示或描述的实现方式，均为所属技术领域中普通技术人员所知的形式，并未进行详细说明。此外，上述对各元件和方法的定义并不仅限于实施例中提到的各种具体结构、形状或方式，本领域普通技术人员可对其进行简单地更改或替换。
还需要说明的是，实施例中提到的方向用语，例如“上”、“下”、“前”、“后”、“左”、“右”等，仅是参考附图的方向，并非用来限制本公开的保护范围。贯穿附图，相同的元素由相同或相近的附图标记来表示。在可能导致对本公开的理解造成混淆时，将省略常规结构或构造。
并且图中各部件的形状和尺寸不反映真实大小和比例，而仅示意本公开实施例的内容。另外，在权利要求中，不应将位于括号之间的任何参考符号构造成对权利要求的限制。
再者，单词“包含”不排除存在未列在权利要求中的元件或步骤。位于元件之前的单词“一”或“一个”不排除存在多个这样的元件。
说明书与权利要求中所使用的序数例如“第一”、“第二”、“第三”等的用词，以修饰相应的元件，其本身并不意味着该元件有任何的序数，也不代表某一元件与另一元件的顺序或是制造方法上的顺序，这些序数的使用仅用来使具有某命名的一元件得以和另一具有相同命名的元件能做出清楚区分。
本领域那些技术人员可以理解，可以对实施例中的设备中的模块进行自适应性地改变并且把他们设置在与该实施例不同的一个或多个设备中。可以把实施例中的模块或单元或组件组合成一个模块或单元或组件，以及此外可以把他们分成多个子模块或子单元或子组件。除了这样的特征和/或过程或者单元中的至少一些是相互排斥之外，可以采用任何组合对本说明书(包括伴随的权利要求、摘要和附图)中公开的所有特征以及如此公开的任何方法或者设备的所有过程或单元进行组合。除非另外明确陈述，本说明书(包括伴随的权利要求、摘要和附图)中公开的每个特征可以由提供相同、等同或相似目的的代替特征来代替。并且，在列举了若干装置的单元权利要求中，这些装置中的若干个可以是通过同一个硬件项来具体体现。
类似地，应当理解，为了精简本公开并帮助理解各个公开方面的一个或多个，在上面对本公开的示例性实施例的描述中，本公开的各个特征有时被一起分组到单个实施例、图、或者对其的描述中。然而，并不应将该公开的方法解释成反映如下意图：即所要求保护的本公开要求比在每个权利要求中所明确记载的特征更多的特征。更确切地说，如下面的权利要求 书所反映的那样，公开方面在于少于前面公开的单个实施例的所有特征。因此，遵循具体实施方式的权利要求书由此明确地并入该具体实施方式，其中每个权利要求本身都作为本公开的单独实施例。
为解决现有技术中传统图像传感运算系统的光信号运算处理需要信号运算处理模块来实现造成的系统组成较为复杂，逻辑处理效率较低的技术问题，本公开提供了一种可直接实现光信号间逻辑运算的图像传感运算单元及其操作方法、图像传感运算器和电子设备。
如图1所示，本公开的一个方面提供了一种图像传感运算单元100，其中，包括第一感光单元101以及第二感光单元102，第二感光单元102与第一感光单元101串联。
其中，第一感光单元101在接收光照时的第一阈值电压V th1变化方向，与第二感光单元102在接收光照时的第二阈值电压V th2变化方向相反，以实现光输入信号间的原位逻辑运算。
图像传感运算单元100可以是具有光电转换功能的结构单元，其中，第一感光单元101和第二感光单元102均可以为具有感光功能的晶体管单元。
第一感光单元101和第二感光单元102相互串联，则其各自在所串联的电路中的等效电阻直接影响二者在电路中的分压效果，等效电阻越大的一方，其分压的电压值越大，等效电阻相对较小的一方，其分压的电压值相对越小。此时，若相互串联的这两个感光单元能够在各自的光照条件下，展现不同变化方向的阈值电压，则其相应的等效电阻也具有相应的不同变化方向。如第一感光单元101在受到光照时，第一阈值电压V th1增大，等效电阻增大；对应地，第二感光单元102在受到光照时，第二阈值电压V th2减小，等效电阻减小。如此，不同的光照情况对应两感光单元不同的分压情况，在该图像传感运算单元100的输出端所输出的输出电压V out便可以直接作为相应逻辑运算结果的电压信号输出，而不需要再经过其他运算处理模块的额外处理，实现光输入信号间的原位逻辑运算。
上述本公开实施例的两个感光单元在光照时阈值电压变化方向相反，使得其光照时的对应等效电阻的变化趋势相反。当两者串联时，根据两者受光照情况的不同，两者的分压关系也会不同，通过设置合理的电压比较 值来确定输出电压值对应的逻辑值，即可实现光输入信号间的原位逻辑运算。
因此，相对于现有技术中图像传感模块仅能用于光电信号转换，且输出的电信号还需要信号运算处理模块作进一步的转换处理之后，才能最终实现光输入信号间的逻辑运算的情况，本公开实施例的图像传感运算单元能够直接在进行光电转换的同时实现原位的逻辑处理功能，使得图像传感运算单元直接输出代表相应逻辑运算结果的电信号，从而可以省略传统逻辑处理作用的信号处理模块，有效降低系统的复杂度，提高光信号处理效率。
需要说明是，本公开的可实现光信号间原位逻辑运算的图像传感运算单元，其对光信号输入可以以光照为逻辑值“1”、无光照为逻辑值“0”进行论述。因此，本领域技术人员应当可以理解，若是以光照为逻辑值“0”、无光照为逻辑值“1”，则本公开实施例的图像传感运算单元实现的则是与上述关于“光照为逻辑值‘1’、无光照为逻辑值‘0’”的论述相反的逻辑操作，后文不作赘述。
如图2-图7所示，根据本公开的实施例，第一感光单元包括第一晶体管、第一埋氧层和第一掺杂阱层。
第一埋氧层位于第一晶体管下；
第一掺杂阱层位于第一埋氧层下。
如图2-图7所示，根据本公开的实施例，第二感光单元包括第二晶体管、第二埋氧层和第二掺杂阱层。
第二埋氧层位于第二晶体管下；
第二掺杂阱层位于第二埋氧层下。
如图2-图7所示，本公开实施例的感光单元可以是在埋氧层上下分别设置晶体管和掺杂阱层的半导体结构，其中，该半导体结构可以构成一超薄体及埋氧结构的感光晶体管单元，即UTBB感光晶体管单元。该半导体结构还包括设置于掺杂阱层下方的支撑作用的衬底层，以及位于掺杂阱层两侧的隔离作用的隔离沟槽，该隔离沟槽一般作为浅槽隔离作用使用，使得对应感光单元与其他相邻的器件单元隔离。在掺杂阱层表面形成埋氧层，在埋氧层上表面上形成晶体管，从而构成该感光单元的主体结构。
其中，对于同一图像传感运算单元，两个相互串联的第一感光单元和第二感光单元的结构形式相同，在具体的某些结构层的结构材料、结构功能类型上可以具有差异。从而，能够保证二者在受到光照时，可以呈现不同变化方向的阈值电压。借此，能够保证本公开实施例的图像传感运算单元的光信号间的原位逻辑处理效果。
如图2-图7所示，根据本公开的实施例，第一晶体管与第二晶体管的晶体管类型不同，第一掺杂阱层和第二掺杂阱层的阱掺杂类型相同。
晶体管类型可以是N型掺杂或者P型掺杂的场效应晶体管，如NMOS和PMOS；阱掺杂类型可以是n型掺杂和p型掺杂的阱结构。如图2-图5所示，根据晶体管类型和阱掺杂类型的不同，本公开实施例的上述感光单元可以分为NMOS晶体管201+p型掺杂阱层203的N-p感光单元200(如图2所示)、NMOS晶体管301+n型掺杂阱层303的N-n感光单元300(如图3所示)、PMOS晶体管401+p型掺杂阱层403的P-p感光单元400(如图4所示)以及PMOS晶体管501+n型掺杂阱层503的P-n感光单元500(如图5所示)。每个晶体管和对应的掺杂阱层之间间隔一埋氧层的结构层，如埋氧层202、302、402以及502。其中埋氧层可以是具有高透光度的支撑层，如二氧化硅层等，能够使得光照透过并对掺杂阱层实现照射，因此，在设置晶体管时，需要在埋氧层表面为光照预留光照窗口，使得晶体管无法全部覆盖埋氧层。
其中，每个晶体管都可以具有栅端G、漏端D以及源端S，相应的掺杂阱层则具有引线端B，具体地，如图2所示N-p感光单元的栅端G2、漏端D2、源端S2和引线端B2，如图3所示N-n感光单元的栅端G3、漏端D3、源端S3和引线端B3，如图4所示P-p感光单元的栅端G4、漏端D4、源端S4和引线端B4，以及如图5所示P-n感光单元的栅端G5、漏端D5、源端S5和引线端B5。可见，如其所对应的等效电路所示，各个感光单元为晶体管单元背栅极联一光敏电容的电路形式，其中，其对应的光敏电容的电容值能够随着光照作用的增强而减小，或者能够随着光照作用的增强而增强，其中优选为上述各个感光单元对应的光敏电容的电容值能够随着光照作用的增强而减小。借此，可以确保相应感光单元在相互串联之后，各自受光照后的阈值电压变化方向相反，以实现上述原位光逻辑 运算的图像传感运算单元。
结合上述图2-图5所示感光单元的结构组成图、对应的等效电路图和感光单元的阈值电压V TH随光照变化的示意图，对上述各个感光单元在光照时的作用原理作进一步说明如下：
如图2所示，N-p感光单元200的掺杂阱层203在曝光时，可以控制对应引线端B2的阱控电压V B＜0，对应掺杂阱层203的阱中产生耗尽区并收集光生电子，从而拉低了耗尽区的电势，一方面其等效电容减小，另一方面会对埋氧层202上方的NMOS晶体管201产生背栅调制作用，使NMOS晶体管201的阈值电压V TH增大。
如图4所示，P-p感光单元400的掺杂阱层403在曝光时，可以控制对应引线端B4的阱控电压V B＜0，对应掺杂阱层403的阱中产生耗尽区并收集光生电子，从而拉低了耗尽区的电势，一方面其等效电容减小，另一方面会对埋氧层402上方的PMOS晶体管产生背栅调制作用，使PMOS晶体管401的阈值电压V TH减小。
如图3所示，N-n感光单元300曝光时，控制其对应的掺杂阱层303的阱控电压V B＞0，掺杂阱层303的耗尽区收集的是光生空穴，则响应会抬高耗尽区电势，减小其等效电容，同时对NMOS晶体管301产生与上述P型掺杂阱层的感光单元相反的背栅调制作用，使NMOS晶体管301的阈值电压V TH减小。
如图5所示，P-n感光单元500曝光时，控制其对应的掺杂阱层503的阱控电压V B＞0，掺杂阱层503的耗尽区收集的是光生空穴，则响应会抬高耗尽区电势，减小其等效电容，同时对PMOS晶体管501产生与上述P型掺杂阱层的感光单元相反的背栅调制作用，使PMOS晶体管501的阈值电压V TH增大。
基于上述各个晶体管类型的感光单元的光照与阈值电压V TH之间的对应关系，结合图6和图7所示不同的两个感光单元的图像传感运算单元的等效电路图及其对应输出结果，对本公开实施例中可实现光信号间‘或非’/‘与非’逻辑的图像传感运算单元600和可实现光信号间‘或’/‘与’逻辑的图像传感运算单元700作相应的说明如下：
如图6所示以P-n感光单元与N-n感光单元相互串联来实现光信号间 ‘或非’/‘与非’逻辑的图像传感运算单元600，P-n感光单元曝光后，阈值电压V TH增大，其等效电阻会增大；与上述P-n感光单元相互串联的N-n感光单元曝光后，阈值电压V TH减小，其等效电阻会减小。
P-n感光单元与N-n感光单元相互串联在一起实现分压，PMOS晶体管的等效电阻所占比重越大，输出结果V out值就越小。可以设定以感光单元的光输入光照为逻辑值‘1’，无光照为逻辑值‘0’。
因此，当上述两个相互串联的感光单元均受到光照时，即光输入为‘1 1’时，输出电压V out输出值最小；当上述两个相互串联的感光单元中只有一个受到光照时，即光输入为‘1 0’和‘0 1’时，输出电压V out输出值次之；当上述两个相互串联的感光单元均无光照时，即光输入为‘0 0’时，输出电压V out输出值最大。
可见，可以进一步通过设定两种不同电压比较值(如图6所示比较值1、2)来确定作为对应图像传感运算单元的输出电压V out所代表的逻辑值，大于比较值则输出为‘1’，小于为‘0’，两种不同的比较值可以得到‘或非’或者‘与非’两种逻辑结果。其中，设定较大的比较值1使得只有输入为‘1 1’的输出电压V out为‘1’时，实现的是‘与非’操作；相反，设定较小的比较值2则是‘或非’操作，在此不作赘述。
如图7所示以P-p感光单元与N-p感光单元相互串联来实现光信号间‘或’/‘与’逻辑的图像传感运算单元700，P-p感光单元曝光后，阈值电压V TH减小，其等效电阻会减小；与上述P-p感光单元相互串联的N-p感光单元曝光后，阈值电压V TH增大，其等效电阻会增大。
因此，与上述图6所示图像传感运算单元600的工作原理类似，但功能表现基本相反，当上述两个相互串联的感光单元均受到光照时，即光输入为‘1 1’时，输出电压V out输出值最大；当上述两个相互串联的感光单元中只有一个受到光照时，即光输入为‘1 0’和‘0 1’时，输出电压V out输出值次之；当上述两个相互串联的感光单元均无光照时，即光输入的逻辑值为‘0 0’时，输出电压V out输出值最小。
可见，可以进一步通过设定两种不同的电压比较值(如图7所示比较值3、4)可以得到‘或’或者‘与’两种逻辑结果，设定较大的比较值3使得只有输入为‘1 1’的输出电压V out为‘1’时，实现的是‘与’操 作，而较小的比较值4则是‘或’操作，在此不作赘述。
因此，本公开实施例的上述图像传感运算单元可以由两个晶体管类型不同、阱掺杂类型相同的超薄体及埋氧结构的感光晶体管单元(UTBB感光晶体管单元)相互串联构成。由于晶体管类型不同、阱掺杂类型相同的两个感光单元在照光时阈值电压变化方向相反，因此照光时的其等效电阻的变化趋势相反。当两者串联时，根据两者受光照情况的不同，两者的分压关系也会不同。因此，通过设定电压比较值可以确定输出电压值对应的逻辑值，即能够实现对光输入信号间的原位逻辑运算。
如图2-图7所示，根据本公开的实施例，第一晶体管的源极接电源电压，
第一晶体管的漏极与第二晶体管的漏极连接，
第二晶体管的源极接地；
其中，第一晶体管的栅极接第一栅控电压，第二晶体管的栅极接第二栅控电压；并且第一掺杂阱层接第一阱控电压，第二掺杂阱层接第二阱控电压。
如图6所示，可实现输入光信号间的‘或非’或者‘与非’逻辑操作的图像传感运算单元600可以由P-n感光单元与N-n感光单元相互串联构成。其中，P-n感光单元的源极接电源电压V DD，其漏极与N-n感光单元的漏极相连，N-n感光单元的源极接地。此外，P-n感光单元的栅极可以接栅控信号V Gp，N-n感光单元的栅极接另一栅控信号V Gn，作为两者的掺杂阱层的各自阱电极共同接阱控信号V B。因此，当该图像传感运算单元600的输入为两感光单元各自的入射光时，输出为N-n感光单元对应的漏端电压。
如图7所示，可实现输入光信号间‘或’或者‘与’逻辑操作的图像传感运算单元700可以由P-p感光单元与N-p感光单元串联，即P-p感光单元的源极接V DD，其漏极与N-p感光单元的漏极相连，N-p感光单元的源极接地。此外，P-p感光单元的栅极可以接栅控信号V Gp，N-p单元的栅极可以接另一栅控信号V Gn，作为两者的掺杂阱层的各自阱电极共同接阱控信号V B。因此，当该图像传感运算单元700的输入为两感光单元各自的入射光时，输出为N-p感光单元对应的漏端电压。
在此基础上，可以进一步通过设定电压比较值来确定输出电压V out的逻辑值，实现光信号间‘或非’/‘与非’逻辑运算和光信号间‘或’/‘与’逻辑运算，且无需额外的信号运算处理模块等电路组成，简化了处理系统，同时也缩短了逻辑运算时间，提高了逻辑运算效率。
如图8所示，本公开的另一个方面提供了一种上述如图1-图7所示的图像传感运算单元的操作方法，其中，包括操作S801-S803。
在操作S801中，对处于关断状态的图像传感运算单元执行曝光操作，使得图像传感运算单元的第一感光单元和/或第二感光单元的等效电阻发生变化；
在操作S802中，控制经过曝光操作的图像传感运算单元的第一感光单元的第一栅控电压和/或第二感光单元的第二栅控电压，生成图像传感运算单元的输出电压，实现对图像传感运算单元的读出操作；以及
在操作S803中，控制经过读出操作的图像传感运算单元的第一感光单元的第一栅控电压和/或第二感光单元的第二栅控电压，以关断第一感光单元和/或第二感光单元；同时控制第一阱控电压和/或第二阱控电压，以实现对图像传感运算单元的复位操作。
如图6-图9所示，根据本公开的实施例，在操作S801对处于关断状态的图像传感运算单元执行曝光操作中，包括：
控制图像传感运算单元的第一感光单元的第一栅控电压和/或第二感光单元的第二栅控电压，使得图像传感运算单元的第一感光单元和/或第二感光单元关断，图像传感运算单元处于关断状态；同时
控制第一感光单元的第一阱控电压和/或第二感光单元的第二阱控电压，实现曝光操作。
结合图6或者图7，如图9所示，当本公开实施例的图像传感运算单元执行曝光操作时，控制两个相互串联的感光单元的栅控电压V Gp＞0，V Gn＝0，使得两感光单元关断并保持该关断状态。在此关断状态下，同时对于如图6所示P-n感光单元和N-n感光单元组成的图像传感运算单元600，控制对应两掺杂阱层的阱控电压V B＜0，在此基础上保持对两个感光单元中至少之一的曝光操作；或者，在此关断状态下，对于如图7所示的P-p感光单元和N-p感光单元组成的图像传感运算单元700，控制对应阱控电 压V B＞0，在此基础上保持对两个感光单元中至少之一的曝光操作。如此，便可以实现对相互串联的两个感光单元中至少之一的曝光操作。
如图6-图9所示，根据本公开的实施例，在操作S802控制经过曝光操作的图像传感运算单元的第一感光单元的第一栅控电压和/或第二感光单元的第二栅控电压，生成图像传感运算单元的输出电压中，包括：
在第一感光单元的第一阱控电压和/或第二感光单元的第二阱控电压保持不变时，控制第一栅控电压和/或第二栅控电压，以开启第一感光单元和/或第二感光单元；
读取第一感光单元和第二感光单元之间的漏端电压作为输出电压。
结合图6或者图7，如图9所示，当对应的图像传感运算单元在执行读出操作时，对应的阱控电压V B保持与曝光操作时的值不变，对应两个不同感光单元的栅控电压V Gp＝0和V Gn＞0，从而实现对这两个感光单元的开启，便可以直接读出输出信号V out的值。
如图6-图9所示，根据本公开的实施例，在操作S803控制经过读出操作的图像传感运算单元的第一感光单元的第一栅控电压和/或第二感光单元的第二栅控电压，实现对图像传感运算单元的复位操作中，包括：
控制第一栅控电压和/或第二栅控电压，以关断第一感光单元和/或第二感光单元；同时
控制第一阱控电压和/或第二阱控电压，以实现复位操作。
结合图6或者图7，如图9所示，当对应的图像传感运算单元在执行复位操作时，对应两个不同感光单元的栅控电压V Gp＞0和V Gn＝0，重新关断两个感光单元。在此开启状态下，同时对于如图6所示P-n感光单元和N-n感光单元组成的图像传感运算单元600，控制对应两掺杂阱层的阱控电压V B＞0，从而实现对各个感光单元的复位；或者，在此开启状态下，对于如图7所示的P-p感光单元和N-p感光单元组成的图像传感运算单元700，控制对应两掺杂阱层的阱控电压V B＜0，从而实现对各个感光单元的复位。其中，在实现复位操作过程中，需要控制第一阱控电压和/或第二阱控电压反转为与曝光操作时的相应阱控电压极性相反的电压值，如此才可以保证复位。
本公开的又一个方面提供了一种图像传感运算器，其中，包括上述的 图像传感运算单元所构成的图像传感阵列。该图像传感阵列可以同时具有N×M个上述的图像传感运算单元，也即具有2N×M个上述的感光单元，其中，每个图像传感运算单元中的两个感光单元相互串联，并保持在光照时各自的阈值电压会发生相反的变化方向，从而实现相应的光信号间的原位逻辑运算，使得该图像传感阵列可以直接作为逻辑电压的输出器件，不再需要额外的运算处理模块。
本公开的还一个方面提供了一种电子设备，其中，包括上述的图像传感运算器。该电子设备可以是具有光通讯和光成像至少之一的功能的设备，如光通信激光器设备等光通讯设备，以实现如人脸识别、指纹识别等图像感知处理功能，也可以是笔记本、电脑、IPAD、智能手机等便携式只能电子设备，从而能够很好地应用于监控安保、人机交互等领域中，具体不作限制。
至此，已经结合附图对本公开实施例进行了详细描述。
以上所述的具体实施例，对本发明的目的、技术方案和有益效果进行了进一步详细说明，应理解的是，以上所述仅为本发明的具体实施例而已，并不用于限制本发明，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (10)

  1. 一种图像传感运算单元，其中，包括：
    第一感光单元，以及
    第二感光单元，与所述第一感光单元串联，
    其中，所述第一感光单元在接收光照时的第一阈值电压变化方向，与所述第二感光单元在接收光照时的第二阈值电压变化方向相反，以实现光输入信号间的原位逻辑运算。
  2. 根据权利要求1所述的图像传感运算单元，其中，所述第一感光单元包括：
    第一晶体管，
    第一埋氧层，位于所述第一晶体管下；
    第一掺杂阱层，位于所述第一埋氧层下。
  3. 根据权利要求2所述的图像传感运算单元，其中，所述第二感光单元包括：
    第二晶体管，
    第二埋氧层，位于所述第二晶体管下；
    第二掺杂阱层，位于所述第二埋氧层下。
  4. 根据权利要求3所述的图像传感运算单元，其中，所述第一晶体管与第二晶体管的晶体管类型不同，所述第一掺杂阱层和所述第二掺杂阱层的阱掺杂类型相同。
  5. 根据权利要求3所述的图像传感运算单元，其中，
    所述第一晶体管的源极接电源电压，
    所述第一晶体管的漏极与所述第二晶体管的漏极连接，
    所述第二晶体管的源极接地；
    其中，所述第一晶体管的栅极接第一栅控电压，所述第二晶体管的栅极接第二栅控电压；并且所述第一掺杂阱层接第一阱控电压，所述第二掺杂阱层接第二阱控电压。
  6. 一种权利要求1-5中任一项所述的图像传感运算单元的操作方法，其中，包括：
    对处于关断状态的所述图像传感运算单元执行曝光操作，使得所述图像传感运算单元的第一感光单元和/或第二感光单元的等效电阻发生变化；
    控制经过所述曝光操作的图像传感运算单元的第一感光单元的第一栅控电压和/或第二感光单元的第二栅控电压，生成所述图像传感运算单元的输出电压，实现对所述图像传感运算单元的读出操作；以及
    控制经过所述读出操作的图像传感运算单元的第一感光单元的第一栅控电压和/或第二感光单元的第二栅控电压，以关断所述第一感光单元和/或第二感光单元；同时控制所述第一阱控电压和/或第二阱控电压，以实现对所述图像传感运算单元的复位操作。
  7. 根据权利要求6所述的操作方法，其中，在所述对处于关断状态的所述图像传感运算单元执行曝光操作中，包括：
    控制所述图像传感运算单元的第一感光单元的第一栅控电压和/或第二感光单元的第二栅控电压，使得所述图像传感运算单元的第一感光单元和/或第二感光单元关断，所述图像传感运算单元处于关断状态；同时
    控制第一感光单元的第一阱控电压和/或第二感光单元的第二阱控电压，实现所述曝光操作。
  8. 根据权利要求6所述的操作方法，其中，在所述控制经过所述曝光操作的图像传感运算单元的第一感光单元的第一栅控电压和/或第二感光单元的第二栅控电压，生成所述图像传感运算单元的输出电压中，包括：
    在所述第一感光单元的第一阱控电压和/或第二感光单元的第二阱控电压保持不变时，控制所述第一栅控电压和/或第二栅控电压，以开启所述第一感光单元和/或第二感光单元；
    读取所述第一感光单元和所述第二感光单元之间的漏端电压作为所述输出电压。
  9. 一种图像传感运算器，其中，包括多个权利要求1-5中任一项所述的图像传感运算单元所构成的图像传感阵列。
  10. 一种电子设备，其中，包括权利要求9所述的图像传感运算器。
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CN103022069A (zh) * 2013-01-10 2013-04-03 上海中科高等研究院 图像传感器
CN108666336A (zh) * 2018-05-29 2018-10-16 北京大学 一种utbb光电探测器阵列及其工作方法
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JP2007158547A (ja) * 2005-12-01 2007-06-21 Honda Motor Co Ltd 光センサ回路およびイメージセンサ
CN102314840A (zh) * 2010-06-30 2012-01-11 格科微电子（上海）有限公司 图像传感器、电子设备及其背光调节方法
CN103022069A (zh) * 2013-01-10 2013-04-03 上海中科高等研究院 图像传感器
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