WO2020093841A1 - 探测电路及其驱动方法、探测基板、探测装置 - Google Patents

探测电路及其驱动方法、探测基板、探测装置 Download PDF

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Publication number
WO2020093841A1
WO2020093841A1 PCT/CN2019/111063 CN2019111063W WO2020093841A1 WO 2020093841 A1 WO2020093841 A1 WO 2020093841A1 CN 2019111063 W CN2019111063 W CN 2019111063W WO 2020093841 A1 WO2020093841 A1 WO 2020093841A1
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Prior art keywords
terminal
circuit
coupled
storage sub
capacitor
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PCT/CN2019/111063
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English (en)
French (fr)
Inventor
华刚
薛艳娜
张勇
白璐
方浩博
林坚
张丽敏
Original Assignee
京东方科技集团股份有限公司
北京京东方光电科技有限公司
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Priority to US16/757,573 priority Critical patent/US11079272B2/en
Publication of WO2020093841A1 publication Critical patent/WO2020093841A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
    • G01J1/00—Photometry, e.g. photographic exposure meter
    • G01J1/42—Photometry, e.g. photographic exposure meter using electric radiation detectors
    • G01J1/44—Electric circuits
    • G01J1/46—Electric circuits using a capacitor
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01D—MEASURING NOT SPECIALLY ADAPTED FOR A SPECIFIC VARIABLE; ARRANGEMENTS FOR MEASURING TWO OR MORE VARIABLES NOT COVERED IN A SINGLE OTHER SUBCLASS; TARIFF METERING APPARATUS; MEASURING OR TESTING NOT OTHERWISE PROVIDED FOR
    • G01D5/00—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable
    • G01D5/26—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable characterised by optical transfer means, i.e. using infrared, visible, or ultraviolet light
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
    • G01J1/00—Photometry, e.g. photographic exposure meter
    • G01J1/42—Photometry, e.g. photographic exposure meter using electric radiation detectors
    • G01J1/44—Electric circuits
    • G01J2001/4446—Type of detector
    • G01J2001/446—Photodiode

Definitions

  • the present disclosure relates to the technical field of detection devices, and in particular, to a detection circuit and a driving method thereof, a detection substrate, and a detection device.
  • the detection device converts the received optical signal into an electrical signal (ie, photo-generated electron) through a sensor.
  • the detection device that can realize fast reading and can meet the larger photo-generated electronic storage capacity is the future development trend of the detection device.
  • a first aspect of an embodiment of the present disclosure provides a detection circuit, including an output control sub-circuit, a first storage sub-circuit, a photosensitive device, and a second storage sub-circuit group.
  • the photosensitive device coupled to the device voltage terminal and the output point, is configured to convert the received optical signal into an electrical signal and transmit the electrical signal to the output point;
  • the first storage sub-circuit coupled Connected to the output point and the first voltage terminal, configured to store at least part of the electrical signal;
  • the second storage sub-circuit group is coupled to the output point, the second voltage terminal group and the second control signal
  • the terminal group is configured to store part of the electrical signal under the control of at least one second turn-on signal transmitted through the second control signal terminal group;
  • the output control subcircuit is coupled to the signal receiving terminal,
  • the first control signal terminal and the output point are configured to transmit the electrical signal of the output point to the signal receiving terminal under the control of the first turn-on signal transmitted through the first control signal terminal.
  • the second storage sub-circuit group includes a second storage sub-circuit, the second voltage terminal group includes a second voltage terminal, and the second control signal terminal group includes a first Two control signal terminals; wherein, the second storage sub-circuit is configured to store part of the electrical signals under the control of the second turn-on signal transmitted through the second control signal terminal.
  • the second storage sub-circuit group includes a plurality of second storage sub-circuits
  • the second voltage terminal group includes a plurality of second voltage terminals
  • the second control signal terminal group includes A plurality of second control signal terminals; each of the second storage subcircuits is coupled to the output point, a corresponding second voltage terminal, and a corresponding second control signal terminal, and is configured to Under the control of the second start signal transmitted by the two control signal terminals, part of the electrical signal is stored.
  • the second storage sub-circuit group includes a plurality of second storage sub-circuits
  • the second voltage terminal group includes a plurality of second voltage terminals
  • the second control signal terminal group includes A plurality of second control signal terminals.
  • each of the part of the second storage sub-circuits includes a plurality of sub-banks arranged in cascade; the first-level sub-banks are coupled to the output point and a corresponding The two voltage terminals and a corresponding second control signal terminal are configured to store part of the electrical signal under the control of the second turn-on signal transmitted by the corresponding second control signal terminal;
  • the sub-banks of each stage coupled to the sub-banks of the previous stage, a corresponding second voltage terminal and a corresponding second control signal terminal, are configured to be transmitted at the corresponding second control signal terminal Under the control of the second on signal, some of the electrical signals are stored.
  • Each of the remaining second storage sub-circuits is coupled to the output point, a corresponding second voltage terminal and a corresponding second control signal terminal, and is configured to be transmitted at the corresponding second control signal terminal Under the control of the second on signal, some of the electrical signals are stored.
  • the second storage sub-circuit group includes a plurality of second storage sub-circuits arranged in cascade, the second voltage terminal group includes a plurality of second voltage terminals, and the second control The signal terminal group includes a plurality of second control signal terminals; a first-stage second storage sub-circuit, coupled to the output point, a corresponding second voltage terminal and a corresponding second control signal terminal, is configured to Under the control of the second start signal transmitted by the corresponding second control signal terminal, part of the electrical signal is stored; the second storage subcircuit of each stage after the first stage is coupled to the second storage subcircuit of the previous stage , A corresponding second voltage terminal and a corresponding second control signal terminal, configured to store part of the electrical signal under the control of the corresponding second control signal terminal.
  • At least two of the plurality of second control signal terminals are different control signal terminals; and / or, at least two of the plurality of second voltage terminals are different voltage terminals.
  • the plurality of second control signal terminals are further coupled to one control signal terminal, and / or the plurality of second voltage terminals are further coupled to one voltage terminal.
  • the maximum storage charge amount of the first storage sub-circuit is different from the maximum storage charge amount of the second storage sub-circuit group.
  • At least two of the plurality of second storage sub-circuits have different maximum stored charge amounts.
  • the photosensitive device includes a photodiode, one pole of the photodiode is coupled to the voltage terminal of the device, and the other pole is coupled to the output point;
  • the first storage subcircuit includes a A capacitor, a first terminal of the first capacitor is coupled to the output point, and a second terminal is coupled to the first voltage terminal;
  • the output control sub-circuit includes a first transistor, the The gate is coupled to the first control signal terminal, the first pole is coupled to the signal receiving terminal, and the second pole is coupled to the output point.
  • the second storage subcircuit includes a second transistor and a second capacitor; the gate of the second transistor is coupled to the second control signal terminal, and the first electrode is coupled to the At the output point, the second pole is coupled to the first terminal of the second capacitor; the second terminal of the second capacitor is coupled to the second voltage terminal.
  • each second storage subcircuit includes a second transistor and a second capacitor; the gate of the second transistor of each second storage subcircuit is coupled to a corresponding second control signal terminal , The first pole is coupled to the output point, and the second pole is coupled to the first end of the second capacitor; the second end of the second capacitor of each second storage subcircuit is coupled to a corresponding second voltage end .
  • each sub-bank includes a third transistor and a third capacitor; in the first-level sub-bank: the gate of the third transistor is coupled to a corresponding second control At the signal terminal, the first pole is coupled to the output point, and the second pole is coupled to the first terminal of the third capacitor; the second terminal of the third capacitor is coupled to a corresponding second voltage terminal; In each of the sub-banks after the first stage: the gate of the third transistor is coupled to a corresponding second control signal terminal, and the first pole is coupled to the second pole of the third transistor of the sub-bank of the previous stage The second pole is coupled to the first terminal of the third capacitor; the second terminal of the third capacitor is coupled to a corresponding second voltage terminal.
  • Each of the remaining second storage sub-circuits includes a second transistor and a second capacitor; wherein, the gate of the second transistor is coupled to a corresponding second control signal terminal, and the first pole is coupled At the output point, the second pole is coupled to the first terminal of the second capacitor; the second terminal of the second capacitor is coupled to a corresponding second voltage terminal.
  • each second storage sub-circuit includes a second transistor and a second capacitor; in the first-stage second storage sub-circuit: the gate of the second transistor is coupled to one Corresponding second control signal terminal, the first pole is coupled to the output point, the second pole is coupled to the first terminal of the second capacitor; the second terminal of the second capacitor is coupled to a corresponding second voltage Terminal; in the second storage subcircuit of each stage after the first level: the gate of the second transistor is coupled to a corresponding second control signal terminal, and the first pole is coupled to the second storage element of the previous stage The second pole of the second transistor of the circuit is coupled to the first terminal of the second capacitor; the second terminal of the second capacitor is coupled to a corresponding second voltage terminal.
  • a second aspect of an embodiment of the present disclosure provides a detection substrate, including a plurality of any of the detection circuits described above.
  • the first storage subcircuit includes a first capacitor; the second storage subcircuit group includes one or more second storage subcircuits, and each second storage subcircuit includes a second capacitor , Wherein the second end of the first capacitor and the second end of the second capacitor are provided in the same layer and made of the same material; and / or, the first end of the first capacitor and the The first end of the second capacitor is arranged in the same layer and made of the same material.
  • the first storage sub-circuit further includes a first transistor; each second storage sub-circuit further includes a second transistor; wherein, the gate of the first transistor, the second transistor , The second end of the first capacitor, and the second end of the second capacitor are arranged in the same layer and made of the same material; and / or, the first electrode of the first transistor and The second pole, the first and second poles of the second transistor, the first end of the first capacitor, and the first end of the second capacitor are provided in the same layer and made of the same material.
  • the first storage sub-circuit includes a first capacitor;
  • the second storage sub-circuit group includes a plurality of second storage sub-circuits, and some of the second storage sub-circuits each include a cascade A plurality of sub-banks provided, each sub-bank includes a third capacitor, and each of the remaining second sub-circuits includes a second capacitor; wherein, the second end of the first capacitor and the second capacitor The second end is provided in the same layer as the second end of the third capacitor and is made of the same material; and / or, the first end of the first capacitor and the first end of the second capacitor, It is arranged in the same layer as the second end of the third capacitor and is made of the same material.
  • the first storage sub-circuit further includes a first transistor
  • each sub-memory bank further includes a third transistor
  • each of the remaining second storage sub-circuits further includes a second transistor;
  • the gate of the first transistor, the gate of the second transistor, the gate of the third transistor, the second end of the first capacitor, the second end of the second capacitor, and The second end of the third capacitor is provided in the same layer and made of the same material; and / or the first and second electrodes of the first transistor and the first and second electrodes of the second transistor Electrodes, the first and second electrodes of the third transistor, the first end of the first capacitor, the first end of the second capacitor, and the first end of the third capacitor are arranged in the same layer, And made of the same material.
  • a third aspect of an embodiment of the present disclosure provides a detection device, including any of the detection substrates described above.
  • the detection apparatus further includes a processor configured to charge an amount of the electrical signal generated by the photosensitive device that is greater than a maximum stored charge amount of the first storage sub-circuit In the case, input at least one second turn-on signal to the second control signal terminal group to turn on the second storage sub-circuit group to store part of the electrical signal; and, the When the charge amount of the electrical signal is less than or equal to the maximum stored charge amount of the first storage sub-circuit, at least one second cut-off signal is input to the second control signal terminal group to turn off the second storage sub-circuit group .
  • a fourth aspect of an embodiment of the present disclosure provides a driving method for any of the above detection circuits, including: inputting a first cut-off signal to the first control signal terminal, the output control sub-circuit receiving the first Closed under the control of the cut-off signal; input a device voltage to the device voltage terminal, the photosensitive device converts the received optical signal into an electrical signal under the action of the received device voltage, and converts the electrical signal Transmitted to the output point; the first storage sub-circuit stores all the electrical signals, and inputs at least one second cut-off signal to the second control signal terminal group, the second storage sub-circuit group is receiving Under the control of the at least one second cut-off signal; or, the first storage sub-circuit stores part of the electrical signal, and inputs at least one second open signal to the second control signal terminal group, The second storage sub-circuit group stores the remaining part of the electrical signal under the control of the received at least one second on signal; On signal, the output control sub-circuit in a first opening of the received signal under the control of an electrical
  • the first storage sub-circuit stores all the electrical signals, and inputs at least one second cut-off signal to the second control signal terminal group
  • the second storage sub-circuit group is The step of turning off under the control of the received at least one second cut-off signal includes: the charge amount of the electrical signal generated by the photosensitive device is less than or equal to the maximum stored charge amount of the first storage sub-circuit
  • at least one second cut-off signal is input to the second control signal terminal group, and the second storage sub-circuit group is turned off under the control of the received second cut-off signal; or, the first storage The sub-circuit stores part of the electrical signal, and inputs at least one second turn-on signal to the second control signal terminal group, the second storage sub-circuit group controls the received at least one second turn-on signal
  • the step of storing the remaining portion of the electrical signal includes: the amount of charge of the electrical signal generated by the photosensitive device is greater than the maximum amount of stored charge of the first storage subcircuit In the case, at
  • FIG. 1 is a schematic structural diagram of a detection circuit provided by some embodiments of the present disclosure.
  • FIG. 2 is a schematic structural diagram of each sub-circuit in a detection circuit provided by some embodiments of the present disclosure
  • FIG. 3 is a schematic structural diagram of yet another detection circuit provided by some embodiments of the present disclosure.
  • FIG. 5 is a schematic structural diagram of yet another detection circuit provided by some embodiments of the present disclosure.
  • FIG. 6 is a schematic structural diagram of each sub-circuit in another detection circuit provided by some embodiments of the present disclosure.
  • FIG. 7 is a schematic structural diagram of yet another detection circuit provided by some embodiments of the present disclosure.
  • FIG. 8 is a schematic structural diagram of each sub-circuit in another detection circuit provided by some embodiments of the present disclosure.
  • FIG. 9 is a flowchart of a method for driving a detection circuit provided by some embodiments of the present disclosure.
  • FIG. 10 is a schematic diagram of a setting manner of each sub-circuit in a detection circuit provided by some embodiments of the present disclosure
  • FIG. 11 is a schematic structural view of a cross section of a detection circuit shown in FIG. 10 including a PIN-type photodiode along the B-B 'direction;
  • FIG. 12 is a schematic structural view of a cross section of the other detection circuit shown in FIG. 10 including the MSM type photodiode along the B-B ′ direction.
  • R is the resistance of the transistor coupled to the signal receiving terminal in the on state. It is usually a fixed value during design, which is difficult to change. Only by designing the capacitance C of the capacitor of the detection circuit to be small enough, can it be read faster. .
  • the photo-generated electrons gather on the capacitor to charge the capacitor, and the difference in the amount of charge in the different detection circuits after charging is finally converted into a gray-scale picture (that is, with a analog-to-digital converter) and other circuit devices. Different color differences from black to white). If the capacitance of the capacitor of the detection circuit is small, after the photo-generated electrons are filled with the capacitor, the remaining dose of photo-generated electrons cannot be stored, resulting in a smaller gray scale range of the final generated picture, resulting in a reduction in the amount of information available from the picture.
  • an embodiment of the present disclosure provides a detection circuit, as shown in FIG. 1, which includes an output control sub-circuit 10, a first storage sub-circuit 20, a photosensitive device 30, and a second storage sub-circuit group 40.
  • the photosensitive device 30, coupled to the device voltage terminal V and the output point A, is configured to convert the received optical signal into an electrical signal and transmit the electrical signal to the output point A.
  • the specific structure of the photosensitive device 30 is not limited, and the optical signal can be converted into an electrical signal.
  • the optical signal here may be, for example, X-ray, visible light, ultraviolet light, etc., according to the photosensitive principle of the photosensitive device 30 ,
  • the generation of electrical signals by induction of X-rays, the generation of electrical signals by visible light, or the generation of electrical signals by ultraviolet radiation) is not limited here.
  • the "coupling" in the embodiments of the present disclosure is not limited to the physical connection, as long as the signal transmission can be achieved.
  • the first storage sub-circuit 20, coupled to the output point A and the first voltage terminal V1, is configured to store electrical signals.
  • the first storage sub-circuit 20 may store all electrical signals, at this time, the second storage sub-circuit group 40 does not work; the first storage sub-circuit 20 It is also possible to store a part of the electrical signal. In this case, the remaining part of the electrical signal is stored by the second storage sub-circuit group 40.
  • the second storage sub-circuit group 40 coupled to the output point A, the second voltage terminal group V20 and the second control signal terminal group G20, is configured to transmit at least one second turn-on signal transmitted via the second control signal terminal group G20 Under control, some electrical signals are stored.
  • the second storage sub-circuit group 40 refers to a set of second storage sub-circuits, and the number of second storage sub-circuits in the set of second storage sub-circuits is one or more (multiple means two or more than two) . That is to say, the second storage sub-circuit group 40 includes at least one second storage sub-circuit 41, and the coupling manner of the at least one second storage sub-circuit 41 in the detection circuit will be described below.
  • the second voltage terminal group V20 refers to a group of second voltage terminals, and the number of second voltage terminals in the group of second voltage terminals is one or more (multiple refers to two or more). That is to say, the second voltage terminal group V20 includes at least one second voltage terminal V2.
  • the at least one second voltage terminal V2 is configured to provide a voltage to at least one second storage sub-circuit 41, and a coupling manner of the at least one second voltage terminal V2 and at least one second storage sub-circuit 41 will be described below.
  • the second control signal terminal group G20 refers to a group of control signal terminals, and the number of second control signal terminals in the group of second control signal terminals is one or more (multiple means two and two the above). That is to say, the second control signal terminal group G20 includes at least one second control signal terminal G1.
  • the at least one second control signal terminal G2 is configured to provide at least one second on signal or at least one second off signal to at least one second storage sub-circuit 41, at least one second control signal terminal G2 and at least one second storage The coupling method of the sub-circuit 41 will be described below.
  • the second storage sub-circuit group 40 is configured to store part of the electrical signals, that is, the second storage sub-circuit group 40 plays a role of auxiliary storage. During the driving process of the detection circuit, the second storage sub-circuit group 40 does not necessarily work. For example, in order to ensure fast reading, in the case where the first storage sub-circuit 20 cannot meet the storage requirements, the second storage sub-circuit group 40 stores the remaining partial electrical signals at the output point A.
  • the output control sub-circuit 10 coupled to the signal receiving terminal D, the first control signal terminal G1 and the output point A, is configured to control the output point A under the control of the first turn-on signal transmitted through the first control signal terminal G1
  • the electrical signal is transmitted to the signal receiving end D.
  • the detection circuit provided by the embodiment of the present disclosure, by adding the second storage sub-circuit group 40, at least one second turn-on signal transmitted by the second control signal terminal group G20 when the first storage sub-circuit 20 cannot meet the storage requirement Can control the operation of the second storage sub-circuit group 40, and when the first storage sub-circuit 20 can meet the storage requirements, at least one second cut-off signal transmitted by the second control signal terminal group G20 can control the second storage sub-circuit group 40 does not work.
  • the detection circuit when the detection circuit is applied to the detection device, the detection device can not only meet the requirements of fast reading, but also meet the needs of a larger amount of electrical signal storage, expanding the scope of application of the detection device.
  • At least one second voltage terminal V2 in the first voltage terminal V1 and the second voltage terminal group V20 may be further coupled to a voltage terminal (that is, the one voltage terminal can simultaneously move to the first voltage terminal V1 and At least one second voltage terminal V2 in the second voltage terminal group V20 provides the same voltage signal), or may be different voltage terminals.
  • the circuit structure is simpler; at the first voltage terminal V1 and the second voltage terminal
  • different voltage terminals can provide different voltage signals respectively. It should be understood that in some examples, different voltage terminals may also provide the same voltage signal.
  • the second storage sub-circuit group 40 includes a second storage sub-circuit 41
  • the second voltage terminal group V20 includes a second voltage terminal V2
  • the second control signal terminal group G20 A second control signal terminal G2 is included.
  • the second storage sub-circuit 41 is configured to store part of the electrical signal under the control of the second on signal transmitted via the second control signal terminal G2.
  • the second storage subcircuit group 40 includes a second storage subcircuit 41, the second voltage terminal group V20 includes a second voltage terminal V2, and the second control signal terminal group G20 A second control signal terminal G2 is included.
  • the second memory sub-circuit 41 includes a second transistor T2 and a second capacitor C2; the gate of the second transistor T2 is coupled to the second control signal terminal G2, the first electrode of the second transistor T2 is coupled to the output point A, The second electrode of the two transistors T2 is coupled to the first terminal of the second capacitor C2; the second terminal of the second capacitor C2 is coupled to the second voltage terminal V2.
  • the photosensitive device 30 includes a photodiode, one pole of the photodiode is connected to the device voltage terminal V, and the other pole is connected to the output point A.
  • the photodiode may be, for example, an MSM (Metal-Semiconductor-Metal, metal-semiconductor-metal) type photodiode, or a PIN (Positive Intrinsic Negative) type photodiode.
  • MSM Metal-Semiconductor-Metal, metal-semiconductor-metal
  • PIN Positive Intrinsic Negative
  • the capacitance of the second capacitor C2 is less than the capacitance of the first capacitor C1.
  • the second storage sub-circuit group 40 includes a plurality of parallel second storage sub-circuits 41
  • the second voltage terminal group V20 includes a plurality of second voltage terminals V2
  • the second control signal terminal group G20 A plurality of second control signal terminals G2 are included.
  • Each second storage sub-circuit 41 is coupled to the output point A, a corresponding second voltage terminal V2 and a corresponding second control signal terminal G2, and is configured to transmit a second turn-on transmitted at the corresponding second control signal terminal G2 Under the control of the signal, part of the electrical signal at the output point A is stored.
  • each second storage sub-circuit 41 is coupled to a second voltage terminal V2, which means that each second storage sub-circuit 41 has a second voltage terminal V2 coupled to it, and a second storage sub-circuit 41 The coupled second voltage terminal V2 is its corresponding second voltage terminal V2.
  • Each second storage sub-circuit 41 is coupled to a second control signal terminal G2, which means that each second storage sub-circuit 41 has a second control signal terminal G2 coupled to it, and is coupled to a second storage sub-circuit 41 The connected second control signal terminal G2 is its corresponding second control signal terminal G2.
  • the plurality of second voltage terminals V2 may be further coupled to one voltage terminal, so that the same voltage signal may be provided to the plurality of second voltage terminals V2 through one voltage terminal, and the plurality of second voltage terminals V2
  • the coupling method may be set according to actual requirements, which is not limited in the embodiments of the present disclosure.
  • the plurality of second control signal terminals G2 may be further coupled to one control signal terminal, so that the same control signal may be provided to the plurality of second control signal terminals G2 through one control signal terminal, and the plurality of second control signal terminals G2
  • the coupling mode between the control signal terminals G2 can be set according to actual needs, which is not limited in the embodiments of the present disclosure.
  • the plurality of second voltage terminals V2 and the first voltage terminal V1 may be further coupled to a voltage terminal (that is, the one voltage terminal can simultaneously provide the same voltage signal to the plurality of second voltage terminals V2 and the first voltage terminal V1 ), Can also be different voltage ends.
  • At least two of the plurality of second voltage terminals V2 in the second voltage terminal group V20 are coupled to different voltage terminals.
  • the plurality of second voltage terminals V2 are all coupled to different voltage terminals; in still other examples, several of the plurality of second voltage terminals V2 are further coupled to one voltage terminal.
  • the second storage sub-circuit group 40 includes three second storage sub-circuits 41.
  • the first second storage sub-circuit 41 is coupled to a single second voltage terminal V2, the second voltage terminal V2 coupled to the second second storage sub-circuit 41 and the third
  • the two voltage terminals V2 are further coupled to a voltage terminal V0.
  • the plurality of second voltage terminals V2 are further coupled to one voltage terminal V0.
  • At least two of the plurality of second control signal terminals G2 in the second control signal terminal group G20 are coupled to different control signal terminals.
  • the plurality of second control signal terminals G2 are all coupled to different control signal terminals; in still other examples, several of the plurality of second control signal terminals G2 are further coupled to one control signal end.
  • the second storage sub-circuit group 40 includes three second storage sub-circuits 41.
  • the first second storage sub-circuit 41 is coupled to a single second control signal terminal G2, the second control signal terminal G2 coupled to the second second storage sub-circuit 41 and the third second storage sub-circuit 41 are coupled
  • the second control signal terminal G2 is further coupled to a control signal terminal G0.
  • control signal terminal G2 only a few of the plurality of second control signal terminals G2 are further coupled to one control signal terminal G0 in FIG. 3-8, which does not affect the plurality of second control signal terminals described in the embodiments of the present disclosure.
  • Several coupling modes of the control signal terminal G2 are further coupled to one control signal terminal are defined. It should be understood that different control signal terminals can also provide the same turn-on signal or turn-off signal.
  • the second control signal terminals G2 are further coupled to one control signal terminal G0.
  • the maximum storage charge amount of the second storage sub-circuit group 40 is different from the maximum storage charge amount of the first storage sub-circuit 20, where the maximum storage charge amount refers to the maximum amount of charge that can be stored by one circuit structure .
  • the capacitance C of the two is the same and the potential difference U is different; In other examples, it means that the capacitance C of the two is different and the potential difference U is the same; in other examples, it means that the capacitance C of the two is different and the potential difference U is also different.
  • the maximum storage charge amount of the second storage sub-circuit group 40 is the maximum storage charge amount of the second storage sub-circuit; when the first When the second storage sub-circuit group 40 includes multiple second storage sub-circuits, the maximum stored charge amount of the second storage sub-circuit group 40 is the sum of the maximum stored charge amounts of the multiple second storage sub-circuits.
  • the maximum storage charge amount of the second storage sub-circuit group 40 is greater than the maximum storage charge amount of the first storage sub-circuit 20.
  • the second storage sub-circuit group 40 includes a plurality of second storage sub-circuits 41.
  • the maximum stored charge amounts of the plurality of second storage sub-circuits 41 are all the same, or are not completely the same. In some embodiments, the plurality of second storage sub-circuits 41 have different maximum stored charge amounts.
  • the second storage sub-circuit group 40 include a plurality of second storage sub-circuits 41 directly coupled to the output point A, the electrical signal at the output point A can be directly transmitted to each second storage sub-circuit 41 , Can store the electric signal of output point A to the greatest extent, reduce the loss of electric signal.
  • the second storage sub-circuit group 40 includes three second storage sub-circuits 41, the second voltage terminal group V20 includes three second voltage terminals V2, and a second control signal terminal
  • the group G20 includes three second control signal terminals G2.
  • Each second storage sub-circuit 41 includes a second transistor T2 and a second capacitor C2.
  • each second storage sub-circuit 41 the gate of the second transistor T2 is coupled to a corresponding second control signal terminal G2, the first electrode of the second transistor T2 is coupled to the output point A, and the second electrode of the second transistor T2 The two poles are coupled to the first end of the second capacitor C2.
  • the second terminal of the second capacitor C2 is coupled to a corresponding second voltage terminal V2.
  • the three second control signal terminals G2 are different control signal terminals; the second voltage terminal V2 coupled with the first second storage sub-circuit 41 is a separate voltage terminal, and is coupled with the second second storage sub-circuit 41 The connected second voltage terminal V2 and the second voltage terminal V2 coupled to the third second storage sub-circuit 41 are further coupled to a voltage terminal V0.
  • the second storage sub-circuit group 40 includes a plurality of second storage sub-circuits 41
  • the second voltage terminal group V20 includes a plurality of second voltage terminals V2
  • the second control signal terminal group G20 includes a plurality of second Two control signal terminal G2.
  • At least one of the plurality of second storage sub-circuits 41 includes a plurality of sub-banks 411 arranged in cascade, that is, the circuit relationship between the plurality of sub-banks 411 is similar to a series connection.
  • the first-stage sub-memory 411 coupled to the output point A, a corresponding second voltage terminal V2 and a corresponding second control signal terminal G2, is configured as a second turn-on transmitted at the corresponding second control signal terminal G2 Under the control of the signal, part of the electrical signal at the output point A is stored.
  • Each sub-bank 411 after the first level, coupled to the sub-bank 411 of the previous level, a corresponding second voltage terminal V2 and a corresponding second control signal terminal G2, is configured to Under the control of the second on signal transmitted by the signal terminal G2, a part of the electrical signal at the output point A is stored.
  • the second storage sub-circuit group 40 includes two second storage sub-circuits 41.
  • the second storage sub-circuit 41 includes three sub-banks 411 arranged in cascade.
  • the first stage sub-memory 411 is coupled to a single second voltage terminal V2, the second voltage end V2 coupled to the second-stage sub-memory 411 and the second voltage terminal coupled to the third-stage sub-memory 411 V2 is further coupled to a voltage terminal V0.
  • the first-level sub-memory 411 is coupled to a single second control signal terminal G2, the second control-signal terminal G2 coupled to the second-level sub-memory 411, and the second coupled to the third-level sub-memory 411
  • the control signal terminal G2 is further coupled to a control signal terminal G0.
  • the maximum amount of stored charge of the plurality of sub-banks 411 are all the same, or not the same. In some embodiments, the plurality of sub-banks 411 have different maximum stored charge amounts.
  • the second control signal terminal group G20 includes a plurality of second control signal terminals G2, and the plurality of second control signal terminals G2 may not simultaneously input an on signal or an off signal.
  • the storage capacity of the detection circuit can be further expanded to realize the signal receiving terminal D on the basis of meeting the demand for the storage amount of electrical signals Fast reading of electrical signals.
  • the second storage sub-circuit group 40 includes two second storage sub-circuits 41.
  • the second second storage sub-circuit 41 includes two sub-banks 411 arranged in cascade.
  • the second voltage terminal group V20 includes three second voltage terminals V2, and the second control signal terminal group G20 includes three second control signal terminals G2.
  • the first and second memory sub-circuits 41 include a second transistor T2 and a second capacitor C2, and each sub-bank 411 includes a third transistor T3 and a third capacitor C3.
  • the second control signal terminal G2 coupled to the gate of the second transistor T2 of the first second memory sub-circuit 41 and the second control coupled to the gate of the third transistor T3 of the two-stage sub-memory 411
  • the signal terminals G2 are all different control signal terminals; the second terminal of the second capacitor C2 of the first and second storage sub-circuit 41 is coupled to a single second voltage terminal V2; and the third terminal of the two-stage sub-bank 411
  • the second voltage terminal V2 coupled to the second terminal of the capacitor C3 is further coupled to a voltage terminal V0.
  • the capacitances of the plurality of third capacitors C3 included in the plurality of sub-banks 411 are all the same, or not the same.
  • the second storage sub-circuit group 40 includes a plurality of second storage sub-circuits 41 arranged in cascade, the second voltage terminal group V20 includes a plurality of second voltage terminals V2, and the second control signal terminal group G20 A plurality of second control signal terminals G2 are included.
  • the first-stage second storage sub-circuit 41 coupled to the output point A, a corresponding second voltage terminal V2, and a corresponding second control signal terminal G2, is configured to transmit the first signal at the corresponding second control signal terminal G2. Under the control of the opening signal, part of the electrical signal at output point A is stored.
  • the second storage subcircuit 41 of each stage after the first stage, coupled to the second storage subcircuit 41 of the previous stage, a corresponding second voltage terminal V2 and a corresponding second control signal terminal G2, are configured to Under the control of the second on signal transmitted by the second control signal terminal G2, a part of the electrical signal at the output point A is stored.
  • the plurality of second voltage terminals V2 and the first voltage terminal V1 may be further coupled to one voltage terminal, or may be different voltage terminals.
  • the second storage sub-circuit group 40 includes three stages of second storage sub-circuits 41 arranged in cascade.
  • the first-stage second storage subcircuit 41 is coupled to the output point A, a corresponding second voltage terminal V2 and a corresponding second control signal terminal G2;
  • the second-stage second storage subcircuit 41 is coupled to the first stage The second storage sub-circuit 41, a corresponding second voltage terminal V2 and a corresponding second control signal terminal G2;
  • the third-stage second storage sub-circuit 41 coupled to the second-stage second storage sub-circuit 41, a corresponding The second voltage terminal V2 and a corresponding second control signal terminal G2.
  • the second voltage terminal V2 coupled to the second-stage second storage sub-circuit 41 and the second voltage terminal V2 coupled to the third-stage second storage sub-circuit 41 are further coupled to a voltage terminal V0;
  • the second control signal terminal G2 coupled to the second-stage second storage sub-circuit 41 and the second control signal terminal G2 coupled to the third-stage second storage sub-circuit 41 are further coupled to a control signal terminal G0.
  • the maximum storage charge amount of the plurality of second storage sub-circuits 41 arranged in cascade is the same; in other embodiments, the maximum storage charge amount of the plurality of second storage sub-circuits 41 arranged in cascade Not exactly the same.
  • the maximum stored charge amount of each second storage sub-circuit 41 should be adjusted according to the design requirements of the above detection circuit, which is not limited here.
  • the detection circuit can meet the requirements of fast reading and large electric signal storage with a simpler structure .
  • the second storage sub-circuit group 40 includes three-stage second storage sub-circuits 41 arranged in cascade, the second voltage terminal group V20 includes three second voltage terminals V2, and the first The second control signal terminal group G20 includes three second control signal terminals G2.
  • Each second storage sub-circuit 41 includes a second transistor T2 and a second capacitor C2.
  • the second control signal terminal G2 coupled to the gate of the second transistor T2 of each second storage sub-circuit 41 is a different control signal terminal; and the second capacitor C2 of each second storage sub-circuit 41
  • the second voltage terminal V2 coupled to the second terminal is further coupled to a voltage terminal V0.
  • the capacitances of the second capacitors C2 included in the plurality of second storage sub-circuits 41 are the same; in other embodiments, the capacitances of the second capacitors C2 included in the plurality of second storage sub-circuits 41 Not exactly the same.
  • the capacitance of each second capacitor C2 should be adjusted according to the design requirements of the above detection circuit, which is not limited here.
  • the types of transistors included in each sub-circuit in the embodiment of the present disclosure are not clearly defined, it means that the types of these transistors may not be limited, that is, the first transistor T1, the second transistor T2, and the third transistor T3 It may be an N-type transistor or a P-type transistor.
  • the above-mentioned transistors included in the detection circuit are all N-type transistors. The following embodiments of the present disclosure are all described by taking the above transistor as an N-type transistor as an example.
  • the first electrode of the above transistor may be a drain and the second electrode may be a source; or, the first electrode may be a source and the second electrode may be a drain.
  • the embodiments of the present disclosure do not limit this.
  • the transistors in the above detection circuit can be divided into enhancement type transistors and depletion type transistors according to the different conduction methods of the transistors.
  • the embodiments of the present disclosure do not limit this.
  • FIG. 9 shows the driving method, which includes:
  • the photosensitive device 30 converts the received optical signal into an electrical signal under the action of the received device voltage, and transmits the electrical signal to the output point A.
  • the photosensitive device 30 may include, for example, a photodiode, and the photodiode may be, for example, a PIN-type photodiode (as shown in FIG. 11), an MSM-type photodiode (as shown in FIG. 12), and so on.
  • the photodiode converts the optical signal into an electrical signal and transmits the electrical signal to the output point A.
  • FIG. 11 schematically shows a PIN-type photodiode, which includes a first electrode 301, a second electrode 302, and a PIN layer 310.
  • the first electrode 301 is coupled to the output point A
  • the second electrode 302 is coupled to the device voltage terminal V.
  • the PIN layer 310 may be configured to receive an optical signal by a P-type semiconductor in the PIN layer 310 or an N-type semiconductor in the PIN layer 310, which is not limited in the embodiments of the present disclosure.
  • FIG. 12 schematically shows an MSM type photodiode, which includes a third electrode 303, a fourth electrode 304, an insulating layer 311, and a semiconductor layer 312.
  • the insulating layer 311 may be made of an insulating material such as polyimide (PI), polyolefin, etc .; the semiconductor layer 312 may be made of a semiconductor material such as a-Si, indium gallium zinc oxide (IGZO).
  • the third electrode 303 is coupled to the output point A, and the fourth electrode 304 is coupled to the device voltage terminal V.
  • the third electrode 303 and the fourth electrode 304 may be interdigitated and cooperate with each other, or configured into other shapes according to actual requirements, which is not limited in the embodiments of the present disclosure.
  • the first storage sub-circuit 20 stores the electrical signal and inputs at least one second cut-off signal to the second control signal terminal group 40.
  • the second storage sub-circuit group 40 controls the received at least one second cut-off signal Off; or, the first storage sub-circuit 20 stores part of the electrical signal, and inputs at least one second turn-on signal to the second control signal terminal group 40, the second storage sub-circuit group 40 receives at least one second turn-on Under the control of the signal, the remaining part of the electrical signal is stored.
  • the first storage sub-circuit 20 must store the electrical signal at the output point A, but the second storage sub-circuit group 40 does not necessarily work.
  • at least one second cut-off signal may be input to the second control signal terminal group G20 to turn off the second storage sub-circuit group 40.
  • the first A memory sub-circuit 20 stores all electrical signals.
  • at least one second turn-on signal is input to the second control signal terminal group G20, and the second storage sub-circuit group 40 receives at least one second turn-on signal Under the control of the storage part of the electrical signal.
  • the first storage sub-circuit 20 stores a part of the electrical signal
  • the second storage sub-circuit group 40 stores the remaining part of the electrical signal.
  • the electrical signal read by the signal reading end D may be the potential difference between the signal reading end D and the output point A, or may be the total charge amount at the output point A.
  • the process of reading the electrical signal should stop providing light to the detection circuit. At this time, the photosensitive device 30 does not convert the optical signal into an electrical signal.
  • the second control signal terminal G2 in the second control signal terminal group G20 has the same signal input in the process of storing the electrical signal and in the process of reading the electrical signal.
  • the second control signal terminal G2 in the second control signal terminal group G20 has the same input signal during the storage of the electrical signal and the process of reading the electrical signal, which means that the second control signal is stored during the storage of the electrical signal.
  • the second cut-off signal is still input to the second control signal terminal G2.
  • the turn-on signal and the turn-off signal input to the control signal terminal may be voltage signals, one of which is a positive voltage and one is a negative voltage.
  • the absolute value of the two values may be the same or different, and can be based on the characteristics of the switch being controlled in the circuit Set accordingly.
  • the device voltage terminal V continues to input the device voltage until after the electrical signal is read.
  • the first storage sub-circuit 20 stores electrical signals and inputs at least one second cut-off signal to the second control signal terminal group 40, and the second storage sub-circuit group 40 receives at least one second cut-off signal
  • the step of turning off under the control of the method includes: in the case where the charge amount of the electrical signal generated by the photosensitive device 30 is less than or equal to the maximum stored charge amount of the first storage sub-circuit 20, input at least one first With the second cut-off signal, the second storage sub-circuit group 40 is turned off under the control of the received at least one second cut-off signal.
  • the first storage sub-circuit 20 stores part of the electrical signals, and inputs at least one second turn-on signal to the second control signal terminal group 40.
  • the second storage sub-circuit group 40 is under the control of the received at least one second turn-on signal.
  • the step of storing the remaining portion of the electrical signal includes: in the case where the charge of the electrical signal generated by the photosensitive device 30 is greater than the maximum stored charge of the first storage sub-circuit 20, inputting at least one first Under the second turn-on signal, the second storage sub-circuit group 40 stores the remaining electrical signals under the control of the received at least one second turn-on signal.
  • S10 includes: inputting a first cut-off signal to the first control signal terminal G1, and the first transistor T1 is turned off under the control of the first cut-off signal;
  • S20 includes: inputting a device voltage to the device voltage terminal V, the photosensitive device 30 converts the received optical signal into an electrical signal under the action of the received device voltage, and transmits the electrical signal to the output point A;
  • S30 includes: the first capacitor C1 stores the electrical signal at the output point A, inputs a second turn-on signal to the second control signal terminal G2, the second transistor T2 turns on, and the second capacitor C2 stores a part of the electrical signal at the output point A Or, input a second cut-off signal to the second control signal terminal G2, control the second transistor T2 to turn off, and the second capacitor C2 will not store the electrical signal at the output point A.
  • S40 includes: inputting a first turn-on signal to the first control signal terminal G1, and under control of the first turn-on signal, the first transistor T1 transmits the electrical signal at the output point A to the signal receiving terminal D.
  • the second control signal terminal G2 in the second control signal terminal group G20 of the detection circuit is further coupled to a control signal terminal.
  • S30 includes: inputting a second turn-on signal to the second control signal terminal group G20, and storing the electric signal under the control of the second turn-on signal by the second storage sub-circuit group 40; or, inputting to the second control signal terminal group G20 With the second cut-off signal, the second storage sub-circuit group 40 is turned off under the control of the second cut-off signal.
  • the second storage sub-circuit group 40 includes a plurality of second storage sub-circuits 41 directly coupled to the output point A, or includes a plurality of second storage sub-circuits 41 arranged in cascade, or directly At least one of the plurality of second memory sub-circuits 41 coupled to the output point A includes a plurality of sub-memory banks 411 arranged in cascade.
  • the detection circuit When a second turn-on signal is input to the second control signal terminal group G20, the detection circuit The second storage sub-circuit 41 in the included second storage sub-circuit group 40 is all turned on, a second cut-off signal is input to the second control signal terminal group G20, and the second storage in the second storage sub-circuit group 40 included in the detection circuit The sub-circuits 41 are all closed.
  • the second storage sub-circuit group 40 includes a plurality of second storage sub-circuits 41 directly coupled to the output point A, and S30 includes: a plurality of second control signals in the second control signal terminal group G20 At least one of the terminals G2 inputs a second turn-on signal; or, a second turn-off signal is input to each second control signal terminal G2 in the second control signal terminal group G20.
  • the second storage sub-circuit group 40 includes three second storage sub-circuits 41 directly coupled to the output point A. If the first and second storage sub-circuits 41 are controlled to be turned on and the second and third second storage sub-circuits 41 are turned off during driving, S30 includes: The control signal terminal G2 inputs a second turn-on signal to control the second transistor T2 in the first second storage sub-circuit 41 to turn on, and the second capacitor C2 in the first second storage sub-circuit 41 performs a part of the electrical signal at the output point A storage. At the same time, a second cut-off signal is input to the second control signal terminal G2 connected to the second and third second storage sub-circuits 41 to control the second transistor T2 in the second and third second storage sub-circuits 41 to turn off.
  • At least one of the plurality of second storage sub-circuits 41 directly coupled to the output point A includes a plurality of sub-banks 411 arranged in cascade, when the second control coupled to the plurality of sub-banks 411 When the signal terminal G2 is further coupled to a control signal terminal, the plurality of sub-banks 411 can be turned on or off at the same time; when the second control signal terminal G2 coupled to the plurality of sub-banks 411 is a different control signal terminal, the The first several levels of the plurality of sub-banks 411 set in cascade can be controlled to be turned on at the same time, or a certain level can be controlled to be turned off (it can also be controlled to control a certain level and subsequent multiple levels to be simultaneously turned off).
  • the second storage sub-circuit group 40 includes a plurality of second storage sub-circuits 41 arranged in cascade, and S30 includes: connecting a second storage sub-circuit 41 connected to the second storage sub-circuit 41 at the current level and before each level.
  • the second control signal terminal G2 inputs a second turn-on signal.
  • at least the second control signal terminal G2 connected to the second storage subcircuit 41 of the next stage adjacent to the current stage inputs a second cut-off signal;
  • at least a second cut-off signal is input to the second control signal terminal G2 connected to the first-stage second storage sub-circuit 41.
  • At least the second cut-off signal is input to the second control signal terminal G2 connected to the first-stage second storage sub-circuit 41, which is only the second A second cut-off signal is input to the control signal terminal G2; in further examples, a second cut-off signal is input to at least the second control signal terminal G2 connected to the second storage subcircuit 41 of the first stage, which is The second control signal terminal G2 connected to the second-stage second storage sub-circuit 41 inputs the second cut-off signal; in still other examples, at least the second control signal terminal G2 connected to the first-stage second storage sub-circuit 41 inputs the second The second cut-off signal is to input the second cut-off signal to the second control signal terminal G2 connected to the second storage sub-circuit 41 of each stage.
  • the second storage sub-circuit group 40 includes three stages of second storage sub-circuits 41 arranged in cascade. If in the driving process, the first and second stages are controlled The second memory sub-circuit 41 is turned on, and the third stage second memory sub-circuit 41 is turned off.
  • S30 includes: inputting the second control signal terminal G2 connected to the first stage and second stage second memory sub-circuit 41 Two turn-on signals to control the second transistor T2 in the second storage subcircuit 41 of the first and second stages to turn on, the second capacitor C2 in the second storage subcircuit 41 of the first and second stages Some electrical signals are stored.
  • a second cut-off signal is input to the second control signal terminal G2 connected to the third-stage second storage sub-circuit 41 to control the second transistor T2 in the third-stage second storage sub-circuit 41 to be turned off.
  • An embodiment of the present disclosure also provides a detection substrate, including a plurality of the detection circuits described above.
  • the multiple detection circuits may be arranged in an array, for example, the multiple detection circuits are arranged such that the first control signal terminal G1 of the same row detection circuit is the same control signal terminal, and the second control signal terminal G2 of the same row detection circuit is The same control signal terminal and the signal receiving terminal D of the same column detection circuit are the same signal receiving terminal.
  • the area of one detection circuit may be, for example, 100 m x 100 m), and the width-to-length ratio of the channel of the transistor in the detection circuit may be, for example, 17/4 m.
  • the detection substrate provided by the embodiments of the present disclosure can also be used in conjunction with a signal conversion device and a display panel.
  • the signal conversion device may convert the electrical signal read by the signal reading end of the detection circuit in the detection substrate into a gray-scale voltage, and drive the pixels on the display panel to emit light, thereby displaying an image.
  • the detection substrate provided by the embodiment of the present disclosure includes any one of the detection circuits described above, and the beneficial effects are the same as those of the detection circuit, which will not be repeated here.
  • the second storage sub-circuit group 40 includes a second storage sub-circuit 41
  • the second storage sub-circuit 41 includes a second capacitor C2
  • the first storage sub-circuit 20 includes a The first capacitor C1; as shown in FIG. 11 or FIG. 12, the second end of the second capacitor C2 and the second end of the first capacitor C1 have the same layer and the same material.
  • the second end of the second capacitor C2 and the second end of the first capacitor C1 have the same layer and the same material means that the second end of the second capacitor C2 and the second end of the first capacitor C1 use the same mask to pass the same pattern Process formation.
  • the above patterning process includes a photolithography process, or a process including a photolithography process and an etching step.
  • the photolithography process refers to a process including film formation (such as chemical vapor deposition film formation, Chemical Vapor Deposition (CVD for short), exposure, development, etc., and forming a pattern using photoresist, reticle, exposure machine, etc.
  • film formation such as chemical vapor deposition film formation, Chemical Vapor Deposition (CVD for short
  • CVD Chemical Vapor Deposition
  • deposit a metal film layer such as Cu, Al, etc.
  • deposit a photoresist use a reticle to form a photoresist pattern
  • expose the metal film layer below and etch the exposed metal film layer to form each metal pattern
  • ashing process is used to remove the remaining photoresist.
  • the second storage sub-circuit group 40 includes a second storage sub-circuit 41
  • the second storage sub-circuit 41 includes a second capacitor C2
  • the first storage sub-circuit 20 includes a The first capacitor C1.
  • the first end of the second capacitor C2 and the first end of the first capacitor C1 have the same layer and the same material.
  • the second storage sub-circuit group 40 includes a second storage sub-circuit 41 including a second transistor T2 and a second capacitor C2, and the output control
  • the sub-circuit 10 includes a first transistor T1
  • the first storage sub-circuit 20 includes a first capacitor C1.
  • the gate of the second transistor T2, the gate of the first transistor T1, the second terminal of the second capacitor C2 and the second terminal of the first capacitor C1 have the same layer and the same material.
  • the second storage sub-circuit group 40 includes a second storage sub-circuit 41 including a second transistor T2 and a second capacitor C2, and the output control
  • the sub-circuit 10 includes a first transistor T1
  • the first storage sub-circuit 20 includes a first capacitor C1.
  • the first and second electrodes of the second transistor T2, the first and second electrodes of the first transistor T1, the first terminal of the second capacitor C2, and The first layer has the same layer and the same material.
  • FIG. 10 only shows a schematic diagram of the distribution of each sub-circuit in a detection circuit, which does not limit the detection circuit in the embodiments of the present disclosure.
  • the detection circuit of the present disclosure can be reasonably designed according to actual needs.
  • the second storage sub-circuit group 40 includes a plurality of second storage sub-circuits 41 directly coupled to the output point A, and each second storage sub-circuit 41 includes a second transistor T2 and a second capacitor C2; the output control sub-circuit 10 includes a first transistor T1, and the first storage sub-circuit 20 includes a first capacitor C1.
  • the gate of the second transistor T2, the gate of the first transistor T1, the second end of the second capacitor C2 and the second end of the first capacitor C1 are of the same layer and the same material; the first and second poles of the second transistor T2 1.
  • the first and second electrodes of the first transistor T1, the first terminal of the second capacitor C2, and the first terminal of the first capacitor C1 have the same layer and the same material.
  • the second storage sub-circuit group 40 includes a plurality of second storage sub-circuits 41 directly coupled to the output point A, and some of the second storage sub-circuits 41 each include a plurality of sub-storages arranged in cascade Body 411, each sub-bank 411 includes a third transistor T3 and a third capacitor C3, and each of the remaining second storage sub-circuits 41 includes a second transistor T2 and a second capacitor C2; output control sub-circuit 10 includes a first transistor T1, and the first storage sub-circuit 20 includes a first capacitor C1.
  • the gate of the second transistor T2, the gate of the third transistor T3, the gate of the first transistor T1, the second terminal of the second capacitor C2, the second terminal of the third capacitor C3, and the second terminal of the first capacitor C1 The same layer and the same material; the first and second electrodes of the second transistor T2, the first and second electrodes of the third transistor T3, the first and second electrodes of the first transistor T1, and the first of the second capacitor C2
  • One end, the first end of the third capacitor C3 and the first end of the first capacitor C1 have the same layer and the same material.
  • the gate of the transistor in the second storage sub-circuit group 40 and the second end of the capacitor, the gate of the transistor in the output control sub-circuit 10, and the second end of the capacitor in the first storage sub-circuit 20 in the same layer , The first and second poles of the transistors in the second storage sub-circuit group 40 and the first end of the capacitor, the first and second poles of the transistors in the output control sub-circuit 10, and the capacitor in the first storage sub-circuit 20
  • the first end has the same layer and the same material, which can simplify the preparation process, save costs, and make the detection substrate thinner and lighter.
  • An embodiment of the present disclosure also provides a detection device, including any one of the detection substrates described above, and the beneficial effects are the same as those of the detection substrates described above, and details are not described herein again.
  • the detection device may be, for example, an amorphous silicon (a-Si) X-ray detector.
  • the amorphous silicon X-ray detector is an X-ray image detector centered on a plurality of amorphous silicon photodiodes arranged in an array. First, X-rays are converted into visible light, and then the amorphous silicon photodiode array generates photo-generated electrons under the action of visible light, and then detects the changes in the electrical signals of the photo-generated electrons and analyzes the read signals to form an image frame.
  • the mode of the detection circuit input signal can be set according to actual needs. Taking the detection circuit in FIG. 1 as an example, mode 1 is to input a second turn-on signal to the second control signal terminal G2 to control the second storage subcircuit 41 is turned on. Mode 2 is to input a second cut-off signal to the second control signal terminal G2 to control the second storage sub-circuit 41 to turn off.
  • the detection device further includes a processor 50, and the processor 50 may be coupled to the output point A.
  • the processor 50 is configured to input at least one second turn-on signal to the second control signal terminal group 40 when the charge amount of the electric signal generated by the photosensitive device 30 is greater than the maximum stored charge amount of the first storage sub-circuit 20, so that The second storage sub-circuit group 40 is turned on to store part of the electrical signal; and, in the case where the electric signal generated by the photosensitive device 30 has a charge amount less than or equal to the maximum stored charge amount of the first storage sub-circuit 20, the second control The signal terminal group 40 inputs at least one second cut-off signal to turn off the second storage sub-circuit group 40.
  • the processor 50 can, for example, detect the charge amount of the electric signal at the output point A and compare it with the known maximum stored charge amount of the first storage sub-circuit 20. In the case where the charge amount of the electric signal at the output point A is greater than the maximum stored charge amount of the first storage sub-circuit 20, at least one second turn-on signal is input to the second control signal terminal group 40 to make the second storage sub-circuit group 40 Turn on to store part of the electrical signal; and, in the case where the electric quantity of the electric signal at the output point A is less than or equal to the maximum stored electrical quantity of the first storage sub-circuit 20, input at least one first Two cut-off signals to turn off the second storage sub-circuit group 40.
  • the detection device can realize intelligent control, by dynamically monitoring the charge amount of the electrical signal at the output point A, to intelligently control the second storage sub-circuit group 40 to be turned on or off.

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Abstract

一种探测电路及其驱动方法、探测基板、探测器装置。探测电路包括：感光器件（30），耦接器件电压端（V）和输出点（A），被配置为将接收到的光信号转换成电信号，并将电信号传输至输出点（A）；第一存储子电路（20），耦接输出点（A）和第一电压端（V1），被配置为对至少部分电信号进行存储；第二存储子电路组（40），耦接输出点（A）、第二电压端组（V20）以及第二控制信号端组（G20），被配置为在经由第二控制信号端组（G20）传输的至少一个第二开启信号的控制下，对部分电信号进行存储；输出控制子电路（10），耦接信号接收端（D）、第一控制信号端（G1）以及输出点（A），被配置为在经由第一控制信号端（G1）传输的第一开启信号的控制下，将输出点（A）的电信号传输至信号接收端（D）。

Description

探测电路及其驱动方法、探测基板、探测装置
本申请要求于2018年11月07日提交中国专利局、申请号为201811317887.1、申请名称为“探测电路及其驱动方法、基板、探测器”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及探测装置技术领域，尤其涉及一种探测电路及其驱动方法、探测基板、探测装置。
背景技术
随着电子技术的发展，采用电子技术实现精确的信息采集的探测装置为人们的日常生活带来了极大的便利。
探测装置通过传感器将接收到的光信号转换为电信号(即光生电子)。能实现快速读取，又能满足较大的光生电子存储量的探测装置，为未来探测装置的发展趋势。
公开内容
本公开实施例第一方面提供一种探测电路，包括输出控制子电路、第一存储子电路、感光器件、以及第二存储子电路组。所述感光器件，耦接器件电压端和输出点，被配置为将接收到的光信号转换成电信号，并将所述电信号传输至所述输出点；所述第一存储子电路，耦接所述输出点和第一电压端，被配置为对至少部分所述电信号进行存储；所述第二存储子电路组，耦接所述输出点、第二电压端组以及第二控制信号端组，被配置为在经由所述第二控制信号端组传输的至少一个第二开启信号的控制下，对部分所述电信号进行存储；所述输出控制子电路，耦接信号接收端、第一控制信号端以及所述输出点，被配置为在经由所述第一控制信号端传输的第一开启信号的控制下，将所述输出点的电信号传输至所述信号接收端。
在本公开一些实施例中，所述第二存储子电路组包括一个第二存储子电路，所述第二电压端组包括一个第二电压端，以及所述第二控制信号端组包括一个第二控制信号端；其中，所述第二存储子电路被配置为在经由所述第二控制信号端传输的第二开启信号的控制下，对部分所述电信号进行存储。
在本公开一些实施例中，所述第二存储子电路组包括多个第二存储子电 路，所述第二电压端组包括多个第二电压端，以及所述第二控制信号端组包括多个第二控制信号端；每个所述第二存储子电路耦接所述输出点、一个相应的第二电压端以及一个相应的第二控制信号端，被配置为在所述相应的第二控制信号端传输的第二开启信号的控制下，对部分所述电信号进行存储。
在本公开一些实施例中，所述第二存储子电路组包括多个第二存储子电路，所述第二电压端组包括多个第二电压端，以及所述第二控制信号端组包括多个第二控制信号端。在所述多个第二存储子电路中，部分第二存储子电路中的每个包括级联设置的多个子存储体；第一级子存储体，耦接所述输出点、一个相应的第二电压端以及一个相应的第二控制信号端，被配置为在所述相应的第二控制信号端传输的第二开启信号的控制下，对部分所述电信号进行存储；第一级以后的每级所述子存储体，耦接前一级所述子存储体、一个相应的第二电压端以及一个相应的第二控制信号端，被配置为在所述相应的第二控制信号端传输的第二开启信号的控制下，对部分所述电信号进行存储。其余部分第二存储子电路中的每个耦接所述输出点、一个相应的第二电压端以及一个相应的第二控制信号端，被配置为在所述相应的第二控制信号端传输的第二开启信号的控制下，对部分所述电信号进行存储。
在本公开一些实施例中，所述第二存储子电路组包括级联设置的多个第二存储子电路，所述第二电压端组包括多个第二电压端，以及所述第二控制信号端组包括多个第二控制信号端；第一级第二存储子电路，耦接所述输出点、一个相应的第二电压端以及一个相应的第二控制信号端，被配置为在所述相应的第二控制信号端传输的第二开启信号的控制下，对部分所述电信号进行存储；第一级以后的每级第二存储子电路，耦接前一级第二存储子电路、一个相应的第二电压端以及一个相应的第二控制信号端，被配置为在所述相应的第二控制信号端的控制下，对部分所述电信号进行存储。
在本公开一些实施例中，多个第二控制信号端中的至少两个为不同的控制信号端；和/或，多个第二电压端中的至少两个为不同的电压端。
在本公开一些实施例中，所述多个第二控制信号端进一步耦接至一个控制信号端，和/或所述多个第二电压端进一步耦接至一个电压端。
在本公开一些实施例中，所述第一存储子电路的最大存储电荷量与所述第二存储子电路组的最大存储电荷量不同。
在本公开一些实施例中，所述多个第二存储子电路中的至少两个的最大 存储电荷量不同。
在本公开一些实施例中，所述感光器件包括光电二极管，所述光电二极管的一极耦接所述器件电压端，另一极耦接所述输出点；所述第一存储子电路包括第一电容器，所述第一电容器的第一端耦接所述输出点，第二端耦接所述第一电压端；和，所述输出控制子电路包括第一晶体管，所述第一晶体管的栅极耦接所述第一控制信号端，第一极耦接所述信号接收端，以及第二极耦接所述输出点。
在本公开一些实施例中，所述第二存储子电路包括一个第二晶体管和一个第二电容器；所述第二晶体管的栅极耦接所述第二控制信号端，第一极耦接所述输出点，第二极耦接所述第二电容器的第一端；所述第二电容器的第二端耦接所述第二电压端。
在本公开一些实施例中，每个第二存储子电路包括一个第二晶体管和一个第二电容器；每个第二存储子电路的第二晶体管的栅极耦接一个相应的第二控制信号端，第一极耦接所述输出点，第二极耦接所述第二电容器的第一端；每个第二存储子电路的第二电容器的第二端耦接一个相应的第二电压端。
在本公开一些实施例中，每个子存储体包括一个第三晶体管和一个第三电容器；在所述第一级子存储体中：所述第三晶体管的栅极耦接一个相应的第二控制信号端，第一极耦接所述输出点，第二极耦接所述第三电容器的第一端；所述第三电容器的第二端耦接一个相应的第二电压端；在第一级以后的每级所述子存储体中：所述第三晶体管的栅极耦接一个相应的第二控制信号端，第一极耦接前一级子存储体的第三晶体管的第二极，第二极耦接所述第三电容器的第一端；所述第三电容器的第二端耦接一个相应的第二电压端。所述其余部分第二存储子电路中的每个包括一个第二晶体管和一个第二电容器；其中，所述第二晶体管的栅极耦接一个相应的第二控制信号端，第一极耦接所述输出点，第二极耦接所述第二电容器的第一端；所述第二电容器的第二端耦接一个相应的第二电压端。
在本公开一些实施例中，每个第二存储子电路包括一个第二晶体管和一个第二电容器；在所述第一级第二存储子电路中：所述第二晶体管的栅极耦接一个相应的第二控制信号端，第一极耦接所述输出点，第二极耦接所述第二电容器的第一端；所述第二电容器的第二端耦接一个相应的第二电压端；在第一级以后的每级所述第二存储子电路中：所述第二晶体管的栅极耦接一 个相应的第二控制信号端，第一极耦接前一级第二存储子电路的第二晶体管的第二极，第二极耦接所述第二电容器的第一端；所述第二电容器的第二端耦接一个相应的第二电压端。
本公开实施例第二方面提供一种探测基板，包括多个上述任一种探测电路。
在本公开一些实施例中，所述第一存储子电路包括第一电容器；所述第二存储子电路组包括一个或多个第二存储子电路，每个第二存储子电路包括第二电容器，其中，所述第一电容器的第二端和所述第二电容器的第二端同层设置、且由同种材料制成；和/或，所述第一电容器的第一端和所述第二电容器的第一端同层设置、且由同种材料制成。
在本公开一些实施例中，所述第一存储子电路还包括第一晶体管；每个第二存储子电路还包括第二晶体管；其中，所述第一晶体管的栅极、所述第二晶体管的栅极、所述第一电容器的第二端、以及所述第二电容器的第二端同层设置、且由同种材料制成；和/或，所述第一晶体管的第一极和第二极、所述第二晶体管的第一极和第二极、所述第一电容器的第一端、以及所述第二电容器的第一端同层设置、且由同种材料制成。
在本公开一些实施例中，所述第一存储子电路包括第一电容器；所述第二存储子电路组包括多个第二存储子电路，部分第二存储子电路中的每个包括级联设置的多个子存储体，每个子存储体包括第三电容器，其余部分第二存储子电路中的每个包括第二电容器；其中，所述第一电容器的第二端、所述第二电容器的第二端、和所述第三电容器的第二端同层设置、且由同种材料制成；和/或，所述第一电容器的第一端、所述第二电容器的第一端、和所述第三电容器的第二端同层设置、且由同种材料制成。
在本公开一些实施例中，所述第一存储子电路还包括第一晶体管，每个子存储体还包括第三晶体管，所述其余部分第二存储子电路中的每个还包括第二晶体管；其中，所述第一晶体管的栅极、所述第二晶体管的栅极、所述第三晶体管的栅极、所述第一电容器的第二端、所述第二电容器的第二端、以及所述第三电容器的第二端同层设置、且由同种材料制成；和/或所述第一晶体管的第一极和第二极、所述第二晶体管的第一极和第二极、所述第三晶体管的第一极和第二极、所述第一电容器的第一端、所述第二电容器的第一端、以及所述第三电容器的第一端同层设置、且由同种材料制成。
本公开实施例第三方面提供一种探测装置，包括上述任一种探测基板。
在本公开一些实施例中，探测装置还包括处理器，所述处理器被配置为在所述感光器件产生的所述电信号的电荷量大于所述第一存储子电路的最大存储电荷量的情况下，向所述第二控制信号端组输入至少一个第二开启信号，使所述第二存储子电路组开启，以存储部分所述电信号；以及，在所述感光器件产生的所述电信号的电荷量小于或等于所述第一存储子电路的最大存储电荷量的情况下，向第二控制信号端组输入至少一个第二截止信号，以使所述第二存储子电路组关闭。
本公开实施例第四方面提供一种上述任一种探测电路的驱动方法，包括：向所述第一控制信号端输入第一截止信号，所述输出控制子电路在接收到的所述第一截止信号的控制下关闭；向所述器件电压端输入器件电压，所述感光器件在接收到的所述器件电压的作用下，将接收到的光信号转换成电信号，并将所述电信号传输至所述输出点；所述第一存储子电路存储所有的所述电信号，且向所述第二控制信号端组输入至少一个第二截止信号，所述第二存储子电路组在接收到的所述至少一个第二截止信号的控制下关闭；或者，所述第一存储子电路存储部分的所述电信号，且向所述第二控制信号端组输入至少一个第二开启信号，所述第二存储子电路组在接收到的所述至少一个第二开启信号的控制下，存储剩余部分的所述电信号；向所述第一控制信号端输入第一开启信号，所述输出控制子电路在接收到的所述第一开启信号的控制下，将所述输出点的电信号传输至所述信号接收端。
在本公开一些实施例中，所述第一存储子电路存储所有的所述电信号，且向所述第二控制信号端组输入至少一个第二截止信号，所述第二存储子电路组在接收到的所述至少一个第二截止信号的控制下关闭的步骤，包括：在所述感光器件产生的所述电信号的电荷量小于或等于所述第一存储子电路的最大存储电荷量的情况下，向所述第二控制信号端组输入至少一个第二截止信号，所述第二存储子电路组在接收到的所述第二截止信号的控制下关闭；或者，所述第一存储子电路存储部分的所述电信号，且向所述第二控制信号端组输入至少一个第二开启信号，所述第二存储子电路组在接收到的所述至少一个第二开启信号的控制下，存储剩余部分的所述电信号的步骤，包括：在所述感光器件产生的所述电信号的电荷量大于所述第一存储子电路的最大存储电荷量的情况下，向所述第二控制信号端组输入至少一个第二开启信号，所述第二存储子电路组在接收到的所述至少一个第二开启信号的控制下，存 储剩余部分的所述电信号。
附图说明
为了更清楚地说明本公开实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开一些实施例提供的一种探测电路的结构示意图；
图2为本公开一些实施例提供的一种探测电路中各子电路的结构示意图；
图3为本公开一些实施例提供的又一种探测电路的结构示意图；
图4为本公开一些实施例提供的又一种探测电路中各子电路结构示意图；
图5为本公开一些实施例提供的又一种探测电路的结构示意图；
图6为本公开一些实施例提供的又一种探测电路中各子电路结构示意图；
图7为本公开一些实施例提供的又一种探测电路的结构示意图；
图8为本公开一些实施例提供的又一种探测电路中各子电路结构示意图；
图9为本公开一些实施例提供的一种探测电路的驱动方法的流程图；
图10为本公开一些实施例提供的一种探测电路中各子电路的设置方式的示意图；
图11为包括有PIN型光电二极管的图10所示的一种探测电路沿B-B′方向的截面的结构示意图；和
图12为包括有MSM型光电二极管的图10所示的另一种探测电路沿B-B′方向的截面的结构示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
在读取探测电路的信号过程中，为达到较高的信号读取量，读取时间需小于或等于10RC。R为与信号接收端耦接的晶体管在开启状态下的阻值，在设计时通常为固定值，难以改变，只有将探测电路的电容器的电容C设计地足够小，才能达到较快地读取。
光生电子聚集在电容器上对电容器进行充电，充电后的不同探测电路中电荷量的差异，最终通过ADC(Analog-to-digital converter，模拟数字转换器)等电路器件转换为灰阶画面(即具有从黑色到白色的不同颜色差异)。如果探测电路的电容器的电容较小，光生电子充满电容器后，剩余剂量的光生电子则无法被存储，导致最终生成的画面整体灰阶范围较小，从而导致可由画面获得的信息量减少。
基于此，本公开实施例提供一种探测电路，如图1所示，其包括输出控制子电路10、第一存储子电路20、感光器件30、以及第二存储子电路组40。
在一些实施例中，感光器件30，耦接器件电压端V和输出点A，被配置为将接收到的光信号转换成电信号，并将电信号传输至输出点A。
其中，不对感光器件30的具体结构进行限定，能够将光信号转换为电信号即可，此处的光信号，例如可以是X射线、可见光、紫外线等，应根据感光器件30的感光原理(即，感应X射线生成电信号、或者感应可见光生成电信号、或者感应紫外线生成电信号)选择，在此不作限定。
本公开实施例中的“耦接”，不限定为物理关系上的连接，只要能实现信号的传输即可。
第一存储子电路20，耦接输出点A和第一电压端V1，被配置为对电信号进行存储。
其中，输出点A上的电信号，根据不同的探测需求，第一存储子电路20可以是对全部电信号进行存储，此时，第二存储子电路组40不工作；第一存储子电路20也可以是对电信号中的部分进行存储，此时，电信号中剩余的部分由第二存储子电路组40进行存储。
第二存储子电路组40，耦接输出点A、第二电压端组V20以及第二控制信号端组G20，被配置为在经由第二控制信号端组G20传输的至少一个第二开启信号的控制下，对部分电信号进行存储。
第二存储子电路组40是指，一组第二存储子电路，一组第二存储子电路中第二存储子电路的数量为一个或多个(多个是指两个及两个以上)。也即是说，第二存储子电路组40包括至少一个第二存储子电路41，该至少一个第二存储子电路41在探测电路中的耦接方式将在下文进行描述。
同样地，第二电压端组V20是指，一组第二电压端，一组第二电压端中的第二电压端的数量为一个或多个(多个是指两个及两个以上)。也即是说， 第二电压端组V20包括至少一个第二电压端V2。该至少一个第二电压端V2被配置为向至少一个第二存储子电路41提供电压，至少一个第二电压端V2与至少一个第二存储子电路41的耦接方式将在下文进行描述。
又同样地，第二控制信号端组G20是指，一组控制信号端，一组第二控制信号端中的第二控制信号端的数量为一个或多个(多个是指两个及两个以上)。也即是说，第二控制信号端组G20包括至少一个第二控制信号端G1。该至少一个第二控制信号端G2被配置为向至少一个第二存储子电路41提供至少一个第二开启信号或至少一个第二截止信号，至少一个第二控制信号端G2与至少一个第二存储子电路41的耦接方式将在下文进行描述。
其中，第二存储子电路组40被配置为对部分电信号进行存储，即第二存储子电路组40起到辅助存储的作用。在探测电路的驱动过程中，第二存储子电路组40不一定工作。示例地，为了保证快速读取，在第一存储子电路20无法满足存储需求的情况下，第二存储子电路组40对输出点A上的剩余的部分电信号进行存储。
输出控制子电路10，耦接信号接收端D、第一控制信号端G1以及输出点A，被配置为在经由第一控制信号端G1传输的第一开启信号的控制下，将输出点A的电信号传输至信号接收端D。
本公开实施例提供的探测电路，通过增加第二存储子电路组40，使得在第一存储子电路20无法满足存储需求的情况下，第二控制信号端组G20传输的至少一个第二开启信号能够控制第二存储子电路组40工作，而在第一存储子电路20能够满足存储需求的情况下，第二控制信号端组G20传输的至少一个第二截止信号能够控制第二存储子电路组40不工作。这样一来，当探测电路应用于探测装置时，探测装置既能满足快速读取的需求，又能满足较大的电信号存储量的需求，扩大探测装置的适用范围。
在一些实施例中，第一电压端V1和第二电压端组V20中的至少一个第二电压端V2可以进一步耦接至一个电压端(即该一个电压端能够同时向第一电压端V1和第二电压端组V20中的至少一个第二电压端V2提供相同的电压信号)，也可以为不同电压端。其中，在第一电压端V1和第二电压端组V20中的至少一个第二电压端V2进一步耦接至一个电压端的情况下，电路结构更简单；在第一电压端V1和第二电压端组V20中的至少一个第二电压端V2为不同电压端的情况下，不同的电压端可以分别提供不同的电压信号。应当理 解的是，在一些示例中，不同的电压端也可以提供相同的电压信号。
在一些实施例中，如图1所示，第二存储子电路组40包括一个第二存储子电路41，第二电压端组V20包括一个第二电压端V2，以及第二控制信号端组G20包括一个第二控制信号端G2。第二存储子电路41被配置为在经由第二控制信号端G2传输的第二开启信号的控制下，对部分电信号进行存储。
在一些实施例中，如图2所示，第二存储子电路组40包括一个第二存储子电路41，第二电压端组V20包括一个第二电压端V2，以及第二控制信号端组G20包括一个第二控制信号端G2。第二存储子电路41包括一个第二晶体管T2和一个第二电容器C2；第二晶体管T2的栅极耦接第二控制信号端G2，第二晶体管T2的第一极耦接输出点A，第二晶体管T2的第二极耦接第二电容器C2的第一端；第二电容器C2的第二端耦接第二电压端V2。
输出控制子电路10包括第一晶体管T1，第一晶体管T1的栅极耦接第一控制信号端G1，第一晶体管T1的第一极耦接信号接收端D，第一晶体管T1的第二极耦接输出点A。
第一存储子电路20包括第一电容器C1，第一电容器C1的第一端耦接输出点A，第一电容器C1的第二端耦接第一电压端V1。
感光器件30包括光电二极管，光电二极管的一极连接器件电压端V，另一极连接输出点A。
其中，光电二极管例如可以是MSM(Metal-Semiconductor-Metal，金属-半导体-金属)型光电二极管，还可以是PIN(Positive Intrinsic Negative)型光电二极管。
在一些实施例中，第二电容器C2的电容量小于第一电容器C1的电容量。
在一些实施例中，第二存储子电路组40包括多个类似于并联的第二存储子电路41，第二电压端组V20包括多个第二电压端V2，以及第二控制信号端组G20包括多个第二控制信号端G2。每个第二存储子电路41耦接输出点A、一个相应的第二电压端V2以及一个相应的第二控制信号端G2，被配置为在相应的第二控制信号端G2传输的第二开启信号的控制下，对输出点A的部分电信号进行存储。
此处，每个第二存储子电路41耦接一个第二电压端V2，是指每个第二存储子电路41均有一个第二电压端V2与其耦接，与一个第二存储子电路41耦接的第二电压端V2即为其相应的第二电压端V2。每个第二存储子电路41 耦接一个第二控制信号端G2，是指每个第二存储子电路41均有一个第二控制信号端G2与其耦接，与一个第二存储子电路41耦接的第二控制信号端G2即为其相应的第二控制信号端G2。在一些示例中，多个第二电压端V2可以进一步耦接至一个电压端，如此，可以通过一个电压端向多个第二电压端V2提供相同的电压信号，多个第二电压端V2之间的耦接方式可以根据实际需求进行设置，本公开实施例对此不做限定。在一些示例中，多个第二控制信号端G2可以进一步耦接至一个控制信号端，如此，可以通过一个控制信号端向多个第二控制信号端G2提供相同的控制信号，多个第二控制信号端G2之间的耦接方式可以根据实际需求进行设置，本公开实施例对此不做限定。
其中，多个第二电压端V2和第一电压端V1可以进一步耦接至一个电压端(即该一个电压端能够同时向多个第二电压端V2和第一电压端V1提供相同的电压信号)，也可以为不同电压端。
在一些实施例中，第二电压端组V20中的多个第二电压端V2中的至少两个耦接至不同的电压端。例如，在一些示例中，多个第二电压端V2均耦接至不同的电压端；在又一些示例中，多个第二电压端V2中的几个进一步耦接至一个电压端。
如图3所示，第二存储子电路组40包括三个第二存储子电路41。第一第二存储子电路41耦接一个单独的第二电压端V2，与第二第二存储子电路41耦接的第二电压端V2和与第三第二存储子电路41耦接的第二电压端V2进一步耦接至一个电压端V0。
需要说明的是，图3-8中仅示意性示出多个第二电压端V2中的几个进一步耦接至一个电压端V0，其不对本公开实施例中描述的多个第二电压端进一步耦接至一个电压端的耦接方式进行限定。应当理解的是，不同的电压端也能够提供相同的电压信号。
在一些实施例中，多个第二电压端V2进一步耦接至一个电压端V0。
在一些实施例中，第二控制信号端组G20中的多个第二控制信号端G2中的至少两个耦接至不同的控制信号端。例如，在一些示例中，多个第二控制信号端G2均耦接至不同的控制信号端；在又一些示例中，多个第二控制信号端G2中的几个进一步耦接至一个控制信号端。
如图3所示，第二存储子电路组40包括三个第二存储子电路41。第一第二存储子电路41耦接一个单独的第二控制信号端G2，与第二第二存储子电 路41耦接的第二控制信号端G2和与第三第二存储子电路41耦接的第二控制信号端G2进一步耦接至一个控制信号端G0。
需要说明的是，图3-8中仅示意性示出多个第二控制信号端G2中的几个进一步耦接至一个控制信号端G0，其不对本公开实施例中描述的多个第二控制信号端G2中的几个进一步耦接至一个控制信号端的耦接方式进行限定。应当理解的是，不同的控制信号端也能够提供相同的开启信号或者截止信号。
在一些实施例中，多个第二控制信号端G2进一步耦接至一个控制信号端G0。
在一些实施例中，第二存储子电路组40的最大存储电荷量与第一存储子电路20的最大存储电荷量不同，其中，最大存储电荷量是指一个电路结构能够存储的最多的电荷量。存储电荷量可以由以下公式得出：Q＝C×U，C为电容量，U为电势差。因此，当第二存储子电路组40的最大存储电荷量与第一存储子电路20的最大存储电荷量不同时，在一些示例中，是指两者的电容量C相同，电势差U不同；在再一些示例中，是指两者的电容量C不同，电势差U相同；在另一些示例中，是指两者的电容量C不同，电势差U也不同。
可以理解的是，当第二存储子电路组40包括一个第二存储子电路时，第二存储子电路组40的最大存储电荷量即为该第二存储子电路的最大存储电荷量；当第二存储子电路组40包括多个第二存储子电路时，第二存储子电路组40的最大存储电荷量即为该多个第二存储子电路的最大存储电荷量之和。
在一些实施例中，第二存储子电路组40的最大存储电荷量大于第一存储子电路20的最大存储电荷量。
在一些实施例中，第二存储子电路组40包括多个第二存储子电路41。其中，多个第二存储子电路41的最大存储电荷量均相同，或者不完全相同。在一些实施例中，多个第二存储子电路41的最大存储电荷量不同。
本公开实施例通过使第二存储子电路组40包括与输出点A直接耦接的多个第二存储子电路41，使得输出点A的电信号可直接传输至每个第二存储子电路41，可以最大限度地存储输出点A的电信号，减少电信号的损失。
在此基础上，当多个第二存储子电路41分别连接不同的第二控制信号端G2时，多个第二存储子电路41被独立控制，这样一来，可根据实际存储需求，控制多个第二存储电路中的某几个开启。从而可在满足电信号存储量需求的基础上，实现信号接收端D对电信号的快速读取。
在一些实施例中，如图4所示，第二存储子电路组40包括三个第二存储子电路41，第二电压端组V20包括三个第二电压端V2，以及第二控制信号端组G20包括三个第二控制信号端G2。每个第二存储子电路41包括一个第二晶体管T2和一个第二电容器C2。
在每个第二存储子电路41中，第二晶体管T2的栅极耦接一个相应的第二控制信号端G2，第二晶体管T2的第一极耦接输出点A，第二晶体管T2的第二极耦接第二电容器C2的第一端。第二电容器C2的第二端耦接一个相应的第二电压端V2。
其中，三个第二控制信号端G2为不同的控制信号端；与第一第二存储子电路41耦接的第二电压端V2为单独的电压端，与第二第二存储子电路41耦接的第二电压端V2和与第三第二存储子电路41耦接的第二电压端V2进一步耦接至一个电压端V0。
在一些实施例中，第二存储子电路组40包括多个第二存储子电路41，第二电压端组V20包括多个第二电压端V2，以及第二控制信号端组G20包括多个第二控制信号端G2。多个第二存储子电路41中的至少一个包括级联设置的多个子存储体411，即多个子存储体411之间的电路关系类似于串联。
第一级子存储体411，耦接输出点A、一个相应的第二电压端V2以及一个相应的第二控制信号端G2，被配置为在相应的第二控制信号端G2传输的第二开启信号的控制下，对输出点A的部分电信号进行存储。
第一级以后的每级子存储体411，耦接前一级子存储体411、一个相应的第二电压端V2以及一个相应的第二控制信号端G2，被配置为在相应的第二控制信号端G2传输的第二开启信号的控制下，对输出点A的部分电信号进行存储。
如图5所示，第二存储子电路组40包括两个第二存储子电路41。第二第二存储子电路41包括级联设置的三级子存储体411。第一级子存储体411耦接一个单独的第二电压端V2，与第二级子存储体411耦接的第二电压端V2和与第三级子存储体411耦接的第二电压端V2进一步耦接至一个电压端V0。第一级子存储体411耦接一个单独的第二控制信号端G2，与第二级子存储体411耦接的第二控制信号端G2和与第三级子存储体411耦接的第二控制信号端G2进一步耦接至一个控制信号端G0。
在一些实施例中，多个子存储体411的最大存储电荷量均相同，或者不 完全相同。在一些实施例中，多个子存储体411的最大存储电荷量不同。
在一些实施例中，第二控制信号端组G20包括多个第二控制信号端G2，多个第二控制信号端G2可不同时输入开启信号或截止信号。
此处，通过使至少一个第二存储子电路41包括级联设置的多个子存储体411，可进一步扩展探测电路的存储能力，以在满足电信号存储量需求的基础上，实现信号接收端D对电信号的快速读取。
在一些实施例中，如图6所示，第二存储子电路组40包括两个第二存储子电路41，第二第二存储子电路41包括级联设置的两级子存储体411，第二电压端组V20包括三个第二电压端V2，以及第二控制信号端组G20包括三个第二控制信号端G2。第一第二存储子电路41包括一个第二晶体管T2和一个第二电容器C2，每个子存储体411包括一个第三晶体管T3和一个第三电容器C3。
其中，与第一第二存储子电路41的第二晶体管T2的栅极耦接的第二控制信号端G2和与两级子存储体411的第三晶体管T3的栅极耦接的第二控制信号端G2均为不同的控制信号端；第一第二存储子电路41的第二电容器C2的第二端与一个单独的第二电压端V2耦接；与两级子存储体411的第三电容器C3的第二端耦接的第二电压端V2进一步耦接至一个电压端V0。
在一些实施例中，多个子存储体411包括的多个第三电容器C3的电容量均相同，或者不完全相同。
在一些实施例中，第二存储子电路组40包括级联设置的多个第二存储子电路41，第二电压端组V20包括多个第二电压端V2，以及第二控制信号端组G20包括多个第二控制信号端G2。
第一级第二存储子电路41，耦接输出点A、一个相应的第二电压端V2以及一个相应的第二控制信号端G2，被配置为在相应的第二控制信号端G2传输的第二开启信号的控制下，对输出点A的部分电信号进行存储。
第一级以后的每级第二存储子电路41，耦接前一级第二存储子电路41、一个相应的第二电压端V2以及一个相应的第二控制信号端G2，被配置为在相应的第二控制信号端G2传输的第二开启信号的控制下，对输出点A的部分电信号进行存储。
其中，多个第二电压端V2和第一电压端V1可以进一步耦接至一个电压端，也可以为不同电压端。
如图7所示，第二存储子电路组40包括级联设置的三级第二存储子电路41。第一级第二存储子电路41，耦接输出点A、一个相应的第二电压端V2和一个相应的第二控制信号端G2；第二级第二存储子电路41，耦接第一级第二存储子电路41、一个相应的第二电压端V2以及一个相应的第二控制信号端G2；第三级第二存储子电路41，耦接第二级第二存储子电路41、一个相应的第二电压端V2以及一个相应的第二控制信号端G2。其中，与第二级第二存储子电路41耦接的第二电压端V2和与第三级第二存储子电路41耦接的第二电压端V2进一步耦接至一个电压端V0；与第二级第二存储子电路41耦接的第二控制信号端G2和与第三级第二存储子电路41耦接的第二制信号端G2进一步耦接至一个控制信号端G0。在一些实施例中，级联设置的多个第二存储子电路41的最大存储电荷量均相同；在另一些实施例中，级联设置的多个第二存储子电路41的最大存储电荷量不完全相同。各个第二存储子电路41的最大存储电荷量应根据上述探测电路的设计需求调整，此处不作限定。
本公开实施例通过使第二存储子电路组40包括级联设置的多个第二存储子电路41，使得探测电路以较简单的结构就能满足快速读取和较大电信号存储量的需求。
在此基础上，当多个第二存储子电路41分别连接不同的第二控制信号端G2时，可根据实际存储需求，控制级联设置的多个第二存储电路41中的前几级开启，如此，可满足不同的电信号存储需求，实现信号接收端D对电信号的快速读取。
在一些实施例中，如图8所示，第二存储子电路组40包括级联设置的三级第二存储子电路41，第二电压端组V20包括三个第二电压端V2，以及第二控制信号端组G20包括三个第二控制信号端G2。每个第二存储子电路41包括一个第二晶体管T2和一个第二电容器C2。
其中，与每个第二存储子电路41的第二晶体管T2的栅极耦接的第二控制信号端G2均为不同的控制信号端；与每个第二存储子电路41的第二电容器C2的第二端耦接的第二电压端V2进一步耦接至一个电压端V0。
在一些实施例中，多个第二存储子电路41包括的第二电容器C2的电容量均相同；在另一些实施例中，多个第二存储子电路41包括的第二电容器C2的电容量不完全相同。各个第二电容器C2的电容量应根据上述探测电路的设计需求调整，此处不作限定。
需要说明的是，本公开实施例中各子电路包括的晶体管的类型没有明确限定时，意味着这些晶体管的类型可以不做限定，即上述第一晶体管T1、第二晶体管T2、第三晶体管T3可以是为N型晶体管或者P型晶体管。在一些实施例中探测电路中包含的上述晶体管均为N型晶体管。本公开以下实施例均是以上述晶体管为N型晶体管为例进行的说明。
其中，上述晶体管的第一极可以是漏极、第二极可以是源极；或者，第一极可以是源极、第二极可以是漏极。本公开实施例对此不作限制。
此外，根据晶体管导电方式的不同，可以将上述探测电路中的晶体管分为增强型晶体管和耗尽型晶体管。本公开实施例对此不作限制。
本公开实施例还提供一种探测电路的驱动方法，图9示出了该驱动方法，其包括：
S10、向第一控制信号端G1输入第一截止信号，输出控制子电路10在接收到的第一截止信号的控制下关闭。
S20、向器件电压端V输入器件电压，感光器件30在接收到的器件电压的作用下，将接收到的光信号转换成电信号，并将电信号传输至输出点A。
其中，感光器件30例如可以包括光电二极管，光电二极管可以为例如PIN型光电二极管(如图11所示)，MSM型光电二极管(如图12所示)等。当向器件电压端V输入器件电压时，光电二极管将光信号转换成电信号，并将电信号传输至输出点A。图11示意性示出了PIN型光电二极管，其包括第一电极301，第二电极302，和PIN层310。第一电极301与输出点A耦接，第二电极302与器件电压端V耦接。其中，PIN层310可以被配置为由PIN层310中的P型半导体接收光信号，或者由PIN层310中的N型半导体接收光信号，本公开实施例对此不作限定。图12示意性示出了MSM型光电二极管，其包括第三电极303，第四电极304，绝缘层311，和半导体层312。绝缘层311可以由例如聚酰亚胺(PI)、聚烯烃等绝缘材料制成；半导体层312可以由例如a-Si、铟镓锌氧化物(IGZO)等半导体材料制成。第三电极303与输出点A耦接，第四电极304与器件电压端V耦接。其中，第三电极303和第四电极304可以为插指状并且互相配合，或者根据实际需求配置为其他形状，本公开实施例对此不作限定。
S30、第一存储子电路20对电信号进行存储，且向第二控制信号端组40输入至少一个第二截止信号，第二存储子电路组40在接收到的至少一个第二 截止信号的控制下关闭；或者，第一存储子电路20存储部分的电信号，且向第二控制信号端组40输入至少一个第二开启信号，第二存储子电路组40在接收到的至少一个第二开启信号的控制下，存储剩余部分的电信号。
也就是说，第一存储子电路20必然要对输出点A的电信号进行存储，但第二存储子电路组40不一定工作。在第一存储子电路20的最大存储电荷量满足存储需求的情况下，可向第二控制信号端组G20输入至少一个第二截止信号，使第二存储子电路组40关闭，此时，第一存储子电路20存储全部的电信号。在第一存储子电路20的最大存储电荷量无法满足存储需求的情况下，向第二控制信号端组G20输入至少一个第二开启信号，第二存储子电路组40在至少一个第二开启信号的控制下，存储部分的电信号。此时，对于输出点A的电信号，第一存储子电路20存储一部分电信号，第二存储子电路组40存储剩余部分的电信号。
S40、向第一控制信号端G1输入第一开启信号，输出控制子电路10在接收到的第一开启信号的控制下，将输出点A的电信号传输至信号接收端D。
其中，信号读取端D读取的电信号可以是信号读取端D与输出点A之间的电势差，也可以是输出点A的总电荷量。
此外，本领域技术人员应该明白，为了确保读取的电信号的准确性，在读取电信号的过程中，应停止向探测电路提供光照。此时，感光器件30不会将光信号转换为电信号。
第二控制信号端组G20中的第二控制信号端G2在存储电信号的过程中和读取电信号的过程中输入的信号相同。
第二控制信号端组G20中的第二控制信号端G2在存储电信号的过程中和读取电信号的过程中输入的信号相同，是指，在存储电信号的过程中向第二控制信号端G2输入第二开启信号，在读取电信号的过程中仍向该第二控制信号端G2输入第二开启信号；在存储电信号的过程中向第二控制信号端G2输入第二截止信号，在读取电信号的过程中仍向该第二控制信号端G2输入第二截止信号。
向控制信号端输入的开启信号和截止信号可以为电压信号，其中，一个是正电压，一个是负电压，两者的数值的绝对值可以相同或者不同，可以根据电路中被控制的开关的特性进行相应设置。
在一些实施例中，在读取电信号的过程中，为了确保读取的电信号的准 确性，器件电压端V持续输入器件电压，直至读取电信号后。在一些实施例中，第一存储子电路20存储电信号，且向第二控制信号端组40输入至少一个第二截止信号，第二存储子电路组40在接收到的至少一个第二截止信号的控制下关闭的步骤，包括：在感光器件30产生的电信号的电荷量小于或等于第一存储子电路20的最大存储电荷量的情况下，向第二控制信号端组40输入至少一个第二截止信号，第二存储子电路组40在接收到的至少一个第二截止信号的控制下关闭。第一存储子电路20存储部分的电信号，且向第二控制信号端组40输入至少一个第二开启信号，第二存储子电路组40在接收到的至少一个第二开启信号的控制下，存储剩余部分的电信号的步骤，包括：在感光器件30产生的电信号的电荷量大于第一存储子电路20的最大存储电荷量的情况下，向第二控制信号端组40输入至少一个第二开启信号，第二存储子电路组40在接收到的至少一个第二开启信号的控制下，存储剩余部分的电信号。
本公开实施例提供的探测电路的驱动方法的有益效果与探测电路的有益效果相同，此处不再赘述。
示例性的，以图2所示的探测电路为例，S10包括：向第一控制信号端G1输入第一截止信号，第一晶体管T1在第一截止信号的控制下关闭；
S20包括：向器件电压端V输入器件电压，感光器件30在接收到的器件电压的作用下，将接收到的光信号转换成电信号，并将电信号传输至输出点A；
S30包括：第一电容器C1对输出点A的电信号进行存储，向第二控制信号端G2输入第二开启信号，第二晶体管T2开启，第二电容器C2对输出点A的部分电信号进行存储；或者，向第二控制信号端G2输入第二截止信号，控制第二晶体管T2关闭，第二电容器C2不会对输出点A的电信号进行存储。
S40包括：向第一控制信号端G1输入第一开启信号，第一晶体管T1在第一开启信号的控制下，将输出点A的电信号传输至信号接收端D。
在一些实施例中，探测电路的第二控制信号端组G20中的第二控制信号端G2进一步耦接至一个控制信号端。S30包括：向第二控制信号端组G20输入第二开启信号，第二存储子电路组40在第二开启信号的控制下，对电信号进行存储；或者，向第二控制信号端组G20输入第二截止信号，第二存储子电路组40在第二截止信号的控制下关闭。
也就是说，此时，无论第二存储子电路组40包括直接与输出点A耦接的 多个第二存储子电路41，还是包括级联设置的多个第二存储子电路41，还是直接与输出点A耦接的多个第二存储子电路41中的至少一个包括级联设置的多个子存储体411，当向第二控制信号端组G20输入第二开启信号的情况下，探测电路包括的第二存储子电路组40中的第二存储子电路41全部开启，向第二控制信号端组G20输入第二截止信号，探测电路包括的第二存储子电路组40中的第二存储子电路41全部关闭。
在一些实施例中，第二存储子电路组40包括直接与输出点A耦接的多个第二存储子电路41，S30包括：向第二控制信号端组G20中的多个第二控制信号端G2的至少一个输入第二开启信号；或者，向第二控制信号端组G20中的每个第二控制信号端G2输入第二截止信号。
示例性的，以图4所示的探测电路为例，第二存储子电路组40包括直接与输出点A耦接的三个第二存储子电路41。若在驱动过程中，控制第一第二存储子电路41开启，控制第二和第三第二存储子电路41截止，此时S30包括：向与第一第二存储子电路41连接的第二控制信号端G2输入第二开启信号，控制第一第二存储子电路41中的第二晶体管T2开启，第一第二存储子电路41中的第二电容器C2对输出点A的部分电信号进行存储。同时，向与第二和第三第二存储子电路41连接的第二控制信号端G2输入第二截止信号，控制第二和第三第二存储子电路41中的第二晶体管T2关闭。
在一些实施例中，直接与输出点A耦接的多个第二存储子电路41中的至少一个包括级联设置的多个子存储体411，当与多个子存储体411耦接的第二控制信号端G2进一步耦接至一个控制信号端时，多个子存储体411可以被同时开启或关闭；当与多个子存储体411耦接的第二控制信号端G2为不同的控制信号端时，可根据需要控制级联设置的多个子存储体411中的前几级同时开启，或者控制某一级关闭(也可以是控制某一级以及之后的多级同时关闭)。
应当理解的是，在控制级联设置的多个子存储体411的某一级关闭的情况下，控制某一级子存储体411关闭后，该级子存储体411之后的子存储体411均处于关闭状态。在控制级联设置的多个子存储体411中的前几级同时开启的情况下，向与前几级子存储体411耦接的第二控制信号端G2均提供第二开启信号。
在一些实施例中，第二存储子电路组40包括级联设置的多个第二存储子电路41，S30包括：向与本级及本级之前的每级第二存储子电路41连接的第 二控制信号端G2输入第二开启信号，本级之后的每级中，至少向与本级相邻的下一级第二存储子电路41连接的第二控制信号端G2输入第二截止信号；或者，至少向与第一级第二存储子电路41连接的第二控制信号端G2输入第二截止信号。
其中，在一些示例中，至少向与第一级第二存储子电路41连接的第二控制信号端G2输入第二截止信号，是仅向与第一级第二存储子电路41连接的第二控制信号端G2输入第二截止信号；在再一些示例中，至少向与第一级第二存储子电路41连接的第二控制信号端G2输入第二截止信号，是向与第一级、第二级第二存储子电路41连接的第二控制信号端G2输入第二截止信号；在又一些示例中，至少向与第一级第二存储子电路41连接的第二控制信号端G2输入第二截止信号，是向与每一级第二存储子电路41连接的第二控制信号端G2输入第二截止信号。
应当理解的是，在控制级联设置的多个第二存储子电路41的某一级关闭的情况下，控制某一级第二存储子电路41关闭后，该级第二存储子电路41之后的第二存储子电路41均处于关闭状态。在控制级联设置的多个第二存储子电路41中的前几级同时开启的情况下，向与前几级第二存储子电路41耦接的第二控制信号端G2均提供第二开启信号。
示例性的，以图8所示的探测电路为例，第二存储子电路组40包括级联设置的三级第二存储子电路41，若在驱动过程中，控制第一级和第二级第二存储子电路41开启，控制第三级第二存储子电路41截止，此时S30包括：向与第一级和第二级第二存储子电路41连接的第二控制信号端G2输入第二开启信号，控制第一级和第二级第二存储子电路41中的第二晶体管T2开启，第一级和第二级第二存储子电路41中的第二电容器C2对输出点A的部分电信号进行存储。同时，向与第三级第二存储子电路41连接的第二控制信号端G2输入第二截止信号，控制第三级第二存储子电路41中的第二晶体管T2关闭。
本公开实施例还提供一种探测基板，包括多个上述探测电路。
其中，多个探测电路例如可以呈阵列排布，例如，多个探测电路设置为同一行探测电路的第一控制信号端G1为同一控制信号端，同一行探测电路的第二控制信号端G2为同一控制信号端，同一列探测电路的信号接收端D为同一信号接收端。一个探测电路的面积例如可以为100μm×100μm)，探测 电路中的晶体管的沟道的宽长比例如可以为17/4μm。
本公开实施例提供的探测基板还可以与信号转换装置以及显示面板配合使用。例如，信号转换装置可以将探测基板中探测电路的信号读取端读取的电信号转换为灰阶电压，并驱动显示面板上的像素发光，从而显示图像。
本公开实施例提供的探测基板，包括上述任一种探测电路，其有益效果与探测电路的有益效果相同，此处不再赘述。
在一些实施例中，如图10所示，第二存储子电路组40包括一个第二存储子电路41，该第二存储子电路41包括一个第二电容器C2，第一存储子电路20包括一个第一电容器C1；如图11或图12所示，第二电容器C2的第二端和第一电容器C1的第二端同层同材料。
其中，第二电容器C2的第二端以及第一电容器C1的第二端同层同材料是指，第二电容器C2的第二端以及第一电容器C1的第二端采用同一掩模版通过同一构图工艺形成。
上述的构图工艺包括光刻工艺，或包括光刻工艺以及刻蚀步骤在内的工艺。光刻工艺是指包括成膜(例如化学气相淀积成膜，Chemical Vapor Deposition，简称CVD)、曝光、显影等过程且利用光刻胶、掩模版、曝光机等形成图形的工艺。例如，沉积金属膜层(例如Cu、Al等金属)，沉积光刻胶，使用一次掩模版形成光刻胶图案、露出下方的金属膜层，对露出的金属膜层进行刻蚀形成各个金属图案，采用例如灰化工艺去除遗留的光刻胶。
在一些实施例中，如图10所示，第二存储子电路组40包括一个第二存储子电路41，该第二存储子电路41包括一个第二电容器C2，第一存储子电路20包括一个第一电容器C1。如图11或图12所示，第二电容器C2的第一端和第一电容器C1的第一端同层同材料。
在一些实施例中，如图10所示，第二存储子电路组40包括一个第二存储子电路41，该第二存储子电路41包括一个第二晶体管T2和一个第二电容器C2，输出控制子电路10包括一个第一晶体管T1，第一存储子电路20包括一个第一电容器C1。如图11或图12所示，第二晶体管T2的栅极、第一晶体管T1的栅极、第二电容器C2的第二端以及第一电容器C1的第二端同层同材料。
在一些实施例中，如图10所示，第二存储子电路组40包括一个第二存储子电路41，该第二存储子电路41包括一个第二晶体管T2和一个第二电容 器C2，输出控制子电路10包括一个第一晶体管T1，第一存储子电路20包括一个第一电容器C1。如图11或图12所示，第二晶体管T2的第一极和第二极、第一晶体管T1的第一极和第二极、第二电容器C2的第一端、以及第一电容器C1的第一端同层同材料。
其中，图10中仅示出了一种探测电路中各子电路的分布的示意图，其不对本公开实施例中的探测电路做任何限定。可以根据实际需要对本公开的探测电路进行合理设计。
在一些实施例中，第二存储子电路组40包括与输出点A直接耦接的多个第二存储子电路41，每个第二存储子电路41包括一个第二晶体管T2和一个第二电容器C2；输出控制子电路10包括一个第一晶体管T1，第一存储子电路20包括一个第一电容器C1。第二晶体管T2的栅极、第一晶体管T1的栅极、第二电容器C2的第二端以及第一电容器C1的第二端同层同材料；第二晶体管T2的第一极和第二极、第一晶体管T1的第一极和第二极、第二电容器C2的第一端、以及第一电容器C1的第一端同层同材料。
在一些实施例中，第二存储子电路组40包括与输出点A直接耦接的多个第二存储子电路41，部分第二存储子电路41中的每个包括级联设置的多个子存储体411，每个子存储体411包括一个第三晶体管T3和一个第三电容器C3，其余部分第二存储子电路41中的每个包括一个第二晶体管T2和一个第二电容器C2；输出控制子电路10包括一个第一晶体管T1，第一存储子电路20包括一个第一电容器C1。第二晶体管T2的栅极、第三晶体管T3的栅极、第一晶体管T1的栅极、第二电容器C2的第二端、第三电容器C3的第二端以及第一电容器C1的第二端同层同材料；第二晶体管T2的第一极和第二极、第三晶体管T3的第一极和第二极、第一晶体管T1的第一极和第二极、第二电容器C2的第一端、第三电容器C3的第一端以及第一电容器C1的第一端同层同材料。
以上，通过将第二存储子电路组40中晶体管的栅极和电容器的第二端、输出控制子电路10中晶体管的栅极、第一存储子电路20中电容器的第二端同层同材料，将第二存储子电路组40中晶体管的第一极和第二极以及电容器的第一端、输出控制子电路10中晶体管的第一极和第二极、第一存储子电路20中电容器的第一端同层同材料，可简化制备工艺，节省成本，使探测基板更轻薄。
本公开实施例还提供一种探测装置，包括上述任一种探测基板，其有益效果与上述探测基板的有益效果相同，此处不再赘述。
其中，探测装置例如可以是非晶硅(a-Si)X射线探测器，非晶硅X射线探测器是一种以阵列排布的多个非晶硅光电二极管为核心的X射线影像探测器。首先X射线被转换为可见光，然后非晶硅光电二极管阵列在可见光的作用下产生光生电子，随后通过检测光生电子的电信号的变化，以及解析读取的信号从而形成影像画面。
在一些实施例中，可根据实际需求设置探测电路输入信号的模式，以图1中的探测电路为例，模式1为向第二控制信号端G2输入第二开启信号以控制第二存储子电路41开启，模式2为向第二控制信号端G2输入第二截止信号以控制第二存储子电路41关闭。
在一些实施例中，如图3所示，探测装置还包括处理器50，处理器50可以与输出点A耦接。处理器50被配置为在感光器件30产生的电信号的电荷量大于第一存储子电路20的最大存储电荷量的情况下，向第二控制信号端组40输入至少一个第二开启信号，使第二存储子电路组40开启，以存储部分电信号；以及，在感光器件30产生的电信号的电荷量小于或等于第一存储子电路20的最大存储电荷量的情况下，向第二控制信号端组40输入至少一个第二截止信号，以使第二存储子电路组40关闭。
处理器50例如可以检测输出点A的电信号的电荷量，并将其与已知的第一存储子电路20的最大存储电荷量进行对比。在输出点A的电信号的电荷量大于第一存储子电路20的最大存储电荷量的情况下，向第二控制信号端组40输入至少一个第二开启信号，使第二存储子电路组40开启，以存储部分电信号；以及，在输出点A的电信号的电荷量小于或等于第一存储子电路20的最大存储电荷量的情况下，向第二控制信号端组40输入至少一个第二截止信号，以使第二存储子电路组40关闭。
这样一来，探测装置可实现智能控制，通过动态监测输出点A的电信号的电荷量，来智能控制开启或关闭第二存储子电路组40。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (23)

  1. 一种探测电路，包括：输出控制子电路、第一存储子电路、感光器件、以及第二存储子电路组；
    所述感光器件，耦接器件电压端和输出点，被配置为将接收到的光信号转换成电信号，并将所述电信号传输至所述输出点；
    所述第一存储子电路，耦接所述输出点和第一电压端，被配置为对至少部分所述电信号进行存储；
    所述第二存储子电路组，耦接所述输出点、第二电压端组以及第二控制信号端组，被配置为在经由所述第二控制信号端组传输的至少一个第二开启信号的控制下，对部分所述电信号进行存储；
    所述输出控制子电路，耦接信号接收端、第一控制信号端以及所述输出点，被配置为在经由所述第一控制信号端传输的第一开启信号的控制下，将所述输出点的电信号传输至所述信号接收端。
  2. 根据权利要求1所述的探测电路，其中，所述第二存储子电路组包括一个第二存储子电路，所述第二电压端组包括一个第二电压端，以及所述第二控制信号端组包括一个第二控制信号端；其中，
    所述第二存储子电路被配置为在经由所述第二控制信号端传输的第二开启信号的控制下，对部分所述电信号进行存储。
  3. 根据权利要求1所述的探测电路，其中，所述第二存储子电路组包括多个第二存储子电路，所述第二电压端组包括多个第二电压端，以及所述第二控制信号端组包括多个第二控制信号端；
    每个所述第二存储子电路耦接所述输出点、一个相应的第二电压端以及一个相应的第二控制信号端，被配置为在所述相应的第二控制信号端传输的第二开启信号的控制下，对部分所述电信号进行存储。
  4. 根据权利要求1所述的探测电路，其中，所述第二存储子电路组包括多个第二存储子电路，所述第二电压端组包括多个第二电压端，以及所述第二控制信号端组包括多个第二控制信号端；
    在所述多个第二存储子电路中，部分第二存储子电路中的每个包括级联设置的多个子存储体；
    第一级子存储体，耦接所述输出点、一个相应的第二电压端以及一个相应的第二控制信号端，被配置为在所述相应的第二控制信号端传输的第二开启信 号的控制下，对部分所述电信号进行存储；
    第一级以后的每级所述子存储体，耦接前一级所述子存储体、一个相应的第二电压端以及一个相应的第二控制信号端，被配置为在所述相应的第二控制信号端传输的第二开启信号的控制下，对部分所述电信号进行存储；
    其余部分第二存储子电路中的每个耦接所述输出点、一个相应的第二电压端以及一个相应的第二控制信号端，被配置为在所述相应的第二控制信号端传输的第二开启信号的控制下，对部分所述电信号进行存储。
  5. 根据权利要求1所述的探测电路，其中，所述第二存储子电路组包括级联设置的多个第二存储子电路，所述第二电压端组包括多个第二电压端，以及所述第二控制信号端组包括多个第二控制信号端；
    第一级第二存储子电路，耦接所述输出点、一个相应的第二电压端以及一个相应的第二控制信号端，被配置为在所述相应的第二控制信号端传输的第二开启信号的控制下，对部分所述电信号进行存储；
    第一级以后的每级第二存储子电路，耦接前一级第二存储子电路、一个相应的第二电压端以及一个相应的第二控制信号端，被配置为在所述相应的第二控制信号端的控制下，对部分所述电信号进行存储。
  6. 根据权利要求3-5中任一项所述的探测电路，其中，
    多个第二控制信号端中的至少两个为不同的控制信号端；和/或，
    多个第二电压端中的至少两个为不同的电压端。
  7. 根据权利要求3-5中任一项所述的探测电路，其中，所述多个第二控制信号端进一步耦接至一个控制信号端，和/或
    所述多个第二电压端进一步耦接至一个电压端。
  8. 根据权利要求2-5中任一项所述的探测电路，其中，所述第一存储子电路的最大存储电荷量与所述第二存储子电路组的最大存储电荷量不同。
  9. 根据权利要求3-5中任一项所述的探测电路，其中，所述多个第二存储子电路中的至少两个的最大存储电荷量不同。
  10. 根据权利要求1所述的探测电路，其中，所述感光器件包括光电二极管，所述光电二极管的一极耦接所述器件电压端，另一极耦接所述输出点；
    所述第一存储子电路包括第一电容器，所述第一电容器的第一端耦接所述输出点，第二端耦接所述第一电压端；和
    所述输出控制子电路包括第一晶体管，所述第一晶体管的栅极耦接所述第一控制信号端，第一极耦接所述信号接收端，以及第二极耦接所述输出点。
  11. 根据权利要求2所述的探测电路，其中，所述第二存储子电路包括一个第二晶体管和一个第二电容器；所述第二晶体管的栅极耦接所述第二控制信号端，第一极耦接所述输出点，第二极耦接所述第二电容器的第一端；所述第二电容器的第二端耦接所述第二电压端。
  12. 根据权利要求3所述的探测电路，其中，
    每个第二存储子电路包括一个第二晶体管和一个第二电容器；
    每个第二存储子电路的第二晶体管的栅极耦接一个相应的第二控制信号端，第一极耦接所述输出点，第二极耦接所述第二电容器的第一端；每个第二存储子电路的第二电容器的第二端耦接一个相应的第二电压端。
  13. 根据权利要求4所述的探测电路，其中，
    每个子存储体包括一个第三晶体管和一个第三电容器；
    在所述第一级子存储体中：
    所述第三晶体管的栅极耦接一个相应的第二控制信号端，第一极耦接所述输出点，第二极耦接所述第三电容器的第一端；所述第三电容器的第二端耦接一个相应的第二电压端；
    在第一级以后的每级子存储体中：
    所述第三晶体管的栅极耦接一个相应的第二控制信号端，第一极耦接前一级子存储体的第三晶体管的第二极，第二极耦接所述第三电容器的第一端；所述第三电容器的第二端耦接一个相应的第二电压端；
    所述其余部分第二存储子电路中的每个包括一个第二晶体管和一个第二电容器；其中，所述第二晶体管的栅极耦接一个相应的第二控制信号端，第一极耦接所述输出点，第二极耦接所述第二电容器的第一端；所述第二电容器的第二端耦接一个相应的第二电压端。
  14. 根据权利要求5所述的探测电路，其中，每个第二存储子电路包括一个第二晶体管和一个第二电容器；
    在所述第一级第二存储子电路中：
    所述第二晶体管的栅极耦接一个相应的第二控制信号端，第一极耦接所述输出点，第二极耦接所述第二电容器的第一端；所述第二电容器的第二端耦接一个相应的第二电压端；
    在第一级以后的每级所述第二存储子电路中：
    所述第二晶体管的栅极耦接一个相应的第二控制信号端，第一极耦接前一级第二存储子电路的第二晶体管的第二极，第二极耦接所述第二电容器的第一 端；所述第二电容器的第二端耦接一个相应的第二电压端。
  15. 一种探测基板，包括多个如权利要求1-14中任一项所述的探测电路。
  16. 根据权利要求15所述的探测基板，其中，所述第一存储子电路包括第一电容器；所述第二存储子电路组包括一个或多个第二存储子电路，每个第二存储子电路包括第二电容器；
    其中，所述第一电容器的第二端和所述第二电容器的第二端同层设置、且由同种材料制成，和/或
    所述第一电容器的第一端和所述第二电容器的第一端同层设置、且由同种材料制成。
  17. 根据权利要求16所述的探测基板，其中，所述第一存储子电路还包括第一晶体管；每个第二存储子电路还包括第二晶体管；
    其中，所述第一晶体管的栅极、所述第二晶体管的栅极、所述第一电容器的第二端、以及所述第二电容器的第二端同层设置、且由同种材料制成，和/或
    所述第一晶体管的第一极和第二极、所述第二晶体管的第一极和第二极、所述第一电容器的第一端、以及所述第二电容器的第一端同层设置、且由同种材料制成。
  18. 根据权利要求15所述的探测基板，其中，所述第一存储子电路包括第一电容器；所述第二存储子电路组包括多个第二存储子电路，部分第二存储子电路中的每个包括级联设置的多个子存储体，每个子存储体包括第三电容器，其余部分第二存储子电路中的每个包括第二电容器；
    其中，所述第一电容器的第二端、所述第二电容器的第二端、和所述第三电容器的第二端同层设置、且由同种材料制成，和/或
    所述第一电容器的第一端、所述第二电容器的第一端、和所述第三电容器的第二端同层设置、且由同种材料制成。
  19. 根据权利要求18所述的探测基板，其中，所述第一存储子电路还包括第一晶体管，每个子存储体还包括第三晶体管，所述其余部分第二存储子电路中的每个还包括第二晶体管；
    其中，所述第一晶体管的栅极、所述第二晶体管的栅极、所述第三晶体管的栅极、所述第一电容器的第二端、所述第二电容器的第二端、以及所述第三电容器的第二端同层设置、且由同种材料制成，和/或
    所述第一晶体管的第一极和第二极、所述第二晶体管的第一极和第二极、所述第三晶体管的第一极和第二极、所述第一电容器的第一端、所述第二电容 器的第一端、以及所述第三电容器的第一端同层设置、且由同种材料制成。
  20. 一种探测装置，包括权利要求15-19中任一项所述的探测基板。
  21. 根据权利要求20所述的探测装置，还包括处理器，所述处理器被配置为在所述感光器件产生的所述电信号的电荷量大于所述第一存储子电路的最大存储电荷量的情况下，向所述第二控制信号端组输入至少一个第二开启信号，使所述第二存储子电路组开启，以存储部分所述电信号；以及，
    在所述感光器件产生的所述电信号的电荷量小于或等于所述第一存储子电路的最大存储电荷量的情况下，向第二控制信号端组输入至少一个第二截止信号，以使所述第二存储子电路组关闭。
  22. 一种权利要求1-14中任一项所述的探测电路的驱动方法，包括：
    向所述第一控制信号端输入第一截止信号，所述输出控制子电路在接收到的所述第一截止信号的控制下关闭；
    向所述器件电压端输入器件电压，所述感光器件在接收到的所述器件电压的作用下，将接收到的光信号转换成电信号，并将所述电信号传输至所述输出点；
    所述第一存储子电路存储所有的所述电信号，且向所述第二控制信号端组输入至少一个第二截止信号，所述第二存储子电路组在接收到的所述至少一个第二截止信号的控制下关闭；或者，所述第一存储子电路存储部分的所述电信号，且向所述第二控制信号端组输入至少一个第二开启信号，所述第二存储子电路组在接收到的所述至少一个第二开启信号的控制下，存储剩余部分的所述电信号；
    向所述第一控制信号端输入第一开启信号，所述输出控制子电路在接收到的所述第一开启信号的控制下，将所述输出点的电信号传输至所述信号接收端。
  23. 根据权利要求22所述的探测电路的驱动方法，其中，
    所述第一存储子电路存储所有的所述电信号，且向所述第二控制信号端组输入至少一个第二截止信号，所述第二存储子电路组在接收到的所述至少一个第二截止信号的控制下关闭的步骤，包括：
    在所述感光器件产生的所述电信号的电荷量小于或等于所述第一存储子电路的最大存储电荷量的情况下，向所述第二控制信号端组输入至少一个第二截止信号，所述第二存储子电路组在接收到的所述第二截止信号的控制下关闭；或者
    所述第一存储子电路存储部分的所述电信号，且向所述第二控制信号端组 输入至少一个第二开启信号，所述第二存储子电路组在接收到的所述至少一个第二开启信号的控制下，存储剩余部分的所述电信号的步骤，包括：
    在所述感光器件产生的所述电信号的电荷量大于所述第一存储子电路的最大存储电荷量的情况下，向所述第二控制信号端组输入至少一个第二开启信号，所述第二存储子电路组在接收到的所述至少一个第二开启信号的控制下，存储剩余部分的所述电信号。
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