WO2021254242A1 - 显示面板及其制作方法、显示装置 - Google Patents

显示面板及其制作方法、显示装置 Download PDF

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Publication number
WO2021254242A1
WO2021254242A1 PCT/CN2021/099355 CN2021099355W WO2021254242A1 WO 2021254242 A1 WO2021254242 A1 WO 2021254242A1 CN 2021099355 W CN2021099355 W CN 2021099355W WO 2021254242 A1 WO2021254242 A1 WO 2021254242A1
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WIPO (PCT)
Prior art keywords
wiring
area
display panel
display
binding
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PCT/CN2021/099355
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English (en)
French (fr)
Inventor
成瑞
张云鹏
孙乐乐
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/770,253 priority Critical patent/US20220393085A1/en
Publication of WO2021254242A1 publication Critical patent/WO2021254242A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/40—OLEDs integrated with touch screens
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04103—Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display panel, a manufacturing method thereof, and a display device.
  • the technology of integrating Touch (On-Cell) on the Cell has gradually become the mainstream.
  • the integrated screen will be made of a Sensor with Touch function on the Panel.
  • Product integration is higher, the screen is lighter and thinner, the frame is narrower, and the user experience is better.
  • An embodiment of the present disclosure provides a display panel, including:
  • a base substrate includes a display area, a wiring area surrounding the display area, and a binding area; the binding area is located on one side of the display area;
  • a first wiring located in the wiring area and at least one second wiring the first wiring is connected to the cathode of the light-emitting element, and both ends of the second wiring are connected with each other in the binding area
  • the first wiring and the second wiring are connected through at least two vias.
  • the display panel further includes two first PIN pins located in the binding area.
  • the two first PIN pins are connected to the second wiring respectively. The two ends are connected, and the voltage applied through the two first PIN pins is the same as the voltage applied on the first trace.
  • the display panel further includes two second PIN pins located in the binding area, which are used to apply a voltage to the first wiring during an aging test.
  • the upper surface of the first trace in the trace area on the opposite side of the binding area is partially covered by the encapsulation layer above it, and the second trace is not connected to the first trace.
  • the part covered by the encapsulation layer is connected.
  • the second wiring located in other wiring areas except the side where the binding area is located and the opposite side of the binding area are arranged on the same layer as the first wiring and located in the first wiring area.
  • the wiring is away from the side of the display area.
  • the second wiring located in other wiring areas except the side where the binding area is located and the opposite side of the binding area are arranged in a different layer from the first wiring.
  • the display panel further includes:
  • the second wiring and the touch layer are provided with the same layer and the same material.
  • the at least two vias are arranged at equal intervals in the wiring area on the opposite side of the binding area.
  • the first wiring is a VSS wiring.
  • Another aspect of the embodiment of the present disclosure also provides a manufacturing method of a display panel, including:
  • the base substrate including a display area, a wiring area surrounding the display area, and a binding area; the binding area is located on one side of the display area;
  • the light-emitting element located in the display area on a side of the first wiring away from the base substrate, the light-emitting element includes a cathode, and the first wiring is connected to the cathode of the light-emitting element;
  • At least one second wiring located in the wiring area is formed, both ends of the second wiring are connected to the first wiring in the binding area, and on the opposite side of the binding area, so The first wire and the second wire are connected by at least two via holes.
  • the forming at least one second wiring located in the wiring area includes:
  • the touch control layer and the second wiring are simultaneously formed by using the same mask through one patterning process.
  • the method further includes:
  • the method further includes:
  • the forming at least one second wiring located in the wiring area includes:
  • the second wiring is formed on a portion of the first wiring that is not covered by the encapsulation layer.
  • the at least two vias are arranged at equal intervals in the wiring area on the opposite side of the binding area.
  • the method further includes: after completing the aging test on the display panel, connecting the side of the binding area and the opposite side of the binding area to the display panel
  • the hierarchical structure including the second wiring is cut to form a display panel with a narrow frame.
  • an embodiment further provides a display device, including the display panel as described above.
  • Figure 1 is a schematic diagram of the design of VSS traces in related technologies
  • FIG. 2a is a schematic structural diagram of a display panel provided by an embodiment of the disclosure.
  • 2b is a schematic structural diagram of a display panel provided by an embodiment of the disclosure.
  • FIG. 3 is a schematic diagram of the overlap between the second wiring and the first wiring in the wiring area on the opposite side of the binding area according to an embodiment of the disclosure
  • FIG. 4 is one of the schematic diagrams of the relative positions of the second wiring and the first wiring in other wiring areas except the side where the binding area is located and the opposite side of the binding area provided by the embodiments of the present disclosure;
  • FIG. 5 is a second schematic diagram of the relative positions of the second wiring and the first wiring of the other wiring areas except the side where the binding area is located and the opposite side of the binding area provided by the embodiments of the present disclosure;
  • FIG. 6 is a schematic flowchart of a manufacturing method of a display panel provided by an embodiment of the disclosure.
  • the display device In the display device manufacturing process, the display device needs to be subjected to an aging test process to eliminate the bright spots and light leakage caused by the PMOS (positive channel Metal Oxide Semiconductor, metal oxide semiconductor field effect transistor) leakage current. At the same time, the use of high current will The R/G/B material has a fast and stable life, thereby eliminating the adverse effects such as image retention.
  • the aging test process it is necessary to make a trade-off between the aging test effect and the applied current/voltage. If the current/voltage is too large, there is a risk of burns in the narrowed area of the power line, and if the current/voltage is too small, there will be weak bright spots. Incomplete elimination or there is a risk of image retention and impure screen display.
  • FIG. 1 is a schematic diagram of the design of the VSS trace in the related technology.
  • the cathode surface of the light-emitting element is overlapped with the peripheral VSS power wiring to realize the power loading of the light-emitting element.
  • the current flowing through all the light-emitting elements in the display area will be converged from the cathode to the VSS power supply line, and finally flow back to the Pad area. That is to say, the current is most concentrated at the VSS power supply line of the Pad area (see Figure 1), all currents of the product are collected in this part.
  • FIG. 2a is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure.
  • the display panel may include a base substrate 20.
  • the base substrate 20 includes a display area 21, a wiring area 22 surrounding the display area 21, and Binding area 23;
  • the binding area 23 is located on one side of the display area 21.
  • the wiring area 22 has a gate shape and is arranged around the display area 21.
  • the binding area 23 is located at the gap of the wiring area 22 in the shape of a gate.
  • a light-emitting element is provided in the display area 21 for light-emitting display.
  • the bonding area 23 is used to set a driving integrated circuit.
  • a first wiring 24 and at least one second wiring 25 are provided in the gate-shaped wiring area 22. The first wiring 24 and the second wiring 25 are both arranged in a gate-shaped manner.
  • the first wiring 24 and the light emitting element The current supplied to the light-emitting element flows in from the anode of the light-emitting element, flows out from the cathode after passing through the luminescent material layer, and finally converges to the first wiring 24, and the two ends of the second wiring 25 are connected to the binding area 23
  • the first wiring 24 is connected, and on the opposite side of the binding area 23, the first wiring 24 and the second wiring 25 are connected through at least two vias 26.
  • the first wiring 24 and the second wiring 25 are arranged in parallel, and both ends of the second wiring 25 are respectively connected to the corner positions of the first wiring 24 in the binding area 23 close to the display area, and, On the opposite side of the binding area 23 (that is, the side far from the binding area 23, the side and the binding area belong to the opposite sides of the display panel), the first wiring 24 and the second wiring 25 pass through at least two paths.
  • the holes 26 are connected, so that the current flowing from the cathode of the light-emitting element to the first trace 24 can finally return to the bonding area through the via 26 and the second trace 25, thereby realizing the shunting effect on the current, thereby reducing
  • the risk of corner burns during the aging test process is reduced, the product yield is effectively improved, and the aging test effect is balanced at the same time.
  • the display panel further includes two first PIN pins 27 located in the binding area 23.
  • the two first PIN pins 27 are respectively connected to both ends of the second trace, and the voltage applied through the two first PIN pins 27 is the same as the voltage applied to the first trace.
  • the display panel further includes two second PIN pins 28 located in the binding area, which are used to apply voltage to the first wiring during the burn-in test.
  • the two second PIN pins 28 may be used to provide voltage to the first wiring 24, and the two first PIN pins 27 may be used to provide voltage to the second wiring 25.
  • the same voltage as in the first wiring 24 is provided.
  • the first wiring 24 and the second wiring 25 can be used to The current flows back to the binding area 23, thereby realizing the shunting effect on the current, thereby reducing the current flowing in the first trace 24, reducing the risk of corner burns during the aging test process, and effectively improving the product yield.
  • the aging test effect is balanced.
  • the bonding area is further provided with a driver integrated circuit, and when the display panel is performing display, the first trace is connected to the driver integrated circuit to provide the current required for the display of the display panel .
  • FIG. 3 is a schematic diagram of the connection between the second wiring and the first wiring in the wiring area on the opposite side of the binding area according to an embodiment of the present disclosure.
  • the first wiring 24 and the second wiring 25 are connected by at least two vias 26.
  • the base substrate 20 may include a base 201 and a buffer layer 202 disposed on the base 201.
  • the base substrate 20 is provided with a first The wiring 24, the first wiring 24 is provided with an interlayer insulating layer 203 and a transfer pattern 204, and a pixel definition layer 206, a spacer layer 207, a first encapsulation layer 208, and a pixel definition layer 206 are sequentially arranged above the transfer pattern 204
  • the upper surface of the first trace 24 is partially covered by the first encapsulation layer 208 located above the first trace 24, and part of the surface of the first trace on the side away from the display area is not partially covered by the first encapsulation layer 208, as shown in FIG. 3 shown.
  • the first trace 24 may be formed on the base substrate, and the first encapsulation layer 208 is formed on the side of the first trace 24 away from the base substrate. At this time, the first encapsulation layer 208 completely covers the first encapsulation layer.
  • the wiring 24 is then patterned to the first encapsulation layer 208 through a patterning process to form at least two via holes 26.
  • the at least two vias 26 expose part of the surface of the first wiring 24, and subsequently, the second wiring 25 may be fabricated on the surface not covered by the first encapsulation layer 208, so as to realize the first wiring 24 and the second wiring 24. Lap connection of trace 25. (Increase the formation process of vias (that is, part of the uncovered surface))
  • the cathode 205 of the light-emitting element is connected to the first wiring 24 through a transfer pattern 204, and the transfer pattern 204 can be made of the same material as the anode of the light-emitting element.
  • a second encapsulation layer 209 may also be provided on the first encapsulation layer 208, and a touch layer 211 and a ground line 210 may also be provided on the second encapsulation layer 209.
  • FIG. 4 is a schematic diagram of the relative positions of the second wiring and the first wiring in other wiring areas except the side where the binding area is located and the opposite side of the binding area provided by the embodiments of the present disclosure. one.
  • the upper surface of the first wiring 24 on the base substrate 20 is located in other wiring areas 22 except for the side where the bonding area is located and the opposite side of the bonding area.
  • the first encapsulation layer 208 above the first trace 24 is completely covered, while the second trace 25 is located on the second encapsulation layer 209 and is arranged adjacent to the ground 210 on the second encapsulation layer 209.
  • the second trace 25 A safe distance should be kept between the ground 210 and the second wiring 25 on the second encapsulation layer 209 to reduce the gap.
  • the display panel further includes a touch layer 211 located above the light-emitting element, and the touch layer 211 may be provided with the same layer and the same material as the second wiring 25.
  • the touch layer 211 and the second wiring 25 are both disposed on the second encapsulation layer 209, and the touch layer 211 may be a touch layer formed by a single layer of metal wiring, or may be formed by a double layer of metal wiring. ⁇ touch layer.
  • the second wiring 25 may be simultaneously formed in the wiring area when a certain layer of metal wiring of the touch layer 211 is formed, or may adopt the same double-layer metal structure as the touch layer.
  • the cathode 205 of the light-emitting element is connected to the first wiring 24 through the transfer pattern 204, and the transfer pattern 204 can be made of the same material as the anode of the light-emitting element.
  • FIG. 5 is a schematic diagram of the relative positions of the second wiring and the first wiring in other wiring areas except the side where the binding area is located and the opposite side of the binding area provided by the embodiments of the present disclosure. of two.
  • the difference from FIG. 4 above is that in other routing areas 22 except for the side where the binding area is located and the opposite side of the binding area, the first routing 24 and the second routing area 22
  • the wiring 25 can be arranged in the same layer, and the second wiring 25 is located on the side of the first wiring 24 away from the display area.
  • the upper surface of the first wiring 24 on the base substrate 20 is located in the first wiring area 22 except for the side where the bonding area is located and the opposite side of the bonding area.
  • the first encapsulation layer 208 above the wiring 24 is completely covered, while the second wiring 25 is located on the side of the first encapsulation layer 208 away from the display area.
  • the narrow frame design of the display device can be facilitated.
  • the hierarchical structure including this part of the second wiring 25 on both sides of the wiring area 22 (when the display panel is rectangular) can be removed, on the basis of realizing the improvement of the aging test effect and reducing the risk of burns , To achieve the purpose of narrow bezel.
  • At least two vias 26 in the wiring area 22 on the opposite side of the bonding area 23 may be arranged at equal intervals to realize that the current flows from the first wiring 24 to the second wiring 25 more dispersedly.
  • 5 vias can be set to obtain a better flow splitting effect.
  • the first wiring 24 is a VSS wiring.
  • the anode of the light-emitting element is connected with the VDD trace, and the cathode is connected with the VSS trace, so as to realize the power loading of the light-emitting element and then the light-emitting display.
  • the current flowing through the first wiring can be shunted, which effectively reduces the current concentration of the first wiring during the normal display and aging test process, and avoids current
  • the occurrence of burns in excessively large areas ensures that a larger current/voltage can be selected during the aging process to obtain a better aging test effect.
  • FIG. 6 is a schematic flowchart of a manufacturing method of a display panel according to an embodiment of the present disclosure.
  • the manufacturing method of the display panel provided by the embodiment of the present disclosure is used to manufacture the display panel in the foregoing embodiment, and the manufacturing method may include:
  • Step 61 Provide a base substrate, the base substrate including a display area, a wiring area surrounding the display area, and a binding area; the binding area is located on one side of the display area;
  • Step 62 forming a first wiring located in the wiring area on the base substrate;
  • Step 63 forming a light-emitting element located in the display area on the side of the first wiring away from the base substrate, the light-emitting element includes a cathode, and the first wiring is connected to the cathode of the light-emitting element ;
  • Step 64 Form at least one second wiring located in the wiring area, the two ends of the second wiring are connected to the first wiring in the binding area, and the pair of the second wiring is in the binding area.
  • the first wire and the second wire are connected through at least two vias.
  • the current flowing through the first trace can be shunted, which effectively reduces the current concentration of the first trace during normal display and aging tests, and avoids excessive current.
  • the occurrence of burns ensures that a larger current/voltage can be selected during the aging test to obtain a better aging test effect.
  • the forming at least one second wiring located in the wiring area includes:
  • the touch control layer and the second wiring are simultaneously formed by using the same mask through one patterning process.
  • the display panel prepared in the embodiment of the present disclosure may also be a touch display panel with a touch function.
  • the touch layer located above the light-emitting element in the display area is formed, it may be simultaneously formed in the wiring area.
  • the second wiring of, that is, the touch layer and the second wiring are formed by a patterning process.
  • the touch layer includes at least one layer of metal traces, a certain layer of metal traces and the second trace of the touch layer are provided with the same layer and the same material.
  • At least two via holes in the wiring area on the opposite side of the bonding area can be arranged at equal intervals to realize that the current flows from the first wiring to the second wiring more dispersedly, and avoiding excessive current concentration .
  • the method further includes:
  • the method further includes:
  • the forming at least one second wiring located in the wiring area includes:
  • the second wiring is formed on a portion of the first wiring that is not covered by the encapsulation layer.
  • the overlap connection of the first wiring and the second wiring is realized.
  • the method further includes:
  • the hierarchical structure of the display panel including the second wiring other than the side where the binding area is located and the opposite side of the binding area Cut off to form a display panel with a narrow frame.
  • the manufacturing method of the display panel of the embodiment of the present disclosure by adding a second wiring in the wiring area during the manufacturing of the display panel, the current flowing through the first wiring can be shunted, effectively reducing normal display and aging tests.
  • the current concentration of the first trace in the process avoids the occurrence of burns where the current is too large, thereby ensuring that a larger current/voltage can be selected during the aging test to obtain a better aging test effect.
  • the display device includes the display panel described in the above product embodiment. Since the display panel in the above embodiment is provided with a second trace, it can be used to control the flow through the first The current of the trace is shunted, which effectively reduces the current concentration of the first trace during the normal display and aging test process, avoids the occurrence of burns where the current is too large, and ensures that the larger selection can be selected during the aging test. To obtain a better aging test effect, the display device in the embodiment of the present disclosure also has the above-mentioned beneficial effects, which will not be repeated here.

Abstract

一种显示面板及其制作方法、显示装置，所述显示面板包括：衬底基板（20），包括显示区域（21）、围绕所述显示区域（21）的走线区域（22）和绑定区域（23）；所述绑定区域（23）位于所述显示区域（21）的一侧；位于显示区域（21）的发光元件；所述发光元件包括阴极（205）；位于走线区域（22）的第一走线（24）和至少一条第二走线（25），第一走线（24）与发光元件的阴极（205）连接，第二走线（25）的两端在绑定区域（23）与第一走线（24）连接，在绑定区域（23）对侧，所述第一走线（24）和所述第二走线（25）通过至少两个过孔（26）进行连接。

Description

显示面板及其制作方法、显示装置
相关申请的交叉引用
本申请主张在2020年6月17日在中国提交的中国专利申请号No.202010553939.6的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，具体涉及一种显示面板及其制作方法、显示装置。
背景技术
随着对柔性屏一体化的要求越来越高，在Cell上集成Touch(On-Cell)的技术逐渐成为主流，与常规柔性屏幕相比，一体化屏幕将具有Touch功能的Sensor制作在Panel上，产品集成度更高，屏幕更加轻薄化，边框更窄、用户体验更好的优点。
发明内容
本公开一方面实施例提供一种显示面板，包括：
衬底基板，所述衬底基板包括显示区域、围绕所述显示区域的走线区域和绑定区域；所述绑定区域位于所述显示区域的一侧；
位于所述显示区域的发光元件；所述发光元件包括阴极；
位于所述走线区域的第一走线和至少一条第二走线，所述第一走线与所述发光元件的阴极连接，所述第二走线的两端在所述绑定区域与所述第一走线连接，在所述绑定区域的对侧，所述第一走线和所述第二走线通过至少两个过孔进行连接。
可选地，所述显示面板还包括位于所述绑定区域中的两个第一PIN引脚，在进行老化测试时，所述两个第一PIN引脚分别与所述第二走线的两端连接，通过所述两个第一PIN引脚施加的电压与施加在所述第一走线上的电压相同。
可选地，所述显示面板还包括位于所述绑定区域中的两个第二PIN引脚， 用于在进行老化测试时，给所述第一走线施加电压。
可选地，位于所述绑定区域对侧的走线区域内的第一走线的上表面被位于其上方的封装层部分覆盖，所述第二走线与所述第一走线上未被所述封装层覆盖的部分连接。
可选地，位于除了所述绑定区域所在的一侧和所述绑定区域对侧的其他走线区域内的第二走线与所述第一走线同层设置并位于所述第一走线远离所述显示区域的一侧。
可选地，位于除了所述绑定区域所在的一侧和所述绑定区域对侧的其他走线区域内的第二走线与所述第一走线不同层设置。
可选地，所述显示面板还包括：
位于所述发光元件上方的触控层，所述第二走线与所述触控层同层同材料设置。
可选地，所述至少两个过孔在所述绑定区域对侧的走线区域内等间隔设置。
可选地，所述第一走线为VSS走线。
本公开另一方面实施例还提供了一种显示面板的制作方法，包括：
提供一衬底基板，所述衬底基板包括显示区域、围绕所述显示区域的走线区域和绑定区域；所述绑定区域位于所述显示区域的一侧；；
在所述衬底基板上形成位于所述走线区域的第一走线，
在所述第一走线远离所述衬底基板的一侧形成位于所述显示区域的发光元件，所述发光元件包括阴极，所述第一走线与所述发光元件的阴极连接；
形成位于所述走线区域的至少一条第二走线，所述第二走线的两端在所述绑定区域与所述第一走线连接，在所述绑定区域的对侧，所述第一走线和所述第二线通过至少两个过孔进行连接。
可选地，所述形成位于所述走线区域的至少一条第二走线包括：
通过一次构图工艺采用同一掩膜板同时形成所述触控层与所述第二走线。
可选地，所述在所述衬底基板上形成位于所述走线区域的第一走线之后，所述方法还包括：
在所述第一走线远离所述衬底基板的一侧形成封装层；
其中，在所述形成位于所述走线区域的至少一条第二走线之前，所述方法还包括：
通过构图工艺形成位于所述绑定区域对侧的走线区域内的至少两个过孔，形成所述第一走线未被所述封装层覆盖的部分；
所述形成位于所述走线区域的至少一条第二走线包括：
在所述第一走线未被所述封装层覆盖的部分上形成所述第二走线。
可选地，所述至少两个过孔在所述绑定区域对侧的走线区域内等间隔设置。
可选地，所述方法还包括：在完成对所述显示面板的老化测试后，将所述绑定区域所在的一侧和所述绑定区域的对侧之外的、所述显示面板的包括所述第二走线的层级结构切除，形成窄边框的显示面板。
本公开又一方面实施例还提供了一种显示装置，包括：如上所述的显示面板。
附图说明
图1为相关技术中VSS走线的设计示意图；
图2a为本公开实施例提供的一种显示面板的结构示意图；
图2b为本公开实施例提供的一种显示面板的结构示意图；
图3为本公开实施例提供的绑定区域对侧的走线区域内的第二走线与第一走线的搭接示意图；
图4为本公开实施例提供的除了所述绑定区域所在的一侧和所述绑定区域的对侧的其他走线区域的第二走线与第一走线的相对位置示意图之一；
图5为本公开实施例提供的除了所述绑定区域所在的一侧和所述绑定区域的对侧的其他走线区域的第二走线与第一走线的相对位置示意图之二；
图6为本公开实施例提供的一种显示面板的制作方法的流程示意图。
具体实施方式
下为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显 然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
在显示设备制作过程中，需要对显示设备进行老化(aging)测试工艺以消除由PMOS(positive channel Metal Oxide Semiconductor，金属氧化物半导体场效应晶体管)漏电流引起的亮点和漏光，同时使用大电流将R/G/B材料寿命快速稳定，从而消除残影等不良影响。老化测试过程中，需要对老化测试效果和所加电流/电压进行取舍，若电流/电压过大，在电源走线变窄区域有灼伤风险，而若电流/电压过小，又会存在弱亮点未完全消除或存在残影以及画面显示不纯的风险。
请参考图1，为相关技术中VSS走线的设计示意图。如图1所示，相关技术中的VSS电源走线设计中，发光元件的阴极面搭接至外围的VSS电源走线以实现发光元件的功率加载。在该设计下，显示区域中流经所有发光元件的电流都将由阴极汇流至VSS电源走线，并最终回流至Pad区，也就是说，在Pad区的VSS电源走线处电流最为集中(见图1中虚线框圈出部分)，产品所有电流都在该部位汇集。进一步，在老化测试工艺过程中，需要将2～3倍于正常显示时的电流加载至显示设备以实现发光元件的老化测试，从而VSS电源走线的电流集中区域将要承受2～3倍于正常显示的电流，发热量极大，从而在老化测试过程中该区域发生灼伤的风险极高，其风险程度与显示设备的显示尺寸以及产品的功耗呈直线正相关，直接影响到产品的产出率。然而，若是为了避免边线灼伤而选用较小的电流进行老化测试，则显示设备则会出现若弱亮点未被完全消除，或存在残影以及画面显示不纯的风险。
请参考图2a，为本公开实施例提供的一种显示面板的结构示意图。如图2所示，本公开实施例提供了一种显示面板，所述显示面板可以包括衬底基板20，衬底基板20上包括显示区域21、围绕所述显示区域21的走线区域22和绑定区域23；所述绑定区域23位于所述显示区域21的一侧。
在一些实施例中，如图2a所示，走线区域22呈门字形，且围绕显示区域21设置。在一些实施例中，绑定区域23位于呈门字形的走线区域22的缺口处。
在一些实施例中，显示区域21内设置有发光元件，用于发光显示。绑定区域23用于设置驱动集成电路。在门字形的走线区域22内设置有第一走线24和至少一条第二走线25，第一走线24和第二走线25均呈门字形设置，第一走线24与发光元件的阴极连接，供给到发光元件的电流由发光元件的阳极流入，经过发光材料层后由阴极流出，最终汇聚到第一走线24，而第二走线25的两端在绑定区域23与第一走线24连接，并且在位于绑定区域23的对侧，第一走线24和第二走线25通过至少两个过孔26进行连接。
也就是说，第一走线24和第二走线25呈并联设置，第二走线25的两端分别与第一走线24在绑定区域23靠近显示区域的拐角位置进行连接，并且，在绑定区域23的对侧(即远离绑定区域23的一侧，该侧与绑定区域属于显示面板的相对的两侧)第一走线24和第二走线25通过至少两个过孔26进行连接，从而使得从发光元件的阴极流到第一走线24的电流还可以通过过孔26经由第二走线25最终回到绑定区域，实现对电流的分流作用，从而减小了第一走线24中流过的电流，降低了老化测试过程可能导致边角灼伤的风险，有效提高了产品良率，同时均衡了老化测试效果。
在一些实施例中，如图2b所示，所述显示面板还包括位于所述绑定区域23中的两个第一PIN引脚27，在进行老化测试时，所述两个第一PIN引脚27分别与所述第二走线的两端连接，通过所述两个第一PIN引脚27施加的电压与施加在所述第一走线上的电压相同。
在一些实施例中，所述显示面板还包括位于所述绑定区域中的两个第二PIN引脚28，用于在进行老化测试时，给所述第一走线施加电压。
在一些实施例中，在进行老化测试时，可以通过所述两个第二PIN引脚28给第一走线24提供电压，通过所述两个第一PIN引脚27给第二走线25提供与第一走线24中相同的电压。这样，进行老化测试时，相比于相关技术中第一走线单独承受2～3倍于正常显示的电流，本公开的显示面板中，可以通过第一走线24和第二走线25将电流回流至绑定区域23，从而实现对电流的分流作用，从而减小了第一走线24中流过的电流，降低了老化测试过程可能导致边角灼伤的风险，有效提高了产品良率，同时均衡了老化测试效果。
在一些实施例中，绑定区域还设置有驱动集成电路，在所述显示面板进 行显示时，所述第一走线与所述驱动集成电路连接，以提供所述显示面板显示所需的电流。
请参考图3，为本公开实施例提供的绑定区域对侧的走线区域内的第二走线与第一走线的连接示意图。
如图3所示，走线区域22中位于绑定区域23对侧的部分区域内，第一走线24和第二走线25通过至少两个过孔26进行连接。
更具体的说，衬底基板20可以包括基底201以及设置于基底201上的缓冲层202，在走线区域22的位于绑定区域23对侧的部分区域内，衬底基板20上设置第一走线24，第一走线24上设置有层间绝缘层203和转接图形204，在转接图形204上方还依次设置有像素定义层206、隔垫物层207、第一封装层208以及第二封装层209。第一走线24的上表面被位于第一走线24上方的第一封装层208部分覆盖，第一走线远离显示区域的一侧的部分表面未被第一封装层208部分覆盖，如图3所示。
在制作工艺中，可以在衬底基板上形成第一走线24，在第一走线24远离衬底基板的一侧形成第一封装层208，此时，第一封装层208完全覆盖第一走线24，之后，通过构图工艺对第一封装层208进行构图，形成至少两个过孔26。所述至少两个过孔26暴露第一走线24的部分表面，后续可以在该未被第一封装层208覆盖的表面上制作第二走线25，从而实现第一走线24和第二走线25的搭接连接。(增加过孔(即部分未覆盖表面)的形成过程)
其中，发光元件的阴极205通过转接图形204与第一走线24连接，转接图形204可以与发光元件的阳极同材料设置。在第一封装层208上还可以设置有第二封装层209，在第二封装层209还可以设置触控层211和地线210。
请参考图4，为本公开实施例提供的除了所述绑定区域所在的一侧和所述绑定区域的对侧的其他走线区域的第二走线与第一走线的相对位置示意图之一。如图4所示，在除了所述绑定区域所在的一侧和所述绑定区域的对侧的其他走线区域22内，衬底基板20上的第一走线24的上表面被位于第一走线24上方的第一封装层208完全覆盖，而第二走线25则位于第二封装层209上，与第二封装层209上的地线210相邻设置，第二走线25与地线210之间需要留有安全距离，将第二走线25设置于第二封装层209上可以减小断差。
本公开实施例中，所述显示面板还包括位于发光元件上方的触控层211，触控层211可以与第二走线25同层同材料设置。
也就是说，触控层211和第二走线25均设置于第二封装层209上，触控层211可以是单层金属走线形成的触控层，也可以是双层金属走线形成的触控层。第二走线25可以在形成触控层211的某一层金属走线时在走线区域同步形成，也可以采用与触控层相同的双层金属的结构。同样的，在走线区域22的两侧区域内，发光元件的阴极205通过转接图形204与第一走线24连接，转接图形204可以与发光元件的阳极同材料设置。
请参考图5，为本公开实施例提供的除了所述绑定区域所在的一侧和所述绑定区域的对侧的其他走线区域的第二走线与第一走线的相对位置示意图之二。如图5所示，与上述图4不同的是，在除了所述绑定区域所在的一侧和所述绑定区域的对侧的其他走线区域22内，第一走线24和第二走线25可以同层设置，并且第二走线25位于第一走线24远离所述显示区域的一侧。
具体地说，在除了所述绑定区域所在的一侧和所述绑定区域的对侧的其他走线区域22内，衬底基板20上的第一走线24的上表面被位于第一走线24上方的第一封装层208完全覆盖，而第二走线25则位于第一封装层208远离所述显示区域的一侧，通过这样的走线设计，可以便于显示设备的窄边框设计，在完成老化测试工艺后，可以将走线区域22两侧(显示面板为矩形时)的包括该部分第二走线25的层级结构切除，在实现老化测试效果提升和降低灼伤风险的基础上，实现了窄边框目的。
在本公开实施例中，绑定区域23的对侧的走线区域22内的至少两个过孔26可以等间隔设置，以实现电流从第一走线24较分散地流向第二走线25，如图2所示，在具体实施时，可以设置5个过孔，以获得较好的分流效果。
本公开实施例中，第一走线24为VSS走线。发光元件的阳极与VDD走线连接，阴极与VSS走线连接，从而实现发光元件的功率加载继而发光显示。
根据本公开实施例的显示面板，通过增设第二走线，可以对流经第一走线的电流进行分流，有效降低了正常显示和老化测试过程中第一走线的电流集中程度，避免了电流过大处发生烧伤的情况的发生，从而确保了老化过程中能够选用较大的电流/电压以获得较好的老化测试效果。
请参考图6，为本公开实施例提供的一种显示面板的制作方法的流程示意图。如图6所示，本公开实施例提供的显示面板的制作方法用于制作上述实施例中的显示面板，所述制作方法可以包括：
步骤61：提供一衬底基板，所述衬底基板包括显示区域、围绕所述显示区域的走线区域和绑定区域；所述绑定区域位于所述显示区域的一侧；
步骤62：在所述衬底基板上形成位于所述走线区域的第一走线；
步骤63：在所述第一走线远离所述衬底基板的一侧形成位于所述显示区域的发光元件，所述发光元件包括阴极，所述第一走线与所述发光元件的阴极连接；
步骤64：形成位于所述走线区域的至少一条第二走线，所述第二走线的两端在所述绑定区域与所述第一走线连接，在所述绑定区域的对侧，所述第一走线和所述第二线通过至少两个过孔进行连接。
本公开实施例中，通过增设第二走线，可以对流经第一走线的电流进行分流，有效降低了正常显示和老化测试过程中第一走线的电流集中程度，避免了电流过大处发生烧伤的情况的发生，从而确保了老化测试过程中能够选用较大的电流/电压以获得较好的老化测试效果。
本公开的一些实施例中，所述形成位于所述走线区域的至少一条第二走线包括：
通过一次构图工艺采用同一掩膜板同时形成所述触控层与所述第二走线。
也就是说，本公开实施例中制备的显示面板还可以是具有触控功能的触控显示面板，在形成位于所述显示区域的发光元件上方的触控层时，可以同步形成位于走线区域的第二走线，也即触控层与所述第二走线通过一次构图工艺形成。在触控层包括至少一层金属走线的情况下，触控层的某一层金属走线与第二走线同层同材料设置。
在本公开实施例中，绑定区域的对侧的走线区域内的至少两个过孔可以等间隔设置，以实现电流从第一走线较分散地流向第二走线，避免电流过于集中。
在一些实施例中，所述在所述衬底基板上形成位于所述走线区域的第一走线之后，所述方法还包括：
在所述第一走线远离所述衬底基板的一侧形成封装层；
其中，在所述形成位于所述走线区域的至少一条第二走线之前，所述方法还包括：
通过构图工艺形成位于所述绑定区域对侧的走线区域内的至少两个过孔，形成所述第一走线未被所述封装层覆盖的部分；
所述形成位于所述走线区域的至少一条第二走线包括：
在所述第一走线未被所述封装层覆盖的部分上形成所述第二走线。
通过在所述第一走线未被所述封装层覆盖的部分上形成所述第二走线，实现所述第一走线和所述第二走线的搭接连接。
在一些实施例中，所述方法还包括：
在完成对所述显示面板的老化测试后，将所述绑定区域所在的一侧和所述绑定区域的对侧之外的、所述显示面板的包括所述第二走线的层级结构切除，形成窄边框的显示面板。
根据本公开实施例的显示面板的制作方法，通过在制作显示面板的过程中在走线区域增设第二走线，可以对流经第一走线的电流进行分流，有效降低了正常显示和老化测试过程中第一走线的电流集中程度，避免了电流过大处发生烧伤的情况的发生，从而确保了老化测试过程中能够选用较大的电流/电压以获得较好的老化测试效果。
本公开再一方面实施例还提供了一种显示装置，所述显示装置包括上述产品实施例所述的显示面板，由于上述实施例中的显示面板通过增设第二走线，可以对流经第一走线的电流进行分流，有效降低了正常显示和老化测试过程中第一走线的电流集中程度，避免了电流过大处发生烧伤的情况的发生，从而确保了老化测试过程中能够选用较大的电流/电压以获得较好的老化测试效果，本公开实施例中的显示装置也对应具有上述有益效果，在此不再赘述。
以上所述是本公开的部分实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (15)

  1. 一种显示面板，包括：
    衬底基板，所述衬底基板包括显示区域、围绕所述显示区域的走线区域和绑定区域；所述绑定区域位于所述显示区域的一侧；
    位于所述显示区域的发光元件；所述发光元件包括阴极；
    位于所述走线区域的第一走线和至少一条第二走线，所述第一走线与所述发光元件的阴极连接，所述第二走线的两端在所述绑定区域与所述第一走线连接，在所述绑定区域的对侧，所述第一走线和所述第二走线通过至少两个过孔进行连接。
  2. 根据权利要求1所述的显示面板，还包括位于所述绑定区域中的两个第一PIN引脚，在进行老化测试时，所述两个第一PIN引脚分别与所述第二走线的两端连接，通过所述两个第一PIN引脚施加的电压与施加在所述第一走线上的电压相同。
  3. 根据权利要求2所述的显示面板，还包括位于所述绑定区域中的两个第二PIN引脚，用于在进行老化测试时，给所述第一走线施加电压。
  4. 根据权利要求1所述的显示面板，其中，位于所述绑定区域对侧的走线区域内的第一走线的上表面被位于其上方的封装层部分覆盖，所述第二走线与所述第一走线上未被所述封装层覆盖的部分连接。
  5. 根据权利要求1所述的显示面板，其中，位于除了所述绑定区域所在的一侧和所述绑定区域对侧的其他走线区域内的第二走线与所述第一走线同层设置并位于所述第一走线远离所述显示区域的一侧。
  6. 根据权利要求1所述的显示面板，其中，位于除了所述绑定区域所在的一侧和所述绑定区域对侧的其他走线区域内的第二走线与所述第一走线不同层设置。
  7. 根据权利要求1所述的显示面板，还包括：
    位于所述发光元件上方的触控层，所述第二走线与所述触控层同层同材料设置。
  8. 根据权利要求1所述的显示面板，其中，所述至少两个过孔在所述绑 定区域对侧的走线区域内等间隔设置。
  9. 根据权利要求1所述的显示面板，其中，所述第一走线为VSS走线。
  10. 一种显示面板的制作方法，包括：
    提供一衬底基板，所述衬底基板包括显示区域、围绕所述显示区域的走线区域和绑定区域；所述绑定区域位于所述显示区域的一侧；
    在所述衬底基板上形成位于所述走线区域的第一走线，
    在所述第一走线远离所述衬底基板的一侧形成位于所述显示区域的发光元件，所述发光元件包括阴极，所述第一走线与所述发光元件的阴极连接；
    形成位于所述走线区域的至少一条第二走线，所述第二走线的两端在所述绑定区域与所述第一走线连接，在所述绑定区域的对侧，所述第一走线和所述第二线通过至少两个过孔进行连接。
  11. 根据权利要求10所述的显示面板的制作方法，其中，所述形成位于所述走线区域的至少一条第二走线包括：
    通过一次构图工艺采用同一掩膜板同时形成所述触控层与所述第二走线。
  12. 根据权利要求10所述的显示面板的制作方法，其中，所述在所述衬底基板上形成位于所述走线区域的第一走线之后，所述方法还包括：
    在所述第一走线远离所述衬底基板的一侧形成封装层；
    其中，在所述形成位于所述走线区域的至少一条第二走线之前，所述方法还包括：
    通过构图工艺形成位于所述绑定区域对侧的走线区域内的至少两个过孔，形成所述第一走线未被所述封装层覆盖的部分；
    所述形成位于所述走线区域的至少一条第二走线包括：
    在所述第一走线未被所述封装层覆盖的部分上形成所述第二走线。
  13. 根据权利要求10所述的显示面板的制作方法，其中，所述至少两个过孔在所述绑定区域对侧的走线区域内等间隔设置。
  14. 根据权利要求10所述的显示面板的制作方法，还包括：
    在完成对所述显示面板的老化测试后，将所述绑定区域所在的一侧和所述绑定区域的对侧之外的、所述显示面板的包括所述第二走线的层级结构切除，形成窄边框的显示面板。
  15. 一种显示装置，包括：如权利要求1-9中任一项所述的显示面板。
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