WO2021249291A1 - 发光二极管外延片及其生长方法、发光二极管芯片 - Google Patents

发光二极管外延片及其生长方法、发光二极管芯片 Download PDF

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WO2021249291A1
WO2021249291A1 PCT/CN2021/098252 CN2021098252W WO2021249291A1 WO 2021249291 A1 WO2021249291 A1 WO 2021249291A1 CN 2021098252 W CN2021098252 W CN 2021098252W WO 2021249291 A1 WO2021249291 A1 WO 2021249291A1
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gan
sublayer
layer
atoms
thickness
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PCT/CN2021/098252
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French (fr)
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姚振
从颖
董彬忠
李鹏
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华灿光电(苏州）有限公司
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Priority to US18/009,655 priority Critical patent/US20240120434A1/en
Publication of WO2021249291A1 publication Critical patent/WO2021249291A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen

Definitions

  • the present disclosure relates to the field of semiconductor technology, in particular to a light-emitting diode epitaxial wafer and a growth method thereof, and a light-emitting diode chip.
  • Light Emitting Diode (English: Light Emitting Diode, abbreviated as: LED) is a semiconductor electronic component that can emit light. As a new type of high-efficiency, environmentally friendly and green solid-state lighting source, LED is a promising new generation of light source, which is being rapidly and widely used in traffic lights, automotive interior and exterior lights, urban landscape lighting, indoor and outdoor displays, and small-pitch displays. Screen and other fields.
  • the epitaxial wafer is the primary finished product in the LED manufacturing process.
  • the LED epitaxial wafer includes a sapphire substrate, and an active layer and a P-type GaN layer formed by alternately stacking a GaN buffer layer, an N-type GaN layer, an InGaN quantum well, and a GaN quantum barrier sequentially stacked on the sapphire substrate.
  • the sapphire substrate is used to provide the epitaxial growth surface
  • the GaN buffer layer is used to provide the nucleation center of the epitaxial growth
  • the N-type GaN layer is used to provide electrons for composite light emission
  • the P-type GaN layer is used to provide holes for composite light emission.
  • the GaN quantum barrier confines electrons and holes in the InGaN quantum well for recombination light emission.
  • the embodiments of the present disclosure provide a light-emitting diode epitaxial wafer, a growth method thereof, and a light-emitting diode chip, which can improve the stability of a GaN crystal core and help reduce line defects caused by lattice mismatch between a sapphire substrate and a GaN-based material .
  • the technical solution is as follows:
  • embodiments of the present disclosure provide a method for growing a light-emitting diode epitaxial wafer, and the growing method includes:
  • each composite layer includes an InGaN sublayer and a GaN sublayer grown on the InGaN sublayer;
  • An N-type GaN layer, an active layer, and a P-type GaN layer are sequentially grown on the buffer layer to form an epitaxial wafer.
  • the active layer includes alternately stacked InGaN quantum wells and GaN quantum barriers.
  • the passing reaction gas into the reaction chamber to form a GaN crystal nucleus containing In atoms in a partial area of the sapphire substrate includes:
  • a Ga source and a N source are passed into the reaction chamber, and Ga atoms and N atoms are gathered in a part of the sapphire substrate to form a plurality of first GaN crystal nuclei arranged at intervals;
  • An In source is introduced into the reaction chamber, In atoms are adsorbed on the first GaN crystal nucleus, and the first GaN crystal nucleus is enlarged to a second GaN crystal nucleus;
  • a Ga source and a N source are passed into the reaction chamber, and a GaN layer formed by the reaction of Ga atoms and N atoms is coated on the second GaN crystal nucleus to form the GaN crystal nucleus.
  • the height of the first GaN crystal core is 8 nm-15 nm.
  • the duration of passing the In source when forming the second GaN crystal nucleus is 10s-50s.
  • the thickness of the GaN layer is 5 nm-10 nm.
  • the at least one composite layer is grown on the GaN crystal core, the GaN crystal core grows to form a buffer layer, and the composite layer includes an InGaN sublayer and a GaN sublayer grown on the InGaN sublayer.
  • Layers including:
  • An In source, a Ga source, and an N source are passed into the reaction chamber, and the first InGaN sublayer formed by the reaction of In atoms, Ga atoms and N atoms is coated on the GaN crystal core;
  • a Ga source and a N source are passed into the reaction chamber, and a first GaN sub-layer formed by the reaction of Ga atoms and N atoms is coated on the first InGaN sub-layer;
  • An In source, Ga source, and N source are passed into the reaction chamber, and a second InGaN sublayer formed by the reaction of In atoms, Ga atoms and N atoms is coated on the first GaN sublayer;
  • a Ga source and a N source are passed into the reaction chamber, and a second GaN sublayer formed by the reaction of Ga atoms and N atoms is coated on the second InGaN sublayer.
  • the thickness of the first InGaN sublayer, the thickness of the first GaN sublayer, the thickness of the second InGaN sublayer, and the thickness of the second GaN sublayer decrease in sequence.
  • the thickness of the first InGaN sublayer is 5nm-10nm
  • the thickness of the first GaN sublayer is 3nm-8nm
  • the thickness of the second InGaN sublayer is 2nm-5nm
  • the second The thickness of the GaN sublayer is 1 nm to 4 nm.
  • the flow rate of the In source when the first InGaN sublayer and the second InGaN sublayer are generated is 50 sccm to 500 sccm.
  • the method further includes: growing an undoped GaN layer on the buffer layer before sequentially growing an N-type GaN layer on the buffer layer.
  • embodiments of the present disclosure provide a light-emitting diode epitaxial wafer, which includes a sapphire substrate, a buffer layer, an N-type GaN layer, an active layer, and a sapphire substrate sequentially stacked on the sapphire substrate.
  • the active layer includes alternately stacked InGaN quantum wells and GaN quantum barriers;
  • the buffer layer includes a plurality of GaN crystal nuclei containing In atoms and at least one composite layer, and the plurality of GaN crystal nuclei are located
  • the at least one composite layer is arranged on the surface of the sapphire substrate at intervals, the at least one composite layer is located on the plurality of GaN crystal nuclei, and each composite layer includes an InGaN sublayer and a GaN sublayer grown on the InGaN sublayer .
  • the GaN crystal nucleus includes a first GaN crystal nucleus, In atoms and a GaN layer, the In atoms are laid on the first GaN crystal nucleus, and the GaN layer is coated on the first GaN crystal nucleus with In atoms. On a GaN crystal core.
  • the height of the first GaN crystal core is 8 nm-15 nm.
  • the thickness of the GaN layer is 5 nm-10 nm.
  • the at least one composite layer includes a first InGaN sublayer, a first GaN sublayer, a second InGaN sublayer, and a second GaN sublayer sequentially stacked on the GaN crystal core.
  • the thickness of the first InGaN sublayer, the thickness of the first GaN sublayer, the thickness of the second InGaN sublayer, and the thickness of the second GaN sublayer decrease in sequence.
  • the thickness of the first InGaN sublayer is 5nm-10nm
  • the thickness of the first GaN sublayer is 3nm-8nm
  • the thickness of the second InGaN sublayer is 2nm-5nm
  • the second The thickness of the GaN sublayer is 1 nm to 4 nm.
  • the light emitting diode epitaxial wafer further includes an undoped GaN layer, and the undoped GaN layer is stacked between the buffer layer and the N-type GaN layer.
  • embodiments of the present disclosure also provide a light-emitting diode chip, including any of the aforementioned epitaxial wafers and electrodes on the epitaxial wafers.
  • the volume of In atoms is larger than that of Ga atoms, which can increase the volume of GaN crystal nuclei to a certain extent, which is conducive to the formation of stable GaN crystals. nuclear.
  • the GaN crystal nucleus containing In atoms can attract the InGaN sublayer and the GaN sublayer in the composite layer to grow on the GaN crystal nucleus.
  • the volume of In atoms is larger than the volume of Ga atoms to increase the volume of the GaN crystal nucleus. A large and stable GaN crystal nucleus is formed. At this time, the distance between two adjacent GaN crystal nuclei is relatively suitable.
  • the two adjacent GaN crystal nuclei When the two adjacent GaN crystal nuclei are combined together, it can effectively offset the crystal crystallization between the sapphire substrate and the GaN-based material.
  • the stress caused by lattice mismatch avoids the generation of line defects extending to the active layer, which is conducive to the combined light emission of electrons and holes, and improves the luminous efficiency of the LED.
  • FIG. 1 is a flowchart of a method for growing a light-emitting diode epitaxial wafer according to an embodiment of the present disclosure
  • FIG. 2 is a schematic diagram of the structure of the light-emitting diode epitaxial wafer after the first step provided by the embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of the structure of the light-emitting diode epitaxial wafer after the second step provided by the embodiment of the present disclosure
  • FIG. 4 is a schematic diagram of the structure of the light-emitting diode epitaxial wafer after the third step provided by the embodiment of the present disclosure
  • FIG. 5 is a schematic structural diagram of a light-emitting diode epitaxial wafer provided by an embodiment of the present disclosure.
  • the LED epitaxial wafer includes a sapphire substrate, and an active layer and a P-type GaN layer formed by alternately stacking a GaN buffer layer, an N-type GaN layer, an InGaN quantum well, and a GaN quantum barrier sequentially stacked on the sapphire substrate.
  • GaN buffer layer grows, Ga atoms and N atoms gradually grow into multiple GaN crystal nuclei on the surface of the sapphire substrate, and multiple crystal nuclei are arranged on the surface of the sapphire substrate at intervals to obtain the buffer layer.
  • the subsequently deposited GaN material grows laterally between the multiple GaN crystal nuclei and bonds together.
  • the thickness of the buffer layer is thinner and the volume of the GaN crystal nucleus is small, the distance between the two adjacent GaN crystal nuclei is farther .
  • two adjacent GaN crystal nuclei are combined together, they cannot effectively offset the stress caused by the lattice mismatch between the sapphire substrate and the GaN-based material, resulting in line defects extending to the active layer, which affects the recombination of electrons and holes. , Reduce the luminous efficiency of the LED. If the thickness of the buffer layer is thicker and the volume of the GaN crystal nucleus is larger, the crystal structure of the GaN crystal nucleus is unstable.
  • the difference between the sapphire substrate and the GaN-based material cannot be effectively offset.
  • the stress caused by the mismatch of the inter-lattice produces line defects that extend to the active layer, which affects the recombination of electrons and holes and reduces the luminous efficiency of the LED.
  • embodiments of the present disclosure provide a method for growing a light-emitting diode epitaxial wafer.
  • hydrogen, or nitrogen, or a mixed gas of hydrogen and nitrogen is used as the carrier gas
  • trimethylgallium or triethylgallium is used as the gallium source
  • high-purity ammonia gas is used as the nitrogen source
  • trimethylindium is used as the indium.
  • Source trimethylaluminum as the aluminum source, silane as the silicon source, and magnesium cerene as the magnesium source.
  • FIG. 1 is a flowchart of a method for growing a light-emitting diode epitaxial wafer according to an embodiment of the disclosure.
  • the growth method includes:
  • Step 101 Put the sapphire substrate into the reaction chamber.
  • the reaction chamber may be a reaction chamber of a metal-organic chemical vapor deposition (English: Metal-organic Chemical Vapor Deposition, abbreviated as: MOCVD) equipment, such as Veeco K465i MOCVD or Veeco C4 MOCVD.
  • MOCVD Metal-organic Chemical Vapor Deposition
  • the growth method further includes:
  • the temperature is controlled to be 1000°C to 1100°C (such as 1050°C)
  • the pressure is 200 torr to 500 torr (such as 350 torr)
  • the substrate is annealed for 5 minutes to 6 minutes (such as 5.5 minutes) in a hydrogen atmosphere.
  • the surface of the substrate is cleaned to prevent impurities from being mixed into the epitaxial wafer, which is beneficial to improve the growth quality of the epitaxial wafer.
  • Step 102 Pass a reaction gas into the reaction chamber to form a GaN crystal nucleus containing In atoms in a part of the sapphire substrate.
  • a plurality of GaN crystal nuclei arranged at intervals are formed on the surface of the sapphire substrate.
  • the surface is a [0001] surface.
  • this step 102 includes:
  • a Ga source and a N source are introduced into the reaction chamber, and Ga atoms and N atoms are gathered in a part of the sapphire substrate to form a plurality of first GaN crystal nuclei arranged at intervals.
  • FIG. 2 is a schematic diagram of the structure of the light emitting diode epitaxial wafer after the first step provided by the embodiment of the disclosure.
  • 10 represents a sapphire substrate
  • 211 represents the first GaN crystal nucleus.
  • a plurality of first GaN crystal nuclei 211 are arranged on the same surface of the sapphire substrate 10 at intervals.
  • a Ga source and a N source are introduced into the reaction chamber, and Ga atoms and N atoms are adsorbed on the sapphire substrate, and gather together in a part of the sapphire substrate, and the first GaN crystal nucleus is formed.
  • an In source is introduced into the reaction chamber, and In atoms are adsorbed on the first GaN crystal nucleus, so that the first GaN crystal nucleus is increased into the second GaN crystal nucleus.
  • FIG. 3 is a schematic diagram of the structure of the light emitting diode epitaxial wafer after the second step provided by the embodiment of the disclosure.
  • 10 represents a sapphire substrate
  • 211 represents the first GaN crystal nucleus
  • 212 represents In atoms.
  • a plurality of first GaN crystal nuclei 211 are arranged on the same surface of the sapphire substrate 10 at intervals, a number of In atoms 212 are laid on the plurality of first GaN crystal nuclei 211, and each first GaN crystal nucleus 211 is laid There are multiple In atoms 212.
  • the In source is introduced into the reaction chamber, and the In atoms are adsorbed on the first GaN crystal nucleus and form a chemical bond with the first GaN crystal nucleus, increasing the volume of the first GaN crystal nucleus and turning it into the first GaN crystal nucleus.
  • Two GaN crystal nuclei are introduced into the reaction chamber, and the In atoms are adsorbed on the first GaN crystal nucleus and form a chemical bond with the first GaN crystal nucleus, increasing the volume of the first GaN crystal nucleus and turning it into the first GaN crystal nucleus.
  • Two GaN crystal nuclei Two GaN crystal nuclei.
  • the Ga source and the N source are introduced into the reaction chamber, and the GaN layer formed by the reaction of Ga atoms and N atoms is coated on the second GaN crystal nucleus to form a GaN crystal nucleus containing In atoms.
  • FIG. 4 is a schematic diagram of the structure of the light-emitting diode epitaxial wafer after the third step provided by the embodiments of the present disclosure.
  • 10 represents a sapphire substrate
  • 211 represents the first GaN crystal nucleus
  • 212 represents In atoms
  • 213 represents a GaN layer.
  • a plurality of first GaN crystal nuclei 211 are arranged at intervals on the same surface of the sapphire substrate 10
  • a number of In atoms 212 are laid on the plurality of first GaN crystal nuclei 211, and a GaN layer 213 is coated on each of the first GaN crystal nuclei.
  • the In atoms 212 are enclosed in the GaN crystal nucleus.
  • the Ga source and N source are introduced into the reaction chamber, and the GaN layer formed by the reaction of Ga atoms and N atoms covers the first GaN crystal nucleus around In atoms and In atoms, and together with the first GaN crystal nucleus In atoms surround the GaN crystal nucleus, forming a GaN crystal nucleus containing In atoms.
  • the Ga atoms and N atoms are gathered in a part of the sapphire substrate to form a plurality of first GaN crystal nuclei, thereby spreading the crystals on the sapphire substrate.
  • kind of establish the basic structure of GaN crystal core.
  • an In source into the reaction chamber to make In atoms adsorb on the first GaN crystal nucleus, and the first GaN crystal nucleus is enlarged to the second GaN crystal nucleus, so that the basic structure of the GaN crystal nucleus is not destroyed.
  • In atoms are mixed into the GaN crystal nucleus, increasing the volume of the GaN crystal nucleus.
  • the height of the first GaN crystal core is 8 nm to 15 nm.
  • the height refers to the maximum distance from the outer surface of the first GaN crystal core to the surface of the sapphire substrate where it is located.
  • the height of the first GaN crystal nucleus is less than 8nm, the structure of the seed crystal may not be completely formed, and the stability of the first GaN crystal nucleus is poor, which affects the establishment of the basic structure of the GaN crystal nucleus, which in turn leads to the final formation of the GaN crystal.
  • the nucleus is unstable, and when two adjacent GaN crystal nuclei are combined together, the stress caused by the lattice mismatch between the sapphire substrate and the GaN-based material cannot be effectively offset, resulting in line defects extending to the active layer, affecting electrons and voids. The compound luminescence of the holes reduces the luminous efficiency of the LED. If the height of the first GaN crystal nucleus is greater than 15 nm, the growth time will be longer and the production efficiency will be affected.
  • the height of the first GaN crystal core is 8 nm to 12 nm, such as 10 nm.
  • the duration of the In source when forming the second GaN crystal nucleus is 10s-50s.
  • the duration of the In source during the formation of the second GaN crystal nucleus is less than 10s, there will be less In source during the formation of the second GaN crystal nucleus, and the In atoms may not cover the entire surface of the GaN crystal nucleus, affecting the InGaN sub-layer Generation in this area; if the duration of the In source during the formation of the second GaN crystal nucleus is longer than 50s, more In sources are introduced during the formation of the second GaN crystal nucleus.
  • the volume of the GaN crystal nucleus may be excessive. It is too large to use the combination of two adjacent GaN crystal cores to offset the stress caused by the lattice mismatch between the sapphire substrate and the GaN-based material. On the other hand, it may also affect the crystal structure of the GaN crystal core, resulting in the overall crystal of the epitaxial wafer The poor quality affects the recombination of electrons and holes and reduces the luminous efficiency of the LED.
  • the duration of the In source is 20s-40s, such as 30s.
  • the thickness of the GaN layer is 5 nm to 10 nm.
  • the GaN layer may not be able to completely encapsulate the In atoms, resulting in unstable GaN crystal nuclei.
  • the stress caused by the inter-lattice mismatch produces line defects that extend to the active layer, which affects the recombination of electrons and holes and reduces the luminous efficiency of the LED; if the thickness of the GaN layer is greater than 10nm, it will cause a longer growth time. Affect production efficiency.
  • the thickness of the GaN layer is 5 nm to 8 nm, such as 8 nm.
  • the temperature in the reaction chamber is 530° C. to 560° C., such as 545° C.; and the pressure is 200 torr to 500 torr, such as 350 torr.
  • Step 103 Growing at least one composite layer on the GaN crystal core, the GaN crystal core grows to form a buffer layer, and each composite layer includes an InGaN sublayer and a GaN sublayer grown on the InGaN sublayer.
  • this step 103 includes:
  • a Ga source and a N source are passed into the reaction chamber, and the second GaN sublayer formed by the reaction of Ga atoms and N atoms is coated on the second InGaN sublayer.
  • the InGaN sublayers and the GaN sublayers are alternately stacked, which can either use InGaN
  • the volume of atoms is larger than that of Ga atoms to increase the volume of the GaN crystal nucleus, which is also conducive to maintaining the main structure of the GaN crystal nucleus, so as to finally form a large and stable GaN crystal nucleus.
  • two adjacent GaN crystals are formed. The distance between the cores is more appropriate.
  • the thickness of the first InGaN sublayer, the thickness of the first GaN sublayer, the thickness of the second InGaN sublayer, and the thickness of the second GaN sublayer are sequentially reduced.
  • the thickness of the first InGaN sublayer is 5 nm-10 nm.
  • the first InGaN sublayer may be too thin to effectively increase the volume of the GaN crystal nucleus, and when two adjacent GaN crystal nuclei are combined together, the sapphire substrate cannot be effectively offset.
  • the stress caused by the lattice mismatch with the GaN-based material if the thickness of the first InGaN sublayer is greater than 10nm, the first InGaN sublayer may be too thick to affect the crystal structure of GaN, resulting in the overall crystal quality of the epitaxial wafer Poor, it affects the recombination of electrons and holes and reduces the luminous efficiency of the LED.
  • the thickness of the first InGaN sublayer is 6 nm-10 nm, such as 8 nm.
  • the thickness of the first GaN sublayer is 3 nm to 8 nm.
  • the first GaN sublayer may be too thin to affect the crystal structure of GaN, resulting in poor crystal quality of the epitaxial wafer as a whole, affecting the recombination of electrons and holes, and reducing the LED If the thickness of the first GaN sublayer is greater than 8nm, it may increase the absorption of light due to the thickness of the first GaN sublayer, which will affect the light extraction efficiency of the LED.
  • the thickness of the first GaN sublayer is 3 nm to 6 nm, such as 5 nm.
  • the thickness of the second InGaN sublayer is 2 nm to 5 nm.
  • the thickness of the second InGaN sublayer is less than 2nm, the thickness of the second InGaN sublayer may be too thin to effectively increase the volume of the GaN crystal nucleus, and the sapphire cannot be effectively offset when two adjacent GaN crystal nuclei are combined.
  • the poor quality of the crystal affects the recombination of electrons and holes and reduces the luminous efficiency of the LED.
  • the thickness of the second InGaN sublayer is 1 nm to 5 nm, such as 3 nm.
  • the thickness of the second GaN sublayer is 1 nm to 4 nm.
  • the second InGaN sublayer may be too thin to affect the crystal structure of GaN, resulting in poor crystal quality of the epitaxial wafer as a whole, affecting the combined light emission of electrons and holes, and reducing the LED If the thickness of the second InGaN sub-layer is greater than 4nm, the second InGaN sub-layer may be too thick and increase the absorption of light, which will affect the light-emitting efficiency of the LED.
  • the thickness of the second GaN sublayer is 1.5 nm to 4 nm, such as 2 nm.
  • the flow rate of the In source when the first InGaN sublayer and the second InGaN sublayer are generated is 50 sccm to 500 sccm.
  • the flow of the In source into the first InGaN sublayer and the second InGaN sublayer is less than 50sccm, it may not be effective due to the small flow into the In source when the first InGaN sublayer and the second InGaN sublayer are generated.
  • the stress caused by the lattice mismatch between the sapphire substrate and the GaN-based material cannot be effectively offset; if the first InGaN sublayer and the second sublayer are generated When the InGaN sublayer flows into the In source when the flow rate is greater than 500sccm, the high flow rate into the In source during the formation of the first InGaN sublayer and the second InGaN sublayer may result in poor crystal quality of the epitaxial wafer as a whole, which affects electrons.
  • the combined light emission with holes reduces the luminous efficiency of the LED.
  • the flow rate of the In source is 100 sccm to 500 sccm, such as 300 sccm.
  • the temperature in the reaction chamber is 530°C to 560°C, such as 545°C; and the pressure is 200 torr to 500 torr, such as 350 torr.
  • Step 104 sequentially growing an N-type GaN layer, an active layer and a P-type GaN layer on the buffer layer to form an epitaxial wafer.
  • the active layer includes alternately stacked InGaN quantum wells and GaN quantum barriers.
  • a GaN crystal nucleus containing In atoms is first formed in a partial area of a sapphire substrate, and the volume of In atoms is larger than that of Ga atoms, which can increase the volume of GaN crystal nuclei to a certain extent, which is beneficial to the formation Stable GaN crystal core. Moreover, the GaN crystal nucleus containing In atoms can attract the InGaN sublayer and the GaN sublayer in the composite layer to grow on the GaN crystal nucleus. Further, the volume of In atoms is larger than the volume of Ga atoms to increase the volume of the GaN crystal nucleus. A large and stable GaN crystal nucleus is formed.
  • the distance between two adjacent GaN crystal nuclei is relatively suitable.
  • the two adjacent GaN crystal nuclei are combined together, it can effectively offset the crystal crystallization between the sapphire substrate and the GaN-based material.
  • the stress caused by lattice mismatch avoids the generation of line defects extending to the active layer, which is conducive to the combined light emission of electrons and holes, and improves the luminous efficiency of the LED.
  • the temperature in the reaction chamber is 1000° C. to 1100° C., such as 1050° C.; and the pressure is 200 torr to 300 torr, such as 250 torr.
  • the temperature in the reaction chamber is 760°C to 780°C, such as 770°C; the pressure is 200 torr.
  • the temperature in the reaction chamber is 860°C ⁇ 890°C, such as 875°C; the pressure is 200torr.
  • the temperature in the reaction chamber is 940°C to 980°C, such as 960°C; and the pressure is 200 torr to 600 torr, such as 400 torr.
  • the thickness of the N-type GaN layer is 2 ⁇ m to 3 ⁇ m, such as 2.5 ⁇ m; the doping concentration of the N-type dopant in the N-type GaN layer is 10 18 /cm 3 to 10 20 /cm 3 , such as 10 19 / cm 3 .
  • the thickness of the InGaN quantum wells is 2 nm to 3 nm, such as 2.5 nm; the number of InGaN quantum wells is 11 to 13, such as 12.
  • the thickness of the GaN quantum barrier is 8 nm to 11 nm, such as 9.5 nm; the number of quantum barriers is 11 to 13, such as 12.
  • the thickness of the P-type GaN layer is 50 nm-80 nm, such as 65 nm; the doping concentration of the P-type dopant in the P-type GaN layer is 10 18 /cm 3 -10 20 /cm 3 , such as 10 19 /cm 3 .
  • the manufacturing method further includes:
  • An undoped GaN layer is grown on the buffer layer.
  • the N-type GaN layer, the active layer, and the P-type GaN layer are sequentially grown on the buffer layer.
  • the undoped GaN layer laterally grows and merges between the GaN crystal nuclei, which can reduce the impurities in the formed growth plane, which is beneficial to improve the growth quality of the active layer, and thus the luminous efficiency of the LED. .
  • the temperature in the reaction chamber is 1000° C. to 1100° C., such as 1050° C.; and the pressure is 200 torr to 600 torr, such as 400 torr.
  • the thickness of the undoped GaN layer may be 2 ⁇ m to 3.5 ⁇ m, such as 2.75 ⁇ m.
  • the manufacturing method further includes:
  • An electron blocking layer is grown on the active layer.
  • an electron blocking layer to prevent electrons from transitioning to the P-type GaN layer, it is beneficial for electrons and holes to perform compound electron emission in the active layer, thereby improving the luminous efficiency of the LED.
  • the temperature in the reaction chamber is 930° C. to 970° C., such as 950° C.; and the pressure is 100 torr.
  • the material of the electron blocking layer is an Al x Ga 1-x N layer doped with Mg, and 0.15 ⁇ x ⁇ 0.25.
  • the thickness of the electron blocking layer is 30nm-50nm, such as 40nm.
  • FIG. 5 is a schematic structural diagram of a light-emitting diode epitaxial wafer provided by an embodiment of the disclosure.
  • the light-emitting diode epitaxial wafer includes a sapphire substrate 10 and a buffer layer 20, an N-type GaN layer 30, an active layer 40, and a P-type GaN layer 50 sequentially stacked on the sapphire substrate 10.
  • the active layer 40 includes InGaN quantum wells 41 and GaN quantum barriers 42 are alternately stacked.
  • the buffer layer 20 includes a plurality of GaN crystal nuclei 21 containing In atoms and at least one composite layer 22, and the plurality of GaN crystal nuclei 21 are located in a partial area of the sapphire substrate, that is, a plurality of GaN crystal nuclei 21 are arranged at intervals on the sapphire substrate.
  • the surface of the bottom At least one composite layer 22 is located on a plurality of GaN crystal nuclei 21, and each composite layer 22 includes an InGaN sublayer 221 and a GaN sublayer 222 grown on the InGaN sublayer 221.
  • a GaN crystal nucleus containing In atoms is first formed in a partial area of a sapphire substrate, and the volume of In atoms is larger than that of Ga atoms, which can increase the volume of GaN crystal nuclei to a certain extent, which is beneficial to the formation Stable GaN crystal core. Moreover, the GaN crystal nucleus containing In atoms can attract the InGaN sublayer and the GaN sublayer in the composite layer to grow on the GaN crystal nucleus. Further, the volume of In atoms is larger than the volume of Ga atoms to increase the volume of the GaN crystal nucleus. A large and stable GaN crystal nucleus is formed.
  • the temperature of the reaction chamber is set to 530°C ⁇ 560°C and the pressure is set to 200torr ⁇ 500torr, so that the distance between two adjacent GaN crystal nuclei is more suitable, which can better offset the sapphire lining.
  • the stress caused by the lattice mismatch between the bottom and the GaN-based material further reduces line defects.
  • the GaN crystal core 21 includes a first GaN crystal nucleus, In atoms and a GaN layer. In atoms are laid on the first GaN crystal nucleus, and the GaN layer is covered on the first GaN crystal nucleus laid with In atoms.
  • the height of the first GaN crystal core is 8 nm-15 nm.
  • the thickness of the GaN layer is 5 nm-10 nm.
  • the number of the composite layer 22 is two, and the two composite layers include a first InGaN sublayer, a first GaN sublayer, a second InGaN sublayer, and a second GaN sublayer that are sequentially stacked on the GaN crystal core.
  • the thickness of the first InGaN sublayer, the thickness of the first GaN sublayer, the thickness of the second InGaN sublayer, and the thickness of the second GaN sublayer are sequentially reduced.
  • the thickness of the first InGaN sublayer is 5nm-10nm
  • the thickness of the first GaN sublayer is 3nm-8nm
  • the thickness of the second InGaN sublayer is 2nm-5nm
  • the thickness of the second GaN sublayer is 1nm ⁇ 4nm.
  • the light emitting diode epitaxial wafer further includes an undoped GaN layer 60, and the undoped GaN layer 60 is stacked between the buffer layer 20 and the N-type GaN layer 30.
  • the buffer layer in the embodiments of the present disclosure is also called a low temperature buffer layer, and the undoped GaN layer 60 is also called a high temperature buffer layer.
  • the embodiment of the present disclosure also provides a light emitting diode chip, which includes the epitaxial wafer shown in FIG. 5 and electrodes on the epitaxial wafer.
  • the electrode includes an N electrode connected to the N-type GaN layer and a P electrode connected to the P-type GaN layer.

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Abstract

本公开提供了一种发光二极管外延片及其生长方法、发光二极管芯片，属于半导体技术领域。所述生长方法包括：将蓝宝石衬底放入反应室内；向所述反应室内通入反应气体，在所述蓝宝石衬底的表面形成包含In原子的多个GaN晶核；在所述GaN晶核上生长至少一个复合层，所述GaN晶核长大形成缓冲层，每个所述复合层包括InGaN子层和生长在所述InGaN子层上的GaN子层；在所述缓冲层上依次生长N型GaN层、有源层和P型GaN层形成外延片，所述有源层包括交替层叠的InGaN量子阱和GaN量子垒。本公开通过形成体积大且稳定的GaN晶核，有效抵消蓝宝石衬底与GaN基材料之间晶格失配产生的应力。

Description

发光二极管外延片及其生长方法、发光二极管芯片
本申请要求于2020年06月11日提交的申请号为202010530055.9、发明名称为“发光二极管外延片的生长方法及发光二极管外延片”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及半导体技术领域，特别涉及一种发光二极管外延片及其生长方法、发光二极管芯片。
背景技术
发光二极管(英文：Light Emitting Diode，简称：LED)是一种能发光的半导体电子元件。作为一种高效、环保、绿色的新型固态照明光源，LED是前景广阔的新一代光源，正在被迅速广泛地应用在如交通信号灯、汽车内外灯、城市景观照明、户内外显示屏和小间距显示屏等领域。
外延片是LED制作过程中的初级成品。相关技术中，LED外延片包括蓝宝石衬底以及依次层叠在蓝宝石衬底上的GaN缓冲层、N型GaN层、InGaN量子阱和GaN量子垒交替层叠而成的有源层、P型GaN层。其中，蓝宝石衬底用于提供外延生长的表面，GaN缓冲层用于提供外延生长的成核中心，N型GaN层用于提供复合发光的电子，P型GaN层用于提供复合发光的空穴，GaN量子垒将电子和空穴限定在InGaN量子阱中进行复合发光。
蓝宝石衬底与GaN基材料之间存在较大的晶格失配，晶格失配产生的线缺陷会延伸到有源层，影响电子和空穴的复合发光，降低LED的发光效率。
发明内容
本公开实施例提供了一种发光二极管外延片及其生长方法、发光二极管芯片，可以提高GaN晶核的稳定性，有利于减少蓝宝石衬底与GaN基材料之间晶格失配产生的线缺陷。所述技术方案如下：
一方面，本公开实施例提供了一种发光二极管外延片的生长方法，所述生长方法包括：
将蓝宝石衬底放入反应室内；
向所述反应室内通入反应气体，在所述蓝宝石衬底的表面形成包含In原子的多个GaN晶核；
在所述GaN晶核上生长至少一个复合层，所述GaN晶核长大形成缓冲层，每个所述复合层包括InGaN子层和生长在所述InGaN子层上的GaN子层；
在所述缓冲层上依次生长N型GaN层、有源层和P型GaN层形成外延片，所述有源层包括交替层叠的InGaN量子阱和GaN量子垒。
可选地，所述向所述反应室内通入反应气体，在所述蓝宝石衬底的部分区域内形成包含In原子的GaN晶核，包括：
向所述反应室内通入Ga源和N源，Ga原子和N原子在所述蓝宝石衬底的部分区域内聚集，形成多个间隔布置的第一GaN晶核；
向所述反应室内通入In源，In原子吸附在所述第一GaN晶核上，所述第一GaN晶核增大为第二GaN晶核；
向所述反应室内通入Ga源和N源，Ga原子和N原子反应生成的GaN层包覆在所述第二GaN晶核上，形成所述GaN晶核。
可选地，所述第一GaN晶核的高度为8nm～15nm。
可选地，形成所述第二GaN晶核时通入In源的时长为10s～50s。
可选地，所述GaN层的厚度为5nm～10nm。
可选地，所述在所述GaN晶核上生长至少一个复合层，所述GaN晶核长大形成缓冲层，所述复合层包括InGaN子层和生长在所述InGaN子层上的GaN子层，包括：
向所述反应室内通入In源、Ga源和N源，In原子、Ga原子和N原子反应生成的第一InGaN子层包覆在所述GaN晶核上；
向所述反应室内通入Ga源和N源，Ga原子和N原子反应生成的第一GaN子层包覆在所述第一InGaN子层上；
向所述反应室内通入In源、Ga源和N源，In原子、Ga原子和N原子反应生成的第二InGaN子层包覆在所述第一GaN子层上；
向所述反应室内通入Ga源和N源，Ga原子和N原子反应生成的第二GaN子层包覆在所述第二InGaN子层上。
可选地，所述第一InGaN子层的厚度、所述第一GaN子层的厚度、所述第二InGaN子层的厚度、所述第二GaN子层的厚度依次减小。
可选地，所述第一InGaN子层的厚度为5nm～10nm，所述第一GaN子层的厚度为3nm～8nm，所述第二InGaN子层的厚度为2nm～5nm，所述第二GaN子层的厚度为1nm～4nm。
可选地，生成所述第一InGaN子层和所述第二InGaN子层时通入In源的流量为50sccm～500sccm。
可选地，所述方法还包括：在所述缓冲层上依次生长N型GaN层之前，在所述缓冲层上生长未掺杂GaN层。
另一方面，本公开实施例提供了一种发光二极管外延片，所述发光二极管外延片包括蓝宝石衬底以及依次层叠在所述蓝宝石衬底上的缓冲层、N型GaN层、有源层和P型GaN层，所述有源层包括交替层叠的InGaN量子阱和GaN量子垒；所述缓冲层包括包含In原子的多个GaN晶核和至少一个复合层，所述多个GaN晶核位于间隔布置在所述蓝宝石衬底的表面，所述至少一个复合层位于所述多个GaN晶核上，每个所述复合层包括InGaN子层和生长在所述InGaN子层上的GaN子层。
可选地，所述GaN晶核包括第一GaN晶核、In原子和GaN层，所述In原子铺设在所述第一GaN晶核上，所述GaN层包覆在铺设有In原子的第一GaN晶核上。
可选地，所述第一GaN晶核的高度为8nm～15nm。
可选地，所述GaN层的厚度为5nm～10nm。
可选地，所述至少一个复合层包括依次层叠在所述GaN晶核上的第一InGaN子层、第一GaN子层、第二InGaN子层和第二GaN子层。
可选地，所述第一InGaN子层的厚度、所述第一GaN子层的厚度、所述第二InGaN子层的厚度、所述第二GaN子层的厚度依次减小。
可选地，所述第一InGaN子层的厚度为5nm～10nm，所述第一GaN子层的厚度为3nm～8nm，所述第二InGaN子层的厚度为2nm～5nm，所述第二GaN子层的厚度为1nm～4nm。
可选地，所述发光二极管外延片还包括：未掺杂GaN层，所述未掺杂GaN层层叠在所述缓冲层和所述N型GaN层之间。
又一方面，本公开实施例还提供了一种发光二极管芯片，包括前述任一种外延片以及位于所述外延片上的电极。
本公开实施例提供的技术方案带来的有益效果是：
通过先在蓝宝石衬底的部分区域内形成包含In原子的GaN晶核，利用In原子的体积大于Ga原子的体积，可以在一定程度上增大GaN晶核的体积，有利于形成稳定的GaN晶核。而且包含In原子的GaN晶核可以吸引复合层中的InGaN子层和GaN子层都选择生长在GaN晶核上，进一步利用In原子的体积大于Ga原子的体积增大GaN晶核的体积，最终形成体积大且稳定的GaN晶核，此时相邻两个GaN晶核之间的距离比较合适，相邻两个GaN晶核结合在一起时可以有效抵消蓝宝石衬底与GaN基材料之间晶格失配产生的应力，避免产生延伸到有源层的线缺陷，有利于电子和空穴的复合发光，提高LED的发光效率。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本公开实施例提供的一种发光二极管外延片的生长方法的流程图；
图2是本公开实施例提供的第一步执行之后发光二极管外延片的结构示意图；
图3是本公开实施例提供的第二步执行之后发光二极管外延片的结构示意图；
图4是本公开实施例提供的第三步执行之后发光二极管外延片的结构示意图；
图5是本公开实施例提供的一种发光二极管外延片的结构示意图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚，下面将结合附图对本公开实施方式作进一步地详细描述。
LED的制作过程中，先在晶体结构匹配的单晶材料上生长半导体薄膜，形成外延片；再在外延片上设置注入电流的电极，形成芯片。相关技术中，LED外延片包括蓝宝石衬底以及依次层叠在蓝宝石衬底上的GaN缓冲层、N型GaN层、InGaN量子阱和GaN量子垒交替层叠而成的有源层、P型GaN层。
其中，GaN缓冲层生长时，Ga原子和N原子在蓝宝石衬底的表面逐渐长成 多个GaN晶核，多个晶核间隔布置在蓝宝石衬底的表面，得到缓冲层。后续沉积的GaN材料在多个GaN晶核之间横向生长并结合在一起。
在相邻两个GaN晶核的中心位置之间的距离一定的情况下，如果缓冲层的厚度较薄，GaN晶核的体积较小，则相邻两个GaN晶核之间的距离较远，相邻两个GaN晶核结合在一起时无法有效抵消蓝宝石衬底与GaN基材料之间晶格失配产生的应力，产生延伸到有源层的线缺陷，影响电子和空穴的复合发光，降低LED的发光效率。而如果缓冲层的厚度较厚，GaN晶核的体积较大，则GaN晶核的晶体结构不稳定，相邻两个GaN晶核结合在一起时也无法有效抵消蓝宝石衬底与GaN基材料之间晶格失配产生的应力，产生延伸到有源层的线缺陷，影响电子和空穴的复合发光，降低LED的发光效率。
基于上述情况，本公开实施例提供了一种发光二极管外延片的生长方法。在该生长方法中，以氢气、或者氮气、或者氢气和氮气的混合气体作为载气，三甲基镓或三乙基镓作为镓源，高纯氨气作为氮源，三甲基铟作为铟源，三甲基铝作为铝源，硅烷作为硅源，二茂镁作为镁源。
图1为本公开实施例提供的一种发光二极管外延片的生长方法的流程图。参见图1，该生长方法包括：
步骤101：将蓝宝石衬底放入反应室内。
示例性地，反应室可以为金属有机化合物化学气相沉淀(英文：Metal-organic Chemical Vapor Deposition，简称：MOCVD)设备的反应腔，如Veeco K465i MOCVD或者Veeco C4 MOCVD。
可选地，在步骤101之后，该生长方法还包括：
控制温度为1000℃～1100℃(如1050℃)，压力为200torr～500torr(如350torr)，在氢气气氛中对衬底进行5分钟～6分钟(如5.5分钟)退火处理。
通过上述步骤清洁衬底的表面，避免杂质掺入外延片中，有利于提高外延片的生长质量。
步骤102：向反应室内通入反应气体，在蓝宝石衬底的部分区域内形成包含In原子的GaN晶核。
也即是，在蓝宝石衬底的表面形成多个间隔布置的GaN晶核。示例性地，该表面为[0001]面。
可选地，该步骤102包括：
第一步，向反应室内通入Ga源和N源，Ga原子和N原子在蓝宝石衬底的 部分区域内聚集，形成多个间隔布置的第一GaN晶核。
图2为本公开实施例提供的第一步执行之后发光二极管外延片的结构示意图。其中，10表示蓝宝石衬底，211表示第一GaN晶核。参见图2，多个第一GaN晶核211间隔设置在蓝宝石衬底10的同一表面上。
在实际应用中，向反应室内通入Ga源和N源，Ga原子和N原子吸附在蓝宝石衬底上，并在蓝宝石衬底的部分区域内聚集在一起，第一GaN晶核形成。
第二步，向反应室内通入In源，In原子吸附在第一GaN晶核上，使得第一GaN晶核增大为第二GaN晶核。
图3为本公开实施例提供的第二步执行之后发光二极管外延片的结构示意图。其中，10表示蓝宝石衬底，211表示第一GaN晶核，212表示In原子。参见图3，多个第一GaN晶核211间隔设置在蓝宝石衬底10的同一表面上，若干In原子212铺设在多个第一GaN晶核211上，每个第一GaN晶核211上铺设有多个In原子212。
在实际应用中，向反应室内通入In源，In原子吸附在第一GaN晶核上，并与第一GaN晶核之间形成化学键，将第一GaN晶核的体积增大，变为第二GaN晶核。
第三步，向反应室内通入Ga源和N源，Ga原子和N原子反应生成的GaN层包覆在第二GaN晶核上，形成包含In原子的GaN晶核。
图4为本公开实施例提供的第三步执行之后发光二极管外延片的结构示意图。其中，10表示蓝宝石衬底，211表示第一GaN晶核，212表示In原子，213表示GaN层。参见图4，多个第一GaN晶核211间隔设置在蓝宝石衬底10的同一表面上，若干In原子212铺设在多个第一GaN晶核211上，GaN层213包覆在各个第一GaN晶核211上的In原子212上，与第一GaN晶核211一起将In原子212围在GaN晶核内。
在实际应用中，向反应室内通入Ga源和N源，Ga原子和N原子反应生成的GaN层覆盖在In原子和In原子周围的第一GaN晶核上，与第一GaN晶核一起将In原子围在GaN晶核内，形成包含In原子的GaN晶核。
本公开实施例通过首先向反应室内通入Ga源和N源，使Ga原子和N原子在蓝宝石衬底的部分区域内聚集形成多个第一GaN晶核，从而在蓝宝石衬底上播散晶种，建立GaN晶核的基础结构。再向反应室内通入In源，使In原子吸附在第一GaN晶核上，第一GaN晶核增大为第二GaN晶核，从而在不破坏GaN 晶核的基础结构的情况下，将In原子混入到GaN晶核中，增大GaN晶核的体积。最后向反应室内通入Ga源和N源，使Ga原子和N原子反应生成的GaN层包覆在第二GaN晶核上，将In原子限定在GaN晶核内，确保GaN晶核的稳定性。
示例性地，第一GaN晶核的高度为8nm～15nm。这里，高度是指第一GaN晶核的外表面到所在的蓝宝石衬底的表面的最大距离。
如果第一GaN晶核的高度小于8nm，则可能导致晶种的结构还未完全形成，第一GaN晶核的稳定性较差，影响GaN晶核基础结构的建立，进而导致最终形成的GaN晶核不稳定，相邻两个GaN晶核结合在一起时也无法有效抵消蓝宝石衬底与GaN基材料之间晶格失配产生的应力，产生延伸到有源层的线缺陷，影响电子和空穴的复合发光，降低LED的发光效率。如果第一GaN晶核的高度大于15nm，则会造成生长时间较长，影响生产效率。
例如，第一GaN晶核的高度为8nm～12nm，如10nm。
示例性地，形成第二GaN晶核时通入In源的时长为10s～50s。
如果形成第二GaN晶核时通入In源的时长小于10s，则形成第二GaN晶核时通入的In源较少，In原子可能没有铺满整个GaN晶核的表面，影响InGaN子层在该区域的生成；如果形成第二GaN晶核时通入In源的时长大于50s，则形成第二GaN晶核时通入的In源较多，一方面可能会导致GaN晶核的体积过大而无法利用相邻两个GaN晶核的结合抵消蓝宝石衬底与GaN基材料之间晶格失配产生的应力，另一方面也可能影响GaN晶核的晶体结构，导致外延片整体的晶体质量较差，影响电子和空穴的复合发光，降低LED的发光效率。
例如，形成第二GaN晶核时通入In源的时长为20s～40s，如30s。
示例性地，GaN层的厚度为5nm～10nm。
如果GaN层的厚度小于5nm，则GaN层可能无法将In原子完全包覆，导致GaN晶核不稳定，相邻两个GaN晶核结合在一起时也无法有效抵消蓝宝石衬底与GaN基材料之间晶格失配产生的应力，产生延伸到有源层的线缺陷，影响电子和空穴的复合发光，降低LED的发光效率；如果GaN层的厚度大于10nm，则会造成生长时间较长，影响生产效率。
例如，GaN层的厚度为5nm～8nm，如8nm。
示例性地，GaN晶核形成时，反应室内的温度为530℃～560℃，如545℃；压力为200torr～500torr，如350torr。
步骤103：在GaN晶核上生长至少一个复合层，GaN晶核长大形成缓冲层，每个复合层包括InGaN子层和生长在InGaN子层上的GaN子层。
可选地，该步骤103包括：
向反应室内通入In源、Ga源和N源，In原子、Ga原子和N原子反应生成的第一InGaN子层包覆在GaN晶核上；
向反应室内通入Ga源和N源，Ga原子和N原子反应生成的第一GaN子层包覆在第一InGaN子层上；
向反应室内通入In源、Ga源和N源，In原子、Ga原子和N原子反应生成的第二InGaN子层包覆在第一GaN子层上；
向反应室内通入Ga源和N源，Ga原子和N原子反应生成的第二GaN子层包覆在第二InGaN子层上。
本公开实施例通过在GaN晶核上依次生长第一InGaN子层、第一GaN子层、第二InGaN子层和第二GaN子层，InGaN子层和GaN子层交替层叠，既可以利用In原子的体积比Ga原子的体积大增大GaN晶核的体积，也有利于维持GaN晶核的主体结构不变，从而最终形成体积大且稳定的GaN晶核，此时相邻两个GaN晶核之间的距离比较合适，相邻两个GaN晶核结合在一起时可以有效抵消蓝宝石衬底与GaN基材料之间晶格失配产生的应力，避免产生延伸到有源层的线缺陷，有利于电子和空穴的复合发光，提高LED的发光效率。
在上述实现方式中，第一InGaN子层的厚度、第一GaN子层的厚度、第二InGaN子层的厚度、第二GaN子层的厚度依次减小。
在GaN晶核越来越稳定的情况下，逐渐减小半导体层的厚度，可以尽可能减少生长时间，提高生长效率。
示例性地，第一InGaN子层的厚度为5nm～10nm。
如果第一InGaN子层的厚度小于5nm，则可能由于第一InGaN子层太薄而无法有效增大GaN晶核的体积，进而相邻两个GaN晶核结合在一起时无法有效抵消蓝宝石衬底与GaN基材料之间晶格失配产生的应力；如果第一InGaN子层的厚度大于10nm，则可能由于第一InGaN子层太厚而影响到GaN的晶体结构，导致外延片整体的晶体质量较差，影响电子和空穴的复合发光，降低LED的发光效率。
例如，第一InGaN子层的厚度为6nm～10nm，如8nm。
示例性地，第一GaN子层的厚度为3nm～8nm。
如果第一GaN子层的厚度小于3nm，则可能由于第一GaN子层太薄而影响到GaN的晶体结构，导致外延片整体的晶体质量较差，影响电子和空穴的复合发光，降低LED的发光效率；如果第一GaN子层的厚度大于8nm，则可能由于第一GaN子层太厚而增加对光线的吸收，影响LED的出光效率。
例如，第一GaN子层的厚度为3nm～6nm，如5nm。
示例性地，第二InGaN子层的厚度为2nm～5nm。
如果第二InGaN子层的厚度小于2nm，则可能由于第二InGaN子层的厚度太薄而无法有效增大GaN晶核的体积，进而相邻两个GaN晶核结合在一起时无法有效抵消蓝宝石衬底与GaN基材料之间晶格失配产生的应力；如果第二InGaN子层的厚度大于5nm，则可能由于第二InGaN子层太厚而影响到GaN的晶体结构，导致外延片整体的晶体质量较差，影响电子和空穴的复合发光，降低LED的发光效率。
例如，第二InGaN子层的厚度为1nm～5nm，如3nm。
示例性地，第二GaN子层的厚度为1nm～4nm。
如果第二InGaN子层的厚度小于1nm，则可能由于第二InGaN子层太薄而影响到GaN的晶体结构，导致外延片整体的晶体质量较差，影响电子和空穴的复合发光，降低LED的发光效率；如果第二InGaN子层的厚度大于4nm，则可能由于第二InGaN子层太厚而增加对光线的吸收，影响LED的出光效率。
例如，第二GaN子层的厚度为1.5nm～4nm，如2nm。
示例性地，生成第一InGaN子层和第二InGaN子层时通入In源的流量为50sccm～500sccm。
如果生成第一InGaN子层和第二InGaN子层时通入In源的流量小于50sccm，则可能由于生成第一InGaN子层和第二InGaN子层时通入In源的流量较少而无法有效增大GaN晶核的体积，进而相邻两个GaN晶核结合在一起时无法有效抵消蓝宝石衬底与GaN基材料之间晶格失配产生的应力；如果生成第一InGaN子层和第二InGaN子层时通入In源的流量大于500sccm，则可能由于生成第一InGaN子层和第二InGaN子层时通入In源的流量较多而导致外延片整体的晶体质量较差，影响电子和空穴的复合发光，降低LED的发光效率。
例如，生成第一InGaN子层和第二InGaN子层时通入In源的流量为100sccm～500sccm，如300sccm。
示例性地，复合层生长时，反应室内的温度为530℃～560℃，如545℃；压 力为200torr～500torr，如350torr。
步骤104：在缓冲层上依次生长N型GaN层、有源层和P型GaN层形成外延片，有源层包括交替层叠的InGaN量子阱和GaN量子垒。
本公开实施例通过先在蓝宝石衬底的部分区域内形成包含In原子的GaN晶核，利用In原子的体积大于Ga原子的体积，可以在一定程度上增大GaN晶核的体积，有利于形成稳定的GaN晶核。而且包含In原子的GaN晶核可以吸引复合层中的InGaN子层和GaN子层都选择生长在GaN晶核上，进一步利用In原子的体积大于Ga原子的体积增大GaN晶核的体积，最终形成体积大且稳定的GaN晶核，此时相邻两个GaN晶核之间的距离比较合适，相邻两个GaN晶核结合在一起时可以有效抵消蓝宝石衬底与GaN基材料之间晶格失配产生的应力，避免产生延伸到有源层的线缺陷，有利于电子和空穴的复合发光，提高LED的发光效率。
可选地，N型GaN层生长时，反应室内的温度为1000℃～1100℃，如1050℃；压力为200torr～300torr，如250torr。
InGaN量子阱生长时，反应室内的温度为760℃～780℃，如770℃；压力为200torr。
GaN量子垒生长时，反应室内的温度为860℃～890℃，如875℃；压力为200torr。
P型GaN层生长时，反应室内的温度为940℃～980℃，如960℃；压力为200torr～600torr，如400torr。
示例性地，N型GaN层的厚度为2μm～3μm，如2.5μm；N型GaN层中N型掺杂剂的掺杂浓度为10 18/cm 3～10 20/cm 3，如10 19/cm 3。InGaN量子阱的厚度为2nm～3nm，如2.5nm；InGaN量子阱的数量为11个～13个，如12个。GaN量子垒的厚度为8nm～11nm，如9.5nm；量子垒的数量为11个～13个，如12个。P型GaN层的厚度为50nm～80nm，如65nm；P型GaN层中P型掺杂剂的掺杂浓度为10 18/cm 3～10 20/cm 3，如10 19/cm 3。
可选地，在步骤104之前，该制作方法还包括：
在缓冲层上生长未掺杂GaN层。
相应地，N型GaN层、有源层和P型GaN层依次生长在缓冲层上。
在这种情况下，未掺杂GaN层在GaN晶核之间横向生长并合并，可以减小所形成的生长平面中的杂质，有利于提高有源层的生长质量，进而提高LED的 发光效率。
示例性地，未掺杂GaN层生长时，反应室内的温度为1000℃～1100℃，如1050℃；压力为200torr～600torr，如400torr。
示例性地，未掺杂GaN层的厚度可以为2μm～3.5μm，如2.75μm。
可选地，该制作方法还包括：
在有源层上生长电子阻挡层。
通过增设电子阻挡层避免电子跃迁到P型GaN层，有利于电子和空穴在有源层内进行复合电子发光，提高LED的发光效率。
示例性地，电子阻挡层生长时，反应室内的温度为930℃～970℃，如950℃；压力为100torr。
示例性地，电子阻挡层的材料采用掺杂Mg的Al xGa 1-xN层，0.15≤x≤0.25。电子阻挡层的厚度为30nm～50nm，如40nm。
本公开实施例提供了一种发光二极管外延片，可以采用如图1所示的生长方法形成。图5为本公开实施例提供的一种发光二极管外延片的结构示意图。参见图5，该发光二极管外延片包括蓝宝石衬底10以及依次层叠在蓝宝石衬底10上的缓冲层20、N型GaN层30、有源层40和P型GaN层50，有源层40包括交替层叠的InGaN量子阱41和GaN量子垒42。缓冲层20包括包含In原子的多个GaN晶核21和至少一个复合层22，多个GaN晶核21位于蓝宝石衬底的部分区域内，即多个GaN晶核21间隔布置在所述蓝宝石衬底的表面。至少一个复合层22位于多个GaN晶核21上，每个复合层22包括InGaN子层221和生长在InGaN子层221上的GaN子层222。
本公开实施例通过先在蓝宝石衬底的部分区域内形成包含In原子的GaN晶核，利用In原子的体积大于Ga原子的体积，可以在一定程度上增大GaN晶核的体积，有利于形成稳定的GaN晶核。而且包含In原子的GaN晶核可以吸引复合层中的InGaN子层和GaN子层都选择生长在GaN晶核上，进一步利用In原子的体积大于Ga原子的体积增大GaN晶核的体积，最终形成体积大且稳定的GaN晶核，相邻两个GaN晶核结合在一起时可以有效抵消蓝宝石衬底与GaN基材料之间晶格失配产生的应力，避免产生延伸到有源层的线缺陷，有利于电子和空穴的复合发光，提高LED的发光效率。
此外，在形成GaN晶核时将反应室的温度设置为530℃～560℃和压力设置为200torr～500torr，使得相邻两个GaN晶核之间的距离比较合适，能够更好地 抵消蓝宝石衬底与GaN基材料之间晶格失配产生的应力，进一步减少线缺陷。
可选地，GaN晶核21包括第一GaN晶核、In原子和GaN层，In原子铺设在第一GaN晶核上，GaN层包覆在铺设有In原子的第一GaN晶核上。
可选地，第一GaN晶核的高度为8nm～15nm。
可选地，GaN层的厚度为5nm～10nm。
可选地，复合层22的数量为两个，两个复合层包括依次层叠在GaN晶核上的第一InGaN子层、第一GaN子层、第二InGaN子层和第二GaN子层。
可选地，第一InGaN子层的厚度、第一GaN子层的厚度、第二InGaN子层的厚度、第二GaN子层的厚度依次减小。
可选地，第一InGaN子层的厚度为5nm～10nm，第一GaN子层的厚度为3nm～8nm，第二InGaN子层的厚度为2nm～5nm，第二GaN子层的厚度为1nm～4nm。
可选地，该发光二极管外延片还包括未掺杂GaN层60，未掺杂GaN层60层叠在缓冲层20和N型GaN层30之间。
需要说明的是，本公开实施例中的缓冲层也被称为低温缓冲层，未掺杂GaN层60也被称为高温缓冲层。
本公开实施例还提供了一种发光二极管芯片，包括图5所示外延片以及位于该外延片上的电极。电极包括与N型GaN层连接的N电极以及与P型GaN层连接的P电极。
以上所述仅为本公开的可选实施例，并不用以限制本公开，凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (19)

  1. 一种发光二极管外延片的生长方法，包括：
    将蓝宝石衬底放入反应室内；
    向所述反应室内通入反应气体，在所述蓝宝石衬底的表面形成包含In原子的多个GaN晶核；
    在所述GaN晶核上生长至少一个复合层，所述GaN晶核长大形成缓冲层，每个所述复合层包括InGaN子层和生长在所述InGaN子层上的GaN子层；
    在所述缓冲层上依次生长N型GaN层、有源层和P型GaN层形成外延片，所述有源层包括交替层叠的InGaN量子阱和GaN量子垒。
  2. 根据权利要求1所述的生长方法，其中，所述向所述反应室内通入反应气体，在所述蓝宝石衬底的部分区域内形成包含In原子的GaN晶核，包括：
    向所述反应室内通入Ga源和N源，Ga原子和N原子在所述蓝宝石衬底的部分区域内聚集，形成多个间隔布置的第一GaN晶核；
    向所述反应室内通入In源，In原子吸附在所述第一GaN晶核上，使得所述第一GaN晶核增大为第二GaN晶核；
    向所述反应室内通入Ga源和N源，Ga原子和N原子反应生成的GaN层包覆在所述第二GaN晶核上，形成所述GaN晶核。
  3. 根据权利要求2所述的生长方法，其中，所述第一GaN晶核的高度为8nm～15nm。
  4. 根据权利要求2或3所述的生长方法，其中，形成所述第二GaN晶核时通入In源的时长为10s～50s。
  5. 根据权利要求2～4任一项所述的生长方法，其中，所述GaN层的厚度为5nm～10nm。
  6. 根据权利要求1～5任一项所述的生长方法，其中，所述在所述GaN晶核 上生长至少一个复合层，包括：
    向所述反应室内通入In源、Ga源和N源，In原子、Ga原子和N原子反应生成的第一InGaN子层包覆在所述GaN晶核上；
    向所述反应室内通入Ga源和N源，Ga原子和N原子反应生成的第一GaN子层包覆在所述第一InGaN子层上；
    向所述反应室内通入In源、Ga源和N源，In原子、Ga原子和N原子反应生成的第二InGaN子层包覆在所述第一GaN子层上；
    向所述反应室内通入Ga源和N源，Ga原子和N原子反应生成的第二GaN子层包覆在所述第二InGaN子层上。
  7. 根据权利要求6所述的生长方法，其中，所述第一InGaN子层的厚度、所述第一GaN子层的厚度、所述第二InGaN子层的厚度、所述第二GaN子层的厚度依次减小。
  8. 根据权利要求6或7所述的生长方法，其中，所述第一InGaN子层的厚度为5nm～10nm，所述第一GaN子层的厚度为3nm～8nm，所述第二InGaN子层的厚度为2nm～5nm，所述第二GaN子层的厚度为1nm～4nm。
  9. 根据权利要求6～8任一项所述的生长方法，其中，生成所述第一InGaN子层和所述第二InGaN子层时通入In源的流量为50sccm～500sccm。
  10. 根据权利要求1至9任一项所述的生长方法，还包括：
    在所述缓冲层上依次生长N型GaN层之前，在所述缓冲层上生长未掺杂GaN层。
  11. 一种发光二极管外延片，所述发光二极管外延片包括蓝宝石衬底以及依次层叠在所述蓝宝石衬底上的缓冲层、N型GaN层、有源层和P型GaN层，所述有源层包括交替层叠的InGaN量子阱和GaN量子垒；其中，所述缓冲层包括包含In原子的多个GaN晶核和至少一个复合层，所述多个GaN晶核间隔布置在所述蓝宝石衬底的表面，所述至少一个复合层位于所述多个GaN晶核上，每 个所述复合层包括InGaN子层和生长在所述InGaN子层上的GaN子层。
  12. 根据权利要求11所述的外延片，其中，所述GaN晶核包括第一GaN晶核、In原子和GaN层，所述In原子铺设在所述第一GaN晶核上，所述GaN层包覆在铺设有In原子的第一GaN晶核上。
  13. 根据权利要求12所述的外延片，其中，所述第一GaN晶核的高度为8nm～15nm。
  14. 根据权利要求13所述的外延片，其中，所述GaN层的厚度为5nm～10nm。
  15. 根据权利要求11至14任一项所述的外延片，其中，所述至少一个复合层至少一个复合层包括依次层叠在所述GaN晶核上的第一InGaN子层、第一GaN子层、第二InGaN子层和第二GaN子层。
  16. 根据权利要求15所述的外延片，其中，所述第一InGaN子层的厚度、所述第一GaN子层的厚度、所述第二InGaN子层的厚度、所述第二GaN子层的厚度依次减小。
  17. 根据权利要求16所述的外延片，其中，所述第一InGaN子层的厚度为5nm～10nm，所述第一GaN子层的厚度为3nm～8nm，所述第二InGaN子层的厚度为2nm～5nm，所述第二GaN子层的厚度为1nm～4nm。
  18. 根据权利要求11至17任一项所述的外延片，还包括：
    未掺杂GaN层，所述未掺杂GaN层层叠在所述缓冲层和所述N型GaN层之间。
  19. 一种发光二极管芯片，包括权利要求11～18任一项所述的外延片以及位于所述外延片上的电极。
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