WO2021248676A1 - 阵列基板及其制备方法 - Google Patents

阵列基板及其制备方法 Download PDF

Info

Publication number
WO2021248676A1
WO2021248676A1 PCT/CN2020/108585 CN2020108585W WO2021248676A1 WO 2021248676 A1 WO2021248676 A1 WO 2021248676A1 CN 2020108585 W CN2020108585 W CN 2020108585W WO 2021248676 A1 WO2021248676 A1 WO 2021248676A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
thin film
film transistor
gate
gate insulating
Prior art date
Application number
PCT/CN2020/108585
Other languages
English (en)
French (fr)
Inventor
李金明
Original Assignee
Tcl华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tcl华星光电技术有限公司 filed Critical Tcl华星光电技术有限公司
Priority to US17/045,187 priority Critical patent/US11784191B2/en
Publication of WO2021248676A1 publication Critical patent/WO2021248676A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1237—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a different composition, shape, layout or thickness of the gate insulator in different devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

  • the invention relates to the field of display technology, in particular to an array substrate and a preparation method thereof.
  • the mobility of the polysilicon active layer of thin film transistors is relatively large, which makes the leakage current (Ioff) of low temperature polysilicon (LTPS) thin film transistors large.
  • the power consumption of LTPS substrates under low frequency driving is relatively large, and it is difficult to maintain static black well.
  • the picture, picture quality is poor; and, in order to better expand the gray scale, in the LTPS substrate, it is necessary to drive thin film transistors (English: Driver Thin Film Transistor; abbreviation: DTFT) channel is made very long, so it is difficult to achieve the high resolution of the LTPS substrate (resolution refers to the number of pixels set per inch (English: Pixel Per Inch; abbreviation: PPI).
  • the hysteresis (English: Hysteresis) of the polysilicon active layer is relatively large, so the LTPS substrate is prone to image afterimages.
  • the leakage current of the oxide thin film transistor is small, and the power consumption of the oxide substrate under low-frequency driving is small, which can maintain a static black picture well and improve the picture quality ; And, in the oxide substrate, without making the DTFT channel very long, the gray scale can be better developed and high PPI can be achieved.
  • the oxide active layer has less hysteresis, and the oxide substrate is not prone to image afterimage problems; therefore, the uniformity of oxide thin film transistors is better than that of LTPS thin film transistors.
  • an array substrate and a preparation method thereof prepare an array substrate in which an oxide thin film transistor and a low-temperature polysilicon thin film transistor are mixed, which can improve the mobility of the transistor and the number of pixels on the panel.
  • an array substrate which is characterized by comprising: a substrate; and at least one first thin film transistor and at least one second thin film transistor arranged in parallel on the substrate, the first thin film transistor Is an oxide thin film transistor, and the second thin film transistor is an LTPS thin film transistor; wherein, the first thin film transistor includes: a first gate provided on the substrate; a gate insulating layer provided on the first A gate and the substrate; an active layer, arranged on the gate insulating layer; a first drain, arranged on the gate insulating layer, the first drain and the active The same layer is prepared; a first etching stopper is provided on the gate insulating layer, and the first etching stopper is located between the second thin film transistor and the first drain; and A source electrode is arranged on the active layer.
  • the first thin film transistor further includes: a second etching stopper, which is provided between the active layer and the first drain.
  • the second etching stopper and the first etching stopper are prepared in the same layer.
  • the material of the active layer and the first drain stage is indium gallium zinc oxide.
  • the second thin film transistor includes: a second gate provided on the substrate and covered by the gate insulating layer, and the second gate is prepared in the same layer as the first gate
  • a polysilicon layer is provided on the gate insulating layer; a second source level is provided on the first etch stop block and the polysilicon layer; a second drain level is provided on the polysilicon layer.
  • the second source stage, the second drain stage and the first source stage are prepared in the same layer.
  • the gate insulating layer is provided with a slot, the slot extends down to the surface of the second gate, and the active layer is connected to the second gate through the through hole.
  • a passivation layer is provided on the first thin film transistor and the second thin film transistor; a first electrode is provided on the passivation layer and is connected to the second thin film transistor.
  • Another object of the present invention is to provide a method for preparing an array substrate, including: providing a substrate; forming a first gate and a second gate on the substrate layer; forming a gate insulating layer on the first gate Electrode, the second gate and the substrate; forming an active layer, a first drain and a polysilicon layer on the gate insulating layer; forming a first etching stopper on the gate insulating layer And the first etching stopper is disposed between the polysilicon layer and the first drain level, a second etching stopper is formed on the active layer; and a first source is formed on the active layer. On the active layer, a second source level is formed on the first etch stop block and the polysilicon layer, and a second drain level is formed on the polysilicon layer.
  • the step of forming an active layer, a first drain level, and a polysilicon layer on the gate insulating layer it specifically includes: forming a semiconductor layer on the gate insulating layer; and forming a first monolithic layer.
  • the semiconductor layer forms the active layer and the first drain level, forms a second monocrystalline silicon layer on the gate insulating layer, and forms an induction layer on the gate insulating layer.
  • the second single crystal silicon layer forms the polysilicon layer; removing the inducing layer, and The first single crystal silicon layer.
  • the present invention provides an array substrate and a preparation method thereof.
  • a first etch stop block defines a first thin film transistor and a second thin film transistor. And by disposing the second etch stop block between the active layer and the first source, and the first drain is close to the active layer, the effective channel of the first thin film transistor is shortened, so that the migration of the transistor The rate and the number of pixels of the panel can be greatly increased.
  • FIG. 1 is a schematic diagram of the structure of an array substrate provided by the present invention.
  • FIG. 2 is a schematic diagram of a part of the structure of steps S1 to S2 of the method for manufacturing an array substrate provided by the present invention.
  • FIG. 3 is a plan view of the first metal layer pattern provided by the present invention.
  • step S3 is a schematic diagram of a part of the structure of step S3 of the method for manufacturing an array substrate provided by the present invention.
  • Fig. 5 is a plan view of the gate insulating layer provided by the present invention for slotting.
  • FIG. 6 is a partial structural diagram of step S4 of the method for manufacturing an array substrate provided by the present invention.
  • FIG. 7 is a plan view of the active layer pattern provided by the present invention.
  • FIG. 8 is a partial structural diagram of step S4 of the method for manufacturing an array substrate provided by the present invention.
  • FIG. 9 is a partial structural diagram of step S4 of the method for manufacturing an array substrate provided by the present invention.
  • FIG. 10 is a plan view of a pattern of a polysilicon layer provided by the present invention.
  • FIG. 11 is a schematic diagram of a part of the structure of step S5 of the method for manufacturing an array substrate provided by the present invention.
  • FIG. 12 is a plan view of a pattern of a polysilicon layer provided by the present invention.
  • FIG. 13 is a partial structural diagram of step S6 of the method for manufacturing an array substrate provided by the present invention.
  • FIG. 14 is a plan view of the second metal layer pattern provided by the present invention.
  • Fig. 15 is a plan view of a passivation layer opening provided by the present invention.
  • FIG. 16 is a plan view of the first electrode pattern provided by the present invention.
  • the present invention provides an array substrate 100 including: a substrate 101, at least one first thin film transistor 110 and at least one second thin film transistor 120.
  • the first thin film transistor 110 is an oxide thin film transistor
  • the second thin film transistor 120 is an LTPS thin film transistor.
  • the substrate 101 is a laminated structure, and the materials of two adjacent layers are different, and the materials include molybdenum or aluminum.
  • the first thin film transistor 110 and the second thin film transistor 120 are arranged in parallel on the substrate 101.
  • the first thin film transistor 110 is used as a switching thin film transistor
  • the second thin film transistor 120 is used as a driving thin film transistor.
  • the first thin film transistor 110 includes: a first gate 1101, a gate insulating layer 102, an active layer 1102, a first drain 1103, a first source 1104, a first etching stopper 1105, and a second etching Block 1106.
  • the first gate 1101 is disposed on the substrate 101; the thickness of the first gate 1101 is 2000-5500 angstroms.
  • the first gate 1101 is prepared by a physical vapor deposition (PVD) process.
  • the gate insulating layer 102 is disposed on the first gate 1101 and the substrate 101; the gate insulating layer 102 is deposited by a plasma-enhanced chemical vapor deposition process with a deposition thickness of 1500-4000 angstroms.
  • the gate insulating layer 102 is a composite layer, and the material of the gate insulating layer 102 includes SiNx or SiOx.
  • the active layer 1102 is disposed on the gate insulating layer 102.
  • the first drain stage 1103 is disposed on the gate insulating layer 102, and the first drain stage 1103 is prepared in the same layer as the active layer 1102. Because of the traditional manufacturing method, a preparation process is omitted, and the preparation process is reduced.
  • the materials of the first drain stage 1103 and the active layer 1102 include indium gallium zinc oxide, and the first drain stage 1103 has conductive characteristics.
  • the thickness of the first drain level 1103 and the active layer 1102 is 300-700 angstroms.
  • the first etch stop block 1105 is disposed on the gate insulating layer 102, and the first etch stop block 1105 is disposed between the second thin film transistor 120 and the first drain stage 1103.
  • the first etching stopper 1105 is deposited and prepared by a plasma-enhanced chemical vapor deposition process.
  • the first etching stopper 1105 is a composite layer whose material includes silicon nitride or silicon oxide.
  • the first source electrode 1104 is disposed on the active layer 1102.
  • the thickness of the first source electrode 1104 is 2000-5500 angstroms, and the first source electrode 1104 has a laminated structure.
  • the adjacent film layers have different materials, and the materials include molybdenum or aluminum.
  • the second thin film transistor 120 and the first thin film transistor 110 are defined by the first etching stopper 1105, so the arrangement is tight and space is saved.
  • the second thin film transistor 120 and the first thin film transistor 110 are generally defined by covering the entire surface with an insulating layer, which will waste materials.
  • the first thin film transistor 110 further includes: a second etching stopper 1106.
  • the second etch stop block 1106 is disposed between the active layer 1102 and the first source electrode 1104, and the active layer 1102 is adjacent to the first drain electrode 1103.
  • the second etch stop block 1106 serves as an effective channel for the first source 1104 and the first drain 1103, the first source 1104 is disposed on the active layer 1102, and the first drain 1103 It is arranged at one end of the active layer 1102, thereby shortening the distance of the channel, so that the mobility of the transistor and the number of pixels of the panel can be greatly improved.
  • the effective channel in the prior art is generally defined by the source and drain electrodes provided at both ends of the active layer 1102, so the distance will be affected by the distance between the source and the drain.
  • the first source electrode 1104 Since the first source electrode 1104 is deposited on the entire surface and rises and falls on the second etching stop block 1106, the first source electrode 1104 has a dam structure.
  • the short effective channel of the first thin film transistor 110 is defined by the second etch stop block 1106, so that the mobility of the transistor and the number of pixels on the panel can be greatly improved.
  • the second etch stop block 1106 and the first etch stop block 1105 are prepared in the same layer.
  • the second thin film transistor 120 includes a second gate 1201, a polysilicon layer 1203, a second source 1202, and a second drain 1204.
  • the second gate 1201 is disposed on the substrate 101 and is covered by the gate insulating layer 102, and the second gate 1201 and the first gate 1101 are prepared in the same layer.
  • the thickness of the second gate 1201 is 2000-5500 angstroms.
  • the second gate 1201 is prepared by a physical vapor deposition (PVD) process.
  • the polysilicon layer 1203 is disposed on the gate insulating layer 102.
  • the polysilicon layer 1203 has a thickness of 400-1000 angstroms and is made by PVD deposition.
  • the second source level 1202 is provided on the first etch stop block 1105 and the polysilicon layer 1203.
  • the thickness of the second source electrode is 2000-5500 angstroms, and the second source electrode has a laminated structure.
  • the adjacent film layers have different materials, and the material includes molybdenum or aluminum.
  • the second drain stage 1204 is provided on the polysilicon layer 1203.
  • the thickness of the second drain electrode is 2000-5500 angstroms, and the second drain electrode has a laminated structure.
  • the adjacent film layers are made of different materials, and the material includes molybdenum or aluminum.
  • the second source stage 1202, the second drain stage 1204, and the first source stage 1104 are prepared in the same layer. Moreover, the first drain stage 1103 and the active layer 1102 are prepared in the same layer, which does not add a new process step.
  • the gate insulating layer 102 is provided with a slot 1121, the slot 1121 extends downward to the surface of the second gate 1201, and the active layer 1102 is connected to the second gate 1201 through the through hole .
  • the array substrate 100 further includes a passivation layer 103 and a first electrode 104.
  • the passivation layer 103 is provided on the first thin film transistor 110 and the second thin film transistor 120.
  • the first electrode 104 is disposed on the passivation layer 103 and connected to the second thin film transistor 120.
  • the first electrode 104 is connected to the second drain 1204 of the second thin film transistor 120 through a groove 1031, the groove 1031 is formed in the passivation layer 103, and the groove 1031 extends downward to The surface of the second drain stage 1204.
  • the present invention provides an array substrate 100, and a first etch stop block 1105 defines a first thin film transistor 110 and a second thin film transistor 120.
  • a first etch stop block 1105 defines a first thin film transistor 110 and a second thin film transistor 120.
  • the present invention also provides a method for preparing an array substrate to prepare the array sophistication, which includes the following steps.
  • a substrate 101 is provided; the substrate 101 is a laminated structure, and the materials of two adjacent layers are different, and the materials include molybdenum or aluminum.
  • the first gate 1101 and the second gate 1201 are patterned by using the PVD process to deposit 2000-5500 angstroms of metal materials, and then using the yellow light process and the etching process to pattern.
  • the area 110 in FIG. 3 is the thin film transistor area of the present invention, and the pattern of the entire pixel structure is given.
  • the left and right sides of the thin film transistor area are sub-pixel areas.
  • FIG. 3 shows the pattern of the first metal layer (M1) in the pixel structure.
  • a gate insulating layer 102 is formed on the first gate 1101, the second gate 1201, and the substrate 101.
  • the gate insulating layer 102 is obtained by depositing silicon nitride or silicon oxide material through a plasma-enhanced chemical vapor deposition process and patterning using a yellow light process and an etching process, and the gate insulating layer 102 has a slot 1121 , The slot 1121 is recessed down to the upper surface of the second gate 1201.
  • the thickness of the gate insulating layer 102 is 1000-2500 angstroms.
  • the steps of forming the active layer 1102, the first drain level 1103, and the polysilicon layer 1203 on the gate insulating layer 102 specifically include S401 to S404.
  • a semiconductor layer 105 is formed on the gate insulating layer 102, and the semiconductor layer 105 is connected to the second gate 1201 through the slot 1121.
  • the semiconductor layer 105 is obtained by depositing an IGZO oxide material with a thickness of 300-700 angstroms using a PVD process, and patterning using a yellow light process and an etching process. Among them, the IGZO oxide material pattern is shown in FIG. 7.
  • the semiconductor layer 105 forms the active layer 1102 and the first drain level 1103; and forms a second monocrystalline silicon layer 106.
  • a layer of crystalline silicon 107 is formed on the gate insulating layer 102, and an inducing layer 108 is formed on the second single crystal silicon layer 107.
  • this part is the first drain stage 1103.
  • the a-Si layer is deposited by a plasma enhanced chemical vapor deposition process with a thickness of 400-1000 angstroms, and then an induction layer of a Ni-Si alloy of 50-200 angstroms is deposited by PVD, and finally patterned by yellow light process and etching process.
  • the active layer 1102 is subjected to defect repair and a-Si crystal bloom to form the polysilicon layer 1203 through high temperature annealing, the annealing temperature is 300 to 600° C., and the time is 0.5 to 4 hours.
  • a first etching stopper 1105 is formed on the gate insulating layer 102, and the first etching stopper 1105 is provided on the polysilicon layer 1203 and the first Between the drain levels 1103, a second etch stop block 1106 is formed on the active layer 1102.
  • a silicon oxide or silicon nitride material with a thickness of 100 to 2000 angstroms is deposited by a plasma enhanced chemical vapor deposition process, and then the first etching stopper 1105 and the first etching stopper 1105 and the The second etching stopper 1106.
  • FIG. 12 shows the patterns of the first etching stopper 1105 and the second etching stopper 1106.
  • a first source electrode 1104 is formed on the active layer 1102, and a second source electrode 1202 is formed on the first etch stop block 1105 and the polysilicon layer 1203 to form The second drain 1204 is on the polysilicon layer 1203.
  • the first source electrode 1104, the second source electrode 1202, and the second drain electrode 1204 are obtained by patterning the first source electrode 1104, the second source electrode 1202, and the second drain electrode 1204 by respectively depositing the metal material of 2000-5500 angstroms through the PVD process, and then patterning by the yellow light process and the etching process.
  • Fig. 14 shows the pattern of the second metal layer (M2), and the upper and lower horizontal lines are the data lines.
  • the cross-sectional structure at the vertical dashed line is shown in FIG. 1.
  • a plurality of pixel structures are arranged in an array to form the display panel of the present invention.
  • the present invention provides a method for preparing an array substrate.
  • the first drain stage 1103 is prepared together when the active layer 1102 is prepared, and two thin film transistors are defined by the first etching stopper 1105;
  • a source electrode 1104 is provided on the second etch stop block 1106, and the channel of the first thin film transistor 110 defined by the second etch stop block 1106 becomes shorter, so that the effective area of each transistor is reduced, In turn, the mobility and the number of pixels of the panel can be greatly improved.
  • the present invention also provides a display device, which includes the array substrate of the present invention.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)

Abstract

一种阵列基板及其制备方法，阵列基板包括：衬底（101）、至少一个第一薄膜晶体管（110）以及至少一个第二薄膜晶体管（120）。阵列基板的制备方法通过第一刻蚀阻挡块（1105）限定了第一薄膜晶体管（110）以及第二薄膜晶体管（120），并且通过将第二刻蚀阻挡块（1106）设置在有源层（1102）与第一源极（1104）之间，而第一漏极（1103）靠近有源层（1102），进而缩短了第一薄膜晶体管（110）的有效沟道，使得晶体管的迁移率和面板的像素数量可以大幅度提升。

Description

阵列基板及其制备方法 技术领域
本发明涉及显示技术领域，特别是一种阵列基板及其制备方法。
 背景技术
一般薄膜晶体管的多晶硅有源层的迁移率较大，使得低温多晶硅（LTPS）薄膜晶体管的漏电流(Ioff)较大，LTPS基板在低频驱动下的功耗较大，难以很好的保持静态黑画面，画面品质较差；并且，为了更好的展开灰阶，在LTPS基板中，需要将驱动薄膜晶体管(英文：Driver Thin Film Transistor；简称：DTFT)的沟道制作的很长，这样就难以实现LTPS基板的高分辨率（分辨率指的是每英寸所设置的像素数目(英文：Pixel Per Inch；简称：PPI)。
 技术问题
此外，多晶硅有源层的迟滞(英文：Hysteresis)较大，因此LTPS基板容易出现画面残像的问题。
由于氧化物材料的有源层的迁移率较小，使得氧化物薄膜晶体管的漏电流较小，氧化物基板在低频驱动下的功耗较小，能够很好的保持静态黑画面，提升画面品质；并且，在氧化物基板中，无需将DTFT的沟道制作的很长，就能更好的展开灰阶，实现高PPI。
此外，氧化物有源层的迟滞较小，氧化物基板不容易出现画面残像问题；所以氧化物薄膜晶体管的均一性比LTPS薄膜晶体管的均一性好。
因此，有必要提供一种阵列基板，能够以金属氧化物薄膜晶体管为开关薄膜晶体管，LTPS为驱动薄膜晶体管，同时解决LTPS基板的分辨率问题和晶体管的迁移率较小的问题。
 技术解决方案
，提供一种阵列基板及其制备方法，制备氧化物薄膜晶体管与低温多晶硅薄膜晶体管混合的阵列基板，能够提升晶体管的迁移率和面板的像素数量。
为了达到上述目的，提供一种阵列基板，其特征在于，包括：衬底；以及并列设于所述衬底上的至少一个第一薄膜晶体管以及至少一个第二薄膜晶体管，所述第一薄膜晶体管为氧化物薄膜晶体管，所述第二薄膜晶体管为LTPS薄膜晶体管；其中，所述第一薄膜晶体管包括：第一栅极，设于所述衬底上；栅极绝缘层，设于所述第一栅极以及所述衬底上；有源层，设于所述栅极绝缘层上；第一漏级，设于所述栅极绝缘层上，所述第一漏级与所述有源层同层制备；第一刻蚀阻挡块，设于所述栅极绝缘层上，且所述第一刻蚀阻挡块位于所述第二薄膜晶体管与所述第一漏级之间；以及第一源极，设于所述有源层上。
进一步地，所述第一薄膜晶体管还包括：第二刻蚀阻挡块，设于所述有源层以及所述第一漏级之间。
进一步地，所述第二刻蚀阻挡块与所述第一刻蚀阻挡块同层制备。
进一步地，所述有源层与所述第一漏级的材料为铟镓锌氧化物。
进一步地，所述第二薄膜晶体管包括：第二栅极，设于所述衬底上且被所述栅极绝缘层包覆，所述第二栅极与所述第一栅极同层制备；多晶硅层，设于所述栅极绝缘层上；第二源级，设于所述第一刻蚀阻挡块以及所述多晶硅层上；第二漏级，设于所述多晶硅层上。
进一步地，所述第二源级、所述第二漏级以及所述第一源级同层制备。
进一步地，所述栅极绝缘层设有一开槽，所述开槽向下延伸至所述第二栅极表面，所述有源层通过所述通孔连接所述第二栅极。
进一步地，钝化层，设于所述第一薄膜晶体管以及所述第二薄膜晶体管上；第一电极，设于所述钝化层且连接所述第二薄膜晶体管。
本发明另一目的为提供一种阵列基板的制备方法，包括：提供一衬底；形成第一栅极以及第二栅极于所述衬底层上；形成栅极绝缘层于所述第一栅极、所述第二栅极以及所述衬底上；形成有源层、第一漏级以及多晶硅层于所述栅极绝缘层上；形成第一刻蚀阻挡块于所述栅极绝缘层上，且所述第一刻蚀阻挡块设于所述多晶硅层与所述第一漏级之间，形成第二刻蚀阻挡块于所述有源层上；以及形成第一源极于所述有源层上，形成第二源级于所述第一刻蚀阻挡块以及所述多晶硅层上，形成第二漏级于所述多晶硅层上。
进一步地，在所述的形成有源层、第一漏级以及多晶硅层于所述栅极绝缘层上的步骤中，具体包括：形成半导体层于所述栅极绝缘层上；形成第一单晶硅层于所述半导体层上后，所述半导体层形成所述有源层以及所述第一漏级，形成第二单晶硅层于所述栅极绝缘层上，形成诱导层于所述第二单晶硅层上；对所述有源层以及所述第二单晶硅层使用高温退火工艺，所述第二单晶硅层形成所述多晶硅层；移除所述诱导层以及所述第一单晶硅层。
 有益效果
本发明提供一种阵列基板及其制备方法，通过第一刻蚀阻挡块限定了第一薄膜晶体管以及第二薄膜晶体管。并且通过将第二刻蚀阻挡块设置在有源层与第一源极之间，而第一漏级靠近所述有源层，进而缩短了第一薄膜晶体管的有效沟道，使得晶体管的迁移率和面板的像素数量可以大幅度提升。
 附图说明
图1为本发明提供的阵列基板的结构示意图。
图2为本发明提供的阵列基板制备方法的步骤S1~S2的部分结构示意图。
图3为本发明提供的第一金属层图案的平面图。
图4为本发明提供的阵列基板制备方法的步骤S3的部分结构示意图。
图5为本发明提供的栅极绝缘层开槽的平面图。
图6为本发明提供的阵列基板制备方法的步骤S4的部分结构示意图。
图7为本发明提供的有源层图案的平面图。
图8为本发明提供的阵列基板制备方法的步骤S4的部分结构示意图。
图9为本发明提供的阵列基板制备方法的步骤S4的部分结构示意图。
图10为本发明提供的多晶硅层图案的平面图。
图11为本发明提供的阵列基板制备方法的步骤S5的部分结构示意图。
图12为本发明提供的多晶硅层图案的平面图。
图13为本发明提供的阵列基板制备方法的步骤S6的部分结构示意图。
图14为本发明提供的第二金属层图案的平面图。
图15为本发明提供的钝化层开孔的平面图。
图16为本发明提供的第一电极图案的平面图。
阵列基板100；
衬底101；第一薄膜晶体管110；第二薄膜晶体管120；
第一栅极1101；栅极绝缘层102；有源层1102；
第一漏级1103；第一源极1104；第一刻蚀阻挡块1105；
第二刻蚀阻挡块1106；第二栅极1201；多晶硅层1203；
第二源级1202；第二漏级1204；钝化层103；
第一电极104；开槽1121；凹槽1031。
 本发明的实施方式
本申请提供一种实体键盘输入系统、键盘输入方法及存储介质，为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
如图1所示，本发明提供一种阵列基板100，包括：衬底101、至少一个第一薄膜晶体管110以及至少一个第二薄膜晶体管120。
所述第一薄膜晶体管110为氧化物薄膜晶体管，所述第二薄膜晶体管120为LTPS薄膜晶体管。
所述衬底101为一叠层结构，相邻两层的材质不同，所述材质包括钼或铝。
所述第一薄膜晶体管110以及所述第二薄膜晶体管120并列设于所述衬底101上。所述第一薄膜晶体管110用作开关薄膜晶体管，所述第二薄膜晶体管120用作驱动薄膜晶体管。
所述第一薄膜晶体管110包括：第一栅极1101、栅极绝缘层102、有源层1102、第一漏级1103、第一源极1104、第一刻蚀阻挡块1105以及第二刻蚀阻挡块1106。
所述第一栅极1101设于所述衬底101上；所述第一栅极1101的厚度为2000~5500埃。所述第一栅极1101采用物理气相沉积（PVD）工艺制备得到。
所述栅极绝缘层102设于所述第一栅极1101以及所述衬底101上；所述栅极绝缘层102通过等离子增强化学气相沉积工艺沉积，沉积厚度为1500~4000埃。所述栅极绝缘层102为复合层，所述栅极绝缘层102的材料包括SiNx或SiOx。
所述有源层1102设于所述栅极绝缘层102上。
所述第一漏级1103设于所述栅极绝缘层102上，所述第一漏级1103与所述有源层1102同层制备。在于传统的制作方法，省去一个制备流程，减小了制备工艺。
所述第一漏级1103与所述有源层1102的材料包括铟镓锌氧化物，所述第一漏级1103具有导电特性。所述第一漏级1103与所述有源层1102厚度为300~700埃。
所述第一刻蚀阻挡块1105设于所述栅极绝缘层102上，且所述第一刻蚀阻挡块1105设于所述第二薄膜晶体管120与所述第一漏级1103之间。
所述第一刻蚀阻挡块1105通过等离子增强化学气相沉积工艺沉积制备，所述第一刻蚀阻挡块1105为复合层，其材料包括氮化硅或氧化硅。
所述第一源极1104设于所述有源层1102上。所述第一源极1104的厚度为2000~5500埃，所述第一源极1104为叠层结构，相邻膜层的材料不同，材料包括钼或铝。
本发明所提供的阵列基板100是通过第一刻蚀阻挡块1105限定所述第二薄膜晶体管120与所述第一薄膜晶体管110，因此排布紧密，节省空间。
而现有技术一般通过整面覆盖绝缘层对所述第二薄膜晶体管120与所述第一薄膜晶体管110进行限定，这会浪费材料。
所述第一薄膜晶体管110还包括：第二刻蚀阻挡块1106。
所述第二刻蚀阻挡块1106设于所述有源层1102与所述第一源极1104之间，而所述有源层1102与所述第一漏级1103相邻。
因此所述第二刻蚀阻挡块1106作为所述第一源极1104与所述第一漏级1103的有效沟道，将第一源极1104设置在有源层1102上，第一漏级1103设于有源层1102的一端，进而缩短了沟道的距离，使得晶体管的迁移率和面板的像素数量可以大幅度提升。现有技术的有效沟道一般通过设置在有源层1102两端的源漏电极限定，因而距离会受源漏极的之间的距离影响。
由于所述第一源极1104整面沉积并在所述第二刻蚀阻挡块1106上起落，因此所述第一源极1104为堤坝结构。
本发明提供的第一薄膜晶体管110，通过第二刻蚀阻挡块1106限定了第一薄膜晶体管110较短的有效沟道，进而晶体管的迁移率和面板的像素数量可以大幅度提升。
所述第二刻蚀阻挡块1106与所述第一刻蚀阻挡块1105同层制备。
所述第二薄膜晶体管120包括：第二栅极1201、多晶硅层1203、第二源级1202以及第二漏级1204。
所述第二栅极1201设于所述衬底101上且被所述栅极绝缘层102包覆，所述第二栅极1201与所述第一栅极1101同层制备。
所述第二栅极1201的厚度为2000~5500埃。所述第二栅极1201采用物理气相沉积（PVD）工艺制备得到。
所述多晶硅层1203设于所述栅极绝缘层102上。所述多晶硅层1203的厚度400~1000埃，通过PVD沉积制得。
所述第二源级1202设于所述第一刻蚀阻挡块1105以及所述多晶硅层1203上。所述第二源极的厚度为2000~5500埃，所述第二源极为叠层结构，相邻膜层的材料不同，材料包括钼或铝。
所述第二漏级1204设于所述多晶硅层1203上。所述第二漏极的厚度为2000~5500埃，所述第二漏极为叠层结构，相邻膜层的材料不同，材料包括钼或铝。
所述第二源级1202、所述第二漏级1204以及所述第一源级1104同层制备。并且所述第一漏级1103与所述有源层1102同层制备，这并未增加新的制程步骤。
所述栅极绝缘层102设有一开槽1121，所述开槽1121向下延伸至所述第二栅极1201表面，所述有源层1102通过所述通孔连接所述第二栅极1201。
所述阵列基板100还包括：钝化层103以及第一电极104。
所述钝化层103设于所述第一薄膜晶体管110以及所述第二薄膜晶体管120上。所述第一电极104设于所述钝化层103且连接所述第二薄膜晶体管120。
具体地，所述第一电极104通过凹槽1031连接所述第二薄膜晶体管120第二漏级1204，所述凹槽1031形成于所述钝化层103，所述凹槽1031向下延伸至所述第二漏级1204的表面。
本发明提供一种阵列基板100，通过第一刻蚀阻挡块1105限定了第一薄膜晶体管110以及第二薄膜晶体管120。通过将第二刻蚀阻挡块1106设置在有源层1102与第一源极1104之间，而第一漏级1103靠近所述有源层1102，进而缩短了第一薄膜晶体管110较短的有效沟道（指源极与漏级之间的距离），使得晶体管的迁移率和面板的像素数量可以大幅度提升。
本发明还提供一种阵列基板的制备方法，用以制备得到所述的阵列狡辩，包括如下步骤。
S1、如图2所示，提供一衬底101；所述衬底101为一叠层结构，相邻两层的材质不同，所述材质包括钼或铝。
S2、同时参照图3所示，形成第一栅极1101以及第二栅极1201于所述衬底101层上。
具体地，通过使用PVD工艺分别沉积2000~5500埃的金属材料, 再利用黄光工艺和刻蚀工艺图案化得到的所述第一栅极1101以及所述第二栅极1201。
图3中的区域110即为本发明的薄膜晶体管区域，并给出了整个像素结构的图案，薄膜晶体管区域左右两侧为子像素区域。图3为像素结构中第一金属层（M1）的图案。
S3、如图4以及图5所示，形成栅极绝缘层102于所述第一栅极1101、所述第二栅极1201以及所述衬底101上。
具体地，通过等离子增强化学气相沉积工艺沉积氮化硅或氧化硅材料并使用黄光工艺和刻蚀工艺图案化得到所述栅极绝缘层102，所述栅极绝缘层102具有一开槽1121，所述开槽1121向下凹陷至所述第二栅极1201的上表面。
所述栅极绝缘层102的厚度为1000~2500埃。
S4、形成有源层1102、第一漏级1103以及多晶硅层1203于所述栅极绝缘层102上。
在所述的形成有源层1102、第一漏级1103以及多晶硅层1203于所述栅极绝缘层102上的步骤中，具体包括S401~ S404。
S401、如图6所示，形成半导体层105于所述栅极绝缘层102上，所述半导体层105通过所述开槽1121连接所述第二栅极1201。
具体地，通过用PVD工艺沉积IGZO氧化物材料, 厚度为300~700埃，并利用黄光工艺和刻蚀工艺图案化得到所述半导体层105。其中，IGZO氧化物材料图案如图7所示。
S402、参照图8所示，形成第一单晶硅层106于所述半导体层105上后，所述半导体层105形成所述有源层1102以及所述第一漏级1103；形成第二单晶硅107层于所述栅极绝缘层102上，并形成诱导层108于所述第二单晶硅层107上。
因为在所述半导体层105上方的第一单晶硅层106可以通过氢离子，使得对应部分的半导体层105导电，该部分即为所述第一漏级1103。
具体地，通过等离子增强化学气相沉积工艺沉积a-Si层，厚度400~1000埃，再通过PVD沉积50~200埃Ni-Si合金的诱导层，最后通过黄光工艺和刻蚀工艺图案化得到所述第一单晶硅层106、所述第二单晶硅层107以及所述诱导层108。
S403、对所述有源层1102以及所述第二单晶硅层107使用高温退火工艺，所述第二单晶硅层107形成所述多晶硅层1203。
具体地，通过高温退火对所述有源层1102进行缺陷修复和a-Si晶华形成所述多晶硅层1203，退火温度为300~600℃，时间为0.5~4小时。
S404、移除所述诱导层108以及所述第一单晶硅层106，得到如图9所示的结构，图10为该结构的平面图案。
S5、如图11以及12所示，形成第一刻蚀阻挡块1105于所述栅极绝缘层102上，且所述第一刻蚀阻挡块1105设于所述多晶硅层1203与所述第一漏级1103之间，形成第二刻蚀阻挡块1106于所述有源层1102上。
具体地，通过等离子增强化学气相沉积工艺沉积,厚度100~2000埃的氧化硅或氮化硅材料，再依次利用黄光工艺和刻蚀工艺制得所述第一刻蚀阻挡块1105以及所述第二刻蚀阻挡块1106。
图12为所述第一刻蚀阻挡块1105与所述第二刻蚀阻挡块1106的图案。
S6、如图13以及14所示，形成第一源极1104于所述有源层1102上，形成第二源级1202于所述第一刻蚀阻挡块1105以及所述多晶硅层1203上，形成第二漏级1204于所述多晶硅层1203上。
具体地，通过PVD工艺分别沉积形成2000~5500埃的金属材料, 再利用黄光工艺和刻蚀工艺图案化得到的第一源极1104、第二源级1202以及第二漏级1204。
图14为第二金属层（M2）的图案，上下两根水平的线为数据线。垂直的虚线处的剖面结构即为图1。
最后需要进行如图15所示的钝化层开孔，以及如图16所示的第一电极104的涂布形成本发明的像素结构。多个像素结构阵列排布即可形成本发明的显示面板。
本发明提供一种阵列基板的制备方法，通过在制备所述有源层1102的时候一同制备第一漏级1103，并且通过第一刻蚀阻挡块1105对两个薄膜晶体管进行限定；接着将第一源极1104设于第二刻蚀阻挡块1106的上，进而所述第二刻蚀阻挡块1106所限定的第一薄膜晶体管110的沟道变短，使得每个晶体管的有效面积减小，进而使得迁移率和面板的像素数量可以大幅度提升。
本发明还提供一种显示装置，包括本发明所述的阵列基板。
可以理解的是，对本领域普通技术人员来说，可以根据本申请的技术方案及其发明构思加以等同替换或改变，而所有这些改变或替换都应属于本申请所附的权利要求的保护范围。

Claims (18)

  1. 一种阵列基板，其中，包括：
    衬底；以及
    并列设于所述衬底上的至少一个第一薄膜晶体管以及至少一个第二薄膜晶体管，所述第一薄膜晶体管为氧化物薄膜晶体管，所述第二薄膜晶体管为LTPS薄膜晶体管；
    其中，所述第一薄膜晶体管包括：
    第一栅极，设于所述衬底上；
    栅极绝缘层，设于所述第一栅极以及所述衬底上；
    有源层，设于所述栅极绝缘层上；
    第一漏级，设于所述栅极绝缘层上，所述第一漏级与所述有源层同层制备；
    第一刻蚀阻挡层，设于所述栅极绝缘层上，且所述第一刻蚀阻挡块位于所述第二薄膜晶体管与所述第一漏级之间；以及
    第一源极，设于所述有源层上。
  2. 如权利要求1所述的阵列基板，其中，
    所述第一薄膜晶体管还包括：
    第二刻蚀阻挡块，设于所述有源层以及所述第一漏级之间。
  3. 如权利要求2所述的阵列基板，其中，
    所述第二刻蚀阻挡块与所述第一刻蚀阻挡块同层制备。
  4. 如权利要求1所述的阵列基板，其中，
    所述有源层与所述第一漏级的材料为铟镓锌氧化物。
  5. 如权利要求1所述的阵列基板，其中，
    所述第二薄膜晶体管包括：
    第二栅极，设于所述衬底上且被所述栅极绝缘层包覆，所述第二栅极与所述第一栅极同层制备；
    多晶硅层，设于所述栅极绝缘层上；
    第二源级，设于所述第一刻蚀阻挡块以及所述多晶硅层上；
    第二漏级，设于所述多晶硅层上。
  6. 如权利要求5所述的阵列基板，其中，
    所述第二源级、所述第二漏级以及所述第一源级同层制备。
  7. 如权利要求5所述的阵列基板，其中，
    所述栅极绝缘层设有一开槽，所述开槽向下延伸至所述第二栅极表面，所述有源层通过所述通孔连接所述第二栅极。
  8. 如权利要求1所述的阵列基板，其中，还包括
    钝化层，设于所述第一薄膜晶体管以及所述第二薄膜晶体管上；
    第一电极，设于所述钝化层且连接所述第二薄膜晶体管。
  9. 一种阵列基板的制备方法，其中，包括：
    提供一衬底；
    形成第一栅极以及第二栅极于所述衬底层上；
    形成栅极绝缘层于所述第一栅极、所述第二栅极以及所述衬底上；
    形成有源层、第一漏级以及多晶硅层于所述栅极绝缘层上；
    形成第一刻蚀阻挡块于所述栅极绝缘层上，且所述第一刻蚀阻挡块设于所述多晶硅层与所述第一漏级之间，形成第二刻蚀阻挡块于所述有源层上；以及
    形成第一源极于所述有源层上，形成第二源级于所述第一刻蚀阻挡块以及所述多晶硅层上，形成第二漏级于所述多晶硅层上。
  10. 如权利要求9所述的阵列基板的制备方法，其中，
    在所述的形成有源层、第一漏级以及多晶硅层于所述栅极绝缘层上的步骤中，具体包括：
    形成半导体层于所述栅极绝缘层上；
    形成第一单晶硅层于所述半导体层上后，所述半导体层形成所述有源层以及所述第一漏级，形成第二单晶硅层于所述栅极绝缘层上，形成诱导层于所述第二单晶硅层上；
    对所述有源层以及所述第二单晶硅层使用高温退火工艺，所述第二单晶硅层形成所述多晶硅层；
    移除所述诱导层以及所述第一单晶硅层。
  11. 一种显示装置，其中，包括一阵列基板；
    所述阵列基板包括：
    衬底；以及
    并列设于所述衬底上的至少一个第一薄膜晶体管以及至少一个第二薄膜晶体管，所述第一薄膜晶体管为氧化物薄膜晶体管，所述第二薄膜晶体管为LTPS薄膜晶体管；
    其中，所述第一薄膜晶体管包括：
    第一栅极，设于所述衬底上；
    栅极绝缘层，设于所述第一栅极以及所述衬底上；
    有源层，设于所述栅极绝缘层上；
    第一漏级，设于所述栅极绝缘层上，所述第一漏级与所述有源层同层制备；
    第一刻蚀阻挡层，设于所述栅极绝缘层上，且所述第一刻蚀阻挡块位于所述第二薄膜晶体管与所述第一漏级之间；以及
    第一源极，设于所述有源层上。
  12. 如权利要求11所述的显示装置，其中，
    所述第一薄膜晶体管还包括：
    第二刻蚀阻挡块，设于所述有源层以及所述第一漏级之间。
  13. 如权利要求12所述的显示装置，其中，
    所述第二刻蚀阻挡块与所述第一刻蚀阻挡块同层制备。
  14. 如权利要求11所述的显示装置，其中，
    所述有源层与所述第一漏级的材料为铟镓锌氧化物。
  15. 如权利要求11所述的显示装置，其中，
    所述第二薄膜晶体管包括：
    第二栅极，设于所述衬底上且被所述栅极绝缘层包覆，所述第二栅极与所述第一栅极同层制备；
    多晶硅层，设于所述栅极绝缘层上；
    第二源级，设于所述第一刻蚀阻挡块以及所述多晶硅层上；
    第二漏级，设于所述多晶硅层上。
  16. 如权利要求15所述的显示装置，其中，
    所述第二源级、所述第二漏级以及所述第一源级同层制备。
  17. 如权利要求15所述的显示装置，其中，
    所述栅极绝缘层设有一开槽，所述开槽向下延伸至所述第二栅极表面，所述有源层通过所述通孔连接所述第二栅极。
  18. 如权利要求11所述的显示装置，其中，所述阵列基板还包括：
    钝化层，设于所述第一薄膜晶体管以及所述第二薄膜晶体管上；
    第一电极，设于所述钝化层且连接所述第二薄膜晶体管。
PCT/CN2020/108585 2020-06-08 2020-08-12 阵列基板及其制备方法 WO2021248676A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/045,187 US11784191B2 (en) 2020-06-08 2020-08-12 Array substrate, manufacturing method thereof, and display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010511787.3 2020-06-08
CN202010511787.3A CN111668236A (zh) 2020-06-08 2020-06-08 阵列基板及其制备方法

Publications (1)

Publication Number Publication Date
WO2021248676A1 true WO2021248676A1 (zh) 2021-12-16

Family

ID=72385729

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/108585 WO2021248676A1 (zh) 2020-06-08 2020-08-12 阵列基板及其制备方法

Country Status (3)

Country Link
US (1) US11784191B2 (zh)
CN (1) CN111668236A (zh)
WO (1) WO2021248676A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114242736A (zh) * 2021-12-17 2022-03-25 湖北长江新型显示产业创新中心有限公司 一种显示面板及显示装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140231813A1 (en) * 2011-10-03 2014-08-21 Panasonic Corporation Thin-film device, thin-film device array, and method of manufacturing thin-film device
CN104022079A (zh) * 2014-06-19 2014-09-03 深圳市华星光电技术有限公司 薄膜晶体管基板的制造方法
CN104183608A (zh) * 2014-09-02 2014-12-03 深圳市华星光电技术有限公司 Tft背板结构及其制作方法
CN104952884A (zh) * 2015-05-13 2015-09-30 深圳市华星光电技术有限公司 Amoled背板结构及其制作方法
CN106057735A (zh) * 2016-06-07 2016-10-26 深圳市华星光电技术有限公司 Tft背板的制作方法及tft背板
CN107302030A (zh) * 2016-04-08 2017-10-27 群创光电股份有限公司 显示设备
CN110739271A (zh) * 2019-10-16 2020-01-31 南京中电熊猫平板显示科技有限公司 一种阵列基板及其制造方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102227474B1 (ko) * 2013-11-05 2021-03-15 삼성디스플레이 주식회사 박막트랜지스터 어레이 기판, 유기발광표시장치 및 박막트랜지스터 어레이 기판의 제조 방법
CN103715141B (zh) * 2013-12-27 2015-02-18 京东方科技集团股份有限公司 一种阵列基板及其制备方法
US9985082B2 (en) * 2016-07-06 2018-05-29 Lg Display Co., Ltd. Organic light emitting display device comprising multi-type thin film transistor and method of manufacturing the same

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140231813A1 (en) * 2011-10-03 2014-08-21 Panasonic Corporation Thin-film device, thin-film device array, and method of manufacturing thin-film device
CN104022079A (zh) * 2014-06-19 2014-09-03 深圳市华星光电技术有限公司 薄膜晶体管基板的制造方法
CN104183608A (zh) * 2014-09-02 2014-12-03 深圳市华星光电技术有限公司 Tft背板结构及其制作方法
CN104952884A (zh) * 2015-05-13 2015-09-30 深圳市华星光电技术有限公司 Amoled背板结构及其制作方法
CN107302030A (zh) * 2016-04-08 2017-10-27 群创光电股份有限公司 显示设备
CN106057735A (zh) * 2016-06-07 2016-10-26 深圳市华星光电技术有限公司 Tft背板的制作方法及tft背板
CN110739271A (zh) * 2019-10-16 2020-01-31 南京中电熊猫平板显示科技有限公司 一种阵列基板及其制造方法

Also Published As

Publication number Publication date
CN111668236A (zh) 2020-09-15
US11784191B2 (en) 2023-10-10
US20230120164A1 (en) 2023-04-20

Similar Documents

Publication Publication Date Title
CN105390451B (zh) 低温多晶硅tft基板的制作方法
CN103123910B (zh) 阵列基板及其制造方法、显示装置
US10205027B2 (en) Coplanar double gate electrode oxide thin film transistor and manufacture method thereof
CN104102059B (zh) Tft阵列基板及其制造方法
CN109300840B (zh) 显示基板及其制造方法、显示装置
US11114474B2 (en) Thin film transistor, manufacturing method thereof, array substrate, and display panel
WO2016041304A1 (zh) 薄膜晶体管及制备方法、阵列基板及制备方法、显示装置
CN102842601B (zh) 一种阵列基板及其制作方法
RU2634087C1 (ru) Тонкопленочный транзистор из низкотемпературного поликристаллического кремния и способ его изготовления
WO2016086531A1 (zh) 阵列基板及其制作方法
JPH02260661A (ja) アクティブマトリックス液晶表示素子用薄膜トランジスタ
US20160254298A1 (en) Array Substrate, Manufacturing Method Thereof, and Display Device
JP2019537282A (ja) アレイ基板とその製造方法及び表示装置
WO2020224095A1 (zh) 阵列基板及制备方法、显示装置
CN108447822A (zh) Ltps tft基板的制作方法
CN110148601A (zh) 一种阵列基板、其制作方法及显示装置
KR20190131582A (ko) Tft 기판의 제조 방법 및 tft 기판
WO2022088365A1 (zh) 显示面板及其制备方法
US20070218576A1 (en) Method for fabricating polysilicon liquid crystal display device
CN103681514B (zh) 阵列基板及其制作方法、显示装置
WO2021120378A1 (zh) 一种阵列基板及其制作方法
CN105097453A (zh) 低温多晶硅薄膜、薄膜晶体管及各自制备方法、显示装置
WO2013123786A1 (zh) 薄膜晶体管阵列基板及其制作方法
WO2021248676A1 (zh) 阵列基板及其制备方法
WO2015021720A1 (zh) 一种阵列基板及其制备方法及显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20939518

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20939518

Country of ref document: EP

Kind code of ref document: A1