WO2021243641A1 - An array and cmos architecture for 3d phase change memory with higher array efficiency - Google Patents

An array and cmos architecture for 3d phase change memory with higher array efficiency Download PDF

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Publication number
WO2021243641A1
WO2021243641A1 PCT/CN2020/094346 CN2020094346W WO2021243641A1 WO 2021243641 A1 WO2021243641 A1 WO 2021243641A1 CN 2020094346 W CN2020094346 W CN 2020094346W WO 2021243641 A1 WO2021243641 A1 WO 2021243641A1
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Prior art keywords
line decoders
edge
bit line
word line
cell array
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PCT/CN2020/094346
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English (en)
French (fr)
Inventor
Jun Liu
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Yangtze Advanced Memory Industrial Innovation Center Co., Ltd
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Priority to PCT/CN2020/094346 priority Critical patent/WO2021243641A1/en
Priority to CN202080001271.2A priority patent/CN111837188A/zh
Publication of WO2021243641A1 publication Critical patent/WO2021243641A1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0023—Address circuits or decoders
    • G11C13/0026—Bit-line or column circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5678—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using amorphous/crystalline phase transition storage elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0023—Address circuits or decoders
    • G11C13/0028—Word-line or row circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect

Definitions

  • the present disclosure generally relates to three-dimensional electronic memories, and more particularly, to increasing the density of memory cells in three-dimensional phase change memories.
  • Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithm, and fabrication process.
  • feature sizes of the memory cells approach a lower limit
  • planar process and fabrication techniques become challenging and costly.
  • memory density for planar memory cells approaches an upper limit.
  • a three-dimensional (3D) memory architecture can address the density limitation in planar memory cells.
  • each set of bit line decoders extend from a third edge of the bottom cell array and from a fourth edge of the bottom cell array, the third edge being opposite the fourth edge, wherein each set of bit line decoders include a first portion of bit line decoders and a second portion of bit line decoders, and wherein for each set of bit line decoders the first portion of bit line decoders is shifted relative to the second portion of bit line decoders along a direction parallel, or substantially parallel, to the third edge and fourth edge.
  • the three-dimensional memory includes additional memory cells in a region above or below a two-dimensional region defined by the word line decoders
  • each set of bit line decoders extend from an edge of the top cell array that is parallel to a third edge of the bottom cell array and from a fourth edge of the bottom cell array, the third edge being opposite the fourth edge, wherein each set of bit line decoders include a first portion of bit line decoders and a second portion of bit line decoders, and wherein for each set of bit line decoders the first portion of bit line decoders is shifted relative to the second portion of bit line decoders along a direction parallel, or substantially parallel, to the third edge and fourth edge.
  • top cell bit line decoders and the bottom cell bit line decoders are configured for sharing with a second three-dimensional memory.
  • the three-dimensional memory includes additional memory cells in a region above or below a two-dimensional region defined by the word line decoders.
  • a method of forming a three-dimensional memory includes providing a top cell array of memory cells, a bottom cell array of memory cells, a plurality of word lines coupled to the top cell array and coupled to the bottom cell array, and a set of word line decoders coupled to the word lines by a plurality of word line contacts, and operable to selectively activate the word lines; and forming the plurality of word line decoders to extend from a first edge of the bottom cell array and from a second edge of the bottom cell array, the second edge being opposite the first edge, wherein the word line decoders include at least a first portion of word line decoders and a second portion of word line decoders, and wherein the first portion of the word line decoders is shifted relative to the second portion of word line decoders along a direction parallel, or substantially parallel, to the first edge and second edge.
  • the method includes providing two sets of bit line decoders extending from a first edge of the top cell array that is parallel to a third edge of the bottom cell array and from a fourth edge of the bottom cell array, the third edge being opposite the fourth edge, wherein each set of bit line decoders includes a first portion of bit line decoders and a second portion of bit line decoders, and wherein for each set of bit line decoders the first portion of bit line decoders is shifted relative to the second portion of bit line decoders along a direction parallel, or substantially parallel, to the third edge and fourth edge.
  • the method includes providing additional memory cells in a region above or below a two-dimensional region defined by the word line decoders.
  • forming the plurality of word line decoders further includes forming a third portion of word line decoders and a fourth portion of word line decoders, wherein the first, second, third, and fourth portions are sequentially positioned along a direction parallel, or substantially parallel, to the third and fourth edge, and wherein sequentially adjacent portions of the word line decoders are shifted relative to one another along a direction parallel, or substantially parallel, to the first edge and second edge.
  • the method includes providing two sets of bit line decoders extending from an edge of the top cell array that is parallel to a third edge of the bottom cell array and from a fourth edge of the bottom cell array, the third edge being opposite the fourth edge, wherein each set of bit line decoders include a first portion of bit line decoders and a second portion of bit line decoders, and wherein for each set of bit line decoders the first portion of bit line decoders is shifted relative to the second portion of bit line decoders along a direction parallel, or substantially parallel, to the third edge and fourth edge
  • the two sets of bit line decoders are configured for sharing with a second three-dimensional memory.
  • the method includes providing additional memory cells in a region above or below a two-dimensional region defined by the word line decoders.
  • Fig. 1 is an isometric view of a section of three-dimensional phase change memory.
  • Fig. 2 is a plan view of a section of a prior three-dimensional phase change memory.
  • Figs. 3A and 3B are plan views of a section of prior three-dimensional phase change memory.
  • Figs. 4A and 4B are plan views of a section of prior three-dimensional phase change memory.
  • Figs. 5A and 5B are plan views of a section of three-dimensional phase change memory according to an embodiment.
  • Figs. 6A and 6B are plan views of a section of three-dimensional phase change memory in accordance with the embodiment of Figs. 5A and 5B.
  • Figs. 7A and 7B are plan views of a section of prior three-dimensional phase change memory.
  • Fig. 8 is a plan view of a section of a section of three-dimensional phase change memory according to another embodiment.
  • Figs. 9A and 9B are plan views of a section of a prior three-dimensional phase change memory.
  • Fig. 10 is a plan view of a section of three-dimensional phase change memory according to still another embodiment.
  • Fig. 1 is an isometric view of a section of three-dimensional phase change memory.
  • the memory includes a first layer of memory cells 5 and a second layer of memory cells 10. Between the first layer of memory cells 5 and second layer of memory cells is a number of word lines 15 extending in the X direction. Above the first layer of memory cells 5 is a number of first bit lines 20 extending along the Y direction, and below the second layer of memory cells is a number of second bit lines 25 extending along the Y direction.
  • bit lines -memory cells -word lines -memory cells may be repeated along the Z direction to realize a stacked configuration.
  • an individual memory cell may be accessed by selectively activating the word line and bit line corresponding to the cell.
  • the memory includes word line decoders and bit line decoders.
  • the word line decoders are coupled to the word lines by word line contacts and are used to decode word line addresses such that a particular word line is activated when it is addressed.
  • the bit line decoders are coupled to the bit lines by bit line contacts and are used to decode bit line addresses such that a particular bit line is activated when it is addressed. The positioning of the word line decoders and contacts, and the positioning of the bit line decoders and contacts, are discussed further in connection with Fig. 2.
  • FIG. 2 is a plan view of section of three-dimensional phase change memory of a prior configuration.
  • the figure depicts the section as viewed along the Z (depth) direction.
  • the section includes a number of word lines, e.g. word lines 30, extending in the X (horizontal) direction, a number of top cell bit lines, e.g., bit lines 35, extending along the Y (vertical) direction and corresponding to a top cell array of memory cells (not shown) , and a number of bottom cell bit lines, e.g., bit lines 40, extending along the vertical direction and corresponding to a bottom cell array of memory cells (not shown) .
  • the word lines, top cell bit lines, and bottom cell bit lines are typically formed according to a 20 nm /20 nm Line /Space (L/S) pattern and are formed on a silicon substrate.
  • the memory may employ complementary metal-oxide semiconductor (CMOS) technology.
  • CMOS complementary metal-oxide semiconductor
  • the memory section of Fig. 2 also includes a word line contact area 45, a top cell bit line contact area 50, and a bottom cell bit line contact area 55.
  • the word line contact area 45 is elongated along the vertical direction, while the top cell bit line contact area 50 and bottom cell contact area 55 are elongated along the horizontal direction.
  • the word line contact area 45 includes a multiple of word line contacts, e.g., contact 45a, shown as dots enclosed by the word line contact area 45.
  • the top cell bit line contact area 50 includes a multiple of top cell bit line contacts, e.g., contact 50a, shown as dots enclosed by top cell bit line contact area 50.
  • the bottom cell bit line contact area 55 includes a multiple of bottom cell bit line contacts, e.g., contact 55a, shown as dots enclosed by bottom cell bit line contact area 55.
  • the word line contact area 45 includes a multiple of word line decoders (not shown) .
  • the word line decoders generally conform to the word line contact area and generally extend along the vertical direction.
  • the word line decoders couple to the word lines at the word line contacts.
  • the top cell bit line contact area 50 includes a multiple of top cell bit line decoders (not shown) .
  • the top cell bit line decoders generally conform to the top cell bit line contact area 50 and generally extend along the horizontal direction.
  • the top cell bit line decoders couple to the top cell bit lines at the top cell bit line contacts.
  • the bottom cell bit line contact area 55 includes a multiple of bottom cell bit line decoders (not shown) .
  • the bottom cell bit line decoders generally conform to the bottom cell bit line contact area 55 and generally extend along the horizontal direction.
  • the bottom cell bit line decoders couple to the bottom cell bit lines at the bottom cell bit line contacts.
  • Fig. 3A is a plan view of a section of a prior three-dimensional phase change memory. The figure depicts the section as viewed along the depth direction. The figure shows a multiple of bottom cell array architectures (or “bottom cell arrays” ) , including bottom cell array 60, and a multiple of top cell array architectures (or “top cell arrays” ) , including top cell array 65.
  • Fig. 3B is the same plan view as Fig 3A with the exception that the markings denoting the bottom cell array 60 and the top cell array 65 have been removed. For purposes of clarity of presentation Figs.
  • the memory section includes a set of word line decoders 70 that is arranged in a contiguous vertical stripe of area extending from a first edge 75 (or “top edge” ) , of the bottom cell array to a second edge 80 (or “bottom edge” ) , of the bottom cell array.
  • the memory section also includes a set of top cell bit line decoders 85 that is split into two portions 85a and 85b which are vertically aligned, and a set of bottom cell bit line decoders 90 that is split into two portions 90a and 90b which are vertically aligned.
  • the prior configuration dedicates a vertical stripe of the memory to word line contacts and word line decoders. Since the vertical stripe of the prior configuration does not include any bit lines or memory cells for data storage, the vertical stripe limits the density and efficiency of prior memory.
  • FIGs. 4A-5B are plan views of a section of prior three-dimensional phase change memory.
  • Figs. 5A and 5B are plan views of a section of three-dimensional phase change memory according to an embodiment.
  • Fig. 4A shows a bottom cell array architecture of a prior memory. The architecture is similar to that shown in connection with the bottom cell array 60 of Figs. 3A and 3B.
  • Fig. 4A shows bottom cell bit lines 100 that are coupled to bottom cell bit line decoders 90.
  • the bottom cell array architecture 60 includes a vertical stripe of memory area dedicated to the word line decoders 70, and therefore none of the bottom cell bit lines 100 pass through or the overlap the word line decoders 70.
  • Fig. 4B shows how the bottom cell array 60 is overlapped by the top cell array 65, as similarly shown in Figs. 3A and 3B.
  • Fig. 5A shows a bottom cell array architecture 105 according to an embodiment.
  • the architecture includes a bottom cell array of memory cells (not shown) .
  • the bottom cell array is denoted by dashed lines and has a first edge 105a and a second edge 105b that are vertically opposite one another, and a third edge 105c and a fourth edge 105d that are horizontally opposite one another.
  • the bottom cell array architecture 105 includes a multiple of word line decoders 110 coupled to a multiple of word lines (not shown) by a multiple of word line contacts (not shown) , the word line decoders 110 being operable to selectively activate the word lines.
  • the word line decoders 110 extend from the first edge 105a of the bottom cell array and from the second edge 105b of the bottom cell array, and include a first portion of word line decoders 110a and a second portion of word line decoders 110b. The first portion of word line decoders 110a is shifted relative to the second portion of word line decoders 110b along a direction parallel, or substantially parallel, to the first edge 105a and the second edge 105b.
  • the bottom cell array architecture 105 also includes a set of bottom cell bit line decoders 115, which are coupled to a multiple of bottom cell bit lines 113 by a multiple of bottom cell bit line contacts (not shown) .
  • the bottom cell bit line decoders 115 are operable to selectively activate the bottom cell bit lines 113.
  • the bottom cell bit line decoders 115 extend from the third edge 105c of the bottom cell array and from the fourth edge 105d of the bottom cell array, and include a first portion of bottom cell bit line decoders 115a and a second portion of bottom cell bit line decoders 115b.
  • the first portion of bottom cell bit line decoders 115a is shifted relative to the second portion of bottom cell bit line decoders 115b along a direction parallel, or substantially parallel, to the third edge 105c and the fourth edge 105d.
  • arranging the word line decoders in two portions, and shifting the two portions relative to one another allows for shifting of bit line decoder portions.
  • bit lines and memory cells are introduced into the regions of the word line decoders and thus reducing the total silicon area required for a given number of bits as compared with the prior configurations. That is, the present technology does not require an area dedicated to word line decoders, and thus allows for an architecture having a higher memory density and greater efficiency relative to prior architectures.
  • additional memory cells are included in the area provided for the first portion of word line decoders 110a and in the area provided for the second portion of word line decoders 110b.
  • the additional memory cells are included in areas provided for the word line decoders by arranging the additional cells in a region above or below, with respect to the depth direction, the two-dimensional regions defined by the word line decoder portions 110a and 110b.
  • bit lines of the bottom cell bit lines 113 are introduced into the area provided for the first portion of word line decoders 110a and in the area provided for the second portion of word line decoders 110b.
  • the bottom cell bit lines are introduced into the areas provided for the word line decoders by arranging the bottom cell bit lines in a region above or below, with respect to the depth direction, the two-dimensional regions defined by the word line decoder portions 110a and 110b.
  • no memory cells are included in word line decoder portions 110a and 110b, and bottom cell bit lines are introduced into both portions 110a and 110b; memory cells are included in one of portions 110a and 110b, and bottom cell bit lines are introduced into both portions 110a and 110b; memory cells are included in both portions 110a and 110b, and bottom cell bit lines are introduced into one of portions 110a and 110b; memory cells are included in both of portions 110a and 110b, and no bottom cell bit lines are introduced into portions 110a and 110b, and no memory cells are included word line decoder portions 110a and 110b, and no bottom cell bit lines are introduced into portions 110a and 110b.
  • Fig. 5B shows how the bottom cell array architecture 105 of Fig. 5A may be overlapped by a top cell array architecture 120.
  • the embodiment of Fig. 5B includes all of the features of the embodiment of Fig. 5A.
  • the embodiment of Fig. 5B includes a set of top cell bit line decoders 125, a set of the top cell bit lines (not shown) being coupled to the top cell bit line decoders 125 by a multiple of top cell bit line contacts (not shown) .
  • the top cell bit line decoders 125 are operable to selectively activate the top cell bit lines.
  • the set of top cell bit line decoders 125 extend from the third edge 105c of the bottom cell array 105 to an edge 123 of the top cell array 120 which is parallel to the fourth edge 105d of the bottom cell array.
  • the set of top cell bit line decoders includes a first portion of top cell bit line decoders 125a and a second portion of top cell bit line decoders 125b.
  • the first portion of top cell bit line decoders 125a is shifted relative to the second portion of top cell bit line decoders 125b along a direction parallel, or substantially parallel, to the third edge 105c and the fourth edge 105d of the bottom cell array 105.
  • Figs. 6A and 6B are plan views of a section of three-dimensional phase change memory according to the embodiment of Figs. 5A and 5B.
  • the section shown in Figs. 6A and 6B is formed of a multiple of the sections shown in Fig. 5B.
  • a first bottom cell array 130 is overlapped by a top cell array 145.
  • the top cell array 145 also overlaps a second bottom cell array 135, which is also overlapped by a second top cell array 150.
  • the second top cell array 150 overlaps a third bottom cell array 140.
  • Fig. 6B shows the same section as Fig. 6A, with the top cell array markings removed for clarity.
  • the section of Figs. 6A and 6B includes all of the features of the section of Fig. 5B and shows an embodiment in which a section of memory is constructed using a multiple of the sections of Fig. 5B.
  • Figs. 7A and 7B are plan views of a section of prior three-dimensional phase change memory. The section is the same as the section shown in Figs. 4A and 4B. Figs. 7A and 7B are provided for purposes of juxtaposing with Fig. 8.
  • Fig. 8 is a plan view of a section of three-dimensional phase change memory according to another embodiment.
  • the figure shows a bottom cell array 155 overlapped by a top cell array 160.
  • the bottom cell array 155 has a first edge 155a and a second edge 155b that are vertically opposite one another, and a third edge 155c and a fourth edge 155d that are horizontally opposite one another.
  • the bottom cell array architecture 155 includes word line decoders 160 coupled to a multiple of word lines (not shown) by a multiple of word line contacts (not shown) , the word line decoders 160 being operable to selectively activate the word lines.
  • the word line decoders 160 extend from the first edge 155a of the bottom cell array 155 and from the second edge 155b of the bottom cell array 155, and include a first portion of word line decoders 160a, a second portion of word line decoders 160b, a third portion of word line decoders 160c, and a fourth portion of word line decoders 160d.
  • the first portion 160a, second portion 160b, third portion 160c, and fourth portion 160d are sequentially positioned along a direction parallel or substantially parallel to the third edge 155c and fourth edge 155d.
  • sequentially adjacent portions of the word line decoders 160 are shifted relative to one another along a direction parallel, or substantially parallel, to the first edge 155a and the second edge 155b.
  • first portion 160a and second portion 160b are shifted relative to one another along a direction parallel, or substantially parallel, to the first edge 155a and the second edge 155b.
  • the bottom cell array architecture 155 also includes a set of bottom cell bit lines (not shown) and a set of bottom cell bit line decoders 165, the bottom cell bit lines being coupled to the bottom cell bit line decoders 165 by a multiple of bottom cell bit line contacts (not shown) , and the bottom cell bit line decoders 165 being operable to selectively activate the bottom cell bit lines.
  • the bottom cell bit line decoders 165 include a first portion of bottom cell bit line decoders 165a and a second portion of bottom cell bit line decoders 165b.
  • the first portion of bottom cell bit line decoders 165a is shifted relative to the second portion of bottom cell bit line decoders 165b along a direction parallel, or substantially parallel, to the third edge 155c and the fourth edge 155d of the bottom cell array 155.
  • the architecture of Fig. 8 allows for memory cells to be included in the areas provided for the word line decoders. Moreover, the architecture of Fig. 8 allows for bit lines to be introduced in to the areas provided for the word line decoders. That is, the architecture of Fig. 8 does not require an area dedicated to word line decoders, and thus allows for an architecture having a higher memory density and greater efficiency relative to prior architectures.
  • memory cells may be selectively included in none, or one or more of the areas provided for the first portion 160a, second portion 160b, third portion 160c, and fourth portion 160d of the word line decoders. Further, when memory cells are included in a portion, the cells may be arranged in a region above or below, with respect to the depth direction, the two-dimensional region defined by the portion.
  • the bottom cell bit lines may be selectively introduced into none, or one or more of the areas provided for the first portion 160a, second portion 160b, third portion 160c, and fourth portion 160d of the word line decoders. Further, when bottom cell bit lines are introduced into a portion, the lines may be introduced into a region above or below, with respect to the depth direction, the two-dimensional region defined by the portion.
  • the embodiment of Fig. 8 includes a set of top cell bit line decoders 170, a set of the top cell bit lines (not shown) being coupled to the top cell bit line decoders 170 by a multiple of top cell bit line contacts (not shown) , and the set of top cell bit line decoders 170 being operable to selectively activate the top cell bit lines.
  • the set of top cell bit line decoders 170 extend from an edge of the top cell array 173, that is parallel to the third edge 155c of the bottom cell array, to the fourth edge 155d of the bottom cell array155, and include a first portion of top cell bit line decoders 170a and a second portion of top cell bit line decoders 170b.
  • top cell bit line decoders 170a is shifted relative to the second portion of top cell bit line decoders 170b along a direction parallel, or substantially parallel, to the third edge 155c and the fourth edge 155d of the bottom cell array 155.
  • Figs. 9A and 9B are plan views of a section of prior three-dimensional phase change memory. The section is the same as the section shown in Figs. 4A and 4B. Figs. 9A and 9B are provided for purposes of juxtaposing with Fig. 10
  • Fig. 10 is a plan view of a section of three-dimensional phase change memory according to still another embodiment.
  • the elements of the Fig. 10 embodiment are the same as the elements of the Fig. 8 embodiment with the exception that the Fig. 10 embodiment includes a set of bottom cell bit line decoders 175 having a first portion 175a and a second portion 175b in place of bottom cell bit line decoders 165 and portions 165a and 165b, and includes a set of top cell bit line decoders 180 having a first portion 180a and a second portion 180b in place of top cell bit line decoders 170 and portions 170a and 170b.
  • the bottom cell bit line decoders 175 are configured for sharing with adjacent memory sections. That is, in Fig.
  • bottom cell array architecture 155 is divided into two equal memory sections with individual bit lines having a length which is half that of the Fig. 8 embodiment.
  • the bottom cell bit line decoders in portion 175a may be shared between two memory sections placed adjacent to each other.
  • the top cell bit line decoders 180 are configured for sharing with adjacent memory sections.
  • the top cell bit line decoders in portion 180b may be shared between two memory sections placed adjacent to each other.

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PCT/CN2020/094346 2020-06-04 2020-06-04 An array and cmos architecture for 3d phase change memory with higher array efficiency WO2021243641A1 (en)

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CN202080001271.2A CN111837188A (zh) 2020-06-04 2020-06-04 用于具有更高阵列效率的3d相变存储器的阵列和cmos架构

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CN113299682B (zh) * 2021-04-14 2023-07-04 长江先进存储产业创新中心有限责任公司 三维存储器
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