WO2022032512A1 - Novel array and contact architecture for 4 stack 3d crosspoint memory - Google Patents

Novel array and contact architecture for 4 stack 3d crosspoint memory Download PDF

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Publication number
WO2022032512A1
WO2022032512A1 PCT/CN2020/108615 CN2020108615W WO2022032512A1 WO 2022032512 A1 WO2022032512 A1 WO 2022032512A1 CN 2020108615 W CN2020108615 W CN 2020108615W WO 2022032512 A1 WO2022032512 A1 WO 2022032512A1
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Prior art keywords
memory cells
cell array
bottom cell
block
memory
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PCT/CN2020/108615
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French (fr)
Inventor
Jun Liu
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Yangtze Advanced Memory Industrial Innovation Center Co., Ltd
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Priority to PCT/CN2020/108615 priority Critical patent/WO2022032512A1/en
Priority to CN202080002045.6A priority patent/CN112106137B/en
Publication of WO2022032512A1 publication Critical patent/WO2022032512A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out

Definitions

  • the present disclosure generally relates to three-dimensional electronic memories, and more particularly, to increasing the density of memory cells in three-dimensional crosspoint memories.
  • Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithm, and fabrication process.
  • feature sizes of the memory cells approach a lower limit
  • planar process and fabrication techniques become challenging and costly.
  • memory density for planar memory cells approaches an upper limit.
  • a three-dimensional (3D) memory architecture can address the density limitation in planar memory cells.
  • a three-dimensional memory includes a top cell array of memory cells; an upper-middle cell array of memory cells; a lower-middle cell array of memory cells; a bottom cell array of memory cells; a multiple of top cell bit lines coupled to the top cell array of memory cells; a multiple of top cell bit line contacts coupled to the top cell bit lines; a multiple of upper word lines positioned between the top cell array of memory cells and the upper-middle cell array of memory cells, and coupled to the top cell array of memory cells and to the upper-middle cell array of memory cells; a multiple of middle bit lines positioned between the upper-middle cell array of memory cells and the lower-middle cell array of memory cells, and coupled to the upper-middle cell array of memory cells and to the lower-middle cell array of memory cells; a multiple of lower word lines positioned between the lower-middle cell array of memory cells and
  • the top cell bit line contacts are arranged in the middle of the bottom cell array of memory cells with respect to a dimension of the bottom cell array of memory cells.
  • the bottom cell array of memory cells is arranged in two blocks of bottom cell array memory cells, a first block of bottom cell array memory cells and a second block of bottom cell array memory cells, wherein the three-dimensional memory further includes a multiple of middle bit line contacts coupled to the middle bit lines, and wherein the middle bit line contacts are arranged between the first block of bottom cell array memory cells and the second block of bottom cell array memory cells.
  • the bottom cell array of memory cells is arranged in two blocks of bottom cell array memory cells, a first block of bottom cell array memory cells and a second block of bottom cell array memory cells, wherein the first block of bottom cell memory cells is arranged in two sub-blocks, a first sub-block of bottom cell array memory cells and a second sub-bock of bottom cell array memory cells, wherein the three-dimensional memory further includes a multiple of lower word line contacts coupled to the lower word lines, and wherein the lower word line contacts are arranged between the first sub-block of bottom cell array memory cells and the second sub-block of bottom cell array memory cells.
  • the lower word line contacts are arranged in the middle of first block of bottom cell array memory cells with respect to a dimension of the first block of bottom cell array memory cells.
  • the bottom cell array of memory cells is arranged in two blocks of bottom cell array memory cells, a first block of bottom cell array memory cells and a second block of bottom cell array memory cells, wherein the three-dimensional memory further includes a multiple of upper word line contacts coupled to the upper word lines, and wherein the upper word line contacts are arranged between the first block of bottom cell array memory cells and the second block of bottom cell array memory cells.
  • the upper-middle cell array of memory cells is shifted relative to the bottom cell array of memory cells along a direction parallel to, or substantially parallel to, the bottom cell array of memory cells
  • the lower-middle cell array of memory cells is shifted relative to the bottom cell array of memory cells along a direction parallel to, or substantially parallel to, the bottom cell array of memory cells.
  • the upper-middle cell array of memory cells is shifted by an amount equal to, or substantially equal to, one half an extent of a dimension of the first block of bottom cell array memory cells.
  • the upper-middle cell array of memory cells is shifted relative to the bottom cell array of memory cells along a direction parallel to, or substantially parallel to, the bottom cell array of memory cells
  • the lower-middle cell array of memory cells is shifted relative to the bottom cell array of memory cells along a direction parallel to, or substantially parallel to, the bottom cell array of memory cells.
  • the bottom cell array of memory cells is arranged in two blocks of bottom cell array memory cells, a first block of bottom cell array memory cells and a second block of bottom cell array memory cells, and the upper-middle cell array of memory cells is shifted by an amount equal to, or substantially equal to, one half an extent of a dimension of the first block of bottom cell array memory cells.
  • Fig. 1 is an isometric view of a section of three-dimensional crosspoint memory.
  • Fig. 2 is a plan view of a section of a prior three-dimensional crosspoint memory.
  • Fig. 3 is a plan view of a section of three-dimensional crosspoint memory according to an embodiment.
  • Figs. 4A and 4B are cross-sectional views of a section of three-dimensional crosspoint memory according to an embodiment.
  • Fig. 5 is a plan view of a section of three-dimensional crosspoint memory according to an embodiment.
  • Fig. 6 is an isometric view of a section of three-dimensional crosspoint memory according to an embodiment.
  • Fig. 1 is an isometric view of a section of three-dimensional crosspoint memory.
  • the memory includes a first layer (or “first array” ) of memory cells 5 and a second layer (or “second array” ) of memory cells 10. Between the first array of memory cells 5 and the second array of memory cells 10 is a number of word lines 15 extending in the X direction. Above the first array of memory cells 5 is a number of first bit lines 20 extending along the Y direction, and below the second array of memory cells 10 is a number of second bit lines 25 extending along the Y direction.
  • bit lines -memory cells -word lines -memory cells may be repeated along the Z direction to realize a stacked configuration.
  • an individual memory cell may be accessed by selectively activating the word line and bit line corresponding to the cell.
  • the memory includes word line decoders and bit line decoders.
  • the word line decoders are coupled to the word lines by word line contacts and are used to decode word line addresses such that a particular word line is activated when the line is addressed.
  • the bit line decoders are coupled to the bit lines by bit line contacts and are used to decode bit line addresses such that a particular bit line is activated when the line is addressed. The positioning of the word line decoders and contacts, and the positioning of the bit line decoders and contacts, are discussed further in connection with Fig. 2.
  • FIG. 2 is a plan view of section of three-dimensional crosspoint memory of a prior configuration.
  • the figure depicts the section as viewed along the Z (depth) direction.
  • the section includes a number of word lines, e.g. word lines 30, extending in the X (horizontal) direction, a number of top cell bit lines, e.g., bit lines 35, extending along the Y (vertical) direction and corresponding to a top cell array of memory cells (not shown) , and a number of bottom cell bit lines, e.g., bit lines 40, extending along the vertical direction and corresponding to a bottom cell array of memory cells (not shown) .
  • the word lines, top cell bit lines, and bottom cell bit lines are typically formed according to a 20 nm /20 nm Line /Space (L/S) pattern and are formed on a silicon substrate.
  • the memory may employ complementary metal-oxide semiconductor (CMOS) technology.
  • CMOS complementary metal-oxide semiconductor
  • the memory section of Fig. 2 also includes a word line contact area 45, a top cell bit line contact area 50, and a bottom cell bit line contact area 55.
  • the word line contact area 45 is elongated along the vertical direction, while the top cell bit line contact area 50 and bottom cell contact area 55 are elongated along the horizontal direction.
  • the word line contact area 45 includes a multiple of word line contacts, e.g., contact 45a, shown as dots enclosed by the word line contact area 45.
  • the top cell bit line contact area 50 includes a multiple of top cell bit line contacts, e.g., contact 50a, shown as dots enclosed by top cell bit line contact area 50.
  • the bottom cell bit line contact area 55 includes a multiple of bottom cell bit line contacts, e.g., contact 55a, shown as dots enclosed by bottom cell bit line contact area 55.
  • the word line contact area 45 includes a multiple of word line decoders (not shown) .
  • the word line decoders generally conform to the word line contact area and generally extend along the vertical direction.
  • the word line decoders couple to the word lines at the word line contacts.
  • the top cell bit line contact area 50 includes a multiple of top cell bit line decoders (not shown) .
  • the top cell bit line decoders generally conform to the top cell bit line contact area 50 and generally extend along the horizontal direction.
  • the top cell bit line decoders couple to the top cell bit lines at the top cell bit line contacts.
  • the bottom cell bit line contact area 55 includes a multiple of bottom cell bit line decoders (not shown) .
  • the bottom cell bit line decoders generally conform to the bottom cell bit line contact area 55 and generally extend along the horizontal direction.
  • the bottom cell bit line decoders couple to the bottom cell bit lines at the bottom cell bit line contacts.
  • the memory density of the prior configurations can be improved, and that new configurations can provide improved memory density.
  • One of the drawbacks of the prior configurations is related primarily to the arrangement of the memory cells into two two-dimensional arrays of memory cells.
  • the present technology provides a memory employing four two-dimensional arrays of memory cells, which are arranged in a four-stack configuration. Thereby, the present technology allows for crosspoint memories with increased memory density, and provides per-bit cost advantages relative to prior crosspoint memories.
  • Fig. 3 is a plan view of a section of three-dimensional crosspoint memory according to an embodiment of the present technology.
  • the figure depicts a multiple of array block architectures, including a multiple of top/bottom cell array block architectures, e.g., top/bottom cell array block architecture 60, and a multiple of middle cell array block architectures, e.g., middle cell array block architecture 65.
  • each of the top/bottom cell array block architectures is arranged in two sub-blocks, e.g., sub-block 60a and sub-block 60b.
  • the top/bottom cell array block architectures and middle cell array block architectures extend across X-Y areas of the same size, or approximately the same size, although in alternative embodiments the top/bottom cell array block architectures and middle cell array block architectures may extend across X-Y areas of different sizes.
  • the top/bottom cell array block architectures and middle cell array block architectures are generally rectangular in shape and have the same X and Y dimensions, although in alternative embodiments the top/bottom cell array block architectures and middle cell array block architectures may have different shapes or may have the same shape but with a different dimension or dimensions. Further, in Fig.
  • the top/bottom cell array block architectures are offset from the middle cell array block architectures by an amount equal to one half of the Y dimension for the top/bottom cell array block architectures and middle cell array block architectures. That is, the top/bottom cell array block architecture and middle cell array block architecture are shifted relative to one another along a direction parallel or substantially parallel to the X-Y plane by an amount equal to one half of the Y dimension, indicated as “w” in Fig. 3.
  • the top/bottom cell array block architectures of Fig. 3 each include a multiple of top cell bit lines, e.g., top cell bit lines 70, a multiple of upper word lines, e.g., upper word lines 75, a multiple of lower word lines, e.g., lower word lines 80, and a multiple of bottom cell bit lines, e.g., bottom cell bit lines 85.
  • top cell bit lines e.g., top cell bit lines 70
  • upper word lines e.g., upper word lines 75
  • lower word lines e.g., lower word lines 80
  • bottom cell bit lines 85 e.g., bottom cell bit lines 85.
  • the lower word lines are coupled to a multiple of lower word line contacts, e.g., contact 90a, shown as dots enclosed by a lower word line contact area 90; the lower cell bit lines are coupled to a multiple of lower cell bit line contacts, e.g., contact 93a, shown as dots enclosed by an lower cell bit line contact area 93; and the upper word lines are coupled to a multiple of upper word line contacts, e.g., contact 95a, shown as dots enclosed by an upper word line contact area 95.
  • the upper word line contact area 95 is positioned between two top/bottom cell array block architectures.
  • the middle cell array block architectures of Fig. 3 each include a multiple of middle bit lines, e.g., middle bit lines 100.
  • the middle bit lines are coupled to a multiple of middle bit line contacts, e.g., contact 105a, shown as dots enclosed by a middle bit line contact area 105.
  • FIG. 3 is provided to illustrate a framework of a section of memory according to the present technology by depicting only selected elements of the section. A detailed description of a section of memory according to the present technology is provided in view of all the figures.
  • Fig. 4A is a cross-sectional view of a section of three-dimensional crosspoint memory according to an embodiment.
  • the cross-section depicts only bit lines and word lines and generally corresponds to the framework of Fig. 3, although the numbers of bit lines and word lines shown in Fig. 4A differ from the numbers of bit lines and word lines shown in Fig. 3.
  • the cross-section is best understood when considered in the context of a cross-section of the Fig. 3 embodiment as taken along the Y-Z plane, with the portion of Fig. 4A most closely corresponding to Fig. 3 indicated by box 110, and the portion of Fig. 4A most closely corresponding to top/bottom cell array block architecture 60 indicated by box 115.
  • the section includes a multiple of top cell bit lines 120, e.g., to cell bit line 120a, a multiple of upper word lines 125, a multiple of middle bit lines 130, a multiple of lower word lines 135, and a multiple of bottom cell bit lines 140, e.g., bottom cell bit line 140a.
  • a multiple of top cell bit line contacts e.g., top cell bit line contact 145
  • a multiple of middle bit line contacts e.g., middle bit line contact 150
  • bottom cell bit line contacts e.g., bottom cell bit line contact 155.
  • the top cell bit lines are coupled to respective bottom cell bit lines by the top cell bit line contacts.
  • top cell bit line 120a is coupled to bottom cell bit line 140a by top cell bit line contact 145.
  • the middle bit line contacts are arranged between the bottom cell bit lines.
  • Fig. 4B is a cross-sectional view of a section of three-dimensional crosspoint memory according to an embodiment.
  • the cross-section depicts only bit lines and word lines and generally corresponds to the framework of Fig. 3, although the numbers of bit lines and word lines shown in Fig. 4B differ from the numbers of bit lines and word lines shown in Fig. 3.
  • the cross-section is best understood when considered in the context of a cross-section of the Fig. 3 embodiment as taken along the X-Z plane, with the portion of Fig. 4B most closely corresponding to top/bottom cell array block architecture 60 indicated by box 160.
  • the section includes a multiple of top cell bit lines, e.g., to cell bit line 120, a multiple of upper word lines 125, e.g. upper word line 127, a multiple of middle bit lines 130, a multiple of lower word lines 135, e.g., lower word line 137, a multiple of bottom cell bit lines 140, and a multiple of bottom cell bit line contacts, e.g., bottom cell bit line contact 142.
  • a multiple of top cell bit lines e.g., to cell bit line 120
  • a multiple of upper word lines 125 e.g. upper word line 127
  • a multiple of middle bit lines 130 e.g., a multiple of lower word lines 135, e.g., lower word line 137, a multiple of bottom cell bit lines 140
  • bottom cell bit line contacts e.g., bottom cell bit line contact 142.
  • an upper word line contact 165 and a multiple of bottom word line contacts, e.g., bottom word line contact 170.
  • Fig. 5 is a plan view of a section of three-dimensional crosspoint memory according to an embodiment.
  • Fig. 5 is best understood in the context of Fig. 3. The correspondence between the two figures is evident from the like-numbered elements.
  • Fig. 5 depicts the arrangement of the decoders as the section is viewed along the Z direction.
  • Four types of decoders are provided, upper word line decoders, middle bit line decoders, lower word line decoders, and bottom cell bit line decoders. Each type of decoder is associated with a corresponding bit line type or word line type, and with corresponding contacts for the bit line type or word line type.
  • the decoders for the lines a coupled to the lines by the contacts for the lines, and the decoders are located in an area coincident with the area for the contacts.
  • the bottom cell bit lines 140 are coupled to bottom cell bit line decoders that are located in bottom cell bit line contact area 93;
  • the lower word lines 135 are coupled to lower word line decoders that are located in lower word line contact area 90;
  • the middle bit lines 130 are coupled to middle bit line decoders that are located in middle bit line contact area 105;
  • the upper word lines 125 are coupled to upper word line decoders that are located in upper word line contact area 95.
  • Each group of decoders is used to decode addresses for its corresponding group of lines such that a particular line from the group is activated when the line is addressed. By activating lines associated with a memory cell the cell may be accessed for reading and writing. The relationship between the bit lines, word lines, and memory cells is discussed in more detail with reference to Fig. 6.
  • Fig. 6 is an isometric view of a section of three-dimensional crosspoint memory according to an embodiment.
  • the section of three-dimensional memory includes a top cell array of memory cells 200, an upper-middle cell array of memory cells 205, a lower-middle cell array of memory cells 210, and a bottom cell array of memory cells 215.
  • Each of the arrays of memory cells may be arranged in two blocks, illustrated for example by block indicators 220 and 225. Further, each of the blocks may be arranged in two sub-blocks, illustrated for example by sub-block indicators 225a and 225b.
  • the bottom cell array of memory cells 215 may be arranged into a first block of bottom cell array memory cells 215a and a second block of bottom cell array memory cells 215b.
  • the first block of bottom cell array memory cells 215a may be arranged into a first sub-block of bottom cell array memory cells 215aa and second sub-block of bottom cell array memory cells 215ab.
  • each of the arrays of memory cells may be arranged in blocks that are positioned adjacent to one another along the Y direction.
  • the bottom cell array of memory cells 215 may include the first block of bottom cell array memory cells 215a and a second block of bottom cell array memory cells (not shown) that is adjacent to block 215a along the Y direction.
  • top cell bit lines e.g., top cell bit line 230
  • top cell bit line contacts e.g., top cell bit line contact 235
  • upper word lines e.g., upper word lines 240
  • a multiple of middle bit lines e.g., middle bit lines 245, are positioned between the upper-middle cell array of memory cells 205 and the lower-middle cell array of memory cells 210, and are coupled to the upper-middle cell array of memory cells 205 and to the lower-middle cell array of memory cells 210.
  • a multiple of lower word lines e.g., lower word lines 250, are positioned between the lower-middle cell array of memory cells 210 and the bottom cell array of memory cells 215, and are coupled to the lower-middle cell array of memory cells 210 and to the bottom cell array of memory cells 215.
  • a multiple of bottom cell bit lines e.g., bottom cell bit lines 255, are coupled to the bottom cell array of memory cells 215.
  • the pitch of the top cell bit line contacts is the same as the pitch of the bottom cell bit lines, and the top cell bit lines are respectively coupled to the bottom cell bit lines by the top cell bit line contacts.
  • the top cell bit line contacts may be arranged in the middle of the first block of bottom cell array memory cells 215 with respect to the Y dimension of the first block of bottom cell array memory cells 215a and the second block of bottom cell array memory cells 215b.
  • the bottom cell array of memory cells 215 may include the first block of bottom cell memory cells 215a and a second block of bottom cell array of memory cells (not shown) that is adjacent to block 215a along the Y direction.
  • the middle bit lines may be coupled to a multiple of middle bit line contacts (not shown) and the middle bit line contacts may be arranged between the first block of bottom cell array memory cells 215a and the second block of bottom cell array memory cells (not shown) .
  • a multiple of lower word line contacts may be coupled to the lower word lines, and the lower word line contacts may be arranged between the first sub-block of bottom cell array memory cells 215aa and the second sub-block of bottom cell array memory cells 215ab. Further, the lower word line contacts may be arranged in the middle of first block of bottom cell array memory cells 215a with respect to the X dimension of the first block of bottom cell array memory cells 215a.
  • a multiple of upper word line contacts e.g., upper word line contact 265, are coupled to the upper word lines, and the upper word line contacts are arranged between the first block of bottom cell array memory cells 215a and the second block of bottom cell array memory cells 215b.
  • the upper-middle cell array of memory cells 205 may be shifted relative to the bottom cell array of memory cells 215 along a direction parallel to, or substantially parallel to, the bottom cell array of memory cells 215, and the lower-middle cell array of memory cells 210 may be shifted relative to the bottom cell array of memory cells 215 along a direction parallel to, or substantially parallel to, the bottom cell array of memory cells 215.
  • the upper-middle cell array of memory cells 205 may be shifted relative to the bottom cell array of memory cells 215 along a direction parallel to, or substantially parallel to, the X-Y plane
  • the lower-middle cell array of memory cells 210 may be shifted relative to the bottom cell array of memory cells 215 along a direction parallel to, or substantially parallel to, the X-Y plane.
  • the upper-middle cell array of memory cells 205 may be shifted relative to the bottom cell array of memory cells 215 along a direction parallel to, or substantially parallel to, the bottom cell array of memory cells 215 by an amount equal to, or substantially equal to, one half an extent of a dimension (e.g., the Y dimension) of the first block of bottom cell array memory cells 215a.
  • the lower-middle cell array of memory cells 210 may be shifted relative to the bottom cell array of memory cells 215 along a direction parallel to, or substantially parallel to, the bottom cell array of memory cells 215 by an amount equal to, or substantially equal to, one half an extent of a dimension (e.g., the Y dimension) of the first block of bottom cell array memory cells 215a.

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Abstract

A three-dimensional memory including a top cell array of memory cells, an an upper-middle cell array of memory cells, a lower-middle cell array of memory cells, and a bottom cell array of memory cells. The memory has a multiple of top cell bit lines coupled to the top array and a multiple of bottom cell bit lines coupled to the bottom array. The top cell bit lines include a multiple of top cell bit line contacts, a pitch of the top cell bit line contacts is the same as a pitch of the bottom cell bit lines, and the top cell bit lines are respectively coupled to the bottom cell bit lines by the top cell bit line contacts.

Description

[Title established by the ISA under Rule 37.2] NOVEL ARRAY AND CONTACT ARCHITECTURE FOR 4 STACK 3D CROSSPOINT MEMORY TECHNICAL FIELD
The present disclosure generally relates to three-dimensional electronic memories, and more particularly, to increasing the density of memory cells in three-dimensional crosspoint memories.
BACKGROUND
Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithm, and fabrication process. However, as feature sizes of the memory cells approach a lower limit, planar process and fabrication techniques become challenging and costly. As such, memory density for planar memory cells approaches an upper limit. A three-dimensional (3D) memory architecture can address the density limitation in planar memory cells.
SUMMARY
The presently disclosed technology solves the problems of current state of the art memories, and provides other benefits. In accordance with an aspect of the technology, a three-dimensional memory includes a top cell array of memory cells; an upper-middle cell array of memory cells; a lower-middle cell array of memory cells; a bottom cell array of memory cells; a multiple of top cell bit lines coupled to the top cell array of memory cells; a multiple of top cell bit line contacts coupled to the top cell bit lines; a multiple of upper word lines positioned between the top cell array of memory cells and the upper-middle cell array of memory cells, and coupled to the top cell array of memory cells and to the upper-middle cell array of memory cells; a multiple of middle bit lines positioned between the upper-middle cell array of memory cells and the lower-middle cell array of memory cells, and coupled to the upper-middle cell array of memory cells and to the lower-middle cell array of memory cells; a multiple of lower word lines positioned between the lower-middle cell array of memory cells and the bottom cell array of memory cells, and coupled to the lower-middle cell array of memory cells and to the bottom cell array of memory cells; and a multiple of bottom cell bit lines coupled to the bottom cell array of memory cells, wherein the pitch of the top cell bit line contacts is the same as the pitch of the bottom cell bit lines, and the top cell bit lines are respectively coupled to the bottom cell bit lines by the top cell bit line contacts.
In some arrangements the top cell bit line contacts are arranged in the middle of the bottom cell array of memory cells with respect to a dimension of the bottom cell array of memory cells.
In some arrangements the bottom cell array of memory cells is arranged in two blocks of bottom cell array memory cells, a first block of bottom cell array memory cells and a second block of bottom cell array memory cells, wherein the three-dimensional memory further includes a multiple of middle bit line contacts coupled to the middle bit lines, and wherein the middle bit line contacts are arranged between the first block of bottom cell array memory cells and the second block of bottom cell array memory cells.
In some arrangements the bottom cell array of memory cells is arranged in two blocks of bottom cell array memory cells, a first block of bottom cell array memory cells and a second block of bottom cell array memory cells, wherein the first block of bottom cell memory cells is arranged in two sub-blocks, a first sub-block of bottom cell array memory cells and a second sub-bock of bottom cell array memory cells, wherein the three-dimensional memory further includes a multiple of lower word line contacts coupled to the lower word lines, and wherein the lower word line contacts are arranged between the first sub-block of bottom cell array memory cells and the second sub-block of bottom cell array memory cells.
In some arrangements the lower word line contacts are arranged in the middle of first block of bottom cell array memory cells with respect to a dimension of the first block of bottom cell array memory cells.
In some arrangements the bottom cell array of memory cells is arranged in two blocks of bottom cell array memory cells, a first block of bottom cell array memory cells and a second block of bottom cell array memory cells, wherein the three-dimensional memory further includes a multiple of upper word line contacts coupled to the upper word lines, and wherein the upper word line contacts are arranged between the first block of bottom cell array memory cells and the second block of bottom cell array memory cells.
In some arrangements the upper-middle cell array of memory cells is shifted relative to the bottom cell array of memory cells along a direction parallel to, or substantially parallel to, the bottom cell array of memory cells, and the lower-middle cell array of memory cells is shifted relative to the bottom cell array of memory cells along a direction parallel to, or substantially parallel to, the bottom cell array of memory cells.
In some arrangements the upper-middle cell array of memory cells is shifted by an amount equal to, or substantially equal to, one half an extent of a dimension of the first block of bottom cell array memory cells.
In some arrangements the upper-middle cell array of memory cells is shifted relative to the bottom cell array of memory cells along a direction parallel to, or substantially parallel to, the bottom cell array of memory cells, and the lower-middle cell array of memory cells is shifted relative to the bottom cell array of memory cells along a direction parallel to, or substantially parallel to, the bottom cell array of memory cells.
In some arrangements the bottom cell array of memory cells is arranged in two blocks of bottom cell array memory cells, a first block of bottom cell array memory cells and a second block of bottom cell array memory cells, and the upper-middle cell array of memory cells is shifted by an amount equal to, or substantially equal to, one half an extent of a dimension of the first block of bottom cell array memory cells.
BRIEF DESCRIPTION OF THE DRAWINGS
The foregoing aspects, features and advantages of the present disclosure will be further appreciated when considered with reference to the following description of exemplary embodiments and accompanying drawings, wherein like reference numerals represent like elements. In describing the exemplary embodiments of the present disclosure illustrated in the drawings, specific terminology may be used for the sake of clarity. However, the aspects of the present disclosure are not intended to be limited to the specific terms used.
Fig. 1 is an isometric view of a section of three-dimensional crosspoint memory.
Fig. 2 is a plan view of a section of a prior three-dimensional crosspoint memory.
Fig. 3 is a plan view of a section of three-dimensional crosspoint memory according to an embodiment.
Figs. 4A and 4B are cross-sectional views of a section of three-dimensional crosspoint memory according to an embodiment.
Fig. 5 is a plan view of a section of three-dimensional crosspoint memory according to an embodiment.
Fig. 6 is an isometric view of a section of three-dimensional crosspoint memory according to an embodiment.
DETAILED DESCRIPTION
The present technology is applied in the field of three-dimensional memory. A generalized example of a three-dimensional (3D) memory is shown in Fig. 1. In particular, Fig. 1 is an isometric view of a section of three-dimensional crosspoint memory. The memory includes a first layer (or “first array” ) of memory cells 5 and a second layer (or “second array” ) of memory cells 10. Between the first array of memory cells 5 and the second array of memory cells 10 is a number of word lines 15 extending in the X direction. Above the first array of memory cells 5 is a number of first bit lines 20 extending along the Y direction, and below the  second array of memory cells 10 is a number of second bit lines 25 extending along the Y direction. Further, as can be seen from the figure, the sequential structure of bit lines -memory cells -word lines -memory cells may be repeated along the Z direction to realize a stacked configuration. In any event, an individual memory cell may be accessed by selectively activating the word line and bit line corresponding to the cell.
In order to selectively activate the word lines and bit lines, the memory includes word line decoders and bit line decoders. The word line decoders are coupled to the word lines by word line contacts and are used to decode word line addresses such that a particular word line is activated when the line is addressed. Similarly, the bit line decoders are coupled to the bit lines by bit line contacts and are used to decode bit line addresses such that a particular bit line is activated when the line is addressed. The positioning of the word line decoders and contacts, and the positioning of the bit line decoders and contacts, are discussed further in connection with Fig. 2.
FIG. 2 is a plan view of section of three-dimensional crosspoint memory of a prior configuration. The figure depicts the section as viewed along the Z (depth) direction. The section includes a number of word lines, e.g. word lines 30, extending in the X (horizontal) direction, a number of top cell bit lines, e.g., bit lines 35, extending along the Y (vertical) direction and corresponding to a top cell array of memory cells (not shown) , and a number of bottom cell bit lines, e.g., bit lines 40, extending along the vertical direction and corresponding to a bottom cell array of memory cells (not shown) . The word lines, top cell bit lines, and bottom cell bit lines are typically formed according to a 20 nm /20 nm Line /Space (L/S) pattern and are formed on a silicon substrate. Moreover, the memory may employ complementary metal-oxide semiconductor (CMOS) technology.
The memory section of Fig. 2 also includes a word line contact area 45, a top cell bit line contact area 50, and a bottom cell bit line contact area 55. The word line contact area 45 is elongated along the vertical direction, while the top cell bit line contact area 50 and bottom cell contact area 55 are elongated along the horizontal direction. The word line contact area 45 includes a multiple of word line contacts, e.g., contact 45a, shown as dots enclosed by the word line contact area 45. The top cell bit line contact area 50 includes a multiple of top cell bit line contacts, e.g., contact 50a, shown as dots enclosed by top cell bit line contact area 50. The bottom cell bit line contact area 55 includes a multiple of bottom cell bit line contacts, e.g., contact 55a, shown as dots enclosed by bottom cell bit line contact area 55.
The word line contact area 45 includes a multiple of word line decoders (not shown) . The word line decoders generally conform to the word line contact area and generally extend along the vertical direction. The word line decoders couple to the word lines at the word  line contacts. The top cell bit line contact area 50 includes a multiple of top cell bit line decoders (not shown) . The top cell bit line decoders generally conform to the top cell bit line contact area 50 and generally extend along the horizontal direction. The top cell bit line decoders couple to the top cell bit lines at the top cell bit line contacts. The bottom cell bit line contact area 55 includes a multiple of bottom cell bit line decoders (not shown) . The bottom cell bit line decoders generally conform to the bottom cell bit line contact area 55 and generally extend along the horizontal direction. The bottom cell bit line decoders couple to the bottom cell bit lines at the bottom cell bit line contacts.
In creating the present technology, it has been recognized that the memory density of the prior configurations, as exemplified in Fig 2, can be improved, and that new configurations can provide improved memory density. One of the drawbacks of the prior configurations is related primarily to the arrangement of the memory cells into two two-dimensional arrays of memory cells. The present technology provides a memory employing four two-dimensional arrays of memory cells, which are arranged in a four-stack configuration. Thereby, the present technology allows for crosspoint memories with increased memory density, and provides per-bit cost advantages relative to prior crosspoint memories.
Fig. 3 is a plan view of a section of three-dimensional crosspoint memory according to an embodiment of the present technology. The figure depicts a multiple of array block architectures, including a multiple of top/bottom cell array block architectures, e.g., top/bottom cell array block architecture 60, and a multiple of middle cell array block architectures, e.g., middle cell array block architecture 65. In addition, each of the top/bottom cell array block architectures is arranged in two sub-blocks, e.g., sub-block 60a and sub-block 60b.
As can be seen from Fig. 3, the top/bottom cell array block architectures and middle cell array block architectures extend across X-Y areas of the same size, or approximately the same size, although in alternative embodiments the top/bottom cell array block architectures and middle cell array block architectures may extend across X-Y areas of different sizes. Also, in the embodiment of Fig. 3 the top/bottom cell array block architectures and middle cell array block architectures are generally rectangular in shape and have the same X and Y dimensions, although in alternative embodiments the top/bottom cell array block architectures and middle cell array block architectures may have different shapes or may have the same shape but with a different dimension or dimensions. Further, in Fig. 3 the top/bottom cell array block architectures are offset from the middle cell array block architectures by an amount equal to one half of the Y dimension for the top/bottom cell array block architectures and middle cell array block architectures. That is, the top/bottom cell array block architecture and middle cell array  block architecture are shifted relative to one another along a direction parallel or substantially parallel to the X-Y plane by an amount equal to one half of the Y dimension, indicated as “w” in Fig. 3.
The top/bottom cell array block architectures of Fig. 3 each include a multiple of top cell bit lines, e.g., top cell bit lines 70, a multiple of upper word lines, e.g., upper word lines 75, a multiple of lower word lines, e.g., lower word lines 80, and a multiple of bottom cell bit lines, e.g., bottom cell bit lines 85. For each top/bottom cell array block architecture the lower word lines are coupled to a multiple of lower word line contacts, e.g., contact 90a, shown as dots enclosed by a lower word line contact area 90; the lower cell bit lines are coupled to a multiple of lower cell bit line contacts, e.g., contact 93a, shown as dots enclosed by an lower cell bit line contact area 93; and the upper word lines are coupled to a multiple of upper word line contacts, e.g., contact 95a, shown as dots enclosed by an upper word line contact area 95. As can be seen, the upper word line contact area 95 is positioned between two top/bottom cell array block architectures.
The middle cell array block architectures of Fig. 3 each include a multiple of middle bit lines, e.g., middle bit lines 100. For each middle cell array block architecture the middle bit lines are coupled to a multiple of middle bit line contacts, e.g., contact 105a, shown as dots enclosed by a middle bit line contact area 105.
It should be noted that Fig. 3 is provided to illustrate a framework of a section of memory according to the present technology by depicting only selected elements of the section. A detailed description of a section of memory according to the present technology is provided in view of all the figures.
Fig. 4A is a cross-sectional view of a section of three-dimensional crosspoint memory according to an embodiment. The cross-section depicts only bit lines and word lines and generally corresponds to the framework of Fig. 3, although the numbers of bit lines and word lines shown in Fig. 4A differ from the numbers of bit lines and word lines shown in Fig. 3. The cross-section is best understood when considered in the context of a cross-section of the Fig. 3 embodiment as taken along the Y-Z plane, with the portion of Fig. 4A most closely corresponding to Fig. 3 indicated by box 110, and the portion of Fig. 4A most closely corresponding to top/bottom cell array block architecture 60 indicated by box 115.
As can be seen from Fig. 4A, from top to bottom along the Z direction, the section includes a multiple of top cell bit lines 120, e.g., to cell bit line 120a, a multiple of upper word lines 125, a multiple of middle bit lines 130, a multiple of lower word lines 135, and a multiple of bottom cell bit lines 140, e.g., bottom cell bit line 140a. Also shown are a multiple of top cell bit line contacts, e.g., top cell bit line contact 145, a multiple of middle bit line contacts,  e.g., middle bit line contact 150, and a multiple of bottom cell bit line contacts, e.g., bottom cell bit line contact 155. The top cell bit lines are coupled to respective bottom cell bit lines by the top cell bit line contacts. For example, top cell bit line 120a is coupled to bottom cell bit line 140a by top cell bit line contact 145. Moreover, the middle bit line contacts are arranged between the bottom cell bit lines.
Fig. 4B is a cross-sectional view of a section of three-dimensional crosspoint memory according to an embodiment. The cross-section depicts only bit lines and word lines and generally corresponds to the framework of Fig. 3, although the numbers of bit lines and word lines shown in Fig. 4B differ from the numbers of bit lines and word lines shown in Fig. 3. The cross-section is best understood when considered in the context of a cross-section of the Fig. 3 embodiment as taken along the X-Z plane, with the portion of Fig. 4B most closely corresponding to top/bottom cell array block architecture 60 indicated by box 160.
As can be seen from Fig. 4B, from top to bottom along the Z direction, the section includes a multiple of top cell bit lines, e.g., to cell bit line 120, a multiple of upper word lines 125, e.g. upper word line 127, a multiple of middle bit lines 130, a multiple of lower word lines 135, e.g., lower word line 137, a multiple of bottom cell bit lines 140, and a multiple of bottom cell bit line contacts, e.g., bottom cell bit line contact 142. Also shown are an upper word line contact 165, and a multiple of bottom word line contacts, e.g., bottom word line contact 170. The upper word line contacts are arranged between the lower word lines 135 and between the bottom cell bit lines 140. The lower word line contacts are arranged between the bottom cell bit lines 140.
Fig. 5 is a plan view of a section of three-dimensional crosspoint memory according to an embodiment. Fig. 5 is best understood in the context of Fig. 3. The correspondence between the two figures is evident from the like-numbered elements. In addition, Fig. 5 depicts the arrangement of the decoders as the section is viewed along the Z direction. Four types of decoders are provided, upper word line decoders, middle bit line decoders, lower word line decoders, and bottom cell bit line decoders. Each type of decoder is associated with a corresponding bit line type or word line type, and with corresponding contacts for the bit line type or word line type. Further, for a given group of lines, the decoders for the lines a coupled to the lines by the contacts for the lines, and the decoders are located in an area coincident with the area for the contacts. Thus, in top/bottom cell array block architecture 60 the bottom cell bit lines 140 are coupled to bottom cell bit line decoders that are located in bottom cell bit line contact area 93; the lower word lines 135 are coupled to lower word line decoders that are located in lower word line contact area 90; the middle bit lines 130 are coupled to middle bit line decoders that are located in middle bit line contact area 105; and the upper word  lines 125 are coupled to upper word line decoders that are located in upper word line contact area 95. Each group of decoders is used to decode addresses for its corresponding group of lines such that a particular line from the group is activated when the line is addressed. By activating lines associated with a memory cell the cell may be accessed for reading and writing. The relationship between the bit lines, word lines, and memory cells is discussed in more detail with reference to Fig. 6.
Fig. 6 is an isometric view of a section of three-dimensional crosspoint memory according to an embodiment. The section of three-dimensional memory includes a top cell array of memory cells 200, an upper-middle cell array of memory cells 205, a lower-middle cell array of memory cells 210, and a bottom cell array of memory cells 215. Each of the arrays of memory cells may be arranged in two blocks, illustrated for example by block indicators 220 and 225. Further, each of the blocks may be arranged in two sub-blocks, illustrated for example by  sub-block indicators  225a and 225b. In the case of the bottom cell array of memory cells 215, the bottom cell array of memory cells 215 may be arranged into a first block of bottom cell array memory cells 215a and a second block of bottom cell array memory cells 215b. Moreover, the first block of bottom cell array memory cells 215a may be arranged into a first sub-block of bottom cell array memory cells 215aa and second sub-block of bottom cell array memory cells 215ab.
It should be noted that each of the arrays of memory cells may be arranged in blocks that are positioned adjacent to one another along the Y direction. Thus, for example the bottom cell array of memory cells 215 may include the first block of bottom cell array memory cells 215a and a second block of bottom cell array memory cells (not shown) that is adjacent to block 215a along the Y direction.
In any event, a multiple of top cell bit lines, e.g., top cell bit line 230, are coupled to the top cell array of memory cells 200. A multiple of top cell bit line contacts e.g., top cell bit line contact 235, are coupled to the top cell bit lines. A multiple of upper word lines, e.g., upper word lines 240, are positioned between the top cell array of memory cells 200 and the upper-middle cell array of memory cells 205, and are coupled to the top cell array of memory cells 200 and to the upper-middle cell array of memory cells 205. A multiple of middle bit lines, e.g., middle bit lines 245, are positioned between the upper-middle cell array of memory cells 205 and the lower-middle cell array of memory cells 210, and are coupled to the upper-middle cell array of memory cells 205 and to the lower-middle cell array of memory cells 210. A multiple of lower word lines, e.g., lower word lines 250, are positioned between the lower-middle cell array of memory cells 210 and the bottom cell array of memory cells 215, and are coupled to the lower-middle cell array of memory cells 210 and to the bottom cell array of memory cells 215.  A multiple of bottom cell bit lines, e.g., bottom cell bit lines 255, are coupled to the bottom cell array of memory cells 215. Also, in the Fig. 6 embodiment the pitch of the top cell bit line contacts is the same as the pitch of the bottom cell bit lines, and the top cell bit lines are respectively coupled to the bottom cell bit lines by the top cell bit line contacts.
As illustrated in Fig. 6, the top cell bit line contacts may be arranged in the middle of the first block of bottom cell array memory cells 215 with respect to the Y dimension of the first block of bottom cell array memory cells 215a and the second block of bottom cell array memory cells 215b.
Also, in accordance with the embodiment of Fig. 6, the bottom cell array of memory cells 215 may include the first block of bottom cell memory cells 215a and a second block of bottom cell array of memory cells (not shown) that is adjacent to block 215a along the Y direction. And in such embodiment the middle bit lines may be coupled to a multiple of middle bit line contacts (not shown) and the middle bit line contacts may be arranged between the first block of bottom cell array memory cells 215a and the second block of bottom cell array memory cells (not shown) .
As illustrated in Fig. 6, a multiple of lower word line contacts, e.g., lower word line contact 260, may be coupled to the lower word lines, and the lower word line contacts may be arranged between the first sub-block of bottom cell array memory cells 215aa and the second sub-block of bottom cell array memory cells 215ab. Further, the lower word line contacts may be arranged in the middle of first block of bottom cell array memory cells 215a with respect to the X dimension of the first block of bottom cell array memory cells 215a.
As illustrated in Fig. 6, a multiple of upper word line contacts, e.g., upper word line contact 265, are coupled to the upper word lines, and the upper word line contacts are arranged between the first block of bottom cell array memory cells 215a and the second block of bottom cell array memory cells 215b.
As illustrated in Fig. 6, the upper-middle cell array of memory cells 205 may be shifted relative to the bottom cell array of memory cells 215 along a direction parallel to, or substantially parallel to, the bottom cell array of memory cells 215, and the lower-middle cell array of memory cells 210 may be shifted relative to the bottom cell array of memory cells 215 along a direction parallel to, or substantially parallel to, the bottom cell array of memory cells 215. That is, the upper-middle cell array of memory cells 205 may be shifted relative to the bottom cell array of memory cells 215 along a direction parallel to, or substantially parallel to, the X-Y plane, and the lower-middle cell array of memory cells 210 may be shifted relative to the bottom cell array of memory cells 215 along a direction parallel to, or substantially parallel to, the X-Y plane. Further, the upper-middle cell array of memory cells 205 may be shifted  relative to the bottom cell array of memory cells 215 along a direction parallel to, or substantially parallel to, the bottom cell array of memory cells 215 by an amount equal to, or substantially equal to, one half an extent of a dimension (e.g., the Y dimension) of the first block of bottom cell array memory cells 215a. Similarly, the lower-middle cell array of memory cells 210 may be shifted relative to the bottom cell array of memory cells 215 along a direction parallel to, or substantially parallel to, the bottom cell array of memory cells 215 by an amount equal to, or substantially equal to, one half an extent of a dimension (e.g., the Y dimension) of the first block of bottom cell array memory cells 215a.
Most of the foregoing alternative examples are not mutually exclusive, but may be implemented in various combinations to achieve unique advantages. As these and other variations and combinations of the features discussed above may be utilized without departing from the subject matter defined by the claims, the foregoing description of the embodiments should be taken by way of illustration rather than by way of limitation of the subject matter defined by the claims. As an example, the preceding operations do not have to be performed in the precise order described above. Rather, various steps can be handled in a different order, such as reversed, or simultaneously. Steps can also be omitted unless otherwise stated. In addition, the provision of the examples described herein, as well as clauses phrased as "such as, " "including" and the like, should not be interpreted as limiting the subject matter of the claims to the specific examples; rather, the examples are intended to illustrate only one of many possible embodiments. Further, the same reference numbers in different drawings may identify the same or similar elements.
Although the present disclosure herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present disclosure. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present disclosure as defined by the appended claims.

Claims (10)

  1. A three-dimensional memory comprising:
    a top cell array of memory cells;
    an upper-middle cell array of memory cells;
    a lower-middle cell array of memory cells;
    a bottom cell array of memory cells;
    a plurality of top cell bit lines coupled to the top cell array of memory cells;
    a plurality of top cell bit line contacts coupled to the top cell bit lines;
    a plurality of upper word lines positioned between the top cell array of memory cells and the upper-middle cell array of memory cells, and coupled to the top cell array of memory cells and to the upper-middle cell array of memory cells;
    a plurality of middle bit lines positioned between the upper-middle cell array of memory cells and the lower-middle cell array of memory cells, and coupled to the upper-middle cell array of memory cells and to the lower-middle cell array of memory cells;
    a plurality of lower word lines positioned between the lower-middle cell array of memory cells and the bottom cell array of memory cells, and coupled to the lower-middle cell array of memory cells and to the bottom cell array of memory cells; and
    a plurality of bottom cell bit lines coupled to the bottom cell array of memory cells,
    wherein the pitch of the top cell bit line contacts is the same as the pitch of the bottom cell bit lines, and the top cell bit lines are respectively coupled to the bottom cell bit lines by a plurality of top cell bit line contacts.
  2. The three-dimensional memory according to claim 1, wherein the top cell bit line contacts are arranged in the middle of the bottom cell array of memory cells with respect to a dimension of the bottom cell array of memory cells.
  3. The three-dimensional memory according to claim 1, wherein the bottom cell array of memory cells is arranged in two blocks of bottom cell array memory cells, a first block of bottom cell array memory cells and a second block of bottom cell array memory cells, wherein the three-dimensional memory further comprises a plurality of middle bit line contacts coupled to the middle bit lines, and wherein the middle bit line contacts are arranged between the first block of bottom cell array memory cells and the second block of bottom cell array memory cells.
  4. The three-dimensional memory according to claim 1, wherein the bottom cell array of memory cells is arranged in two blocks of bottom cell array memory cells, a first block of  bottom cell array memory cells and a second block of bottom cell array memory cells, wherein the first block of bottom cell memory cells is arranged in two sub-blocks, a first sub-block of bottom cell array memory cells and a second sub-bock of bottom cell array memory cells, wherein the three-dimensional memory further comprises a plurality of lower word line contacts coupled to the lower word lines, and wherein the lower word line contacts are arranged between the first sub-block of bottom cell array memory cells and the second sub-block of bottom cell array memory cells.
  5. The three-dimensional memory according to claim 4, wherein the lower word line contacts are arranged in the middle of first block of bottom cell array memory cells with respect to a dimension of the first block of bottom cell array memory cells.
  6. The three-dimensional memory according to claim 1, wherein the bottom cell array of memory cells is arranged in two blocks of bottom cell array memory cells, a first block of bottom cell array memory cells and a second block of bottom cell array memory cells, wherein the three-dimensional memory further comprises a plurality of upper word line contacts coupled to the upper word lines, and wherein the upper word line contacts are arranged between the first block of bottom cell array memory cells and the second block of bottom cell array memory cells.
  7. The three-dimensional memory according to claim 6, wherein the upper-middle cell array of memory cells is shifted relative to the bottom cell array of memory cells along a direction parallel to, or substantially parallel to, the bottom cell array of memory cells, and the lower-middle cell array of memory cells is shifted relative to the bottom cell array of memory cells along a direction parallel to, or substantially parallel to, the bottom cell array of memory cells.
  8. The three-dimensional memory according to claim 7, wherein the upper-middle cell array of memory cells is shifted by an amount equal to, or substantially equal to, one half an extent of a dimension of the first block of bottom cell array memory cells.
  9. The three-dimensional memory according to claim 1, wherein the upper-middle cell array of memory cells is shifted relative to the bottom cell array of memory cells along a direction parallel to, or substantially parallel to, the bottom cell array of memory cells, and the lower-middle cell array of memory cells is shifted relative to the bottom cell array of memory cells along a direction parallel to, or substantially parallel to, the bottom cell array of memory cells.
  10. The three-dimensional memory according to claim 9, wherein the bottom cell array of memory cells is arranged in two blocks of bottom cell array memory cells, a first block of bottom cell array memory cells and a second block of bottom cell array memory cells, and the upper-middle cell array of memory cells is shifted by an amount equal to, or substantially equal to, one half an extent of a dimension of the first block of bottom cell array memory cells.
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