WO2021238814A1 - 显示面板、显示装置 - Google Patents

显示面板、显示装置 Download PDF

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Publication number
WO2021238814A1
WO2021238814A1 PCT/CN2021/095316 CN2021095316W WO2021238814A1 WO 2021238814 A1 WO2021238814 A1 WO 2021238814A1 CN 2021095316 W CN2021095316 W CN 2021095316W WO 2021238814 A1 WO2021238814 A1 WO 2021238814A1
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WIPO (PCT)
Prior art keywords
pixel
display panel
area
base substrate
sub
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PCT/CN2021/095316
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English (en)
French (fr)
Inventor
韩龙
王品凡
曹方旭
李文强
刘利宾
Original Assignee
京东方科技集团股份有限公司
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Priority to US17/908,017 priority Critical patent/US20230088068A1/en
Publication of WO2021238814A1 publication Critical patent/WO2021238814A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H10K77/111—Flexible substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/352—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels the areas of the RGB subpixels being different
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/311—Flexible OLED
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display panel and a display device.
  • the four-curved screen display panel means that the periphery of the display panel can be curved according to a certain bending radius, thereby presenting a comprehensive stereoscopic display effect that simultaneously displays the front and side surfaces.
  • the four-curved screen display panel can be composed of an array substrate, an encapsulation layer packaged on one side of the array substrate, and a cover plate. The bottom substrate is bent in the direction, and then the cover is bonded through the 3D Cover Glass (3D cover glass) bonding technology.
  • the corner areas need to be stretched in the bending direction, which easily causes the four corners of the array substrate and the packaging layer to wrinkle or break when stretched. ;
  • the corner area of the display panel will be wrinkled, which will squeeze and destroy the structure of the corner area of the display panel.
  • a display panel includes an array substrate and an encapsulation layer encapsulated on one side of the array substrate.
  • the display panel further includes a stretching zone located on the display panel.
  • the corner area of the display panel is at least partially located in the display area of the display panel, and the stretching area is provided with a hollow opening penetrating the array substrate and the packaging layer.
  • the display panel further includes a normal display area located in the display area
  • the array substrate includes a base substrate and a functional layer located on a side of the base substrate facing the packaging layer, A sub-pixel unit is formed in the functional layer, the stretched area includes a first stretched area, the first stretched area is located in the display area, and the pixel density of the first stretched area is less than that of the normal display area The pixel density; wherein, the orthographic projection of the sub-pixel unit in the base substrate and the orthographic projection of the hollow opening in the base substrate in the first stretching zone do not overlap.
  • the display panel further includes a frame area located at the periphery of the display area, the stretching area further includes a second stretching area, and the second stretching area is located in the frame area.
  • the display panel further includes a transition area, the transition area is located in the display area between the first stretching area and the normal display area, and the pixel density of the transition area is less than that of the transition area.
  • the pixel density of the normal display area wherein, the transition area is integrated with a gate drive circuit, and the gate drive circuit is used for sub-pixel units in the transition area and in line with the sub-pixel units in the transition area.
  • the sub-pixel unit provides a driving signal; the orthographic projection of the sub-pixel unit on the base substrate in the transition zone and the orthographic projection of the gate drive circuit on the base substrate do not overlap.
  • the gate driving circuit includes: a first gate driving circuit and a second gate driving circuit.
  • the first gate driving circuit is used to provide a gate driving signal to the sub-pixel unit; the second gate driving circuit is used to provide an enable signal to the sub-pixel unit.
  • the display panel is a rectangle with rounded corners, there are four stretched regions, and the four stretched regions are respectively four rounded regions located in the rounded rectangle.
  • the first stretching zone, the second stretching zone, and the transition zone are in the shape of a concentric fan, and the first stretching zone is located where the second stretching zone faces.
  • the transition zone is located on the side of the first stretching zone facing the center of the circle where it is located.
  • R pixel openings, G pixel openings, and B pixel openings are alternately distributed along the same pixel opening row, and in the same pixel opening row, two G pixel openings distributed along the column direction are arranged between the R pixel opening and the B pixel opening.
  • the pixel openings of the same color are not located in the same column, and in two pixel opening rows separated by one pixel opening row, the pixel openings of the same color are located in the same column.
  • the display panel includes a plurality of pixel islands distributed in an array, and the hollow opening is located between the pixel island and the orthographic projection of the base substrate on the base substrate; the gate driving circuit is located in the orthographic projection of the base substrate.
  • the orthographic projection of the base substrate is located between the pixel islands and the orthographic projection of the base substrate.
  • each of the pixel islands includes: B pixel openings and R pixel openings located in a row of first pixel openings and arranged adjacently, two pixel openings located in a row of second pixels and distributed along a column direction.
  • the pixel openings are located in the same column, and the pixel openings of different colors are located in different columns.
  • the pixel island includes R pixel openings, G pixel openings, and B pixel openings located in the same pixel opening row, and in the same pixel opening row, the R pixel opening and the G pixel opening are The pixel openings are distributed along the column direction.
  • the normal display area is driven by the GGRB algorithm; the first stretching area and the transition area are driven by the true RGB algorithm.
  • the sub-pixel unit includes a light-emitting unit and a pixel driving circuit for providing a driving current to the light-emitting unit.
  • the pixel The aspect ratio of the driving circuit is 3:1; in the normal display area, the aspect ratio of the pixel driving circuit is 2:1.
  • the pixel driving circuit includes a driving transistor and a capacitor connected to the gate of the driving transistor.
  • the pixel driving circuit in the first stretching region and the transition region includes: a first conductive portion, the first conductive portion is located in the first gate layer, and is used to form the gate of the driving transistor and the first electrode of the capacitor.
  • the pixel driving circuit in the normal display area includes: a second conductive portion, the second conductive portion is located on the first gate layer, and is used to form the gate of the driving transistor and the first electrode of the capacitor.
  • the ratio of the size of the first conductive portion in the row direction to the size of the column direction is smaller than the ratio of the size of the second conductive portion in the row direction to the size of the column direction, and the row direction is the width direction of the pixel drive circuit,
  • the column direction is the length direction of the pixel driving circuit.
  • the pixel driving circuit includes a driving transistor, a second transistor, a second end of the second transistor is connected to the gate of the driving transistor, and the second transistor is a double-channel transistor. Tao structure.
  • the pixel driving circuit in the normal display area includes: a first active part, a first shielding part, the first active part is located in the active layer, and the first active part is connected to the two channels of the second transistor Between; the first shielding portion is located in the second gate layer, and is connected to a stable voltage source, the first shielding portion extends in the row direction in the orthographic projection of the base substrate, and the first shielding portion is in the substrate
  • the orthographic projection of the substrate and the orthographic projection of the first active part in the adjacent pixel driving circuit at least partially overlap with the orthographic projection of the base substrate.
  • the pixel driving circuit in the first stretching zone and the transition zone includes: a second active part, a third active part, and a second shielding part, the second active part is located in the active layer, and the second active part Connected between the two channels of the second transistor; the third active part is connected to the gate of the driving transistor; the second shielding part is located on the second gate layer and is connected to a stable voltage source, the second shielding The part includes a first sub-shielding part and a second sub-shielding part that are connected, the first sub-shielding part extends in the column direction in the orthographic projection of the base substrate, and the second sub-shielding part is on the base substrate.
  • the orthographic projection extends in the row direction; wherein the orthographic projection of the first sub-shielding portion on the base substrate and the orthographic projection of the third active portion on the base substrate at least partially overlap, and the second sub-shielding portion is in the The orthographic projection of the base substrate and the second active part in the adjacent pixel driving circuit at least partially overlap with the orthographic projection of the base substrate.
  • a display device including the above-mentioned display panel.
  • the present disclosure provides a display panel and a display device.
  • the display panel includes an array substrate and an encapsulation layer encapsulated on one side of the array substrate.
  • the stretching area is provided with a hollow opening penetrating the array substrate and the packaging layer.
  • the display panel provided by the present disclosure is provided with a hollow opening penetrating the array substrate and the packaging layer in the stretching area.
  • the hollow opening can improve the bending ability and the stretching ability of the stretching area of the display panel, thereby avoiding the stretching area. Fracture damage during bending; on the other hand, the hollow opening can provide accommodating space for wrinkles when the stretch zone is bent, so as to avoid wrinkles when the stretch zone is bent.
  • FIG. 1 is a schematic structural diagram of an exemplary embodiment of a display panel of the present disclosure
  • Figure 2 is a cross-sectional view of the broken line A-A in Figure 1;
  • FIG. 3 is a cross-sectional view of a corner area in an exemplary embodiment of the display panel of the present disclosure
  • FIG. 4 is a distribution diagram of pixel openings in an exemplary embodiment of the display panel of the present disclosure
  • FIG. 5 is a distribution diagram of pixel openings in another exemplary embodiment of the display panel of the present disclosure.
  • FIG. 6 is a schematic diagram of a circuit structure of a pixel driving circuit in an embodiment of a display panel of the present disclosure
  • FIG. 7 is a timing diagram of each node of the pixel driving circuit in FIG. 6;
  • FIG. 8 is a schematic structural diagram of a pixel driving circuit in a normal display area in an embodiment of a display panel of the present disclosure
  • FIG. 9 is a schematic structural diagram of a pixel driving circuit in a first stretching area in an embodiment of a display panel of the present disclosure.
  • FIG. 10 is a schematic structural diagram of another exemplary embodiment of the display panel of the present disclosure.
  • FIG. 1 is a schematic structural diagram of an exemplary embodiment of the display panel of the present disclosure
  • FIG. 2 is a cross-sectional view of the dashed line A-A in FIG. 1.
  • the display panel includes an array substrate 1 and an encapsulation layer 2 encapsulated on one side of the array substrate.
  • the display panel also includes a stretched area 3, which is located at a corner area of the display panel and at least partially In the display area 41 of the display panel, the stretching area 3 is provided with a hollow opening 5 penetrating through the array substrate 1 and the packaging layer 2.
  • the display panel provided by the present disclosure is provided with a hollow opening penetrating the array substrate and the packaging layer in the stretching area.
  • the hollow opening can improve the bending ability and the stretching ability of the stretching area of the display panel, thereby avoiding the stretching area. Fracture damage during bending; on the other hand, the hollow opening can provide accommodating space for wrinkles when the stretch zone is bent, so as to avoid wrinkles when the stretch zone is bent.
  • the display panel may also only have hollow openings on the array substrate, and no hollow openings are provided on the packaging layer.
  • the corner area of the display panel may refer to the intersection position of the two sides of the display panel, and the position of the two intersection sides may be a right-angle connection or a rounded connection.
  • the display panel may be a rectangle with rounded corners, there may be four stretched areas 3, and the four stretched areas 3 may be located in four rounded areas of the rounded rectangle, respectively.
  • the display panel may also be a special-shaped display panel.
  • the display panel may be hexagonal. Accordingly, the display panel may include six stretch areas, six The stretching zone can be respectively arranged in the six corner areas of the hexagon, and the stretching zone 3 can also have other shapes.
  • the display panel may further include a normal display area 411 located in the display area 41, as shown in FIG. 3, in an exemplary embodiment of the display panel of the present disclosure
  • the array substrate 1 may include a base substrate 11 and a functional layer 12 on the side of the base substrate 11 facing the packaging layer 2.
  • the functional layer 12 is provided with a plurality of sub-pixel units 121, and
  • the stretching zone 3 includes a first stretching zone 31, the first stretching zone 31 is located in the display zone 41, and the pixel density of the first stretching zone 31 is smaller than the pixel density of the normal display zone 411;
  • the orthographic projection of the sub-pixel unit 121 in the first stretching region 31 on the base substrate 11 and the orthographic projection of the hollow opening 5 on the base substrate 11 do not overlap.
  • the first stretching area 31 is provided with sub-pixel units, that is, the first stretching area 31 can realize a display function. When the four-curved screen display panel is formed, the first stretched area 31 is bent, so that the display panel can present a comprehensive stereoscopic display effect in which the front and side surfaces are simultaneously displayed.
  • the functional layer may include a transistor TFT layer, a pixel definition layer, a light-emitting unit layer, and the like.
  • the orthographic projection of the sub-pixel unit 121 on the base substrate 11 and the orthographic projection of the hollow opening 5 on the base substrate 11 do not overlap, so as to avoid hollowing through the array substrate and the packaging layer.
  • the opening 5 affects the sub-pixel unit 121.
  • the pixel density of the first stretched area 31 is set to be smaller than the pixel density of the normal display area 411, so that the first stretched area 31 may be reserved for arranging hollow openings. 5 space.
  • the space for arranging the hollow opening 5 may also be reserved in other ways. For example, the area of the sub-pixel unit in the first stretched region 31 may be reduced to reserve the space.
  • a space for arranging the hollow opening 5 is provided.
  • the display panel may further include a frame area 42 located at the periphery of the display area 41, and the stretching area 3 may also include a second stretching area 32.
  • the area 32 is located in the border area 42.
  • the second stretching area 32 may not be provided with sub-pixel units, and the second stretching area 32 is only used to realize the bending of the frame of the display panel.
  • the normal display area and the first stretched area have different pixel densities, and correspondingly, the normal display area and the first stretched area have different pixel opening distributions.
  • FIG. 4 it is a distribution diagram of pixel openings in an exemplary embodiment of the display panel of the present disclosure.
  • R pixel openings 81, G pixel openings 82, and B pixel openings 83 are alternately distributed along the same pixel opening row, and in the same pixel opening row, between R pixel openings 81 and B pixel openings 83
  • Two G pixel openings 82 distributed along the column direction are provided.
  • the pixel openings of the same color are not located in the same column, and in two pixel opening rows separated by one pixel opening row, the pixel openings of the same color The pixel openings are located in the same column.
  • the display panel in the first stretching zone: may include a plurality of pixel islands 9 distributed in an array, and the hollow opening 5 is orthographically projected on the base substrate It may be located between the adjacent pixel islands 9 in the orthographic projection of the base substrate.
  • each of the pixel islands 9 may include: B pixel openings 83 and R pixel openings 81 located in a row of first pixel openings and adjacently arranged, and located in a second pixel opening row.
  • the pixel openings in the first stretched area and the normal display area have the same shape and size, and the pixel openings in the first stretched area 31 are the same as those in the normal display area 411. The only difference is that, in the first stretched area 31, there are no pixel openings in some positions.
  • the display panel evaporates each organic layer of the light-emitting unit on the pixel definition layer through a high-precision metal mask, it can pass
  • the high-precision metal mask with the same opening shape and opening density at each position vaporizes the light-emitting units in the normal display area and the first stretched area. This setting can improve the stress of each area when the high-precision metal mask is opened. Uniformity.
  • the hollow openings 5 are distributed in a "cross" shape. It should be understood that in other exemplary embodiments, the hollow openings 5 may be distributed in other ways, such as I-shaped and King-shaped. Wait.
  • the display panel is vapor-deposited through a high-precision metal mask with the same opening shape and opening density, in the first stretching zone, the vapor-deposited organic layer can only be formed at the pixel opening position to emit light.
  • the pixel opening is provided with an anode exposed outside the pixel defining layer. Therefore, the organic layer vaporized at the pixel opening can form a light-emitting unit connected to the anode, and there is no area where the pixel opening is provided.
  • the anode is not exposed, or a hollow opening is provided, therefore, a light-emitting unit capable of emitting light cannot be formed in the area outside the pixel opening.
  • the sub-pixel unit in the normal display area 411 can be driven by the GGRB algorithm, that is, the R sub-pixel can form a pixel unit with a B sub-pixel and a G sub-pixel on the left, and the R sub-pixel can also be connected to the right.
  • a B sub-pixel and a G sub-pixel on the side form another pixel unit; in the same way, the B sub-pixel can form a pixel unit with a R sub-pixel and a G sub-pixel on the left, and the B sub-pixel can also be connected with the right sub-pixel.
  • One R sub-pixel and G sub-pixel form another pixel unit. This driving method can improve the resolution of the display panel.
  • the sub-pixel units in the first stretched area 31 can be driven by a true RGB algorithm, that is, each R, G, and B sub-pixel only forms one pixel unit. It should be noted that since the R and B sub-pixels are shared in the GGRB algorithm, the number of G sub-pixels in the normal display area is twice that of the R and B sub-pixels; and the pixel units in the true RGB algorithm do not share the sub-pixel units. The number of three sub-pixels of RGB in a stretched area 31 is the same. Therefore, the number of G sub-pixels in the first stretched area 31 is half of the G sub-pixels in the normal display area.
  • the normal display area 411 uses the GGRB algorithm to drive the sub-pixel units, and each R and B sub-pixels are two pixel units in common. Therefore, only two sub-pixels need to be provided in each square pixel unit.
  • the first stretching area 31 is driven by a true RGB algorithm, and three sub-pixels need to be set in each square pixel unit. Therefore, in the first stretching area, the aspect ratio of the pixel unit is 3:1, and in the normal display area, the aspect ratio of the pixel unit is 2:1.
  • the display panel may be a top emission display panel. In the top emission display panel, the orthographic projection of the pixel opening on the base substrate is located on the orthographic projection of the pixel drive circuit on the base substrate.
  • the length and width of the pixel unit in the display panel is The ratio is the aspect ratio of the pixel drive circuit. Therefore, in the first stretching area, the aspect ratio of the pixel driving circuit is 3:1, and in the normal display area, the aspect ratio of the pixel driving circuit is 2:1.
  • FIG. 5 it is a distribution diagram of pixel openings in another exemplary embodiment of the display panel of the present disclosure.
  • the pixel island may include R pixel openings 81, G pixel openings 82, and B pixel openings 83 located in the same pixel opening row, and in the same pixel opening row, the R pixel openings and the G pixel openings are distributed along the column direction. .
  • This setting can avoid the above-mentioned technical problems of "horizontal pixel brightness center shift, loss of picture balance, upper and lower edge color shift inversion, and sawtooth in the diagonal direction". It should be understood that, in other exemplary embodiments, the pixel island may also have other pixel opening distribution modes, which all fall within the protection scope of the present disclosure.
  • FIG. 6 is a schematic diagram of a circuit structure of a pixel driving circuit in an embodiment of a display panel of the disclosure
  • FIG. 7 is a timing diagram of each node of the pixel driving circuit in FIG. 8 is a schematic structural diagram of a pixel driving circuit in a normal display area in an embodiment of a display panel of the present disclosure
  • FIG. 9 is a schematic structural diagram of a pixel driving circuit in a first stretching area in an embodiment of a display panel of the present disclosure .
  • the aspect ratio of the pixel driving circuit in FIG. 9 is 3:1
  • the aspect ratio of the pixel driving circuit in FIG. 8 is 2:1.
  • the pixel driving circuit has a 7T1C structure, wherein the first terminal of the fourth transistor T4 is connected to the data signal terminal Vdata, the second terminal is connected to the second node N2, and the gate is connected to the gate driving signal terminal.
  • the first terminal of the fifth transistor T5 is connected to the second node N2, the second terminal is connected to the first power supply terminal VDD, the gate is connected to the enable signal terminal EM, the first terminal of the third transistor T3 is connected to the second node N2, and the second terminal Connected to the third node N3, the gate is connected to the first node N1; the first end of the second transistor T2 is connected to the third node N3, the second end is connected to the first node N1, and the gate is connected to the gate drive signal terminal Gate; the first transistor T1 The first terminal is connected to the first node N1, the second terminal is connected to the initialization signal terminal Vint, the gate is connected to the reset signal terminal Re, the first terminal of the sixth transistor T6 is connected to the third node N3, the second terminal is connected to the fourth node N4, and the gate is Connect the enable signal terminal EM; the first terminal of the seventh transistor T7 is connected to the initialization signal terminal Vint, the second terminal is connected to the fourth node N4, and the gate is connected to the
  • the driving method of the pixel driving circuit includes three stages: a reset stage T1, a threshold value writing stage T2, and a light-emitting stage T3.
  • the reset signal terminal Re outputs a low-level signal
  • the enable signal terminal EM and the gate drive signal terminal Gate output a high-level signal
  • the first transistor T1 and the seventh transistor T7 are turned on
  • the initialization signal terminal Vint The fourth node N4 and the first node N1 input initialization signals.
  • the gate drive signal terminal Gate outputs a low level signal
  • the enable signal terminal EM and the reset signal terminal Re output high level signals
  • the data signal terminal writes to the first node N1 including the third transistor T3
  • the display panel may include a base substrate, an active layer, a first gate layer, a second gate layer, and a source-drain layer stacked in sequence.
  • the active layer can be used to form the channel region of each transistor.
  • the first gate layer may include a reset signal line Re for providing a reset signal terminal, a gate driving signal line Gate for providing a gate driving signal terminal, an enable signal line EM for providing an enable signal terminal, and a capacitor C.
  • the second gate layer may include an initial signal line Vinit for providing an initial signal terminal, and a second electrode of the capacitor C.
  • the source drain layer may include a power line VDD for providing the first power terminal, and a data line Data for providing a data signal terminal.
  • the pixel driving circuit in the first stretching zone may include a first conductive portion 11, and the first conductive portion 11 may be located in the first gate layer for forming the The gate of the driving transistor and the first electrode of the capacitor.
  • the pixel driving circuit in the normal display area may include: a second conductive portion 12, which is located on the first gate layer, and is used to form the gate and capacitor of the driving transistor.
  • the first electrode wherein, the ratio of the size of the first conductive portion 11 in the row direction to the size of the column direction is smaller than the ratio of the size of the second conductive portion 12 in the row direction to the size of the column direction, and the row direction is the width of the pixel drive circuit.
  • the column direction is the length direction of the pixel driving circuit.
  • the pixel driving circuit in the normal display area includes: a first active portion 51, a first shielding portion 21, the first active portion 51 is located in the active layer, and the first active portion 51 is connected to Between the two channels of the second transistor; the first shielding portion 21 is located on the second gate layer and connected to a stable voltage source.
  • the first shielding portion 21 can be connected to the power line through a via hole (white square hole) VDD.
  • the first shielding portion 21 may extend in the row direction in the orthographic projection of the base substrate, and the first shielding portion 21 may be the first active portion in the orthographic projection of the base substrate and the pixel driving circuit adjacent thereto.
  • the orthographic projection of 51 on the base substrate at least partially overlaps can be used to shield the first active portion 51 in the pixel driving circuit on the left side thereof.
  • the first shielding portion 21 can stabilize the first active portion 51 to avoid current between the first active portion 51 in the floating state and the source and drain of the second transistor, thereby further stabilizing the light-emitting stage The voltage at the gate of the driving transistor.
  • the pixel driving circuit in the first stretching zone includes: a second active portion 52, a third active portion 53, and a second shielding portion 22.
  • the second active portion 52 is located in the active layer, The second active part 52 is connected between the two channels of the second transistor; the third active part 53 is connected to the gate of the driving transistor; the second shielding part is located in the second gate layer and connected to The stable voltage source, for example, the second shielding part may be connected to the power supply line VDD through a via hole (white square hole).
  • the second shielding part may include a first sub-shielding part 221 and a second sub-shielding part 222 that are connected, the first sub-shielding part 221 extends in the column direction on the orthographic projection of the base substrate, and the second The sub-shielding portion 222 extends in the row direction on the orthographic projection of the base substrate; wherein, the first sub-shielding portion 221 is on the orthographic projection of the base substrate and the third active portion 53 is on the base substrate.
  • the orthographic projections are at least partially overlapped, and the second sub-shielding portion 222 is at least partially overlapped in the orthographic projection of the base substrate and the adjacent pixel drive circuit of the second active portion 52 in the orthographic projection of the base substrate, as shown in FIG. 9
  • the second sub-shielding portion 222 can be used to shield the second active portion 52 in the pixel driving circuit on its left side.
  • the first sub-shielding portion 221 can stabilize the gate of the driving transistor, and the second sub-shielding portion 222 can stabilize the second active portion 52.
  • the display panel further includes a transition area 6, which is located in the display area between the first stretching area 31 and the normal display area 411, and The pixel density of the transition area 6 may be less than the pixel density of the normal display area 411.
  • FIG. 10 it is a schematic structural diagram of another exemplary embodiment of the display panel of the present disclosure.
  • the transition area 6 is integrated with a gate drive circuit 7, and the gate drive circuit 7 can be used to transfer sub-pixel units in the transition area 6 and sub-pixel units in the same line with the sub-pixel units in the transition area 6 Provide driving signals.
  • the gate driving circuit 7 located in the transition region 6 can provide driving signals to the sub-pixel units in the first stretching region 31 and the normal display region 411, respectively.
  • the orthographic projection of the sub-pixel unit on the base substrate and the orthographic projection of the gate drive circuit on the base substrate do not overlap.
  • the pixel density of the transition area 6 is set to be smaller than the pixel density of the normal display area 411, so that a space for setting the gate driving circuit can be reserved in the transition area 6.
  • the orthographic projection of the sub-pixel unit on the base substrate in the transition zone 6 and the orthographic projection of the gate drive circuit on the base substrate are set to not overlap, so as to prevent the gate drive circuit from affecting the pixel unit. Impact.
  • the distribution of pixel openings in the transition area 6, the circuit structure of the pixel drive circuit, the structure and shape of the pixel unit may be the same as those of the first stretched area 31.
  • the gate drive circuit may be located between the pixel island and the orthographic projection of the base substrate on the base substrate.
  • the gate driving circuit 7 may include: a first gate driving circuit 71 and a second gate driving circuit 72.
  • the first gate driving circuit 71 may be used to provide a gate driving signal to the sub-pixel unit Pix; the second gate driving circuit 72 may be used to provide an enable signal to the sub-pixel unit Pix.
  • the first stretching zone 31, the second stretching zone 32, and the transition zone 6 may be concentric fan-shaped, and the first stretching zone 31 is located in the The second stretching zone 32 faces the side of the center of the circle where it is located, and the transition zone 6 may be located on the side of the first stretching zone 31 facing the center of the circle where it is located.
  • the fan-shaped stretching zone can pass through the intersection of the two intersecting edges at the corner area where the fan-shaped stretching zone passes through the circular center dividing line. Setting the first stretching zone 31, the second stretching zone 32, and the transition zone 6 into a fan shape can greatly reduce the first stretching zone 31, the second stretching zone 31, and the second stretching zone 31 while fulfilling their functions.
  • the first stretching zone 31, the second stretching zone 32, and the transition zone 6 may have other shapes, for example, the first stretching zone 31,
  • the second stretching zone 32 and the transition zone 6 may be trapezoidal, rectangular, or the like.
  • This exemplary embodiment also provides a display device including the above-mentioned display panel.
  • the display device may be a display device such as a mobile phone, a TV, a tablet computer, etc.

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Abstract

一种显示面板、显示装置，显示面板包括阵列基板（1），显示面板还包括拉伸区（3），拉伸区位于显示面板的边角区域，拉伸区设置有贯穿所述阵列基板的镂空开口（5）。显示面板四周可以按照一定弯曲半径形成弧度，从而实现正面侧面同时显示的全面立体显示。

Description

显示面板、显示装置
相关申请的交叉引用
本申请要求于2020年05月26日递交的、名称为《显示面板、显示装置》的中国专利申请第202010454585.X号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板、显示装置。
背景技术
四曲面屏显示面板是指显示面板的周边可以按照一定弯曲半径形成弧度，从而呈现一种正面侧面同时显示的全面立体显示效果。相关技术中，四曲面屏显示面板可以由阵列基板、封装于阵列基板一侧的封装层以及盖板组成，在制作四曲面屏显示面板时，阵列基板和封装层的周边需要向阵列基板的衬底基板方向弯折，然后通过3D Cover Glass(3D盖板玻璃)贴合技术实现盖板贴合。
然而，阵列基板和封装层的周边向阵列基板的衬底基板方向弯折时，其边角区域需要向弯折方向拉伸，从而容易造成阵列基板和封装层四个角出现褶皱或拉伸断裂；同时由于显示面板弯折前的边长大于弯折后的边长，显示面板在周边弯折时，其边角区域会出现褶皱，从而会挤压破坏显示面板边角区域的结构。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
公开内容
根据本公开的一个方面，提供一种显示面板，该显示面板包括阵列基板和封装于所述阵列基板一侧的封装层，所述显示面板还包括拉伸区，拉伸区位于所述显示面板的边角区域，且至少部分位于所述显示面板的显示区，所述拉伸区设置有贯穿所述阵列基板和所述封装层的镂空开口。
本公开一种示例性实施例中，所述显示面板还包括位于所述显示区的正常显示区，所述阵列基板包括衬底基板和位于所述衬底基板面向封装层一侧的功能层，所述功能层内形成有子像素单元，所述拉伸区包括第一拉伸区，第一拉伸区位于所述显示区，所述第一拉伸区的像素密度小于所述正常显示区的像素密度；其中，第一拉伸区中子像素单元在所述衬底基板正投影与所述镂空开口在所述衬底基板正投影不交叠。
本公开一种示例性实施例中，所述显示面板还包括位于显示区周边的边框区，所述拉伸区还包括第二拉伸区，第二拉伸区位于所述边框区。
本公开一种示例性实施例中，所述显示面板还包括过渡区，过渡区位于所述第一 拉伸区和所述正常显示区之间的显示区，所述过渡区的像素密度小于所述正常显示区的像素密度；其中，所述过渡区集成有栅极驱动电路，所述栅极驱动电路用于向所述过渡区中的子像素单元以及与所述过渡区中子像素单元同行的子像素单元提供驱动信号；所述过渡区中子像素单元在所述衬底基板的正投影与所述栅极驱动电路在所述衬底基板的正投影不交叠。
本公开一种示例性实施例中，所述栅极驱动电路包括：第一栅极驱动电路、第二栅极驱动电路。第一栅极驱动电路用于向所述子像素单元提供栅极驱动信号；第二栅极驱动电路用于向所述子像素单元提供使能信号。
本公开一种示例性实施例中，所述显示面板为一圆角矩形，所述拉伸区为四个，四个所述拉伸区分别为位于所述圆角矩形四个圆角区域。
本公开一种示例性实施例中，所述第一拉伸区、所述第二拉伸区、过渡区为同心扇形，所述第一拉伸区位于所述第二拉伸区面向其所在圆圆心的一侧，所述过渡区位于所述第一拉伸区面向其所在圆圆心的一侧。
本公开一种示例性实施例中，在所述正常显示区中：
R像素开口、G像素开口、B像素开口沿同一像素开口行依次交替分布，且在同一像素开口行中，R像素开口和B像素开口之间设置有两个沿列方向分布的G像素开口，在相邻像素开口行中，同一颜色的像素开口不位于同一列，且在相间隔一像素开口行的两像素开口行中，同一颜色的像素开口位于同一列。
本公开一种示例性实施例中，在所述第一拉伸区、过渡区中：
所述显示面板包括多个阵列分布的像素岛，所述镂空开口在所述衬底基板正投影位于所述像素岛在所述衬底基板正投影之间；所述栅极驱动电路在所述衬底基板正投影位于所述像素岛在所述衬底基板正投影之间。
本公开一种示例性实施例中，每个所述像素岛包括：位于第一像素开口行且相邻设置的B像素开口和R像素开口、位于第二像素行且沿列方向分布的两个G像素开口、位于第三像素开口行且相邻设置的B像素开口和R像素开口；其中，第二像素开口行位于所述第一像素开口行和第三像素开口行之间，且相同颜色像素开口位于同一列，不同颜色像素开口位于不同列。
本公开一种示例性实施例中，所述像素岛包括位于同一像素开口行的R像素开口、G像素开口、B像素开口，且在同一像素开口行中，所述R像素开口和所述G像素开口沿列方向分布。
本公开一种示例性实施例中，所述正常显示区采用GGRB算法驱动；所述第一拉伸区、过渡区中采用真RGB算法驱动。
本公开一种示例性实施例中，所述子像素单元包括发光单元和用于向所述发光单元提供驱动电流的像素驱动电路，在所述第一拉伸区、过渡区中，所述像素驱动电路的长宽比为3：1；在所述正常显示区中，所述像素驱动电路的长宽比为2：1。
本公开一种示例性实施例中，所述像素驱动电路包括驱动晶体管和连接于所述驱动晶体管栅极的电容。所述第一拉伸区、过渡区中像素驱动电路包括：第一导电部，第一导电部位于第一栅极层，用于形成所述驱动晶体管的栅极和电容的第一电极。所述正常显示区中像素驱动电路包括：第二导电部，第二导电部位于所述第一栅极层，用于形成所述驱动晶体管的栅极和电容的第一电极。其中，所述第一导电部在行方向尺寸与列方向尺寸的比值小于所述第二导电部在行方向尺寸与列方向尺寸的比值，所述行方向为所述像素驱动电路的宽度方向，所述列方向为所述像素驱动电路的长度方向。
本公开一种示例性实施例中，所述像素驱动电路包括驱动晶体管，第二晶体管，所述第二晶体管的第二端连接所述驱动晶体管的栅极，且所述第二晶体管为双沟道结构。所述正常显示区中像素驱动电路包括：第一有源部、第一遮挡部，第一有源部位于有源层，所述第一有源部连接于所述第二晶体管的两沟道之间；第一遮挡部位于第二栅极层，且连接稳定电压源，所述第一遮挡部在所述衬底基板正投影沿行方向延伸，所述第一遮挡部在所述衬底基板正投影和与其相邻的像素驱动电路中第一有源部在所述衬底基板正投影至少部分重合。所述第一拉伸区、过渡区中像素驱动电路包括：第二有源部、第三有源部、第二遮挡部，第二有源部位于有源层，所述第二有源部连接于所述第二晶体管的两沟道之间；第三有源部连接所述驱动晶体管的栅极；第二遮挡部位于第二栅极层，且连接稳定电压源，所述第二遮挡部包括相连接的第一子遮挡部和第二子遮挡部，所述第一子遮挡部在所述衬底基板正投影沿列方向延伸，所述第二子遮挡部在所述衬底基板正投影沿行方向延伸；其中，所述第一子遮挡部在所述衬底基板正投影与所述第三有源部在所述衬底基板正投影至少部分重合，第二子遮挡部在所述衬底基板正投影和与其相邻的像素驱动电路中第二有源部在所述衬底基板正投影至少部分重合。
根据本公开的一个方面，提供一种显示装置，该显示装置包括上述的显示面板。
本公开提出一种显示面板、显示装置，该显示面板包括阵列基板和封装于所述阵列基板一侧的封装层，所述显示面板还包括拉伸区，该拉伸区位于所述显示面板的边角区域，所述拉伸区设置有贯穿所述阵列基板和所述封装层的镂空开口。本公开提供的显示面板在拉伸区设置有贯穿阵列基板和封装层的镂空开口，一方面，该镂空开口可以提高了显示面板拉伸区的弯折能力和拉伸能力，从而避免拉伸区弯折时断裂损害；另一方面，该镂空开口可以提供拉伸区弯折时褶皱的容纳空间，从而避免拉伸区弯折时出现褶皱。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开显示面板一种示例性实施例的结构示意图；
图2为图1中虚线A-A的剖视图；
图3为本公开显示面板一种示例性实施例中边角区域的剖视图；
图4为本公开显示面板一种示例性实施例中像素开口的分布图；
图5为本公开显示面板另一种示例性实施例中像素开口的分布图；
图6为本公开显示面板一种实施例实施例中像素驱动电路的电路结构示意图；
图7为图6中像素驱动电路各节点的时序图；
图8为本公开显示面板一种实施例实施例中正常显示区中像素驱动电路的结构示意图；
图9为本公开显示面板一种实施例实施例中第一拉伸区中像素驱动电路的结构示意图；
图10为本公开显示面板另一种示例性实施例的结构示意图。
具体实施方式
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施例使得本公开将更加全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。其他相对性的用语，例如“高”“低”“顶”“底”“左”“右”等也作具有类似含义。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“所述”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。
本示例性实施例提供一种显示面板，如图1、2所示，图1为本公开显示面板一种示例性实施例的结构示意图，图2为图1中虚线A-A的剖视图。该显示面板包括阵列基板1和封装于所述阵列基板一侧的封装层2，所述显示面板还包括拉伸区3，拉伸区3位于所述显示面板的边角区域，且至少部分位于所述显示面板的显示区41，所述拉 伸区3设置有贯穿所述阵列基板1和所述封装层2的镂空开口5。
本公开提供的显示面板在拉伸区设置有贯穿阵列基板和封装层的镂空开口，一方面，该镂空开口可以提高了显示面板拉伸区的弯折能力和拉伸能力，从而避免拉伸区弯折时断裂损害；另一方面，该镂空开口可以提供拉伸区弯折时褶皱的容纳空间，从而避免拉伸区弯折时出现褶皱。
应该理解的是，在其他示例性实施例中，该显示面板还可以仅在阵列基板上开设镂空开口，封装层上不设置镂空开口。
本示例性实施例中，显示面板的边角区域可以指显示面板的两边的相交位置，该两相交边位置可以为直角连接也可以为圆角连接。如图1所示，该显示面板可以为一圆角矩形，所述拉伸区3可以为四个，四个所述拉伸区3可以分别位于所述圆角矩形四个圆角区域。应该理解的是，在其他示例性实施例中，该显示面板还可以为异形显示面板，例如，该显示面板可以为六边形，相应的，该显示面板可以包括六个拉伸区，六个拉伸区可以分别设置于六边形的六个边角区域，该拉伸区3还可以为其他形状。
本示例性实施例中，如图1所示，所述显示面板还可以包括位于所述显示区41的正常显示区411，如图3所示，为本公开显示面板一种示例性实施例中边角区域的剖视图，所述阵列基板1可以包括衬底基板11以及位于所述衬底基板11面向封装层2一侧的功能层12，功能层12中设置有多个子像素单元121，所述拉伸区3包括第一拉伸区31，第一拉伸区31位于所述显示区41，所述第一拉伸区31的像素密度小于所述正常显示区411的像素密度；其中，在第一拉伸区31中的子像素单元121在所述衬底基板11正投影与所述镂空开口5在所述衬底基板11正投影不交叠。该第一拉伸区31中设置有子像素单元，即该第一拉伸区31可以实现显示功能。在形成四曲面屏显示面板时，该第一拉伸区31发生弯折，从而该显示面板可以呈现一种正面侧面同时显示的全面立体显示效果。其中，功能层可以包括晶体管TFT层，像素定义层、发光单元层等。
需要说明的是，所述子像素单元121在所述衬底基板11正投影与所述镂空开口5在所述衬底基板11正投影不交叠，从而可以避免贯穿阵列基板和封装层的镂空开口5对子像素单元121造成影响。同时，本示例性实施例将所述第一拉伸区31的像素密度设置为小于所述正常显示区411的像素密度，从而可以在第一拉伸区31中预留出用于设置镂空开口5的空间。应该理解的是，在其他示例性实施例中，也可以通过其他方式预留用于设置镂空开口5的空间，例如，可以通过减小第一拉伸区31中子像素单元的面积以预留出用于设置镂空开口5的空间。
本示例性实施例中，如图1所示，所述显示面板还可以包括位于显示区41周边的边框区42，所述拉伸区3还可以包括第二拉伸区32，第二拉伸区32位于所述边框区42。第二拉伸区32内可以不设置子像素单元，第二拉伸区32仅用于实现显示面板边框弯折。
本示例性实施例中，正常显示区和第一拉伸区具有不同的像素密度，相应的，正常显示区和第一拉伸区具有不同的像素开口分布。如图4所示，为本公开显示面板一种示例性实施例中像素开口的分布图。在所述正常显示区中：R像素开口81、G像素开口82、B像素开口83沿同一像素开口行依次交替分布，且在同一像素开口行中，R像素开口81和B像素开口83之间设置有两个沿列方向分布的G像素开口82，在相邻像素开口行中，同一颜色的像素开口不位于同一列，且在相间隔一像素开口行的两像素开口行中，同一颜色的像素开口位于同一列。
本示例性实施例中，如图4所示，在所述第一拉伸区：所述显示面板可以包括多个阵列分布的像素岛9，所述镂空开口5在所述衬底基板正投影可以位于相邻所述像素岛9在所述衬底基板正投影之间。其中，如图4所示，本示例性实施例中，每个所述像素岛9可以包括：位于第一像素开口行且相邻设置的B像素开口83和R像素开口81、位于第二像素行且沿列方向分布的两个G像素开口82、位于第三像素开口行且相邻设置的B像素开口83和R像素开口81；其中，第二像素开口行位于所述第一像素开口行和第三像素开口行之间，且相同颜色像素开口位于同一列，不同颜色像素开口位于不同列。如图4所示，本示例性实施例中，第一拉伸区和正常显示区中的像素开口具有相同的形状、大小，第一拉伸区31中像素开口与正常显示区411中像素开口的区别仅在于，在第一拉伸区31中，部分位置没有设置像素开口，因此，该显示面板在像素定义层上通过高精度金属掩膜版蒸镀发光单元的各个有机层时，可以通过各个位置开口形状、开口密度完全相同的高精度金属掩膜版蒸镀正常显示区和第一拉伸区中的发光单元，该设置可以提高了高精度金属掩膜版张网时各个区域应力的均一性。
在图4中镂空开口5的分布方式为“十”字型，应该理解的是，在其他示例性实施例中，镂空开口5的分布还可以为其他方式，例如，工字型、王字型等。
需要说明的是，该显示面板虽然通过开口形状、开口密度相同的高精度金属掩膜版蒸镀，但是在第一拉伸区中，蒸镀的有机层也只能在像素开口位置形成能够发光的发光单元。在第一拉伸区31中，像素开口位置设置有裸露于像素定义层之外的阳极，因此，在像素开口位置蒸镀的有机层可以形成与阳极连接的发光单元，未设置像素开口的区域未裸露出阳极，或设置有镂空开口，因此，像素开口以外区域不能形成能够发光的发光单元。
如图4所示，正常显示区411中的子像素单元可以采用GGRB算法驱动，即R子像素可以与左侧的一个B子像素和G子像素形成一个像素单元，R子像素还可以与右侧的一个B子像素和G子像素形成另一个像素单元；同理，即B子像素可以与左侧的一个R子像素和G子像素形成一个像素单元，B子像素还可以与右侧的一个R子像素和G子像素形成另一个像素单元。该驱动方法可以提高显示面板的分辨率。
如图4所示，第一拉伸区31中的子像素单元可以采用真RGB算法驱动，即每个R、G、B子像素仅形成一个像素单元。需要说明的是，由于GGRB算法中，R和B 子像素共用，正常显示区中G子像素数量是R和B子像素的2倍；而真RGB算法中的像素单元不共用子像素单元，第一拉伸区31中RGB三种子像素数量相同。因此，第一拉伸区31中G子像素的数量是正常显示区中G子像素的一半，相应的，在驱动第一拉伸区31中的子像素单元时，需要提高G子像素的驱动电压。该方案可以通过设计IC算法实现，也可以通过不同的IC分别驱动正常显示区411和第一拉伸区31的子像素单元实现。
如图4所示，正常显示区411采用GGRB算法驱动子像素单元，每个R、B子像素公共为两个像素单元，因此，每个方形的像素单元中仅需要设置两个子像素。然而，第一拉伸区31采用真RGB算法驱动，每个方形的像素单元中需要设置三个子像素。因此，在所述第一拉伸区中，所述像素单元的长宽比为3：1，在所述正常显示区中像素单元的长宽比为2：1。其中，该显示面板可以为顶发射显示面板，在顶发射显示面板中，像素开口在衬底基板的正投影位于像素驱动电路在衬底基板的正投影上，该显示面板中像素单元的长宽比即为像素驱动电路的长宽比。因此，在所述第一拉伸区中，像素驱动电路的长宽比为3：1，在所述正常显示区中像素驱动电路的长宽比为2：1。
本示例性实施例中，如图4所示，为在像素岛9之间设置预留空白位置以设置镂空开口5，需要将两个G像素开口82设置于相邻行R像素开口、B像素开口之间，然而，该设置导致了横向像素亮度中心偏移，失去画面均衡感，同时导致上下边缘色偏反转，斜线方向产生锯齿感，且该技术问题无法通过算法补偿。如图5所示，为本公开显示面板另一种示例性实施例中像素开口的分布图。所述像素岛可以包括位于同一像素开口行的R像素开口81、G像素开口82、B像素开口83，且在同一像素开口行中，所述R像素开口和所述G像素开口沿列方向分布。该设置可以避免上述的“横向像素亮度中心偏移，失去画面均衡感，上下边缘色偏反转，斜线方向产生锯齿感”的技术问题。应该理解的是，在其他示例性实施例中，像素岛还可以有其他的像素开口分布方式，这些都属于本公开的保护范围。
如图6、7、8、9所示，图6为本公开显示面板一种实施例实施例中像素驱动电路的电路结构示意图，图7为图6中像素驱动电路各节点的时序图，图8为本公开显示面板一种实施例实施例中正常显示区中像素驱动电路的结构示意图，图9为本公开显示面板一种实施例实施例中第一拉伸区中像素驱动电路的结构示意图。图9中像素驱动电路的长宽比为3：1，图8中像素驱动电路的长宽比为2：1。
如图6、8、9所示，该像素驱动电路为7T1C结构，其中，第四晶体管T4第一端连接数据信号端Vdata，第二端连接第二节点N2，栅极连接栅极驱动信号端Gate；第五晶体管T5第一端连接第二节点N2，第二端连接第一电源端VDD，栅极连接使能信号端EM，第三晶体管T3第一端连接第二节点N2，第二端连接第三节点N3，栅极连接第一节点N1；第二晶体管T2第一端连接第三节点N3，第二端连接第一节点N1，栅极连接栅极驱动信号端Gate；第一晶体管T1第一端连接第一节点N1，第二端连接 初始化信号端Vint，栅极连接复位信号端Re，第六晶体管T6第一端连接第三节点N3，第二端连接第四节点N4，栅极连接使能信号端EM；第七晶体管T7第一端连接初始化信号端Vint，第二端连接第四节点N4，栅极连接复位信号端Re，该像素驱动电路还可以包括发光单元OLED，发光单元OLED连接于第四节点和第二电源端VSS之间。
如图7所示，该像素驱动电路的驱动方法包括三个阶段：复位阶段T1、阈值写入阶段T2、发光阶段T3。在复位阶段T1，复位信号端Re输出低电平信号，使能信号端EM、栅极驱动信号端Gate输出高电平信号，第一晶体管T1、第七晶体管T7导通，初始化信号端Vint向第四节点N4、第一节点N1输入初始化信号。在阈值写入阶段T2，栅极驱动信号端Gate输出低电平信号，使能信号端EM、复位信号端Re输出高电平信号，数据信号端向第一节点N1写入包括第三晶体管T3阈值的电压，在发光阶段，使能信号端EM输出低电平信号，发光单元发光。
如图8、9所示，该显示面板可以包括依次层叠设置的衬底基板、有源层、第一栅极层、第二栅极层、源漏层。其中，有源层可以用于形成各个晶体管的沟道区。第一栅极层可以包括用于提供复位信号端的复位信号线Re、用于提供栅极驱动信号端的栅极驱动信号线Gate、用于提供使能信号端的使能信号线EM、电容C的第一电极。第二栅极层可以包括用于提供初始信号端的初始信号线Vinit，电容C的第二电极。源漏层可以包括用于提供第一电源端的电源线VDD、用于提供数据信号端的数据线Data。
如图9所示，本示例性实施例中，所述第一拉伸区中像素驱动电路可以包括第一导电部11，第一导电部11可以位于第一栅极层，用于形成所述驱动晶体管的栅极和电容的第一电极。如图8所示，所述正常显示区中像素驱动电路可以包括：第二导电部12，第二导电部12位于所述第一栅极层，用于形成所述驱动晶体管的栅极和电容的第一电极。其中，所述第一导电部11在行方向尺寸与列方向尺寸的比值小于所述第二导电部12在行方向尺寸与列方向尺寸的比值，所述行方向为所述像素驱动电路的宽度方向，所述列方向为所述像素驱动电路的长度方向。
如图8所示，所述正常显示区中像素驱动电路包括：第一有源部51、第一遮挡部21，第一有源部51位于有源层，所述第一有源部51连接于所述第二晶体管的两沟道之间；第一遮挡部21位于第二栅极层，且连接稳定电压源，例如，第一遮挡部21可以通过过孔(白色方孔)连接电源线VDD。所述第一遮挡部21在所述衬底基板正投影可以沿行方向延伸，所述第一遮挡部21在所述衬底基板正投影和与其相邻的像素驱动电路中第一有源部51在所述衬底基板正投影至少部分重合，即图8中的第一遮挡部21可以用于遮挡位于其左侧像素驱动电路中的第一有源部51。该第一遮挡部21可以对第一有源部51起到稳压作用，以避免悬浮状态的第一有源部51与第二晶体管的源漏极之间产生电流，从而进一步稳定在发光阶段驱动晶体管栅极的电压。
如图9所示，所述第一拉伸区中像素驱动电路包括：第二有源部52、第三有源部53、第二遮挡部22，第二有源部52位于有源层，所述第二有源部52连接于所述第二 晶体管的两沟道之间；第三有源部53连接所述驱动晶体管的栅极；第二遮挡部位于第二栅极层，且连接稳定电压源，例如，第二遮挡部可以通过过孔(白色方孔)连接电源线VDD。所述第二遮挡部可以包括相连接的第一子遮挡部221和第二子遮挡部222，所述第一子遮挡部221在所述衬底基板正投影沿列方向延伸，所述第二子遮挡部222在所述衬底基板正投影沿行方向延伸；其中，所述第一子遮挡部221在所述衬底基板正投影与所述第三有源部53在所述衬底基板正投影至少部分重合，第二子遮挡部222在所述衬底基板正投影和与其相邻的像素驱动电路中第二有源部52在所述衬底基板正投影至少部分重合，即图9中第二子遮挡部222可以用于遮挡位于其左侧像素驱动电路中的第二有源部52。第一子遮挡部221可以对驱动晶体管栅极起到稳压作用，第二子遮挡部222可以对第二有源部52起到稳压作用。
本示例性实施例中，如图1所示，所述显示面板还包括过渡区6，过渡区6位于所述第一拉伸区31和所述正常显示区411之间的显示区，所述过渡区6的像素密度可以小于所述正常显示区411的像素密度。其中，如图10所示，为本公开显示面板另一种示例性实施例的结构示意图。所述过渡区6集成有栅极驱动电路7，所述栅极驱动电路7可以用于向所述过渡区6中的子像素单元以及与所述过渡区6中子像素单元同行的子像素单元提供驱动信号，例如，位于过渡区6的栅极驱动电路7分别可以向第一拉伸区31和正常显示区411中子像素单元提供驱动信号。所述过渡区6中子像素单元在所述衬底基板的正投影与所述栅极驱动电路在所述衬底基板的正投影不交叠。其中，将所述过渡区6的像素密度设置为小于所述正常显示区411的像素密度，从而可以在渡区6中预留出用于设置栅极驱动电路的空间。将所述过渡区6中子像素单元在所述衬底基板的正投影与所述栅极驱动电路在所述衬底基板的正投影设置为不交叠，从而避免栅极驱动电路对像素单元的影响。过渡区6中像素开口的分布、像素驱动电路的电路结构、像素单元的结构、形状可以与第一拉伸区31相同。所述栅极驱动电路在所述衬底基板正投影可以位于所述像素岛在所述衬底基板正投影之间。
本示例性实施例中，如图10所示，所述栅极驱动电路7可以包括：第一栅极驱动电路71、第二栅极驱动电路72。第一栅极驱动电路71可以用于向所述子像素单元Pix提供栅极驱动信号；第二栅极驱动电路72可以用于向所述子像素单元Pix提供使能信号。
本示例性实施例中，如图1所示，所述第一拉伸区31、所述第二拉伸区32、过渡区6可以为同心扇形，所述第一拉伸区31位于所述第二拉伸区32面向其所在圆圆心的一侧，所述过渡区6可以位于所述第一拉伸区31面向其所在圆圆心的一侧。该扇形拉伸区过其圆形的中分线可以经过其所在边角区域处两相交边的交点。将所述第一拉伸区31、所述第二拉伸区32、过渡区6设置为扇形，可以在实现其功能的前提下，极大减小第一拉伸区31、所述第二拉伸区32、过渡区6的面积。应该理解的是，在其他示例性实施例中，所述第一拉伸区31、所述第二拉伸区32、过渡区6可以为其他形状， 例如，所述第一拉伸区31、所述第二拉伸区32、过渡区6可以为梯形、矩形等。
本示例性实施例还提供一种显示装置，该显示装置包括上述的显示面板。该显示装置可以为手机、电视、平板电脑等显示装置。
本领域技术人员在考虑说明书及实践这里公开的内容后，将容易想到本公开的其他实施例。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限定。

Claims (17)

  1. 一种显示面板，其中，包括阵列基板，以及显示区，所述显示面板还包括：
    拉伸区，位于所述显示面板的边角区域，且至少部分位于所述显示面板的显示区，所述拉伸区设置有贯穿所述阵列基板的镂空开口。
  2. 根据权利要求1所述的显示面板，其中，所述显示面板还包括封装于所述阵列基板一侧的封装层，所述镂空开口贯穿所述封装层。
  3. 根据权利要求1所述的显示面板，其中，所述显示面板还包括位于所述显示区的正常显示区，所述阵列基板包括衬底基板和位于所述衬底基板面向封装层一侧的功能层，所述功能层内形成有子像素单元，所述拉伸区包括：
    第一拉伸区，位于所述显示区，所述第一拉伸区的像素密度小于所述正常显示区的像素密度；
    其中，第一拉伸区中子像素单元在所述衬底基板正投影与所述镂空开口在所述衬底基板正投影不交叠。
  4. 根据权利要求3所述的显示面板，其中，所述显示面板还包括位于显示区周边的边框区，所述拉伸区还包括：
    第二拉伸区，位于所述边框区。
  5. 根据权利要求4所述的显示面板，其中，所述显示面板还包括：
    过渡区，位于所述第一拉伸区和所述正常显示区之间的显示区，所述过渡区的像素密度小于所述正常显示区的像素密度；
    其中，所述过渡区集成有栅极驱动电路，所述栅极驱动电路用于向所述过渡区中的子像素单元以及与所述过渡区中子像素单元同行的子像素单元提供驱动信号；
    其中，所述过渡区中子像素单元在所述衬底基板的正投影与所述栅极驱动电路在所述衬底基板的正投影不交叠。
  6. 根据权利要求5所述的显示面板，其中，所述栅极驱动电路包括：
    第一栅极驱动电路，用于向所述子像素单元提供栅极驱动信号；
    第二栅极驱动电路，用于向所述子像素单元提供使能信号。
  7. 根据权利要求5所述的显示面板，其中，所述显示面板为一圆角矩形，所述拉伸区为四个，四个所述拉伸区分别位于所述圆角矩形四个圆角区域。
  8. 根据权利要求7所述的显示面板，其中，
    所述第一拉伸区、所述第二拉伸区、过渡区为同心扇形，所述第一拉伸区位于所 述第二拉伸区面向其所在圆圆心的一侧，所述过渡区位于所述第一拉伸区面向其所在圆圆心的一侧。
  9. 根据权利要求5所述的显示面板，其中，在所述正常显示区中：
    R像素开口、G像素开口、B像素开口沿同一像素开口行依次交替分布，且在同一像素开口行中，R像素开口和B像素开口之间设置有两个沿列方向分布的G像素开口，在相邻像素开口行中，同一颜色的像素开口不位于同一列，且在相间隔一像素开口行的两像素开口行中，同一颜色的像素开口位于同一列。
  10. 根据权利要求9所述的显示面板，其中，在所述第一拉伸区、过渡区中：
    所述显示面板包括多个阵列分布的像素岛，所述镂空开口在所述衬底基板正投影位于相邻所述像素岛在所述衬底基板正投影之间；
    所述栅极驱动电路在所述衬底基板正投影位于相邻所述像素岛在所述衬底基板正投影之间。
  11. 根据权利要求10所述的显示面板，其中，
    每个所述像素岛包括：位于第一像素开口行且相邻设置的B像素开口和R像素开口、位于第二像素行且沿列方向分布的两个G像素开口、位于第三像素开口行且相邻设置的B像素开口和R像素开口；
    其中，第二像素开口行位于所述第一像素开口行和第三像素开口行之间，且相同颜色像素开口位于同一列，不同颜色像素开口位于不同列。
  12. 根据权利要求10所述的显示面板，其中，
    所述像素岛包括位于同一像素开口行的R像素开口、G像素开口、B像素开口，且在同一像素开口行中，所述R像素开口和所述G像素开口沿列方向分布。
  13. 根据权利要求11或12所述的显示面板，其中，
    所述正常显示区采用GGRB算法驱动；
    所述第一拉伸区、过渡区采用真RGB算法驱动。
  14. 根据权利要求13所述的显示面板，其中，所述子像素单元包括发光单元和用于向所述发光单元提供驱动电流的像素驱动电路，在所述第一拉伸区、过渡区中，所述像素驱动电路的长宽比为3：1；
    在所述正常显示区中，所述像素驱动电路的长宽比为2：1。
  15. 根据权利要求14所述的显示面板，其中，所述显示面板还包括位于所述衬底基板一侧的第一栅极层，所述像素驱动电路包括驱动晶体管和连接于所述驱动晶体 管栅极的电容；
    所述第一拉伸区、过渡区中像素驱动电路包括：
    第一导电部，位于第一栅极层，用于形成所述驱动晶体管的栅极和电容的第一电极；
    所述正常显示区中像素驱动电路包括：
    第二导电部，位于所述第一栅极层，用于形成所述驱动晶体管的栅极和电容的第一电极；
    其中，所述第一导电部在行方向尺寸与列方向尺寸的比值小于所述第二导电部在行方向尺寸与列方向尺寸的比值，所述行方向为所述像素驱动电路的宽度方向，所述列方向为所述像素驱动电路的长度方向。
  16. 根据权利要求14所述的显示面板，其中，所述显示面板还包括有源层、第二栅极层，所述有源层位于所述衬底基板的一侧，所述第二栅极层位于所述有源层背离所述衬底基板的一侧，所述像素驱动电路包括驱动晶体管，第二晶体管，所述第二晶体管的第二端连接所述驱动晶体管的栅极，且所述第二晶体管为双沟道结构；
    所述正常显示区中像素驱动电路包括：
    第一有源部，位于有源层，所述第一有源部连接于所述第二晶体管的两沟道之间；
    第一遮挡部，位于第二栅极层，且连接稳定电压源，所述第一遮挡部在所述衬底基板正投影沿行方向延伸，所述第一遮挡部在所述衬底基板正投影和与其相邻的像素驱动电路中第一有源部在所述衬底基板正投影至少部分重合；
    所述第一拉伸区、过渡区中像素驱动电路包括：
    第二有源部，位于有源层，所述第二有源部连接于所述第二晶体管的两沟道之间；
    第三有源部，连接所述驱动晶体管的栅极；
    第二遮挡部，位于第二栅极层，且连接稳定电压源，所述第二遮挡部包括相连接的第一子遮挡部和第二子遮挡部，所述第一子遮挡部在所述衬底基板正投影沿列方向延伸，所述第二子遮挡部在所述衬底基板正投影沿行方向延伸；
    其中，所述第一子遮挡部在所述衬底基板正投影与所述第三有源部在所述衬底基板正投影至少部分重合，第二子遮挡部在所述衬底基板正投影和与其相邻的像素驱动电路中第二有源部在所述衬底基板正投影至少部分重合。
  17. 一种显示装置，其中，包括权利要求1-16任一项所述的显示面板。
PCT/CN2021/095316 2020-05-26 2021-05-21 显示面板、显示装置 WO2021238814A1 (zh)

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