WO2022165658A9 - 显示基板和显示装置 - Google Patents

显示基板和显示装置 Download PDF

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Publication number
WO2022165658A9
WO2022165658A9 PCT/CN2021/074979 CN2021074979W WO2022165658A9 WO 2022165658 A9 WO2022165658 A9 WO 2022165658A9 CN 2021074979 W CN2021074979 W CN 2021074979W WO 2022165658 A9 WO2022165658 A9 WO 2022165658A9
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Prior art keywords
transistor
pole
gate
driving
node
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PCT/CN2021/074979
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English (en)
French (fr)
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WO2022165658A1 (zh
Inventor
韩龙
王品凡
曹方旭
李文强
刘利宾
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/615,489 priority Critical patent/US20230169900A1/en
Priority to PCT/CN2021/074979 priority patent/WO2022165658A1/zh
Priority to EP21923686.6A priority patent/EP4148801A4/en
Priority to CN202180000148.3A priority patent/CN115280508A/zh
Publication of WO2022165658A1 publication Critical patent/WO2022165658A1/zh
Publication of WO2022165658A9 publication Critical patent/WO2022165658A9/zh

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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/03—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes specially adapted for displays having non-planar surfaces, e.g. curved displays
    • G09G3/035—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes specially adapted for displays having non-planar surfaces, e.g. curved displays for flexible display surfaces
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
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    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
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    • H10K59/131—Interconnections, e.g. wiring lines or terminals
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Definitions

  • Embodiments of the present disclosure relate to a display substrate and a display device.
  • the four-curved screen design is widely used in smart electronic products such as mobile phones and tablet computers.
  • the four-curved screen design is combined with 3D cover glass lamination technology to bend the edges or corners of the display substrate according to a certain bending radius and form a radian to achieve a comprehensive three-dimensional display on the front and sides, thereby realizing the four-curved surface.
  • 3D stereoscopic effect which can create a three-dimensional immersive display, which is in line with the future technology development trend.
  • Embodiments of the present disclosure provide a display substrate and a display device.
  • the display substrate provides a GIP (Gate in Pixel) design, that is, the display substrate provides a transition area between a high pixel density area and a low pixel density area, and sets a row drive circuit in the transition area, such as a gate drive circuit (GOA), so that The high pixel density area and the low pixel density area on both sides of the transition area are driven for display.
  • GIP Gate in Pixel
  • At least one embodiment of the present disclosure provides a display substrate, which includes: a first display area; a second display area located on at least one side of the first display area in a first direction; and a transition area located on the first display area.
  • the first display area, the second display area, and the transition area are provided with a plurality of pixels, and the plurality of pixels are arranged along the first direction and the The second direction intersecting the first direction is arranged in an array, the pixel density of the first display area is greater than the pixel density of the second display area and the pixel density of the transition area, and the transition area is also provided with row A driving circuit, the row driving circuit is configured to drive the plurality of pixels in the first display area, the second display area and the transition area by row.
  • the row driving circuit includes a plurality of row driving circuit units arranged along the second direction.
  • each of the pixels includes a plurality of sub-pixels, each of the sub-pixels includes a pixel driving circuit and a driving electrode electrically connected to the pixel driving circuit, and the transition region It includes: a plurality of pixel circuit islands, each of the pixel circuit islands is provided with a plurality of the pixel driving circuits of at least one pixel; a plurality of first intervals, each of the first intervals is located in the first between two adjacent pixel circuit islands in a direction; and at least one driving spacer, each of which is also located between two adjacent pixel circuit islands in the first direction, The driving spacer is provided with the row driving circuit unit.
  • the transition region further includes: a plurality of driving electrode islands, which are arranged corresponding to the plurality of pixel circuit islands, and each of the driving electrode islands is provided with at least one of the a plurality of the driving electrodes of a pixel; and a plurality of second spacers, each of the second spacers is located between two of the driving electrode islands adjacent in the first direction.
  • the widths of the plurality of first spacers in the first direction are equal, and the widths of the plurality of second spacers in the first direction are Equally, the width of the first spacer in the first direction is smaller than the width of the driving spacer in the first direction.
  • the widths of the plurality of first spacers in the first direction are equal, and the widths of the plurality of second spacers in the first direction are equal, the width of the second spacer in the first direction is 0.5-1.5 times the width of the drive space, and the width of the first spacer in the first direction is smaller than the drive space width in the first direction.
  • the row driving circuit unit includes a first row driving circuit unit and a second row driving circuit unit, the first row driving circuit unit has an output terminal, and the second row driving circuit unit The output end of a row driving circuit unit is configured to simultaneously drive a plurality of pixels belonging to the same row in the first display area, the second display area and the transition area.
  • the display substrate provided by an embodiment of the present disclosure further includes: a plurality of connection electrode structures located on a side of the plurality of driving electrode islands close to the pixel circuit island in a direction perpendicular to the transition region, the A plurality of connecting electrode structures are provided in one-to-one correspondence with the plurality of driving electrode islands and the plurality of pixel circuit islands, and each of the connecting electrode structures includes a plurality of connecting electrodes, so as to connect the corresponding pixel circuit islands to A plurality of the pixel driving circuits are electrically connected to a plurality of the driving electrodes in the corresponding driving electrode islands.
  • the pixel driving unit includes a driving transistor, and the driving transistor is disposed on a film layer corresponding to the driving electrode at an orthographic projection and spaced from the corresponding driving electrode.
  • the row drive circuit includes a gate drive circuit and a light emission control drive circuit
  • the row drive circuit unit includes a gate drive unit and a light emission control unit
  • the region includes two driving spacers, one of the two driving spacers is provided with the gate driving unit, and the other of the two driving spacers is provided with the light emission control unit.
  • At least two first spacers are spaced between two driving spacers.
  • the light emission control unit includes: a first transistor, the gate of the first transistor is connected to a first clock signal line to receive a first clock signal, and the first transistor The first pole of a transistor is connected to the first node, and the second pole of the first transistor is connected to the input terminal; for the second transistor, the gate of the second transistor is connected to the first node, and the gate of the second transistor is connected to the first node.
  • the first pole is connected to the second node, the second pole of the second transistor is connected to the first clock signal line to receive the first clock signal; the third transistor, the gate of the third transistor is connected to the first clock signal line; A clock signal line is connected to receive the first clock signal, the first pole of the third transistor is connected to the second node, and the second pole of the third transistor is connected to the first power line to receive the first voltage; a fourth transistor, the gate of the fourth transistor is connected to the second clock signal line to receive the second clock signal, the first pole of the fourth transistor is connected to the first node, and the fourth transistor The second pole of the fifth transistor is connected to the second pole of the fifth transistor; the fifth transistor, the gate of the fifth transistor is connected to the second node, and the first pole of the fifth transistor is connected to the second power supply line connected to receive the second voltage; the sixth transistor, the first pole of the sixth transistor is connected to the second clock signal line to receive the second clock signal, the second pole of the sixth transistor is connected to the third node connection: a seventh transistor, the gate
  • the ninth transistor and the tenth transistor are disposed at intervals from the plurality of connection electrode structures in an orthographic projection on the film layer where the plurality of connection electrode structures are located.
  • the gate drive unit includes: an input transistor, a first control transistor, a second control transistor, an output control transistor, a gate output transistor, a first noise reduction transistor, a second Two noise reduction transistors, a voltage stabilizing transistor, a first scanning capacitor and a second scanning capacitor, the gate of the input transistor is connected to the third clock signal line, the second pole of the input transistor is connected to the input terminal, and the input
  • the first electrode of the transistor is connected to the first scanning node;
  • the gate of the first control transistor is connected to the first scanning node, the second electrode of the first control transistor is connected to the third clock signal line, and the The first pole of the first control transistor is connected to the second scanning node;
  • the gate of the second control transistor is connected to the third clock signal line, and the second pole of the second control transistor is connected to the third power supply line, so
  • the first pole of the second control transistor is connected to the second scan node;
  • the gate of the output control transistor is connected to the second scan node, and the first pole
  • the orthographic projection of the output control transistor and the gate output transistor on the film layer where the plurality of connection electrode structures are located is spaced apart from the plurality of connection electrode structures. set up.
  • the display substrate provided by an embodiment of the present disclosure further includes: a plurality of first driving lines configured to drive the plurality of gate driving units, the plurality of gate driving units are arranged in dislocations in the first direction, Each of the first driving lines includes a first portion extending along the second direction and a second portion extending along the first direction, the first portion is connected to the corresponding gate driving unit, and the second portion Connecting the first parts of two adjacent gate driving units.
  • the display substrate provided by an embodiment of the present disclosure further includes: a data line, the first part and the data line are located in the first source-drain metal layer, and the second part is located in the second source-drain metal layer.
  • each of the first driving lines is stepped.
  • the display substrate provided by an embodiment of the present disclosure further includes: a plurality of second drive lines configured to drive the plurality of light emission control units, the plurality of light emission control units are arranged in dislocations in the first direction,
  • Each of the second driving lines includes a third portion extending along the second direction and a fourth portion extending along the first direction, the third portion is connected to the corresponding light-emitting control unit, and the first The four parts connect the third parts of two adjacent lighting control units.
  • the display substrate provided by an embodiment of the present disclosure further includes a data line, the third part and the data line are located in the first source-drain metal layer, and the fourth part is located in the second source-drain metal layer.
  • each of the second driving lines is stepped.
  • the part of the display substrate located in the second display area is curved in a direction perpendicular to the first display area.
  • the display substrate provided by an embodiment of the present disclosure further includes: a third display area, located on one side of the first display area in the second direction, and a plurality of the pixels, the pixel density of the third display area is approximately equal to the pixel density of the first display area, and the orthographic projection of the third display area on the reference line extending along the first direction is the same as that of the first display area. Orthographic projections of the display area, the second display area, and the transition area on the reference line all overlap.
  • the second display area includes: a plurality of pixel islands arranged in an array along the first direction and the second direction, and each of the pixel islands includes at least one a pixel; a first opening extending along the first direction and located between two pixel islands adjacent in the second direction; and a second opening extending along the second direction and located between the two pixel islands adjacent in the second direction Between two adjacent pixel islands in the first direction.
  • At least one embodiment of the present disclosure further provides a display device, including the display substrate described in any one of the above.
  • FIG. 1A is a schematic plan view of a display substrate provided by an embodiment of the present disclosure
  • FIG. 1B is a schematic connection diagram of a row driving circuit in a display substrate provided by an embodiment of the present disclosure
  • FIG. 1C is a schematic diagram of a gate driving unit in a display substrate provided by an embodiment of the present disclosure
  • FIG. 1D is a schematic diagram of a lighting control unit in a display substrate provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic plan view of another display substrate provided by an embodiment of the present disclosure.
  • FIG. 3 is a schematic plan view of another display substrate provided by an embodiment of the present disclosure.
  • FIG. 4 is a schematic plan view of another display substrate provided by an embodiment of the present disclosure.
  • FIG. 5 is a schematic plan view of another display substrate provided by an embodiment of the present disclosure.
  • FIG. 6 is a schematic plan view of another display substrate provided by an embodiment of the present disclosure.
  • FIG. 7 is an equivalent schematic diagram of a pixel driving circuit in a display substrate provided by an embodiment of the present disclosure.
  • Fig. 8 is an equivalent circuit diagram of a lighting control unit provided by an embodiment of the present disclosure.
  • FIG. 9 is an equivalent circuit diagram of a gate driving unit provided by an embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of a second display area on a display substrate provided by an embodiment of the present disclosure.
  • FIG. 11 is a schematic plan view of a display substrate provided by an embodiment of the present disclosure.
  • the edges or corners of the display substrate can be bent according to a certain The radius is bent to achieve a four-curved screen design.
  • the greater the stretching amount of the stretchable structure located in the four corner regions the lower the pixel density of the four corner regions, that is, the low pixel density region.
  • the opening pattern of the stretchable structure needs to extend beyond the low pixel density area until the cutting line. Therefore, the gate driving circuit (GOA circuit) in the low pixel density area cannot be placed outside the pixel in a conventional manner.
  • inventions of the present disclosure provide a display substrate and a display device.
  • the display substrate includes a first display area; a second display area located on one side of the first display area in the first direction; and a transition area located between the first display area and the second display area, the first display area, the second display area
  • the second display area and the transition area are provided with a plurality of pixels, and the plurality of pixels are arranged in an array along the first direction and the second direction intersecting the second direction, and the pixel density of the first display area (that is, the high pixel density area) is higher than that of the second direction.
  • the pixel density of the second display area i.e.
  • the transition area is also provided with a row drive circuit, and the row drive circuit is configured to drive the first display area, the second display area and the transition area by row Multiple pixels in . Therefore, the display substrate provides a GIP (Gate in Pixel) design, that is, the display substrate provides a transition area between a high pixel density area and a low pixel density area, and sets a row drive circuit in the transition area, such as a gate drive circuit (GOA ), so as to drive the high pixel density area and the low pixel density area on both sides of the transition area for display.
  • GIP Gate in Pixel
  • FIG. 1A is a schematic plan view of a display substrate provided by an embodiment of the present disclosure.
  • the display substrate 100 includes a first display area 110, a second display area 120, and a transition area 130; the second display area 120 is located on at least one side of the first display area 110 in the first direction X, and the transition area 130 is located between the first display area 110 and the second display area 120 .
  • the first display area 110, the second display area 120, and the transition area 130 are provided with a plurality of pixels 210, and the plurality of pixels 210 are arranged in an array along the first direction and the second direction intersecting the second direction, that is to say, the plurality of Each pixel 210 forms multiple rows of pixels and multiple columns of pixels; the pixel density of the first display area 110 is greater than the pixel density of the second display area 120 and the pixel density of the transition area 130; the transition area 130 is also provided with a row driver circuit 220, the row driver The circuit 220 is configured to drive the plurality of pixels 210 in the first display area 110 , the second display area 120 and the transition area 130 row by row. It should be noted that a plurality of pixels are also arranged in the transition area provided by the embodiment of the present disclosure, and the transition area can be displayed together with the first display area and the second display area.
  • the first display area is a high pixel density area
  • the second display area is Areas of low pixel density.
  • a transition area is inserted between the high pixel density area and the low pixel density area, and a row driving circuit is arranged in the transition area, so that the row driving circuit in the transition area can be used to drive the first display area, the second display area by row.
  • Two display areas and multiple pixels in the transition area are displayed. Therefore, the display substrate does not need to provide an additional area for placing the row driving circuit outside the low pixel density area.
  • the frame width of the display substrate can be reduced; The problem that the row driving circuit cannot be arranged due to the opening pattern in the region.
  • the second display area 120 is located on both sides of the first display area 110 in the first direction, and two transition areas 130 are respectively located on the first display area 110 and the two second display areas 120 between.
  • the row driving circuit 220 includes a plurality of row driving circuit units 225 arranged along the second direction.
  • the row driving circuit 220 may be a gate driving circuit
  • the row driving circuit unit 225 may be a gate driving unit, that is, a GOA unit.
  • the driving circuit unit 225 includes a first row driving circuit unit 225A and a second row driving circuit unit 225B; the first row driving circuit unit 225A has an output respectively on both sides of the first direction. terminal OUT, so that the first row driving circuit unit 225A can simultaneously drive multiple pixels 210 belonging to the same row in the first display area 110, the second display area 120 and the transition area 130; The side close to the first display area 110 in the direction has an output terminal OUT, and the second row driving circuit unit 225 is configured to only drive a plurality of pixels 210 belonging to the same row in the first display area 110 .
  • the pixel density in the first display area 110 is greater than the pixel density in the second display area 120, so the number of rows of pixels 210 in the first display area 110 may be greater than that in the second display area. The case of the number of rows of pixels 210 in area 120 .
  • the row driving circuit unit 225 is configured to simultaneously drive the first display area 110, the second row driving circuit unit The plurality of pixels 210 belonging to the same row in the second display region 120 and the transition region 130, and the second row driving circuit unit 225 is configured to only drive the plurality of pixels 210 belonging to the same row in the first display region 110, which can be better Driving the pixels 210 in the first display area 110 and the second display area 120 having different pixel densities is realized.
  • FIG. 1B is a schematic connection diagram of a row driving circuit in a display substrate provided by an embodiment of the present disclosure.
  • the row driving circuit 220 includes a gate driving circuit 2202 and a light emitting control driving circuit 2204 ;
  • the row driving circuit unit 225 includes a gate driving unit 2252 and a light emitting control unit 2254 .
  • the gate drive circuit 2202 and the light emission control drive circuit 2204 are arranged in steps; a plurality of gate drive units 2252 can form a gate drive unit group 2252G, and then the plurality of gate drive unit groups 2252G in the first direction Orthographic projections are arranged at intervals, that is to say, a plurality of gate driving unit groups 2252G are arranged in dislocations in the first direction.
  • multiple gate driving units 2252 in one gate driving unit group 2252G can be cascaded with each other, and two adjacent gate driving unit groups 2252G are connected by connecting wires to transmit clock signals and other signals.
  • a plurality of light emission control units 2254 can form a light emission control unit group 2254G, and then the orthographic projections of the plurality of light emission control unit groups 2254G in the first direction are arranged at intervals, that is, the plurality of light emission control unit groups 2254G in the first direction Misaligned settings in one direction upwards.
  • multiple light emission control units 2254 in one light emission control unit group 2254G can be cascaded with each other, and two adjacent light emission control unit groups 2254G are connected by connecting wires to transmit clock signals and other signals.
  • FIG. 1C is a schematic diagram of a gate driving unit in a display substrate provided by an embodiment of the present disclosure
  • FIG. 1D is a schematic diagram of a light emission control unit in a display substrate provided by an embodiment of the present disclosure.
  • the output terminal of the gate driving unit 2252 is connected to the gate line 650A through a via hole 650H.
  • the two parts of the gate line 650A located on both sides of the via hole 650H can be equivalent to the two output terminals of the gate driving unit 2252.
  • OUT As shown in Figure 1D, the output terminal of the light emission control unit 2254 is connected to the light emission control line 660A through the via hole 660H. At this time, the two parts of the light emission control line 660A located on both sides of the via hole 660H can be equivalent to the two parts of the light emission control unit 2254.
  • Output terminal OUT is a schematic diagram of a gate driving unit in a display substrate provided by an embodiment of the present disclosure.
  • FIG. 2 is a schematic plan view of another display substrate provided by an embodiment of the present disclosure. As shown in FIG. 2 , the planar shape of the display substrate 100 is roughly a rounded rectangle, and the four corner regions of the display substrate 100 , that is, the above-mentioned second display region 120 , can be curved to realize a four-curved screen design.
  • the display substrate 100 further includes a third display area 180 , a plurality of pixels 210 are arranged in the third display area 180 , and the pixel density of the third display area 180 is the same as that of the first display area 110 .
  • the pixel densities are approximately equal.
  • the third display area 180 is located on one side of the first display area 110 in the second direction Y, and the orthographic projection of the third display area 180 on the reference line 500 extending along the first direction X Orthographic projections of the display area 120 and the transition area 130 on the reference line 500 overlap.
  • the width of the orthographic projection of the third display region 180 on a reference line 500 extending along the first direction X is the same as that of the first display region 110 , the second display region 120 and the transition region 130 on the reference line.
  • the sum of the widths of the orthographic projections on 500 is equal.
  • the display substrate 100 further includes an edge driving circuit 280 located on at least one side of the third display region 180 in the first direction X. As shown in FIG. The edge driving circuit 280 is configured to drive the pixels 210 in the third display area 180 .
  • the portion of the display substrate 100 located in the second display region 120 is bent in a direction perpendicular to the first display region 110 .
  • the display substrate 100 includes a light-emitting side, that is, the side where the light emitted by the display substrate 100 exits, and the part of the display substrate 100 located in the second display area 120 can be bent to the side opposite to the light-emitting side, thereby realizing a
  • the 3D stereoscopic effect of the curved surface can create a sense of immersion in the display.
  • the second display region 120 may be provided with an opening pattern so as to be stretched and bent, while neither the first display region 110 nor the transition region 130 is provided with an opening pattern.
  • FIG. 3 is a schematic plan view of another display substrate provided by an embodiment of the present disclosure.
  • the pixel 210 may include a plurality of sub-pixels 215 , and each sub-pixel 215 includes a pixel driving circuit 2152 and a driving electrode 2154 electrically connected to the pixel driving circuit 2152 .
  • the transition region 130 includes a plurality of pixel circuit islands 131 , a plurality of first spacers 132 and at least one driving spacer 133 .
  • each pixel circuit island 131 is provided with a plurality of pixel driving circuits 2152 of at least one pixel 210; In one pixel circuit island 131 .
  • the shortest distance between the pixel circuits in the aforementioned pixel circuit islands is smaller than the shortest distance between two adjacent pixel circuit islands.
  • FIG. 3 shows that the pixel circuit island includes pixel driving circuits for two pixels, embodiments of the present disclosure include but are not limited thereto, and the pixel circuit island can be provided with more pixel driving circuits for pixels.
  • each first spacer 132 is located between two adjacent pixel circuit islands 131 in the first direction, and each driving spacer 133 is also located between two adjacent pixel circuit islands in the first direction.
  • the driving spacer 133 is provided with a row driving circuit unit 225 .
  • the transition region 130 can be divided into a pixel circuit island 131, a first spacer 132 and a driving spacer 133, the driving spacer 133 is located between two adjacent pixel circuit islands 131 in the first direction, And a row driving circuit unit 225 is provided.
  • the display substrate can be provided with a pixel driving circuit 2152 on the pixel circuit island 131 for applying data signals to the driving sub-pixels 215, and a row driving circuit unit 225 can be provided at the driving spacer 133 for supplying the row driving circuit unit 225 Apply row drive signals.
  • the above-mentioned driving electrode can be an anode; of course, embodiments of the present disclosure include but are not limited thereto.
  • the transition region 130 further includes: a plurality of driving electrode islands 134 and a plurality of second spacers 135;
  • the electrode island 138 is provided with a plurality of driving electrodes 2154 of at least one pixel 210; for example, when a pixel 210 includes three sub-pixels 215 (for example, a red sub-pixel, a blue sub-pixel and a green sub-pixel), each driving electrode island 138 Three driving electrodes 2154 may be provided.
  • Each second spacer 135 is located between two adjacent driving electrode islands 134 in the first direction. It should be noted that the driving electrode islands and the pixel circuit islands respectively belong to different film layers of the display substrate, so they can overlap each other.
  • the widths of the plurality of first spacers 132 in the first direction are equal, the widths of the plurality of second spacers 135 in the first direction are equal, and the widths of the first spacers 132 in the first direction are equal.
  • the width in one direction is equal to the width of the driving spacer 133 in the first direction.
  • the driving electrode islands 134 in the first direction are also equidistantly distributed, so that the pixel light emission ratio in the positive transition region can be ensured. Even, there will be no defects such as bright lines or dark lines.
  • the first spacer 132 of the row drive circuit unit 225 is not provided and between the two adjacent pixel circuit islands 131 in the first direction.
  • the widths of the driving spacers 133 where the row driving circuit units 225 are arranged are the same.
  • the pixel circuit islands 131 in the first direction are equidistantly distributed. Therefore, the display substrate can ensure that the pixels in the positive transition region emit light more uniformly, and there are no defects such as bright lines or dark lines, and has the advantages of simple layout and the like.
  • FIG. 4 is a schematic plan view of another display substrate provided by an embodiment of the present disclosure.
  • a plurality of first spacers 132 that is, spacers between adjacent pixel circuit islands 131 except for the driving spacer 133 have equal widths in the first direction
  • a plurality of second spacers The widths of the regions 135 (that is, the intervals between adjacent drive electrode islands 134) in the first direction are equal, the width of the second intervals 135 in the first direction is smaller than the width of the drive intervals 133, and the first intervals 132 The width in the first direction is smaller than the width of the driving spacer 133 in the first direction.
  • the plurality of second spacers 135 have the same width in the first direction, so as to ensure that the pixels in the transition region emit light evenly, and there are no defects such as bright lines or dark lines.
  • the pixel circuit islands 131 in the first direction are not equidistantly arranged, and there is no arrangement between two adjacent pixel circuit islands 131 in the first direction.
  • the width of the first spacer 132 of the row driving circuit unit 225 is smaller than the width of the driving spacer 133 of the row driving circuit unit 225 disposed between two adjacent pixel circuit islands 131 in the first direction.
  • the display substrate can increase the width of the driving spacer 133 by reducing the width of the first spacer 132, so that the driving The spacer 133 can place the row driving circuit unit 225 . Therefore, the display substrate can still have a higher pixel density in the transition area under the premise of ensuring that the pixels in the transition area emit light uniformly, thereby having better display quality. It should be noted that, in the display substrate shown in FIG. 4 , the corresponding pixel circuit islands and driving electrode islands are misaligned, so connection electrodes need to be used to connect the output ends of the corresponding pixel circuit islands to the driving electrode islands. The driving electrodes are connected.
  • the width of the first spacer region 132 in the first direction is 0.5-1.5 times the width of the driving spacer region 133 in the first direction, so that the pixels in the transition region are guaranteed to emit light evenly. Regions still have a higher pixel density and thus better display quality.
  • the display substrate 100 further includes a plurality of connecting electrode structures 150 located between the plurality of pixel circuit islands 131 and the plurality of driving electrode islands 134 in a direction perpendicular to the transition region 130 , That is to say, the plurality of connection electrode structures 150 are located on the side of the plurality of driving electrode islands 131 close to the pixel circuit island 131 in the direction perpendicular to the transition region 130;
  • Each pixel circuit island 131 is provided in one-to-one correspondence, and each connection electrode structure 150 includes a plurality of connection electrodes 152, so as to connect the plurality of pixel driving circuits 2152 in the corresponding pixel circuit island 131 to the plurality of corresponding driving electrode islands 134.
  • the driving electrodes 2154 are electrically connected.
  • one pixel 210 includes three sub-pixels 215, at this time, one connection electrode structure 150 may include three connection electrodes 152, so that the three pixel drive circuits 2152 in the corresponding pixel 210 are respectively It is electrically connected with three driving electrodes 2154 .
  • FIG. 5 is a schematic plan view of another display substrate provided by an embodiment of the present disclosure.
  • the pixel driving unit 2152 includes a driving transistor 2152T, and the driving transistor 2152T is projected orthographically on the film layer where the corresponding driving electrode 1254 is located, and is spaced apart from the corresponding driving electrode 2154 .
  • the pixel circuit island 131 and the driving electrode island 134 are dislocated, so the driving transistor 2152T is projected on the film layer corresponding to the driving electrode 1254 and spaced apart from the corresponding driving electrode 2154 .
  • FIG. 6 is a schematic plan view of another display substrate provided by an embodiment of the present disclosure.
  • the row drive circuit 220 includes a gate drive circuit 2202 and a light emission control drive circuit 2204, and the row drive circuit unit 225 includes a gate drive unit 2252 and a light emission control unit 2254; at least one drive spacer 133 includes two drive spacers 133 , that is to say, the number of driving spacers 133 between a row of pixels 210 in the transition region 130 is two.
  • one of the two driving spacers 133 is provided with the gate driving unit 2252
  • the other of the two driving spacers 133 is provided with the light emission control unit 2254 .
  • the row driving circuit unit may also include other circuit units that apply signals along the row direction; in addition, the gate driving unit and the light emission control unit may also be disposed in a driving spacer.
  • At least two first spacers 132 are separated between two driving spacers 133 . Therefore, the display substrate can avoid uneven light emission caused by driving the spacer region 133 closer. Moreover, the long distance between the two driving spacers 133 also facilitates wiring.
  • the display substrate 100 further includes: a plurality of first driving lines 510 configured to drive a plurality of gate driving units 2202 , and the plurality of gate driving units 2202 are arranged in dislocations in the first direction.
  • each first driving line 510 includes a first portion 510A extending along the second direction and a second portion 510B extending along the first direction, the first portion 510A is connected to the corresponding gate driving unit 2202 , and the second portion 510B connects two adjacent The first part 510A of the gate driving unit 2202 is connected.
  • the display substrate 100 further includes a data line 610 , the first portion 510A and the data line 610 are located in the first source-drain metal layer SD1 , and the second portion 510B is located in the second source-drain metal layer SD2 .
  • each first driving line 510 is stepped.
  • the display substrate 100 further includes: a plurality of second drive lines 520 configured to drive a plurality of light emission control units 2204 , and the plurality of light emission control units 2204 are arranged in dislocations in the first direction , each second driving line 520 includes a third portion 520A extending along the second direction and a fourth portion 520B extending along the first direction, the third portion 520A is connected to the corresponding light emission control unit 2204, and the fourth portion 520B connects the two The third portions 520A of adjacent lighting control units 2204 are connected.
  • the display substrate includes a data line 610 , the third part 520A and the data line 610 are located in the first source-drain metal layer SD1 , and the fourth part is located in the second source-drain metal layer SD2 .
  • each second driving line 520 is stepped.
  • FIG. 7 is an equivalent schematic diagram of a pixel driving circuit in a display substrate provided by an embodiment of the present disclosure.
  • the pixel driving circuit 2152 includes a first thin film transistor T21, a second thin film transistor T22, a third thin film transistor T23, a fourth thin film transistor T24, a fifth thin film transistor T25, a sixth thin film transistor T26 and a seventh thin film transistor T26.
  • the first thin film transistor T21 includes a first gate G1 and a first source S1 and a first drain D1 located on both sides of the first gate G1
  • the second thin film transistor T22 includes a second gate G2 and a first drain located on both sides of the second gate G1.
  • the third thin film transistor T23 includes a third gate G3 and a third source S3 and a third drain D3 located on both sides of the third gate G3, the third thin film transistor T23
  • the four thin film transistors T24 include a fourth gate G4 and a fourth source S4 and a fourth drain D4 located on both sides of the fourth gate G4, and the fifth thin film transistor T25 includes a fifth gate G5 and a fourth drain D4 located on both sides of the fifth gate G5.
  • the fifth source S5 and the fifth drain S5 on both sides, the sixth thin film transistor T26 includes the sixth gate G6 and the sixth source S6 and the sixth drain D6 located on both sides of the sixth gate G6, the seventh
  • the thin film transistor T27 includes a seventh gate G7 and a seventh source S7 and a seventh drain D7 located on both sides of the seventh gate G7.
  • the storage capacitor Cst includes a first electrode block CE1 and a second electrode block CE2. It should be noted that the pixel driving circuit shown in FIG. 7 adopts a 7T1C structure. However, embodiments of the present disclosure include but are not limited thereto, and the pixel driving circuit may also adopt other circuit structures.
  • the reset signal line 640 is connected to the gate G6 of the sixth thin film transistor T26; the sixth drain D6 is connected to the third drain D3; the third source S3, the first drain D1 and the fifth The source S5 is connected to the first node N1, the first source S1, the second drain D2 and the fourth drain D4 are connected to the second node N2, and the fifth drain D5 is connected to the seventh drain D7.
  • the sixth source S6 and the seventh source S7 are connected to the initialization signal line 630, the second source S2 can be connected to the data line 610; the fourth source S4 is connected to the power line 620, and the gate line 650 is connected to the third thin film transistor T23 connected to the third grid G, and the light emission control line 660 is connected to the fifth grid G5.
  • a working mode of the pixel driving circuit shown in FIG. 7 will be schematically described below.
  • the reset signal is transmitted to the reset signal line 640 and the seventh thin film transistor T7 is turned on, the residual current flowing through the anode of each sub-pixel is discharged to the sixth thin film transistor T6 through the seventh thin film transistor T7, thereby suppressing the Light emission caused by residual current flowing through the anode of each sub-pixel.
  • the reset signal is transmitted to the reset signal line 640 and the initialization signal is transmitted to the initialization signal line 630
  • the sixth thin film transistor T6 is turned on, and the first gate G1 and the first gate G1 of the first thin film transistor T1 are transmitted through the sixth thin film transistor T6.
  • the initialization voltage Vint is applied to the first electrode block CE1 of the storage capacitor Cst, so that the first gate G1 and the storage capacitor Cst are initialized.
  • the initialization of the first gate G1 can make the first thin film transistor T1 turn on.
  • both the second thin film transistor T2 and the third thin film transistor T3 are turned on, and the second thin film transistor T2 and the third thin film transistor T3 are connected to the second thin film transistor T3.
  • a gate G1 applies the data voltage Vd.
  • the voltage applied to the first gate G1 is the compensation voltage Vd+Vth, and the compensation voltage applied to the first gate G1 is also applied to the first electrode block CE1 of the storage capacitor Cst.
  • the power supply line 620 applies the driving voltage Vel to the second electrode block CE2 of the storage capacitor Cst, and applies the compensation voltage Vd+Vth to the first electrode block CE1, so that the voltage between the two electrodes of the storage capacitor Cst is The charge corresponding to the difference is stored in the storage capacitor Cst, and the first thin film transistor T1 is turned on for a predetermined time.
  • both the fourth TFT T4 and the fifth TFT T5 are turned on, so that the fourth TFT T4 applies the driving voltage Vel to the fifth TFT T5.
  • the driving voltage Vel passes through the first thin film transistor T1 turned on by the storage capacitor Cst, the corresponding difference between the driving voltage Vel and the voltage applied to the first gate G1 through the storage capacitor Cst flows through the first thin film transistor T1.
  • the driving current Id is applied to each sub-pixel through the fifth thin film transistor T5, so that the light-emitting layer of each sub-pixel emits light.
  • Fig. 8 is an equivalent circuit diagram of a lighting control unit provided by an embodiment of the present disclosure.
  • the light emission control unit includes: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8 , the ninth transistor T9, the tenth transistor T10 (also known as the output transistor), the first capacitor C1, the second capacitor C2 and the third capacitor C3.
  • the light emission control unit adopts a 10T3C structure, and of course the embodiments of the present disclosure include but are not limited thereto. It should be noted that the above-mentioned light emission control unit is a light emission control shift register.
  • the second pole of the first transistor T1 in the first stage light emission control shift register can be connected with the input terminal, the input terminal is configured to be connected to the trigger signal line STV to receive the trigger signal as an input signal, while the second pole of the first transistor T1 in the light-emitting control shift register units of other levels and the light-emitting control shift of the previous stage
  • the output terminal of the bit register unit is electrically connected to receive the output signal output by the output terminal OUT of the upper-level light-emitting control shift register unit as an input signal, thereby realizing a shift output to the array array in the display area of the display substrate
  • the pixels of the cloth provide, for example, light emission control signals shifted row by row.
  • the gate of the first transistor T1 is connected to the first clock signal line 310 to receive the first clock signal, the first pole of the first transistor T1 is connected to the first node N1, and the second electrode of the first transistor T1 connected to the input terminal.
  • the input terminal is connected to the trigger signal line STV to receive a trigger signal; when the lighting control unit is a lighting control unit of other levels except the first-level lighting control unit When , the input terminal is connected to the output terminal OUT of the upper-level lighting control unit.
  • the second transistor T2 As shown in FIG. 8, the second transistor T2, the gate of the second transistor T2 is connected to the first node N1, the first pole of the second transistor T2 is connected to the second node N2, and the second pole of the second transistor T2 is connected to the first node N1.
  • a clock signal line 310 is connected to receive the first clock signal.
  • the gate of the third transistor T3 is connected to the first clock signal line 310 to receive the first clock signal
  • the first pole of the third transistor T3 is connected to the second node N2
  • the second electrode of the third transistor T3 The pole is connected to the first power line 410 to receive the first voltage.
  • the gate of the fourth transistor T4 is connected to the second clock signal line 320 to receive the second clock signal, the first pole of the fourth transistor T4 is connected to the first node N1, and the second electrode of the fourth transistor T4 The pole is connected to the second pole of the fifth transistor T5.
  • the gate of the fifth transistor T5 is connected to the second node N2 , and the first electrode of the fifth transistor T5 is connected to the second power line 420 to receive the second voltage.
  • the first pole of the sixth transistor T6 is connected to the second clock signal line 320 to receive the second clock signal, and the second pole of the sixth transistor T6 is connected to the third node N3 .
  • the gate of the seventh transistor T7 is connected to the second clock signal line 320 to receive the second clock signal, the first pole of the seventh transistor T7 is connected to the third node N3, and the second electrode of the seventh transistor T7 pole is connected to the fourth node N4.
  • the gate of the eighth transistor T8 is connected to the first node N1, the first pole of the eighth transistor T8 is connected to the fourth node N4, and the second pole of the eighth transistor T8 is connected to the second power line 420. to receive the second voltage.
  • the gate of the ninth transistor T9 is connected to the fourth node N4, the first pole of the ninth transistor T9 is connected to the second power supply line 420 to receive the second voltage, and the second pole of the ninth transistor T9 is connected to the second power supply line 420. output connection.
  • the first pole of the tenth transistor T10 is connected to the first power line 410 to receive the first voltage, and the second pole of the tenth transistor T10 is connected to the output terminal.
  • the second pole of the first capacitor C1 is connected to the third node N3; the second pole of the second capacitor C2 is connected to the second clock signal line 320 to receive the second clock signal; the second pole of the third capacitor C3 One pole is connected to the fourth node N4, and the second pole of the third capacitor C3 is connected to the second power line 420 to receive the second voltage.
  • the transistors in the light-emitting control unit shown in FIG. 8 are all described using p-type transistors as an example, that is, each transistor is turned on when the gate is connected to a low level (conduction level), and Cut off when connected to high level (cut-off level).
  • the first pole of the transistor may be a source
  • the second pole of the transistor may be a drain.
  • the embodiments of the present disclosure include but are not limited thereto.
  • Each transistor can also use n-type transistors or use a mixture of p-type transistors and n-type transistors, as long as the terminal polarity of the selected type of transistors is changed according to the embodiment of the present disclosure. Just connect the port polarity of the corresponding transistor in it.
  • the transistors used in the luminescence control unit can be thin film transistors or field effect transistors or other switching devices with the same characteristics.
  • thin film transistors are used as examples for illustration, for example, the active layer (channel region) using semiconductor materials, such as polysilicon (such as low-temperature polysilicon or high-temperature polysilicon), amorphous silicon, indium gallium tin oxide (IGZO), etc., while the gate, source, drain, etc. are made of metal materials, such as metal aluminum or aluminum alloy.
  • the source and drain of the transistor used here may be symmetrical in structure, so there may be no difference in structure between the source and drain.
  • the electrodes of the capacitor may be metal electrodes or one of the electrodes may be a semiconductor material (such as doped polysilicon).
  • the ninth transistor T9 and the tenth transistor T10 are projected on the film layer where the multiple connection electrode structures 150 are located, and are spaced apart from the multiple connection electrode structures 150, so as to avoid the signal on the connection electrode structure 150 from affecting the light emission. control unit. Since the channel width-to-length ratio (W/L) of the ninth transistor T9 and the tenth transistor T10 is relatively large, by orthographically projecting the ninth transistor T9 and the tenth transistor T10 on the film layer where the plurality of connection electrode structures 150 are located The arrangement of the plurality of connecting electrode structures 150 at intervals can prevent the connecting electrode structures from affecting the ninth transistor T9 and the tenth transistor T10 , thereby improving problems such as display brightness difference and color shift after the pixel emits light.
  • W/L channel width-to-length ratio
  • FIG. 9 is an equivalent circuit diagram of a gate driving unit provided by an embodiment of the present disclosure.
  • the gate drive unit 2252 includes: an input transistor 241, a first control transistor 242, a second control transistor 243, an output control transistor 244, a gate output transistor 245, a first noise reduction transistor 246, a second noise reduction transistor noise transistor 247 , voltage stabilizing transistor 248 , first scan capacitor 251 and second scan capacitor 252 . Therefore, the gate driving unit may adopt an 8T2C structure, of course, embodiments of the present disclosure include but are not limited thereto, and the gate driving unit may also adopt other circuit structures.
  • the above-mentioned gate drive unit is a gate scan shift register; when multiple gate drive units are cascaded, the first pole of the input transistor T1 in the gate drive unit of the first stage is connected to the input terminal, and the input terminal It is configured to be connected to the trigger signal line STV to receive the trigger signal as an input signal, and the first pole of the input transistor T1 in the gate drive unit of the other stages is electrically connected to the output end of the gate drive unit of the previous stage to receive the trigger signal of the previous stage.
  • the output signal output from the output terminal OUT of the stage gate driving unit is used as an input signal, thereby realizing a shift output for progressively scanning pixels in the display substrate.
  • the gate of the input transistor 241 is connected to the third clock signal line 330 , the second pole of the input transistor 241 is connected to the input terminal, and the first pole of the input transistor 241 is connected to the first scan node SN1 .
  • the gate of the first control transistor 242 is connected to the first scan node SN1
  • the second pole of the first control transistor 242 is connected to the third clock signal line 330
  • the first pole of the first control transistor 242 is connected to the third clock signal line 330.
  • the second scanning node SN2 is connected.
  • the gate of the second control transistor 243 is connected to the third clock signal line 330, the second pole of the second control transistor 243 is connected to the third power line 430, and the first pole of the second control transistor 243 is connected to the third power line 430.
  • the second scanning node SN2 is connected.
  • the gate of the output control transistor 244 is connected to the second scanning node SN2 , the first pole of the output control transistor 244 is connected to the fourth power line 440 , and the second pole of the output control transistor 245 is connected to the output terminal.
  • the first pole of the first scan capacitor 251 is connected to the second scan node SN2 , and the second pole of the first scan capacitor 251 is connected to the fourth power line 440 .
  • the gate of the gate output transistor 245 is connected to the third scan node SN3, the first pole of the gate output transistor 245 is connected to the fourth clock signal line 340, the second pole of the gate output transistor 245 is connected to output connection.
  • the first pole of the second scan capacitor 252 is connected to the third scan node SN3 , and the second pole of the second scan capacitor 252 is connected to the output terminal.
  • the gate of the first noise reduction transistor 246 is connected to the second scanning node SN2
  • the first pole of the first noise reduction transistor 246 is connected to the fourth power line 440
  • the second electrode of the first noise reduction transistor 246 The pole is connected to the second pole of the second noise reduction transistor 247.
  • the gate of the second noise reduction transistor 247 is connected to the fourth clock signal line 340 , and the first electrode of the second noise reduction transistor 247 is connected to the first scan node SN1 .
  • the gate of the voltage stabilizing transistor 248 is connected to the third power supply line 430, the second pole of the voltage stabilizing transistor 248 is connected to the first scanning node SN1, and the first pole of the stabilizing transistor 248 is connected to the third scanning node SN1.
  • SN3 connection As shown in FIG. 9, the gate of the voltage stabilizing transistor 248 is connected to the third power supply line 430, the second pole of the voltage stabilizing transistor 248 is connected to the first scanning node SN1, and the first pole of the stabilizing transistor 248 is connected to the third scanning node SN1.
  • the transistors in the gate drive unit shown in FIG. 9 are all described by taking p-type transistors as an example, that is, each transistor is turned on when the gate is connected to a low level (turn-on level), and It is cut off when it is connected to a high level (cut-off level).
  • the first pole of the transistor may be a source
  • the second pole of the transistor may be a drain.
  • the embodiments of the present disclosure include but are not limited thereto.
  • Each transistor can also use n-type transistors or use a mixture of p-type transistors and n-type transistors, as long as the terminal polarity of the selected type of transistors is changed according to the embodiment of the present disclosure. Just connect the port polarity of the corresponding transistor in it.
  • the transistors used in the gate drive unit can all be thin film transistors or field effect transistors or other switching devices with the same characteristics.
  • thin film transistors are used as examples for illustration.
  • the gate, source, drain, etc. are made of metal materials, such as metal aluminum or aluminum alloy.
  • the source and drain of the transistor used here may be symmetrical in structure, so there may be no difference in structure between the source and drain.
  • the electrodes of the capacitor may be metal electrodes or one of the electrodes may be a semiconductor material (such as doped polysilicon).
  • the orthographic projection of the output control transistor 244 and the gate output transistor 245 on the film layer where the plurality of connection electrode structures 150 are located is spaced apart from the plurality of connection electrode structures 150 . Since the channel width-to-length ratio (W/L) of the output control transistor 244 and the gate output transistor 245 is relatively large, by placing the output control transistor 244 and the gate output transistor 245 on the film layer where the plurality of connection electrode structures 150 are located The orthographic projection and multiple connecting electrode structures 150 are arranged at intervals to prevent the connecting electrode structures from affecting the output control transistor 244 and the gate output transistor 245 , thereby improving problems such as display brightness difference and color shift after the pixel emits light.
  • W/L channel width-to-length ratio
  • FIG. 10 is a schematic diagram of a second display area on a display substrate provided by an embodiment of the present disclosure.
  • the second display area 120 includes: a plurality of pixel islands 1202 arranged in an array along the first direction and the second direction, and each pixel island 1202 includes at least one pixel; a first opening 1204 extends along the first direction and located between two adjacent pixel islands 1202 in the second direction; and a second opening 1206 extending along the second direction and located between two adjacent pixel islands 1202 in the first direction. Since the second display area is provided with the first opening and the second opening, that is, the above-mentioned opening pattern, it can be easily bent and stretched.
  • FIG. 11 is a schematic plan view of a display substrate provided by an embodiment of the present disclosure.
  • the display device 900 includes any one of the display substrates 100 described above. Since the display substrate 100 inserts a transition region between the high pixel density region and the low pixel density region, and arranges a row driving circuit in the transition region, the row driving circuit in the transition region can be used to drive the first display region by row. , the second display area and a plurality of pixels in the transition area for display.
  • the display substrate does not need to provide an additional area for placing the row driving circuit outside the low pixel density area.
  • the frame width of the display substrate can be reduced; There is a problem that the row driving circuit cannot be provided due to the opening pattern. Therefore, the display device has a narrow frame width and can realize a four-curved screen design.
  • the above-mentioned display device may be an electronic product with a display function such as a television, a mobile phone, a computer, a navigator, and an electronic picture frame.
  • a display function such as a television, a mobile phone, a computer, a navigator, and an electronic picture frame.

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Abstract

一种显示基板和显示装置。该显示基板（100）包括第一显示区域（110）；第二显示区域（120），位于第一显示区域（110）在第一方向X的一侧；以及过渡区域（130），位于第一显示区域（110）和第二显示区域（120）之间，第一显示区域（110）、第二显示区域（120）和过渡区域（130）设置有多个像素（210），多个像素（210）沿第一方向X和与第一方向X相交的第二方向Y呈阵列排布，第一显示区域（110）的像素密度大于第二显示区域（120）的像素密度和过渡区域（130）的像素密度，过渡区域（130）还设置有行驱动电路（220），行驱动电路（220）被配置为按行驱动第一显示区域（110）、第二显示区域（120）和过渡区域（130）中的多个像素（210）。由此，该显示基板（100）在第一显示区域（110）和第二显示区域（120）之间设置过渡区域（130），并在过渡区域（130）设置行驱动电路（220），从而驱动过渡区域（130）两侧的第一显示区域（110）和第二显示区域（120）进行显示。

Description

显示基板和显示装置 技术领域
本公开的实施例涉及一种显示基板和显示装置。
背景技术
随着显示技术的不断发展，柔性显示技术因其功耗低、体积小、便携、显示方式多样等优点已经被广泛地应用在各种各样的显示装置中。为了提升显示品质和使用效果，四曲面屏设计在手机、平板电脑等智能电子产品中得到广泛应用。四曲面屏设计是结合3D玻璃盖板(Cover Glass)贴合技术，将显示基板的边缘或角落按照一定弯曲半径进行弯曲并形成弧度，以实现正面侧面的全面立体显示，从而实现四曲面形态的3D立体效果，由此可营造显示立体沉浸感，符合未来技术发展趋势。
发明内容
本公开实施例提供一种显示基板和显示装置。该显示基板提供一种GIP(Gate in Pixel)设计，即显示基板通过在高像素密度区域和低像素密度区域设置过渡区域，并在过渡区域设置行驱动电路，例如栅驱动电路(GOA)，从而驱动过渡区域两侧的高像素密度区域和低像素密度区域进行显示。
本公开至少一个实施例提供一种显示基板，其包括：第一显示区域；第二显示区域，位于所述第一显示区域在第一方向的至少一侧；以及过渡区域，位于所述第一显示区域和所述第二显示区域之间，所述第一显示区域、所述第二显示区域和所述过渡区域设置有多个像素，所述多个像素沿所述第一方向和与所述第一方向相交的第二方向呈阵列排布，所述第一显示区域的像素密度大于所述第二显示区域的像素密度和所述过渡区域的像素密度，所述过渡区域还设置有行驱动电路，所述行驱动电路被配置为按行驱动所述第一显示区域、所述第二显示区域和所述过渡区域中的所述多个像素。
例如，在本公开一实施例提供的显示基板中，所述行驱动电路包括沿所述第二方向排列的多个行驱动电路单元。
例如，在本公开一实施例提供的显示基板中，各所述像素包括多个子像素，各所述子像素包括像素驱动电路和与所述像素驱动电路电性相连的驱动电极， 所述过渡区域包括：多个像素电路岛，各所述像素电路岛设置有至少一个所述像素的多个所述像素驱动电路；多个第一间隔区，各所述第一间隔区位于在所述第一方向上相邻的两个所述像素电路岛之间；以及至少一个驱动间隔区，各所述驱动间隔区也位于在所述第一方向上相邻的两个所述像素电路岛之间，所述驱动间隔区设置有所述行驱动电路单元。
例如，在本公开一实施例提供的显示基板中，所述过渡区域还包括：多个驱动电极岛，与所述多个像素电路岛对应设置，各所述驱动电极岛设置有至少一个所述像素的多个所述驱动电极；以及多个第二间隔区，各所述第二间隔区位于在所述第一方向上相邻的两个所述驱动电极岛之间。
例如，在本公开一实施例提供的显示基板中，所述多个第一间隔区在所述第一方向上的宽度相等，所述多个第二间隔区在所述第一方向上的宽度相等，所述第一间隔区在所述第一方向上的宽度小于所述驱动间隔区在所述第一方向上的宽度。
例如，在本公开一实施例提供的显示基板中，所述多个第一间隔区在所述第一方向上的宽度相等，所述多个第二间隔区在所述第一方向上的宽度相等，所述第二间隔区在所述第一方向上的宽度为所述驱动间隔的宽度的0.5-1.5倍，所述第一间隔区在所述第一方向上的宽度小于所述驱动间隔在所述第一方向上的宽度。
例如，在本公开一实施例提供的显示基板中，所述行驱动电路单元包括第一行驱动电路单元和第二行驱动电路单元，所述第一行驱动电路单元具有输出端，所述第一行驱动电路单元的所述输出端被配置为同时驱动所述第一显示区域、所述第二显示区域和所述过渡区域中的同属一行的多个所述像素。
例如，本公开一实施例提供的显示基板还包括：多个连接电极结构，在垂直于所述过渡区域的方向上位于所述多个驱动电极岛靠近所述像素电路岛的一侧，所述多个连接电极结构与所述多个驱动电极岛和所述多个像素电路岛分别一一对应设置，各所述连接电极结构包括多个连接电极，以将对应的所述像素电路岛中的多个所述像素驱动电路与对应的所述驱动电极岛中的多个所述驱动电极电性相连。
例如，在本公开一实施例提供的显示基板中，所述像素驱动单元包括驱动晶体管，所述驱动晶体管在对应所述驱动电极所在的膜层上正投影与对应所述驱动电极间隔设置。
例如，在本公开一实施例提供的显示基板中，所述行驱动电路包括栅驱动电路和发光控制驱动电路，所述行驱动电路单元包括栅驱动单元和发光控制单元，所述至少一个驱动间隔区包括两个所述驱动间隔区，两个所述驱动间隔区中的一个设置所述栅驱动单元，两个所述驱动间隔区中的另一个设置所述发光控制单元。
例如，在本公开一实施例提供的显示基板中，两个所述驱动间隔区之间间隔至少两个所述第一间隔区。
例如，在本公开一实施例提供的显示基板中，所述发光控制单元包括：第一晶体管，所述第一晶体管的栅极和第一时钟信号线连接以接收第一时钟信号，所述第一晶体管的第一极和第一节点连接，所述第一晶体管的第二极和输入端连接；第二晶体管，所述第二晶体管的栅极和所述第一节点连接，第二晶体管的第一极和第二节点连接，第二晶体管的第二极和所述第一时钟信号线连接以接收所述第一时钟信号；第三晶体管，所述第三晶体管的栅极和所述第一时钟信号线连接以接收所述第一时钟信号，所述第三晶体管的第一极和所述第二节点连接，所述第三晶体管的第二极和第一电源线连接以接收第一电压；第四晶体管，所述第四晶体管的栅极和第二时钟信号线连接以接收第二时钟信号，所述第四晶体管的第一极和所述第一节点连接，所述第四晶体管的第二极和第五晶体管的第二极连接；所述第五晶体管，所述第五晶体管的栅极和所述第二节点连接，所述第五晶体管的第一极和第二电源线连接以接收第二电压；第六晶体管，所述第六晶体管的第一极和所述第二时钟信号线连接以接收所述第二时钟信号，所述第六晶体管的第二极和第三节点连接；第七晶体管，所述第七晶体管的栅极和所述第二时钟信号线连接以接收所述第二时钟信号，所述第七晶体管的第一极和所述第三节点连接，所述第七晶体管的第二极和第四节点连接；第八晶体管，所述第八晶体管的栅极和所述第一节点连接，所述第八晶体管的第一极和所述第四节点连接，所述第八晶体管的第二极和所述第二电源线连接以接收所述第二电压；第九晶体管，所述第九晶体管的栅极和所述第四节点连接，所述第九晶体管的第一极和所述第二电源线连接以接收所述第二电压，所述第九晶体管的第二极和输出端连接；第十晶体管，所述第十晶体管的第一极和所述第一电源线连接以接收所述第一电压，所述第十晶体管的第二极和所述输出端连接；第一电容，所述第一电容的第二极和所述第三节点连接；第二电容，所述第二电容的第二极和所述第二时钟信号线连接以接收所述第二 时钟信号；以及第三电容，所述第三电容的第一极和所述第四节点连接，所述第三电容的第二极和所述第二电源线连接以接收所述第二电压。
例如，在本公开一实施例提供的显示基板中，所述第九晶体管和所述第十晶体管在所述多个连接电极结构所在的膜层上正投影与所述多个连接电极结构间隔设置。
例如，在本公开一实施例提供的显示基板中，所述栅驱动单元包括：输入晶体管、第一控制晶体管、第二控制晶体管、输出控制晶体管、栅极输出晶体管、第一降噪晶体管、第二降噪晶体管以及稳压晶体管、第一扫描电容和第二扫描电容，所述输入晶体管的栅极和第三时钟信号线连接，所述输入晶体管的第二极和输入端连接，所述输入晶体管的第一极和第一扫描节点连接；所述第一控制晶体管的栅极和第一扫描节点连接，所述第一控制晶体管的第二极和所述第三时钟信号线连接，所述第一控制晶体管的第一极和第二扫描节点连接；所述第二控制晶体管的栅极和第三时钟信号线连接，所述第二控制晶体管的第二极和第三电源线连接，所述第二控制晶体管的第一极和所述第二扫描节点连接；所述输出控制晶体管的栅极和所述第二扫描节点连接，所述输出控制晶体管的第一极和第四电源线连接，所述输出控制晶体管的第二极和输出端连接；所述第一扫描电容的第一极和所述第二扫描节点连接，所述第一扫描电容的第二极和所述第四电源线连接；所述栅极输出晶体管的栅极和第三扫描节点连接，所述栅极输出晶体管的第一极和第二时钟子信号线连接，所述栅极输出晶体管的第二极和所述输出端连接；所述第二扫描电容的第一极和所述第三扫描节点连接，所述第二扫描电容的第二极和所述输出端连接；所述第一降噪晶体管的栅极和所述第二扫描节点连接，所述第一降噪晶体管的第一极和所述第四电源线连接，所述第一降噪晶体管的第二极和第二降噪晶体管的第二极连接；所述第二降噪晶体管的栅极和第四时钟信号线连接，所述第二降噪晶体管的第一极和所述第一扫描节点连接；以及所述稳压晶体管的栅极和所述第三电源线连接，所述稳压晶体管的第二极和所述第一扫描节点连接，所述稳压晶体管的第一极和所述第三扫描节点连接。
例如，在本公开一实施例提供的显示基板中，所述输出控制晶体管和所述栅极输出晶体管在所述多个连接电极结构所在的膜层上正投影与所述多个连接电极结构间隔设置。
例如，本公开一实施例提供的显示基板还包括：多条第一驱动线，被配置 为驱动所述多个栅驱动单元，所述多个栅驱动单元在所述第一方向上错位设置，各所述第一驱动线包括沿所述第二方向延伸的第一部分和沿所述第一方向延伸的第二部分，所述第一部分与对应的所述栅驱动单元相连，所述第二部分将两个相邻的所述栅驱动单元的第一部分相连。
例如，本公开一实施例提供的显示基板还包括：数据线，所述第一部分与所述数据线位于第一源漏金属层，所述第二部分位于第二源漏金属层。
例如，在本公开一实施例提供的显示基板中，各所述第一驱动线呈台阶状。
例如，本公开一实施例提供的显示基板还包括：多条第二驱动线，被配置为驱动所述多个发光控制单元，所述多个发光控制单元在所述第一方向上错位设置，各所述第二驱动线包括沿所述第二方向延伸的第三部分和沿所述第一方向延伸的第四部分，所述第三部分与对应的所述发光控制单元相连，所述第四部分将两个相邻的所述发光控制单元的第三部分相连。
例如，本公开一实施例提供的显示基板还包括数据线，所述第三部分与所述数据线位于第一源漏金属层，所述第四部分位于第二源漏金属层。
例如，在本公开一实施例提供的显示基板中，各所述第二驱动线呈台阶状。
例如，在本公开一实施例提供的显示基板中，所述显示基板位于所述第二显示区域的部分在垂直于所述第一显示区域的方向上弯曲。
例如，本公开一实施例提供的显示基板还包括：第三显示区域，位于所述第一显示区域在所述第二方向上的一侧，所述第三显示区域中设置有多个所述像素，所述第三显示区域的像素密度与所述第一显示区域的像素密度大致相等，所述第三显示区域在沿所述第一方向延伸的参考线上的正投影与所述第一显示区域、所述第二显示区域和所述过渡区域在所述参考线上的正投影均交叠。
例如，在本公开一实施例提供的显示基板中，所述第二显示区包括：多个像素岛，沿所述第一方向和所述第二方向阵列设置，各所述像素岛包括至少一个像素；第一开口，沿所述第一方向延伸且位于在所述第二方向上相邻的两个所述像素岛之间；以及第二开口，沿所述第二方向延伸且位于在所述第一方向上相邻的两个所述像素岛之间。
本公开至少一个实施例还提供一种显示装置，包括上述任一项所述的显示基板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1A为本公开一实施例提供的一种显示基板的平面示意图；
图1B为本公开一实施例提供的一种显示基板中行驱动电路的连接示意图；
图1C为本公开一实施例提供的一种显示基板中栅驱动单元的示意图；
图1D为本公开一实施例提供的一种显示基板中发光控制单元的示意图；
图2为本公开一实施例提供的另一种显示基板的平面示意图；
图3为本公开一实施例提供的另一种显示基板的平面示意图；
图4为本公开一实施例提供的另一种显示基板的平面示意图；
图5为本公开一实施例提供的另一种显示基板的平面示意图；
图6为本公开一实施例提供的另一种显示基板的平面示意图；
图7为本公开一实施例提供的一种显示基板中的像素驱动电路的等效示意图；
图8为本公开一实施例提供的一种发光控制单元的等效电路图；
图9为本公开一实施例提供的一种栅驱动单元的等效电路图；
图10为本公开一实施例提供的一种显示基板上第二显示区的示意图；以及
图11为本公开一实施例提供的一种显示基板的平面示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的 组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
通常，可通过降低显示基板的四个角落区域的像素密度(PPI)，并在这四个角落区域设置带有开孔图形的可拉伸结构，从而可将显示基板的边缘或角落按照一定弯曲半径进行弯曲，从而实现四曲面屏设计。此时，位于四个角落区域的可拉伸结构的拉伸量越大，则这四个角落区域的像素密度越低，即为低像素密度区。另一方面，可拉伸结构的开孔图形需要延伸至低像素密度区域外直至切割线处。因此低像素密度区域的栅驱动电路(GOA电路)无法按照常规方式摆放在像素外侧。
对此，本公开实施例提供一种显示基板和显示装置。该显示基板包括第一显示区域；第二显示区域，位于第一显示区域在第一方向的一侧；以及过渡区域，位于第一显示区域和第二显示区域之间，第一显示区域、第二显示区域和过渡区域设置有多个像素，多个像素沿第一方向和与第二方向相交的第二方向呈阵列排布，第一显示区域(即高像素密度区域)的像素密度大于第二显示区域(即低像素密度区域)的像素密度和过渡区域的像素密度，过渡区域还设置有行驱动电路，行驱动电路被配置为按行驱动第一显示区域、第二显示区域和过渡区域中的多个像素。由此，该显示基板提供一种GIP(Gate in Pixel)设计，即显示基板通过在高像素密度区域和低像素密度区域设置过渡区域，并在过渡区域设置行驱动电路，例如栅驱动电路(GOA)，从而驱动过渡区域两侧的高像素密度区域和低像素密度区域进行显示。
下面，结合附图对本公开实施例提供的显示基板和显示装置进行详细的说明。
本公开一实施例提供一种显示基板。图1A为本公开一实施例提供的一种显示基板的平面示意图。如图1A所示，该显示基板100包括第一显示区域110、第二显示区域120和过渡区域130；第二显示区域120位于第一显示区域110在第一方向X的至少一侧，过渡区域130位于第一显示区域110和第二显示区域120之间。第一显示区域110、第二显示区域120和过渡区域130设置有多个像素210，多个像素210沿第一方向和与第二方向相交的第二方向呈阵列排布，也就是说，多个像素210形成多行像素和多列像素；第一显示区域110的 像素密度大于第二显示区域120的像素密度和过渡区域130的像素密度；过渡区域130还设置有行驱动电路220，行驱动电路220被配置为按行驱动第一显示区域110、第二显示区域120和过渡区域130中的多个像素210。值得注意的是，本公开实施例提供的过渡区域中也设置有多个像素，该过渡区域与第一显示区域和第二显示区域可共同进行显示。
在本公开实施例提供的显示基板中，由于第一显示区域的像素密度大于第二显示区域的像素密度和过渡区域的像素密度，因此第一显示区域为高像素密度区域，第二显示区域为低像素密度区域。该显示基板通过在高像素密度区域和低像素密度区域之间插入过渡区域，并在过渡区域中设置行驱动电路，从而可利用过渡区域中的行驱动电路来按行驱动第一显示区域、第二显示区域和过渡区域中的多个像素进行显示。由此，该显示基板不用在低像素密度区域之外额外设置一个用于放置行驱动电路的区域，一方面可降低该显示基板的边框宽度，另一方面可解决四曲面屏设计中四个角落区域因设置有开口图案而导致的无法设置行驱动电路的问题。
在一些示例中，如图1A所示，第二显示区域120位于第一显示区域110在第一方向的两侧，两个过渡区域130分别位于第一显示区域110和两个第二显示区域120之间。
在一些示例中，如图1A所示，行驱动电路220包括沿第二方向排列的多个行驱动电路单元225。例如，行驱动电路220可为栅驱动电路，行驱动电路单元225可为栅驱动单元，即GOA单元。
在一些示例中，如图1A所示，驱动电路单元225包括第一行驱动电路单元225A和第二行驱动电路单元225B；第一行驱动电路单元225A在第一方向的两侧分别具有一个输出端OUT，由此第一行驱动电路单元225A可同时驱动第一显示区域110、第二显示区域120和过渡区域130中的同属一行的多个像素210；第二行驱动电路单元225B在第一方向上靠近第一显示区域110的一侧具有一个输出端OUT，第二行驱动电路单元225被配置为仅驱动第一显示区域110中的同属一行的多个像素210。
在本公开实施例提供的显示基板中，第一显示区域110中的像素密度大于第二显示区域120中的像素密度，因此可能出现第一显示区域110中的像素210的行数大于第二显示区域120中像素210的行数的情况。此时，通过将行驱动电路单元225设置为包括上述的第一行驱动电路单元225A和第二行驱动电路 单元225B，第一行驱动电路单元225A被配置为同时驱动第一显示区域110、第二显示区域120和过渡区域130中的同属一行的多个像素210，而第二行驱动电路单元225被配置为仅驱动第一显示区域110中的同属一行的多个像素210，可较好地实现驱动具有不同像素密度的第一显示区域110和第二显示区域120中的像素210。
图1B为本公开一实施例提供的一种显示基板中行驱动电路的连接示意图。如图1B所示，行驱动电路220包括栅驱动电路2202和发光控制驱动电路2204；行驱动电路单元225包括栅驱动单元2252和发光控制单元2254。
如图1B所示，栅驱动电路2202和发光控制驱动电路2204呈阶梯排布；多个栅驱动单元2252可组成一个栅驱动单元组2252G，然后多个栅驱动单元组2252G在第一方向上的正投影间隔设置，也就是说，多个栅驱动单元组2252G在第一方向上错位设置。此时，在一个栅驱动单元组2252G中的多个栅驱动单元2252可以相互级联，而相邻的两个栅驱动单元组2252G通过连接线相连，以传输时钟信号等信号。同样地，多个发光控制单元2254可组成一个发光控制单元组2254G，然后多个发光控制单元组2254G在第一方向上的正投影间隔设置，也就是说，多个发光控制单元组2254G在第一方向上错位设置。此时，在一个发光控制单元组2254G中的多个发光控制单元2254可以相互级联，而相邻的两个发光控制单元组2254G通过连接线相连，以传输时钟信号等信号。
如图1B所示，由于相邻的两个栅驱动单元组2252G通过连接线相连，相邻的两个发光控制单元组2254G通过连接线相连，因此，位于同一列，且相邻的栅驱动单元组2252G和发光控制单元组2254G间隔设置，例如，间隔一个单元长度，该单元长度可为一个栅驱动单元或者发光控制单元在第二方向上的长度。也就是说，位于同一列，且相邻的栅驱动单元组2252G和发光控制单元组2254G之间设置有间隔2209，间隔2209可提供走线空间。
图1C为本公开一实施例提供的一种显示基板中栅驱动单元的示意图；图1D为本公开一实施例提供的一种显示基板中发光控制单元的示意图。如图1C所示，栅驱动单元2252的输出端与栅线650A通过过孔650H相连，此时栅线650A位于过孔650H两侧的两个部分可相当于栅驱动单元2252的两个输出端OUT。如图1D所示，发光控制单元2254的输出端与发光控制线660A通过过孔660H相连，此时发光控制线660A位于过孔660H两侧的两个部分可相当于 发光控制单元2254的两个输出端OUT。
图2为本公开一实施例提供的另一种显示基板的平面示意图。如图2所示，该显示基板100的平面形状大致为圆角矩形，在该显示基板100的四个角落区域，即上述的第二显示区域120可进行弯曲，从而可实现四曲面屏设计。
在一些示例中，如图2所示，该显示基板100还包括第三显示区域180，第三显示区域180中设置有多个像素210，第三显示区域180的像素密度与第一显示区域110的像素密度大致相等。第三显示区域180位于第一显示区域110在第二方向Y上的一侧，第三显示区域180在沿第一方向X延伸的参考线500上的正投影与第一显示区域110、第二显示区域120和过渡区域130在该参考线500上的正投影均交叠。
例如，如图2所示，第三显示区域180在沿第一方向X延伸的参考线500上的正投影的宽度与第一显示区域110、第二显示区域120和过渡区域130在该参考线500上的正投影的宽度之和相等。
在一些示例中，如图2所示，该显示基板100还包括边缘驱动电路280，位于第三显示区域180在第一方向X上的至少一侧。边缘驱动电路280被配置为驱动第三显示区域180中的像素210。
在一些示例中，如图1A和图2所示，显示基板100位于第二显示区域120的部分在垂直于第一显示区域110的方向上弯曲。例如，该显示基板100包括出光侧，即显示基板100发出的光线出射的一侧，显示基板100位于第二显示区域120的部分可向与该出光侧相反的一侧进行弯曲，从而实现一种曲面形态的3D立体效果，由此可营造显示立体沉浸感。
在一些示例中，第二显示区域120可设置有开口图案，从而可进行拉伸和弯曲，而第一显示区域110和过渡区域130均不设置开口图案。
图3为本公开一实施例提供的另一种显示基板的平面示意图。如图3所示，在过渡区域130，像素210可包括多个子像素215，各子像素215包括像素驱动电路2152和与像素驱动电路2152电性相连的驱动电极2154。此时，过渡区域130包括多个像素电路岛131、多个第一间隔区132和至少一个驱动间隔区133。
如图3所示，各像素电路岛131设置有至少一个像素210的多个像素驱动电路2152；图3示出了在第二方向上相邻的两个像素210的六个像素驱动电路2152设置在一个像素电路岛131之中。需要说明的是，上述的像素电路岛之中 的像素电路之间最短距离小于相邻的两个像素电路岛之间的最短距离。另外，虽然图3示出了像素电路岛包括两个像素的像素驱动电路，但是本公开实施例包括但不限于此，像素电路岛可设置更多的像素的像素驱动电路。
如图3所示，各第一间隔区132位于在第一方向上相邻的两个像素电路岛131之间，各驱动间隔区133也位于在第一方向上相邻的两个像素电路岛131之间，驱动间隔区133设置有行驱动电路单元225。在该显示基板中，过渡区域130可分为像素电路岛131、第一间隔区132和驱动间隔区133，驱动间隔区133位于在第一方向上相邻的两个像素电路岛131之间，并设置有行驱动电路单元225。由此，该显示基板可在像素电路岛131设置像素驱动电路2152，用于向驱动子像素215施加数据信号，在驱动间隔区133设置行驱动电路单元225，用于向该行驱动电路单元225施加行驱动信号。
例如，当上述的显示基板为有机发光二极管显示基板时，上述的驱动电极可为阳极；当然，本公开实施例包括但不限于此。
在一些示例中，如图3所示，过渡区域130还包括：多个驱动电极岛134和多个第二间隔区135；多个驱动电极岛134与多个像素电路岛131对应设置，各驱动电极岛138设置有至少一个像素210的多个驱动电极2154；例如，当一个像素210包括三个子像素215(例如，红色子像素、蓝色子像素和绿色子像素)时，各驱动电极岛138可设置三个驱动电极2154。各第二间隔区135位于在第一方向上相邻的两个驱动电极岛134之间。需要说明的是，驱动电极岛和像素电路岛分别属于显示基板的不同膜层，因此相互是可以重叠的。
在一些示例中，如图3所示，多个第一间隔区132在第一方向上的宽度相等，多个第二间隔区135在第一方向上的宽度相等，第一间隔区132在第一方向上的宽度与驱动间隔区133在第一方向上的宽度相等。在该显示基板中，由于多个第二间隔区135在第一方向上的宽度相等，因此在第一方向上的驱动电极岛134也是等距分布的，从而可保正过渡区域中的像素发光比较均匀，不会存在亮线或者暗线等不良。另一方面，在第一方向上相邻的两个像素电路岛131之间不设置行驱动电路单元225的第一间隔区132和在第一方向上相邻的两个像素电路岛131之间设置行驱动电路单元225的驱动间隔区133的宽度是相同的。此时，在第一方向上的像素电路岛131是等距分布的。由此，该显示基板在可保正过渡区域中的像素发光比较均匀，不会存在亮线或者暗线等不良的同时具有布局简单等优点。
图4为本公开一实施例提供的另一种显示基板的平面示意图。如图4所示，多个第一间隔区132(即除了驱动间隔区133之外的，相邻像素电路岛131之间的间隔区)在第一方向上的宽度相等，多个第二间隔区135(即相邻的驱动电极岛134之间的间隔区)在第一方向上的宽度相等，第二间隔区135在第一方向上的宽度小于驱动间隔133的宽度，第一间隔区132在第一方向上的宽度小于驱动间隔区133在第一方向上的宽度。在该显示基板中，多个第二间隔区135在第一方向上的宽度相等，从而可保证过渡区域中的像素发光比较均匀，不会存在亮线或者暗线等不良。另一方面，与图3所示的显示基板不同的是，在第一方向上的像素电路岛131并非等距设置的，在第一方向上相邻的两个像素电路岛131之间不设置行驱动电路单元225的第一间隔区132的宽度小于在第一方向上相邻的两个像素电路岛131之间设置行驱动电路单元225的驱动间隔区133的宽度。由此，该显示基板可在过渡区域在第一方向上的尺寸或者过渡区域的像素密度较大时，通过减小第一间隔区132的宽度，来增加驱动间隔区133的宽度，以使得驱动间隔区133可放置行驱动电路单元225。所以，该显示基板可在保证该过渡区域的像素发光均匀的前提下，过渡区域仍然具有较高的像素密度，从而具有较好的显示质量。需要说明的是，在图4所示的显示基板中，对应的像素电路岛和驱动电极岛是错位设置的，因此需要采用连接电极来将对应的像素电路岛的输出端与驱动电极岛中的驱动电极相连。
在一些示例中，第一间隔区132在第一方向上的宽度为驱动间隔区133在第一方向上的宽度的0.5-1.5倍，从而在保证该过渡区域的像素发光均匀的前提下，过渡区域仍然具有较高的像素密度，从而具有较好的显示质量。
在一些示例中，如图4所示，该显示基板100还包括多个连接电极结构150，在垂直于过渡区域130的方向上位于多个像素电路岛131和多个驱动电极岛134之间，也就是说，多个连接电极结构150在垂直于过渡区域130的方向上位于多个驱动电极岛131靠近像素电路岛131的一侧；多个连接电极结构150与多个驱动电极岛134和多个像素电路岛131分别一一对应设置，各连接电极结构150包括多个连接电极152，以将对应的像素电路岛131中的多个像素驱动电路2152与对应的驱动电极岛134中的多个驱动电极2154电性相连。
在一些示例中，如图4所示，一个像素210包括三个子像素215，此时一个连接电极结构150可包括三个连接电极152，从而分别将对应的像素210中的三个像素驱动电路2152与三个驱动电极2154电性相连。
图5为本公开一实施例提供的另一种显示基板的平面示意图。如图5所示，像素驱动单元2152包括驱动晶体管2152T，驱动晶体管2152T在对应驱动电极1254所在的膜层上正投影与对应驱动电极2154间隔设置。在本公开实施例提供的显示基板中，像素电路岛131和驱动电极岛134是错位设置的，因此驱动晶体管2152T在对应驱动电极1254所在的膜层上正投影与对应驱动电极2154间隔设置。
图6为本公开一实施例提供的另一种显示基板的平面示意图。如图6所示，行驱动电路220包括栅驱动电路2202和发光控制驱动电路2204，行驱动电路单元225包括栅驱动单元2252和发光控制单元2254；至少一个驱动间隔区133包括两个驱动间隔区133，也就是说，过渡区域130中的一行像素210之间的驱动间隔区133的数量为两个。此时，这两个驱动间隔区133中的一个设置栅驱动单元2252，两个驱动间隔区133中的另一个设置发光控制单元2254。当然，本公开实施例包括但不限于此，行驱动电路单元还可包括其他沿行方向施加信号的电路单元；另外，栅驱动单元和发光控制单元也可同时设置在一个驱动间隔区之内。
在一些示例中，如图6所示，两个驱动间隔区133之间间隔至少两个第一间隔区132。由此，该显示基板可避免驱动间隔区133较近而导致的发光不均的情况。并且，两个驱动间隔区133的距离较远也方便进行布线。
在一些示例中，如图6所示，该显示基板100还包括：多条第一驱动线510，被配置为驱动多个栅驱动单元2202，多个栅驱动单元2202在第一方向上错位设置，各第一驱动线510包括沿第二方向延伸的第一部分510A和沿第一方向延伸的第二部分510B，第一部分510A与对应的栅驱动单元2202相连，第二部分510B将两个相邻的栅驱动单元2202的第一部分510A相连。
在一些示例中，如图6所示，该显示基板100还包括数据线610，第一部分510A与数据线610位于第一源漏金属层SD1，第二部分510B位于第二源漏金属层SD2。
在一些示例中，如图6所示，各第一驱动线510呈台阶状。
在一些示例中，如图6所示，该显示基板100还包括：多条第二驱动线520，被配置为驱动多个发光控制单元2204，多个发光控制单元2204在第一方向上错位设置，各第二驱动线520包括沿第二方向延伸的第三部分520A和沿第一方向延伸的第四部分520B，第三部分520A与对应的发光控制单元2204相连， 第四部分520B将两个相邻的发光控制单元2204的第三部分520A相连。
在一些示例中，如图6所示，该显示基板包括数据线610，第三部分520A与数据线610位于第一源漏金属层SD1，第四部分位于第二源漏金属层SD2。
在一些示例中，如图6所示，各第二驱动线520呈台阶状。
图7为本公开一实施例提供的一种显示基板中的像素驱动电路的等效示意图。如图7所示，该像素驱动电路2152包括第一薄膜晶体管T21、第二薄膜晶体管T22、第三薄膜晶体管T23、第四薄膜晶体管T24、第五薄膜晶体管T25、第六薄膜晶体管T26和第七薄膜晶体管T27和存储电容Cst。第一薄膜晶体管T21包括第一栅极G1和位于第一栅极G1两侧的第一源极S1和第一漏极D1，第二薄膜晶体管T22包括第二栅极G2和位于第二栅极G2两侧的第二源极S2和第二漏极D2，第三薄膜晶体管T23包括第三栅极G3和位于第三栅极G3两侧的第三源极S3和第三漏极D3，第四薄膜晶体管T24包括第四栅极G4和位于第四栅极G4两侧的第四源极S4和第四漏极D4，第五薄膜晶体管T25包括第五栅极G5和位于第五栅极G5两侧的第五源极S5和第五漏极S5，第六薄膜晶体管T26包括第六栅极G6和位于第六栅极G6两侧的第六源极S6和第六漏极D6，第七薄膜晶体管T27包括第七栅极G7和位于第七栅极G7两侧的第七源极S7和第七漏极D7。存储电容Cst包括第一电极块CE1和第二电极块CE2。需要说明的是，图7示出的像素驱动电路采用了7T1C结构。然而，本公开实施例包括但不限于此，该像素驱动电路也可采用其他电路结构。
例如，如7所示，复位信号线640与第六薄膜晶体管T26的栅极G6相连；第六漏极D6和第三漏极D3相连，第三源极S3、第一漏极D1和第五源极S5连接至第一节点N1，第一源极S1、第二漏极D2和第四漏极D4连接至第二节点N2，第五漏极D5和第七漏极D7相连。第六源极S6和第七源极S7与初始化信号线630相连，第二源极S2可与数据线610相连；第四源极S4与电源线620相连，栅线650与第三薄膜晶体管T23的第三栅极G相连，发光控制线660与第五栅极G5相连。
下面将对图7所示的像素驱动电路的一种工作方式进行示意性描述。首先，当向复位信号线640传输复位信号并使得第七薄膜晶体管T7导通时，流经各个子像素的阳极的剩余电流通过第七薄膜晶体管T7放电到第六薄膜晶体管T6，从而可抑制由于流经各个子像素的阳极的剩余电流导致的发光。然后，当向复位信号线640传输复位信号并向初始化信号线630传输初始化信号时，第 六薄膜晶体管T6导通，并且通过第六薄膜晶体管T6向第一薄膜晶体管T1的第一栅极G1和存储电容Cst的第一电极块CE1施加初始化电压Vint，使得第一栅极G1和存储电容Cst初始化。第一栅极G1初始化可使得第一薄膜晶体管T1导通。
随后，当向栅线650传输栅极信号并向数据线610传输数据信号时，第二薄膜晶体管T2和第三薄膜晶体管T3都导通，通过第二薄膜晶体管T2和第三薄膜晶体管T3向第一栅极G1施加数据电压Vd。此时，施加到第一栅极G1的电压是补偿电压Vd+Vth，并且施加到第一栅极G1的补偿电压也被施加到存储电容Cst的第一电极块CE1。
随后，电源线620向存储电容Cst的第二电极块CE2施加驱动电压Vel，向第一电极块CE1施加补偿电压Vd+Vth，使得与分别施加到存储电容Cst的两个电极的电压之间的差对应的电荷存储在存储电容Cst中，第一薄膜晶体管T1导通达到预定时间。
随后，当向发光控制线660施加发射控制信号时，第四薄膜晶体管T4和第五薄膜晶体管T5都导通，使得第四薄膜晶体管T4向第五薄膜晶体管T5施加驱动电压Vel。驱动电压Vel穿过由存储电容Cst导通的第一薄膜晶体管T1时，对应的驱动电压Vel与通过存储电容Cst向第一栅极G1施加的电压之间的差驱动电流Id流经第一薄膜晶体管T1的第一漏极区D3，驱动电流Id通过第五薄膜晶体管T5施加到各个子像素，使得各个子像素的发光层发光。
图8为本公开一实施例提供的一种发光控制单元的等效电路图。如图8所示，发光控制单元包括：第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、第八晶体管T8、第九晶体管T9、第十晶体管T10(又称输出晶体管)、第一电容C1、第二电容C2和第三电容C3。该发光控制单元采用10T3C结构，当然本公开实施例包括但不限于此。需要说明的是，上述发光控制单元即为发光控制移位寄存器，当多个发光控制移位寄存器级联时，第一级发光控制移位寄存器中的第一晶体管T1的第二极可与输入端连接，该输入端被配置为与触发信号线STV连接以接收触发信号作为输入信号，而其它各级发光控制移位寄存器单元中的第一晶体管T1的第二极和上一级发光控制移位寄存器单元的输出端电连接，以接收上一级发光控制移位寄存器单元的输出端OUT输出的输出信号作为输入信号，由此实现移位输出，以向显示基板的显示区中的阵列排布的像素提供例 如逐行移位的发光控制信号。
如图8所示，第一晶体管T1的栅极和第一时钟信号线310连接以接收第一时钟信号，第一晶体管T1的第一极和第一节点N1连接，第一晶体管T1的第二极和输入端连接。例如，当该发光控制单元为第一级发光控制单元时，输入端与触发信号线STV连接以接收触发信号，当该发光控制单元为除第一级发光控制单元以外的其他各级发光控制单元时，输入端与其上一级发光控制单元的输出端OUT连接。
如图8所示，第二晶体管T2，第二晶体管T2的栅极和第一节点N1连接，第二晶体管T2的第一极和第二节点N2连接，第二晶体管T2的第二极和第一时钟信号线310连接以接收第一时钟信号。
如图8所示，第三晶体管T3的栅极和第一时钟信号线310连接以接收第一时钟信号，第三晶体管T3的第一极和第二节点N2连接，第三晶体管T3的第二极和第一电源线410连接以接收第一电压。
如图8所示，第四晶体管T4的栅极和第二时钟信号线320连接以接收第二时钟信号，第四晶体管T4的第一极和第一节点N1连接，第四晶体管T4的第二极和第五晶体管T5的第二极连接。
如图8所示，第五晶体管T5的栅极和第二节点N2连接，第五晶体管T5的第一极和第二电源线420连接以接收第二电压。
如图8所示，第六晶体管T6的第一极和第二时钟信号线320连接以接收第二时钟信号，第六晶体管T6的第二极和第三节点N3连接。
如图8所示，第七晶体管T7的栅极和第二时钟信号线320连接以接收第二时钟信号，第七晶体管T7的第一极和第三节点N3连接，第七晶体管T7的第二极和第四节点N4连接。
如图8所示，第八晶体管T8的栅极和第一节点N1连接，第八晶体管T8的第一极和第四节点N4连接，第八晶体管T8的第二极和第二电源线420连接以接收第二电压。
如图8所示，第九晶体管T9的栅极和第四节点N4连接，第九晶体管T9的第一极和第二电源线420连接以接收第二电压，第九晶体管T9的第二极和输出端连接。
如图8所示，第十晶体管T10的第一极和第一电源线410连接以接收第一电压，第十晶体管T10的第二极和输出端连接。
如图8所示，第一电容C1的第二极和第三节点N3连接；第二电容C2的第二极和第二时钟信号线320连接以接收第二时钟信号；第三电容C3的第一极和第四节点N4连接，第三电容C3的第二极和第二电源线420连接以接收第二电压。
需要说明的是，图8所示的发光控制单元中的晶体管均是以p型晶体管为例进行说明的，即各个晶体管在栅极接入低电平(导通电平)时导通，而在接入高电平(截止电平)时截止。此时，晶体管的第一极可以是源极，晶体管的第二极可以是漏极。当然，本公开实施例包括但不限于此，各个晶体管也可以采用n型晶体管或混合采用p型晶体管和n型晶体管，只需同时将选定类型的晶体管的端口极性按照本公开的实施例中的相应晶体管的端口极性进行连接即可。另外，该发光控制单元的工作原理可参考本领域的相关介绍，在此不在赘述。
需要说明的是，该发光控制单元中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，这里均以薄膜晶体管为例进行说明，例如该晶体管的有源层(沟道区)采用半导体材料，例如，多晶硅(例如低温多晶硅或高温多晶硅)、非晶硅、氧化铟镓锡(IGZO)等，而栅极、源极、漏极等则采用金属材料，例如金属铝或铝合金。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极。此外，在本公开的实施例中，电容的电极可以采用金属电极或其中一个电极采用半导体材料(例如掺杂的多晶硅)。
在一些示例中，第九晶体管T9和第十晶体管T10在多个连接电极结构150所在的膜层上正投影与多个连接电极结构150间隔设置，从而可避免连接电极结构150上的信号影响发光控制单元。由于第九晶体管T9和第十晶体管T10的沟道的宽长比(W/L)较大，通过将第九晶体管T9和第十晶体管T10在多个连接电极结构150所在的膜层上正投影与多个连接电极结构150间隔设置可避免连接电极结构影响第九晶体管T9和第十晶体管T10，从而可改善像素发光后的显示亮度差异和色偏等问题。
图9为本公开一实施例提供的一种栅驱动单元的等效电路图。如图9所示，该栅驱动单元2252包括：输入晶体管241、第一控制晶体管242、第二控制晶体管243、输出控制晶体管244、栅极输出晶体管245、第一降噪晶体管246、 第二降噪晶体管247、稳压晶体管248、第一扫描电容251和第二扫描电容252。由此，该栅驱动单元可采用8T2C结构，当然本公开实施例包括但不限于此，该栅驱动单元也可采用其他电路结构。
需要说明的是，上述的栅驱动单元即为栅扫描移位寄存器；当多个栅驱动单元级联时，第一级栅驱动单元中的输入晶体管T1的第一极和输入端连接，输入端被配置为与触发信号线STV连接以接收触发信号作为输入信号，而其它各级栅驱动单元中的输入晶体管T1的第一极和上一级栅驱动单元的输出端电连接，以接收上一级栅驱动单元的输出端OUT输出的输出信号作为输入信号，由此实现移位输出，以用于对显示基板中的像素进行逐行扫描。
如图9所示，输入晶体管241的栅极和第三时钟信号线330连接，输入晶体管241的第二极和输入端连接，输入晶体管241的第一极和第一扫描节点SN1连接。
如图9所示，第一控制晶体管242的栅极和第一扫描节点SN1连接，第一控制晶体管242的第二极和第三时钟信号线330连接，第一控制晶体管242的第一极和第二扫描节点SN2连接。
如图9所示，第二控制晶体管243的栅极和第三时钟信号线330连接，第二控制晶体管243的第二极和第三电源线430连接，第二控制晶体管243的第一极和第二扫描节点SN2连接。
如图9所示，输出控制晶体管244的栅极和第二扫描节点SN2连接，输出控制晶体管244的第一极和第四电源线440连接，输出控制晶体管245的第二极和输出端连接。
如图9所示，第一扫描电容251的第一极和第二扫描节点SN2连接，第一扫描电容251的第二极和第四电源线440连接。
如图9所示，栅极输出晶体管245的栅极和第三扫描节点SN3连接，栅极输出晶体管245的第一极和第四时钟信号线340连接，栅极输出晶体管245的第二极和输出端连接。
如图9所示，第二扫描电容252的第一极和第三扫描节点SN3连接，第二扫描电容252的第二极和输出端连接。
如图9所示，第一降噪晶体管246的栅极和第二扫描节点SN2连接，第一降噪晶体管246的第一极和第四电源线440连接，第一降噪晶体管246的第二极和第二降噪晶体管247的第二极连接。
如图9所示，第二降噪晶体管247的栅极和第四时钟信号线340连接，第二降噪晶体管247的第一极和第一扫描节点SN1连接。
如图9所示，稳压晶体管248的栅极和第三电源线430连接，稳压晶体管248的第二极和第一扫描节点SN1连接，稳压晶体管248的第一极和第三扫描节点SN3连接。
需要说明的是，图9中所示的栅驱动单元中的晶体管均是以p型晶体管为例进行说明的，即各个晶体管在栅极接入低电平时导通(导通电平)，而在接入高电平时截止(截止电平)。此时，晶体管的第一极可以是源极，晶体管的第二极可以是漏极。当然，本公开实施例包括但不限于此，各个晶体管也可以采用n型晶体管或混合采用p型晶体管和n型晶体管，只需同时将选定类型的晶体管的端口极性按照本公开的实施例中的相应晶体管的端口极性进行连接即可。另外，该栅驱动单元的工作原理可参考本领域的相关介绍，在此不在赘述。
需要说明的是，该栅驱动单元中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，这里均以薄膜晶体管为例进行说明，例如该晶体管的有源层(沟道区)采用半导体材料，例如，多晶硅(例如低温多晶硅或高温多晶硅)、非晶硅、氧化铟镓锡(IGZO)等，而栅极、源极、漏极等则采用金属材料，例如金属铝或铝合金。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极。此外，在本公开的实施例中，电容的电极可以采用金属电极或其中一个电极采用半导体材料(例如掺杂的多晶硅)。
在一些示例中，输出控制晶体管244和栅极输出晶体管245在多个连接电极结构150所在的膜层上正投影与多个连接电极结构150间隔设置。由于输出控制晶体管244和栅极输出晶体管245的沟道的宽长比(W/L)较大，通过将输出控制晶体管244和栅极输出晶体管245在多个连接电极结构150所在的膜层上正投影与多个连接电极结构150间隔设置可避免连接电极结构影响输出控制晶体管244和栅极输出晶体管245，从而可改善像素发光后的显示亮度差异和色偏等问题。
图10为本公开一实施例提供的一种显示基板上第二显示区的示意图。如图10所示，第二显示区120包括：多个像素岛1202，沿第一方向和第二方向 阵列设置，各像素岛1202包括至少一个像素；第一开口1204，沿第一方向延伸且位于在第二方向上相邻的两个像素岛1202之间；以及第二开口1206，沿第二方向延伸且位于在第一方向上相邻的两个像素岛1202之间。由于第二显示区设置有第一开口和第二开口，即上述的开口图案，从而可便于弯曲和拉伸。
本公开至少一个实施例还提供一种显示装置。图11为本公开一实施例提供的一种显示基板的平面示意图。如图11所示，该显示装置900包括上述任一项的显示基板100。由于该显示基板100通过在高像素密度区域和低像素密度区域之间插入过渡区域，并在过渡区域中设置行驱动电路，从而可利用过渡区域中的行驱动电路来按行驱动第一显示区域、第二显示区域和过渡区域中的多个像素进行显示。该显示基板不用在低像素密度区域之外额外设置一个用于放置行驱动电路的区域，一方面可降低该显示基板的边框宽度，另一方面可解决四曲面屏设计中四个角落区域因设置有开口图案而导致的无法设置行驱动电路的问题。因此，该显示装置具有较窄的边框宽度，并且可实现四曲面屏设计。
例如，上述的显示装置可为电视、手机、电脑、导航仪、电子画框等具有显示功能的电子产品。
有以下几点需要说明：
(1)本公开实施例附图中，只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开同一实施例及不同实施例中的特征可以相互组合。
以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。

Claims (25)

  1. 一种显示基板，包括：
    第一显示区域；
    第二显示区域，位于所述第一显示区域在第一方向的至少一侧；以及
    过渡区域，位于所述第一显示区域和所述第二显示区域之间，
    其中，所述第一显示区域、所述第二显示区域和所述过渡区域设置有多个像素，所述多个像素沿所述第一方向和与所述第一方向相交的第二方向呈阵列排布，所述第一显示区域的像素密度大于所述第二显示区域的像素密度和所述过渡区域的像素密度，
    所述过渡区域还设置有行驱动电路，所述行驱动电路被配置为按行驱动所述第一显示区域、所述第二显示区域和所述过渡区域中的所述多个像素。
  2. 根据权利要求1所述的显示基板，其中，所述行驱动电路包括沿所述第二方向排列的多个行驱动电路单元。
  3. 根据权利要求2所述的显示基板，其中，各所述像素包括多个子像素，各所述子像素包括像素驱动电路和与所述像素驱动电路电性相连的驱动电极，所述过渡区域包括：
    多个像素电路岛，各所述像素电路岛设置有至少一个所述像素的多个所述像素驱动电路；
    多个第一间隔区，各所述第一间隔区位于在所述第一方向上相邻的两个所述像素电路岛之间；以及
    至少一个驱动间隔区，各所述驱动间隔区也位于在所述第一方向上相邻的两个所述像素电路岛之间，
    其中，所述驱动间隔区设置有所述行驱动电路单元。
  4. 根据权利要求3所述的显示基板，其中，所述过渡区域还包括：
    多个驱动电极岛，与所述多个像素电路岛对应设置，各所述驱动电极岛设置有至少一个所述像素的多个所述驱动电极；以及
    多个第二间隔区，各所述第二间隔区位于在所述第一方向上相邻的两个所述驱动电极岛之间。
  5. 根据权利要求4所述的显示基板，其中，所述多个第一间隔区在所述第一方向上的宽度相等，所述多个第二间隔区在所述第一方向上的宽度相等， 所述第一间隔区在所述第一方向上的宽度小于所述驱动间隔区在所述第一方向上的宽度。
  6. 根据权利要求4所述的显示基板，其中，所述多个第一间隔区在所述第一方向上的宽度相等，所述多个第二间隔区在所述第一方向上的宽度相等，所述第二间隔区在所述第一方向上的宽度为所述驱动间隔区的0.5-1.5倍，所述第一间隔区在所述第一方向上的宽度小于所述驱动间隔区在所述第一方向上的宽度。
  7. 根据权利要求4所述的显示基板，其中，所述行驱动电路单元包括第一行驱动电路单元和第二行驱动电路单元，所述第一行驱动电路单元具有输出端，所述第一行驱动电路单元的所述输出端被配置为同时驱动所述第一显示区域、所述第二显示区域和所述过渡区域中的同属一行的多个所述像素。
  8. 根据权利要求4所述的显示基板，还包括：
    多个连接电极结构，在垂直于所述过渡区域的方向上位于所述多个驱动电极岛靠近所述像素电路岛的一侧，
    其中，所述多个连接电极结构与所述多个驱动电极岛和所述多个像素电路岛分别一一对应设置，各所述连接电极结构包括多个连接电极，以将对应的所述像素电路岛中的多个所述像素驱动电路与对应的所述驱动电极岛中的多个所述驱动电极电性相连。
  9. 根据权利要求8所述的显示基板，其中，所述像素驱动单元包括驱动晶体管，所述驱动晶体管在对应所述驱动电极所在的膜层上正投影与对应所述驱动电极间隔设置。
  10. 根据权利要求9所述的显示基板，其中，所述行驱动电路包括栅驱动电路和发光控制驱动电路，所述行驱动电路单元包括栅驱动单元和发光控制单元，
    所述至少一个驱动间隔区包括两个所述驱动间隔区，两个所述驱动间隔区中的一个设置所述栅驱动单元，两个所述驱动间隔区中的另一个设置所述发光控制单元。
  11. 根据权利要求10所述的显示基板，其中，两个所述驱动间隔区之间间隔至少两个所述第一间隔区。
  12. 根据权利要求10所述的显示基板，其中，所述发光控制单元包括：
    第一晶体管，其中，所述第一晶体管的栅极和第一时钟信号线连接以接收 第一时钟信号，所述第一晶体管的第一极和第一节点连接，所述第一晶体管的第二极和输入端连接；
    第二晶体管，其中，所述第二晶体管的栅极和所述第一节点连接，第二晶体管的第一极和第二节点连接，第二晶体管的第二极和所述第一时钟信号线连接以接收所述第一时钟信号；
    第三晶体管，其中，所述第三晶体管的栅极和所述第一时钟信号线连接以接收所述第一时钟信号，所述第三晶体管的第一极和所述第二节点连接，所述第三晶体管的第二极和第一电源线连接以接收第一电压；
    第四晶体管，其中，所述第四晶体管的栅极和第二时钟信号线连接以接收第二时钟信号，所述第四晶体管的第一极和所述第一节点连接，所述第四晶体管的第二极和第五晶体管的第二极连接；
    所述第五晶体管，其中，所述第五晶体管的栅极和所述第二节点连接，所述第五晶体管的第一极和第二电源线连接以接收第二电压；
    第六晶体管，其中，所述第六晶体管的第一极和所述第二时钟信号线连接以接收所述第二时钟信号，所述第六晶体管的第二极和第三节点连接；
    第七晶体管，其中，所述第七晶体管的栅极和所述第二时钟信号线连接以接收所述第二时钟信号，所述第七晶体管的第一极和所述第三节点连接，所述第七晶体管的第二极和第四节点连接；
    第八晶体管，其中，所述第八晶体管的栅极和所述第一节点连接，所述第八晶体管的第一极和所述第四节点连接，所述第八晶体管的第二极和所述第二电源线连接以接收所述第二电压；
    第九晶体管，其中，所述第九晶体管的栅极和所述第四节点连接，所述第九晶体管的第一极和所述第二电源线连接以接收所述第二电压，所述第九晶体管的第二极和输出端连接；
    第十晶体管，其中，所述第十晶体管的第一极和所述第一电源线连接以接收所述第一电压，所述第十晶体管的第二极和所述输出端连接；
    第一电容，其中，所述第一电容的第二极和所述第三节点连接；
    第二电容，其中，所述第二电容的第二极和所述第二时钟信号线连接以接收所述第二时钟信号；以及
    第三电容，其中，所述第三电容的第一极和所述第四节点连接，所述第三电容的第二极和所述第二电源线连接以接收所述第二电压。
  13. 根据权利要求12所述的显示基板，其中，所述第九晶体管和所述第十晶体管在所述多个连接电极结构所在的膜层上正投影与所述多个连接电极结构间隔设置。
  14. 根据权利要求10-13中任一项所述的显示基板，其中，所述栅驱动单元包括：输入晶体管、第一控制晶体管、第二控制晶体管、输出控制晶体管、栅极输出晶体管、第一降噪晶体管、第二降噪晶体管以及稳压晶体管、第一扫描电容和第二扫描电容，
    其中，所述输入晶体管的栅极和第三时钟信号线连接，所述输入晶体管的第二极和输入端连接，所述输入晶体管的第一极和第一扫描节点连接；
    所述第一控制晶体管的栅极和第一扫描节点连接，所述第一控制晶体管的第二极和所述第三时钟信号线连接，所述第一控制晶体管的第一极和第二扫描节点连接；
    所述第二控制晶体管的栅极和第三时钟信号线连接，所述第二控制晶体管的第二极和第三电源线连接，所述第二控制晶体管的第一极和所述第二扫描节点连接；
    所述输出控制晶体管的栅极和所述第二扫描节点连接，所述输出控制晶体管的第一极和第四电源线连接，所述输出控制晶体管的第二极和输出端连接；
    所述第一扫描电容的第一极和所述第二扫描节点连接，所述第一扫描电容的第二极和所述第四电源线连接；
    所述栅极输出晶体管的栅极和第三扫描节点连接，所述栅极输出晶体管的第一极和第二时钟子信号线连接，所述栅极输出晶体管的第二极和所述输出端连接；
    所述第二扫描电容的第一极和所述第三扫描节点连接，所述第二扫描电容的第二极和所述输出端连接；
    所述第一降噪晶体管的栅极和所述第二扫描节点连接，所述第一降噪晶体管的第一极和所述第四电源线连接，所述第一降噪晶体管的第二极和第二降噪晶体管的第二极连接；
    所述第二降噪晶体管的栅极和第四时钟信号线连接，所述第二降噪晶体管的第一极和所述第一扫描节点连接；以及
    所述稳压晶体管的栅极和所述第三电源线连接，所述稳压晶体管的第二极和所述第一扫描节点连接，所述稳压晶体管的第一极和所述第三扫描节点连 接。
  15. 根据权利要求14所述的显示基板，其中，所述输出控制晶体管和所述栅极输出晶体管在所述多个连接电极结构所在的膜层上的正投影与所述多个连接电极结构间隔设置。
  16. 根据权利要求10-15中任一项所述的显示基板，还包括：
    多条第一驱动线，被配置为驱动所述多个栅驱动单元，
    其中，所述多个栅驱动单元在所述第一方向上错位设置，各所述第一驱动线包括沿所述第二方向延伸的第一部分和沿所述第一方向延伸的第二部分，所述第一部分与对应的所述栅驱动单元相连，所述第二部分将两个相邻的所述栅驱动单元的第一部分相连。
  17. 根据权利要求16所述的显示基板，还包括：数据线，所述第一部分与所述数据线位于第一源漏金属层，所述第二部分位于第二源漏金属层。
  18. 根据权利要求16所述的显示基板，其中，各所述第一驱动线呈台阶状。
  19. 根据权利要求10-18中任一项所述的显示基板，还包括：
    多条第二驱动线，被配置为驱动所述多个发光控制单元，
    其中，所述多个发光控制单元在所述第一方向上错位设置，各所述第二驱动线包括沿所述第二方向延伸的第三部分和沿所述第一方向延伸的第四部分，所述第三部分与对应的所述发光控制单元相连，所述第四部分将两个相邻的所述发光控制单元的第三部分相连。
  20. 根据权利要求19所述的显示基板，还包括数据线，所述第三部分与所述数据线位于第一源漏金属层，所述第四部分位于第二源漏金属层。
  21. 根据权利要求8所述的显示基板，其中，各所述第二驱动线呈台阶状。
  22. 根据权利要求1-21中任一项所述的显示基板，其中，所述显示基板位于所述第二显示区域的部分在垂直于所述第一显示区域的方向上弯曲。
  23. 根据权利要求1-21中任一项所述的显示基板，还包括：
    第三显示区域，位于所述第一显示区域在所述第二方向上的一侧，
    其中，所述第三显示区域中设置有多个所述像素，所述第三显示区域的像素密度与所述第一显示区域的像素密度大致相等，所述第三显示区域在沿所述第一方向延伸的参考线上的正投影与所述第一显示区域、所述第二显示区域和所述过渡区域在所述参考线上的正投影均交叠。
  24. 根据权利要求1-21中任一项所述的显示基板，其中，所述第二显示区包括：
    多个像素岛，沿所述第一方向和所述第二方向阵列设置，各所述像素岛包括至少一个像素；
    第一开口，沿所述第一方向延伸且位于在所述第二方向上相邻的两个所述像素岛之间；以及
    第二开口，沿所述第二方向延伸且位于在所述第一方向上相邻的两个所述像素岛之间。
  25. 一种显示装置，包括根据权利要求1-24中任一项所述的显示基板。
PCT/CN2021/074979 2021-02-03 2021-02-03 显示基板和显示装置 WO2022165658A1 (zh)

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