WO2021234875A1 - プリント配線板 - Google Patents

プリント配線板 Download PDF

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Publication number
WO2021234875A1
WO2021234875A1 PCT/JP2020/020002 JP2020020002W WO2021234875A1 WO 2021234875 A1 WO2021234875 A1 WO 2021234875A1 JP 2020020002 W JP2020020002 W JP 2020020002W WO 2021234875 A1 WO2021234875 A1 WO 2021234875A1
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WO
WIPO (PCT)
Prior art keywords
copper plating
copper
layer
laminated
conductive layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2020/020002
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
将一郎 酒井
隼一 本村
耕司 新田
昌 岩本
光隆 坪倉
万里 曽我部
哲 土子
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Sumitomo Electric Printed Circuits Inc
Original Assignee
Sumitomo Electric Industries Ltd
Sumitomo Electric Printed Circuits Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd, Sumitomo Electric Printed Circuits Inc filed Critical Sumitomo Electric Industries Ltd
Priority to JP2022524774A priority Critical patent/JP7427776B2/ja
Priority to US17/922,872 priority patent/US12177973B2/en
Priority to CN202080100891.1A priority patent/CN115605636B/zh
Priority to PCT/JP2020/020002 priority patent/WO2021234875A1/ja
Publication of WO2021234875A1 publication Critical patent/WO2021234875A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
    • H05K3/427—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in metal-clad substrates
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/1601—Process or apparatus
    • C23C18/1633—Process of electroless plating
    • C23C18/1646—Characteristics of the product obtained
    • C23C18/165—Multilayered product
    • C23C18/1653—Two or more layers with at least one layer obtained by electroless plating and one layer obtained by electroplating
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/18—Pretreatment of the material to be coated
    • C23C18/20—Pretreatment of the material to be coated of organic surfaces, e.g. resins
    • C23C18/2006—Pretreatment of the material to be coated of organic surfaces, e.g. resins by other methods than those of C23C18/22 - C23C18/30
    • C23C18/2046—Pretreatment of the material to be coated of organic surfaces, e.g. resins by other methods than those of C23C18/22 - C23C18/30 by chemical pretreatment
    • C23C18/2073—Multistep pretreatment
    • C23C18/2086—Multistep pretreatment with use of organic or inorganic compounds other than metals, first
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/18—Pretreatment of the material to be coated
    • C23C18/20—Pretreatment of the material to be coated of organic surfaces, e.g. resins
    • C23C18/28—Sensitising or activating
    • C23C18/30—Activating or accelerating or sensitising with palladium or other noble metal
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/31—Coating with metals
    • C23C18/38—Coating with copper
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/54—Electroplating of non-metallic surfaces
    • C25D5/56—Electroplating of non-metallic surfaces of plastics
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/422—Plated through-holes or plated via connections characterised by electroless plating method; pretreatment therefor
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/1601—Process or apparatus
    • C23C18/1603—Process or apparatus coating on selected surface areas
    • C23C18/1607—Process or apparatus coating on selected surface areas by direct patterning
    • C23C18/1608—Process or apparatus coating on selected surface areas by direct patterning from pretreatment step, i.e. selective pre-treatment
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0338—Layered conductor, e.g. layered metal substrate, layered finish layer or layered thin film adhesion layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0344—Electroless sublayer, e.g. Ni, Co, Cd or Ag; Transferred electroless sublayer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0355—Metal foils
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09509—Blind vias, i.e. vias having one side closed
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703—Plating
    • H05K2203/072—Electroless plating, e.g. finish plating or initial plating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703—Plating
    • H05K2203/0723—Electroplating, e.g. finish plating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/022—Processes for manufacturing precursors of printed circuits, i.e. copper-clad substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/421—Blind plated via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/423—Plated through-holes or plated via connections characterised by electroplating method

Definitions

  • This disclosure relates to a printed wiring board.
  • the multilayer printed wiring board is provided with via holes penetrating a base material layer on which a metal foil is laminated as a conductive layer, for example, on the front surface side and the back surface side in order to connect patterns of different conductive layers.
  • a via hole penetrating a base material layer on which a metal foil is laminated as a conductive layer, for example, on the front surface side and the back surface side in order to connect patterns of different conductive layers.
  • an electroless copper plating layer and an electrolytic copper plating layer are formed on the inner peripheral surface of the hole penetrating the base material layer.
  • the printed wiring board of the present disclosure is laminated directly or indirectly on the surface of the base material layer having an insulating property, and on the first conductive layer containing a copper foil and the back surface of the base material layer.
  • the first conductive layer which is directly or indirectly laminated and contains a copper foil, is laminated on the inner circumference and the bottom of a connection hole penetrating the first conductive layer and the base material layer in the thickness direction.
  • a via hole laminate that electrically connects the conductive layer and the second conductive layer is provided, and the via hole laminate is a electroless copper plating layer laminated on the inner circumference and the bottom of the connection hole, and the non-electrolytic copper plating layer.
  • the electrolytic copper plating layer contains copper crystal grains in which the copper foil is oriented in the (100) plane orientation, and the average crystal grain size of copper in the copper foil is 10 ⁇ m.
  • the electrolytic copper plating layer contains palladium, and the laminated amount of the palladium per unit area of the copper foil surface is 0.03 ⁇ g / cm 2 or more and 0.15 ⁇ g / cm 2 or less.
  • FIG. 1 is a schematic cross-sectional view showing a printed wiring board according to an embodiment.
  • FIG. 2 is a schematic perspective view showing a connection hole of the printed wiring board of FIG.
  • Copper foil is generally widely used as the wiring layer of the via hole, and further improvement of mechanical properties such as flexibility is required for this copper foil.
  • mechanical properties such as flexibility
  • the orientation of copper crystals, the crystal grain size, and the like have been studied in order to improve the mechanical properties.
  • electrolytic copper plating is performed after electroless copper plating is performed on the surface of a copper foil having a specific range of crystal orientation and crystal grain size, the copper crystals in the electrolytic copper plating layer are partially abnormal. May grow.
  • the surface of the electrolytic copper plating layer becomes uneven, so that it is erroneously detected as defective in the visual inspection by an automatic optical inspection device (AOI: Automated Optical Inspection system). It may end up.
  • AOI Automated Optical Inspection system
  • an object of the present invention is to provide a printed wiring board capable of suppressing erroneous detection in visual inspection by an automatic optical inspection device and peeling of the bottom of a via hole.
  • the printed wiring board of the present disclosure is laminated directly or indirectly on the surface of the base material layer having an insulating property, and on the first conductive layer containing a copper foil and the back surface of the base material layer.
  • the first conductive layer which is directly or indirectly laminated and contains a copper foil, is laminated on the inner circumference and the bottom of a connection hole penetrating the first conductive layer and the base material layer in the thickness direction.
  • a via hole laminate that electrically connects the conductive layer and the second conductive layer is provided, and the via hole laminate is a electroless copper plating layer laminated on the inner circumference and the bottom of the connection hole, and the non-electrolytic copper plating layer.
  • the electrolytic copper plating layer contains copper crystal grains in which the copper foil is oriented in the (100) plane orientation, and the average crystal grain size of copper in the copper foil is 10 ⁇ m.
  • the electrolytic copper plating layer contains palladium, and the laminated amount of the palladium per unit area of the copper foil surface is 0.03 ⁇ g / cm 2 or more and 0.15 ⁇ g / cm 2 or less.
  • the copper foil laminated on the surface of the base material layer of the printed wiring board contains (100) copper crystal grains oriented in the plane orientation, and the average crystal grain size of the copper is 10 ⁇ m or more.
  • the orientation of the copper crystal grains of the copper foil is likely to be inherited by the copper crystal grains precipitated by the electrolytic copper plating and the copper crystal grains precipitated by the electrolytic copper plating.
  • a non-electrolytic copper plating layer and an electrolytic copper plating layer having the same orientation as the copper crystal grains of the copper foil are formed. Then, there is a possibility that the copper crystals of the electrolytic copper plating layer partially grow abnormally and the surface of the electrolytic copper plating layer becomes uneven.
  • the electroless copper plating layer contains palladium particularly near the interface with the conductive layer below it, so that the orientation of the copper crystal grains of the copper foil is precipitated by the electroless copper plating. It is suppressed that it is inherited by the crystal grains of. As a result, the formation of irregularities on the surface of the electrolytic copper plating layer due to the abnormal growth of copper crystals in the electrolytic copper plating layer is suppressed. Therefore, the printed wiring board can suppress erroneous detection and peeling of the bottom of the via hole in the visual inspection by the automatic optical inspection device.
  • the laminated amount of the palladium per unit area of the copper foil surface is 0.03 ⁇ g / cm 2 or more and 0.15 ⁇ g / cm 2 or less, so that the catalyst nucleus by electroless copper plating is formed.
  • the amount of production is increased, and the growth of plating having an orientation different from that of the copper crystal grains of the copper foil is promoted.
  • the form of the catalyst containing palladium of the present application is an aqueous solution containing palladium ions, and does not include a colloidal colloid type solution such as a tin-palladium solution. Therefore, in the printed wiring board of the present disclosure, the electroless copper plating layer does not contain tin.
  • the crystal grain size means, for example, the crystal grain boundary is detected by analyzing the surface of the copper foil as a sample by the EBSD (Electron Backscatter Diffraction) method, and the crystal grain boundary is detected.
  • the region surrounded by is defined as a crystal grain, and the diameter of a circle having the same area as the area of the region is defined as the crystal grain size of each crystal grain.
  • the "average crystal grain size” means the average value of the crystal grain size of each crystal grain existing in a predetermined measurement field of view.
  • the plane orientation of the copper crystal grains of the copper foil is calculated by measuring the location of the copper foil surface randomly extracted by the EBSD method a plurality of times.
  • the "average thickness” means the average value of the thickness measured at any 10 points.
  • the ratio of the area of the copper crystal grains present on the copper foil surface to the area of the copper foil surface and oriented in the (100) plane direction is 50% or more.
  • the ratio of the area of the (100) plane-oriented copper crystal grains present on the copper foil surface to the area of the copper foil surface is 50% or more, the copper crystals in the electrolytic copper plating layer are partially. The inhibitory effect on abnormal growth is improved.
  • the ratio of the area of the copper crystal grains oriented in the (100) plane orientation is the ratio of the area of the region of the copper crystal grains oriented in the (100) plane orientation to the area of the entire copper foil surface. say.
  • the amount of palladium laminated per unit area of the copper foil surface is 0.05 ⁇ g / cm 2 or more and 0.10 ⁇ g / cm 2 or less.
  • the amount of catalyst nuclei produced by electroless copper plating is in an appropriate range. As a result, it is considered that the electroless copper plating layer and the electrolytic copper plating layer having the same orientation as the copper crystal grains of the copper foil are less likely to be formed.
  • the ratio of the area of the copper crystal grains present on the copper foil surface (100) oriented in the plane direction to the area of the copper foil surface is 60% or more.
  • the ratio of the area of the copper crystal grains oriented in the (100) plane orientation existing on the copper foil surface is in the above range, the effect of suppressing the partial abnormal growth of the copper crystals in the electrolytic copper plating layer is improved. do.
  • the average thickness of the electroless copper plating layer is preferably 0.01 ⁇ m or more and 1.0 ⁇ m or less.
  • the electrolytic copper plating layer can be uniformly formed, and the orientation of the copper crystal grains of the copper foil is deposited by the electrolytic copper plating. It is possible to suppress the inheritance to the crystal grains.
  • FIG. 1 shows a printed wiring board according to an embodiment of the present disclosure.
  • the printed wiring board 20 is laminated directly or indirectly on the surface of the base material layer 1 having an insulating property, the first conductive layer 2 containing a copper foil, and the back surface of the base material layer 1.
  • the second conductive layer 3 containing the copper foil is laminated directly or indirectly on the inner circumference and the bottom of the connection hole 5 penetrating the first conductive layer 2 and the base material layer 1 in the thickness direction.
  • a via hole laminate 10 for electrically connecting between the first conductive layer 2 and the second conductive layer 3 is provided.
  • the via hole 4 for connecting the patterns of different conductive layers is formed by laminating the via hole laminate 10 in the connection hole 5.
  • base material layer 1 examples include polyamide, polyimide, polyamideimide, and polyester.
  • polyamide, polyimide and polyamide-imide are preferably used in terms of mechanical strength such as heat resistance.
  • the printed wiring board does not necessarily have to have flexibility.
  • the lower limit of the average thickness of the base material layer 1 5 ⁇ m is preferable, and 10 ⁇ m is more preferable.
  • the upper limit of the average thickness of the base material layer 1 is preferably 100 ⁇ m, more preferably 50 ⁇ m. If the average thickness of the base material layer 1 is less than the above lower limit, the strength of the base material layer 1 may be insufficient. On the contrary, when the average thickness of the base material layer 1 exceeds the above upper limit, the flexibility may be insufficient.
  • the first conductive layer 2 and the second conductive layer 3 are formed by patterning a copper foil laminated on the base material layer 1.
  • the copper foil contains copper crystal grains oriented in the (100) plane orientation, and the average crystal grain size of copper in the copper foil is 10 ⁇ m or more. When the plane orientation and the average crystal grain size of the copper crystal grains of the copper foil are within the above ranges, the mechanical properties such as flexibility are excellent.
  • the first conductive layer 2 and the second conductive layer 3 may have a land to which the via hole 4 is connected and a wiring pattern having a width smaller than the land and extending linearly in order to improve the wiring density. good.
  • the copper foil contains (100) copper crystal grains oriented in a plane orientation.
  • the lower limit of the average crystal grain size of copper in the copper foil is 10 ⁇ m, preferably 12 ⁇ m.
  • the upper limit of the average crystal grain size of copper in the copper foil is not particularly limited, but may be, for example, 100 ⁇ m, preferably 80 ⁇ m, and more preferably 55 ⁇ m.
  • the average crystal grain size of copper in the copper foil is less than 10 ⁇ m, the appearance of the surface of the electrolytic copper plating layer is unlikely to deteriorate, so that the effect of the printed wiring board cannot be fully exhibited.
  • the lower limit of the ratio of the area of the copper crystal grains oriented in the (100) plane orientation existing on the copper foil surface to the area of the copper foil surface is preferably 50%, more preferably 60%. It is preferable, and 80% is more preferable.
  • the ratio of the area of the (100) plane-oriented copper crystal grains existing on the copper foil surface to the area of the copper foil surface is in the above range, the copper crystals in the electrolytic copper plating layer are partially. The inhibitory effect on abnormal growth is improved. If the ratio of the above area is less than 40%, the appearance of the electrolytic copper plating layer surface is unlikely to be deteriorated, so that the effect of the printed wiring board cannot be fully exhibited.
  • the ratio of the area of the (100) plane-oriented copper crystal grains present on the copper foil surface to the area of the copper foil surface is not particularly limited, but is not particularly limited, for example. This can be achieved by controlling the element content, controlling the rolling conditions, heat treatment, and the like.
  • the lower limit of the average thickness of the first conductive layer 2 and the second conductive layer 3 is preferably 2 ⁇ m, more preferably 5 ⁇ m, from the viewpoint of ensuring sufficient conductivity.
  • the upper limit of the average thickness of the first conductive layer 2 and the second conductive layer 3 is preferably 100 ⁇ m, more preferably 50 ⁇ m, from the viewpoint of circuit formability.
  • the via hole laminate 10 has an electrolytic copper plating layer 8 laminated on the inner circumference and the bottom of the connection hole 5, and an electrolytic copper plating layer 7 laminated on the surface of the electrolytic copper plating layer 8.
  • the via hole laminate 10 is laminated on the inner circumference and the bottom of the connection hole 5 that penetrates the first conductive layer 2 and the base material layer 1 in the thickness direction.
  • the via hole laminate 10 electrically connects between the first conductive layer 2 and the second conductive layer 3. More specifically, the via hole laminate 10 is exposed on the inner circumference of the connection hole 5, the surface of the first conductive layer 2 opposite to the base material layer 1, and the inside of the connection hole 5 of the second conductive layer 3.
  • the configuration may include an electrolytic copper plating layer 8 laminated on the surface (that is, the bottom) and an electrolytic copper plating layer 7 further laminated on the electrolytic copper plating layer 8.
  • FIG. 2 shows a state before forming the via hole 4 and patterning the first conductive layer 2 and the second conductive layer 3 in order to show the shape of the connection hole 5.
  • the connection hole 5 is defined by a cylindrical surface that penetrates the base material layer 1 and the first conductive layer 2 in the thickness direction and forms the connection hole 5. Then, by laminating the via hole laminate 10 in the connection hole 5, the via hole 4 for connecting the patterns of the first conductive layer 2 and the second conductive layer is formed.
  • the electrolytic copper plating layer 8 is a thin layer having conductivity, and is used as an adherend when the electrolytic copper plating layer 7 is formed by electrolytic copper plating.
  • the electroless copper plating layer 8 can be formed of copper laminated by electroless copper plating. Copper plating is suitable for printed wiring boards because it has good flexibility, thickening possibility, adhesion to electrolytic copper plating, and high conductivity.
  • This electroless copper plating is a treatment for precipitating a metal having catalytic activity by the reducing action of the catalyst, and can be performed by applying various commercially available electroless copper plating solutions. By using the electrolytic copper plating layer in this way, the electrolytic copper plating layer 8 can be easily laminated, and the electrolytic copper plating layer 7 can be further laminated reliably.
  • the lower limit of the average thickness of the electroless copper plating layer 8 is preferably 0.05 ⁇ m, more preferably 0.10 ⁇ m.
  • the upper limit of the average thickness of the electroless copper plating layer 8 is preferably 1.0 ⁇ m, more preferably 0.5 ⁇ m. If the average thickness of the electrolytic copper plating layer 8 is less than the above lower limit, the continuity of the electrolytic copper plating layer 8 cannot be ensured, and the electrolytic copper plating layer 8 may not be formed uniformly. Further, when the average thickness is less than the above lower limit, the orientation of the copper crystal grains of the copper foil may be easily taken over by the copper crystal grains precipitated by the electroless copper plating.
  • the average thickness of the electroless copper plating layer 8 exceeds the above upper limit, the cost may increase unnecessarily.
  • the electrolytic copper plating layer can be uniformly formed, and the orientation of the copper crystal grains of the copper foil is deposited by the electrolytic copper plating. It is possible to suppress the inheritance to the crystal grains.
  • the electroless copper plating layer 8 contains palladium as a catalyst. Palladium is applied as a catalyst before the electroless copper plating layer laminating step described later, and the electroless copper plating layer is laminated on the palladium. Therefore, palladium is present in a high content in the vicinity of the interface with the conductive layer in the electroless copper plating layer. In the printed wiring board 20, since the electroless copper plating layer 8 contains palladium, it is suppressed that the orientation of the copper crystal grains of the copper foil is taken over by the copper crystal grains precipitated by the electroless copper plating. NS.
  • examples of the form of the catalyst containing palladium of the present application include an aqueous solution containing palladium ions, and water is used as the solvent.
  • the lower limit of the amount of lamination of palladium per unit area of the copper foil surface is 0.03 ⁇ g / cm 2, 0.05 ⁇ g / cm 2 is preferred.
  • the upper limit of the amount of lamination of the palladium, 0.15 ⁇ g / cm 2, 0.10 ⁇ g / cm 2 is preferred.
  • the amount of catalyst nuclei produced by electroless copper plating is in an appropriate range. As a result, it is considered that the electroless copper plating layer 8 and the electrolytic copper plating layer 7 having the same orientation as the copper crystal grains of the copper foil are less likely to be formed.
  • the connection strength between the copper foil contained in the second conductive layer 3 and the electrolytic copper plating layer 8 and the electrolytic copper plating layer 7 at the bottom of the via hole 4 weakens, and the bottom of the via hole 4 May peel off.
  • the electrolytic copper plating layer 7 is laminated on the surface of the electrolytic copper plating layer 8 by electrolytic copper plating.
  • electrolytic copper plating layer 8 By forming the electroless copper plating layer 8 in this way and then providing the electrolytic copper plating layer 7 on the inner circumference and the bottom thereof, the via hole 4 having excellent conductivity can be easily and surely formed.
  • copper is inexpensive and has high conductivity, copper is preferably used as the metal for forming the electrolytic copper plating layer.
  • the lower limit of the average thickness of the electrolytic copper plating layer 7 is preferably 1 ⁇ m, more preferably 5 ⁇ m.
  • the upper limit of the average thickness of the electrolytic copper plating layer 7 is preferably 50 ⁇ m, more preferably 30 ⁇ m.
  • the via hole 4 is broken due to bending or the like of the printed wiring board 20, and the electrical connection between the first conductive layer 2 and the second conductive layer 3 is made. May be cut off.
  • the average thickness is less than the above lower limit, the orientation of the copper crystal grains of the copper foil may be easily taken over by the copper crystal grains precipitated by the electrolytic copper plating.
  • the average thickness of the electrolytic copper plating layer 7 exceeds the above upper limit, the printed wiring board 20 may become excessively thick or the manufacturing cost may increase unnecessarily.
  • the method for manufacturing the printed wiring board is, for example, a conductive layer laminating step of laminating a first conductive layer containing a copper foil on the surface of a base material layer and laminating a second conductive layer containing a copper foil on the back surface of the base material layer. And, a connection hole forming step of forming a connection hole penetrating the first conductive layer and the base material layer in the thickness direction, and pretreatment before performing electrolytic copper plating on the inner circumference and the bottom of the connection hole.
  • the electroless copper plating pretreatment step the electroless copper plating layer laminating step of laminating the electroless copper plating layer on the inner circumference and the bottom of the connection hole where the electroless copper plating pretreatment was performed, and the electroless copper It is provided with an electrolytic copper plating layer laminating step of laminating an electrolytic copper plating layer on the surface of the plating layer.
  • the first conductive layer is formed by laminating the above-mentioned copper foil on the surface of the base material layer. Further, the second conductive layer is formed by laminating the above-mentioned copper foil on the back surface of the base material layer. In the conductive layer laminating step, a conductive pattern is formed on the surface of the base material layer by a known method.
  • the method of laminating the copper foil constituting the first conductive layer and the second conductive layer on the base material layer is not particularly limited, and for example, a bonding method in which the copper foil is bonded with an adhesive, or a method of laminating the base material layer on the copper foil.
  • a laminating method in which a copper foil is attached to a base material layer by a hot press can be used.
  • the method for forming a hole for electrically connecting the first conductive layer and the second conductive layer is not particularly limited, and for example, a hole is made in the first conductive layer and the base material layer with a microdrill or a laser. 2 A method of exposing the copper foil of the conductive layer can be used.
  • the electroless copper plating pretreatment step is a step of performing pretreatment before performing electroless copper plating on the inner circumference and the bottom of the connection hole. In this step, for example, a cleaner step, an acid treatment step, a predip step, a catalyst treatment step, a reduction step and the like are performed.
  • the pre-dip step is a step of immersing the catalyst in a solution obtained by removing the catalyst from the catalyst solution before immersing in the catalyst solution.
  • a laminate having a base material layer and a conductive layer is immersed in an activator containing palladium ions.
  • a water washing step is performed.
  • the catalyst treatment step using palladium is performed after the conductive layer laminating step and before the electroless copper plating layer laminating step. Therefore, palladium is present in a high content in the vicinity of the interface with the conductive layer in the electroless copper plating layer.
  • the catalyst is reduced. Specifically, in the reduction step, palladium ion (Pd 2+ ) is reduced to become palladium (Pd 0 ) and formed on the surface to form a catalyst nucleus, and the palladium catalyst is supported on the surface of the conductive pattern. After the reduction step, a washing step is performed.
  • the electroless copper plating layer laminating step the electroless copper plating layer is formed by applying electroless copper plating to the inner circumference and the bottom of the connection hole.
  • a laminate having a base material layer and a conductive layer is immersed in an electroless copper plating solution whose plating reaction is activated by heating, and copper is laminated on the surface of a conductive pattern.
  • the electroless copper plating solution is preferably an alkaline bath.
  • the lower limit of the heating temperature of the electroless copper plating solution is preferably 20 ° C.
  • the upper limit of the heating temperature of the electroless copper plating solution is preferably 40 ° C. If the heating temperature of the electroless copper plating solution does not reach the above lower limit, the plating reaction may be insufficient. On the other hand, when the heating temperature of the electroless copper plating solution exceeds the above upper limit, it may not be easy to adjust the thickness of the formed electroless copper plating layer.
  • the lower limit of the immersion time in the electroless copper plating solution is preferably 1 minute, more preferably 2 minutes.
  • the upper limit of the immersion time in the electroless copper plating solution is preferably 30 minutes, more preferably 20 minutes. If the immersion time in the electroless copper plating solution does not reach the above lower limit, it may not be possible to form an electroless copper plating layer having a sufficient thickness. On the other hand, if the immersion time in the electroless copper plating solution exceeds the above upper limit, it may not be possible to sufficiently prevent the erosion of the conductive pattern due to the action of the local battery.
  • electrolytic copper plating layer laminating process In the electrolytic copper plating layer laminating step, the electrolytic copper plating layer is laminated on the surface of the electrolytic copper plating layer by electrolytic copper plating. In this electrolytic copper plating step, the thickness of the laminate for via holes is increased to a desired thickness.
  • electrolytic copper plating in contact with the inner circumference and the bottom of the electrolytic copper plating layer by laminating metal by electrolytic copper plating with the electrolytic copper plating layer as an adherend It is possible to form a layer and form a via hole with sufficient thickness.
  • the printed wiring board when a copper foil having copper crystal grains oriented in the (100) plane orientation and an average crystal grain size of 10 ⁇ m or more is used for the conductive layer, electrolytic copper plating of the laminate for via holes is performed. The formation of irregularities on the layer surface is suppressed. Therefore, the printed wiring board can suppress erroneous detection and peeling of the bottom of the via hole in the visual inspection by the automatic optical inspection device. Therefore, the printed wiring board can be particularly preferably used as a flexible printed wiring board used in a small portable electronic device or the like.
  • the first conductive layer and the second conductive layer are relative to each other, and even if the conductive layer to be the first conductive layer in one via hole is used as the second conductive layer in another via hole. good.
  • the printed wiring board may be a multilayer wiring board on which a further base material layer and a conductive layer are laminated. Further, the printed wiring board may include other layers such as a coverlay, a solder resist, and a shield film. Further, the via hole when the printed wiring board is a multilayer wiring board may be a via hole penetrating the multilayer.
  • the sample was immersed in an aqueous solution (activator) containing palladium ions as a catalytic treatment.
  • activator aqueous solution containing palladium ions as a catalytic treatment.
  • the conditions of the electroless copper plating pretreatment step 5 were as follows.
  • the electroless copper plating was performed at 23 ° C. for 15 minutes, and an electroless copper plating layer having an average thickness of 0.10 ⁇ m was laminated (electroless copper plating layer laminating step). Subsequently, the current density was adjusted to 2 A / dm 2 with respect to the exposed area of the conductive layer, and electrolytic copper plating was performed under the conditions of 25 ° C. and 28 minutes. Then, an electrolytic copper plating layer having an average thickness of 12 ⁇ m was laminated (electrolytic copper plating layer laminating step).
  • Table 1 shows the evaluation results.
  • the average crystal grain size of copper in the copper foil is 10 ⁇ m or more, and the laminated amount of the palladium per unit area of the copper foil surface is 0.03 ⁇ g / cm 2 or more and 0.15 ⁇ g / cm 2 or less.
  • Test No. 1 and No. 4-No. No. 5 had a good effect of suppressing erroneous detection in the visual inspection by the automatic optical inspection device and peeling of the bottom of the via hole.
  • Test No. the amount of the above-mentioned palladium laminated per unit area of the copper foil surface was less than 0.03 ⁇ g / cm 2. In No. 2, the effect of suppressing erroneous detection in the visual inspection by the automatic optical inspection device was inferior. In addition, Test No. 1 in which the amount of the above-mentioned palladium laminated per unit area of the copper foil surface was more than 0.15 ⁇ g / cm 2. No. 3 was inferior in the effect of suppressing the peeling of the bottom of the via hole.

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  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Materials Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Chemical & Material Sciences (AREA)
  • Mechanical Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Inorganic Chemistry (AREA)
  • Electrochemistry (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Chemically Coating (AREA)
  • Electroplating And Plating Baths Therefor (AREA)
  • Other Surface Treatments For Metallic Materials (AREA)
  • Manufacturing Of Printed Wiring (AREA)
PCT/JP2020/020002 2020-05-20 2020-05-20 プリント配線板 Ceased WO2021234875A1 (ja)

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US17/922,872 US12177973B2 (en) 2020-05-20 2020-05-20 Printed wiring board
CN202080100891.1A CN115605636B (zh) 2020-05-20 2020-05-20 印刷布线板
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Publication number Priority date Publication date Assignee Title
EP4395477A1 (en) * 2022-12-22 2024-07-03 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft A component carrier assembly and method for manufacturing a component carrier assembly
WO2025114130A1 (en) * 2023-11-29 2025-06-05 At & S Austria Technologie & Systemtechnik Aktiengesellschaft A component carrier assembly and method for manufacturing a component carrier assembly

Citations (3)

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JP2003209330A (ja) * 2002-01-15 2003-07-25 Ube Ind Ltd 両面回路基板及びその製造方法
WO2008050584A1 (en) * 2006-10-24 2008-05-02 Nippon Mining & Metals Co., Ltd. Rolled copper foil excellent in bending resistance
JP2009071132A (ja) * 2007-09-14 2009-04-02 Hitachi Aic Inc 多層配線基板の製造方法

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JP3152633B2 (ja) 1996-12-19 2001-04-03 イビデン株式会社 多層プリント配線板およびその製造方法
JP4282134B2 (ja) 1999-02-25 2009-06-17 イビデン株式会社 プリント配線板の製造方法
JP2004214410A (ja) 2002-12-27 2004-07-29 Ykc:Kk 多層配線基板の製造方法及び多層配線基板
JP6350064B2 (ja) * 2013-10-09 2018-07-04 日立化成株式会社 多層配線基板の製造方法
CN113811641B (zh) * 2019-05-15 2023-12-05 住友电气工业株式会社 印刷布线板

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Publication number Priority date Publication date Assignee Title
JP2003209330A (ja) * 2002-01-15 2003-07-25 Ube Ind Ltd 両面回路基板及びその製造方法
WO2008050584A1 (en) * 2006-10-24 2008-05-02 Nippon Mining & Metals Co., Ltd. Rolled copper foil excellent in bending resistance
JP2009071132A (ja) * 2007-09-14 2009-04-02 Hitachi Aic Inc 多層配線基板の製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4395477A1 (en) * 2022-12-22 2024-07-03 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft A component carrier assembly and method for manufacturing a component carrier assembly
WO2025114130A1 (en) * 2023-11-29 2025-06-05 At & S Austria Technologie & Systemtechnik Aktiengesellschaft A component carrier assembly and method for manufacturing a component carrier assembly

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