WO2021229837A1 - Dispositif à semi-conducteurs - Google Patents

Dispositif à semi-conducteurs Download PDF

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Publication number
WO2021229837A1
WO2021229837A1 PCT/JP2020/034571 JP2020034571W WO2021229837A1 WO 2021229837 A1 WO2021229837 A1 WO 2021229837A1 JP 2020034571 W JP2020034571 W JP 2020034571W WO 2021229837 A1 WO2021229837 A1 WO 2021229837A1
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Prior art keywords
circuit board
semiconductor device
terminal
wire
electrode pad
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PCT/JP2020/034571
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English (en)
Japanese (ja)
Inventor
達志 金田
弘貴 大森
錬 木村
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住友電気工業株式会社
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Priority to JP2022522499A priority Critical patent/JPWO2021229837A1/ja
Publication of WO2021229837A1 publication Critical patent/WO2021229837A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Definitions

  • This disclosure relates to semiconductor devices.
  • a fuse may be placed to protect the device connected to the outside of the semiconductor device.
  • a fuse is arranged on the P-side connection terminal.
  • a fuse is formed in a part of a substrate pattern located outside the semiconductor module.
  • a semiconductor device is a substrate having a circuit pattern including a first circuit board and a second circuit board arranged at intervals from the first circuit board, and a substrate arranged on the first circuit board and having a thickness.
  • a semiconductor chip through which a current flows in a direction and a capacitor connecting the first circuit board and the second circuit board are provided.
  • the semiconductor chip has a semiconductor layer, a first electrode pad arranged on one side in the thickness direction of the semiconductor layer so as to face the first circuit board, and a second electrode pad arranged on the other side in the thickness direction of the semiconductor layer. Including electrode pads.
  • the semiconductor device further includes a first wire connecting the second electrode pad and the second circuit board.
  • FIG. 1 is a schematic plan view of a part of the semiconductor device according to the first embodiment as viewed in the thickness direction of the substrate.
  • FIG. 2 is an enlarged cross-sectional view when the line segment II-II in FIG. 1 is cut.
  • FIG. 3 is an enlarged cross-sectional view when the line segment III-III in FIG. 1 is cut.
  • FIG. 4 is a schematic plan view of a part of the semiconductor device according to the second embodiment as viewed in the thickness direction of the substrate.
  • FIG. 5 is an equivalent circuit diagram of a part of the semiconductor device according to the third embodiment.
  • FIG. 6 is a schematic plan view of a part of the semiconductor device according to the fourth embodiment as viewed in the thickness direction of the substrate.
  • FIG. 1 is a schematic plan view of a part of the semiconductor device according to the first embodiment as viewed in the thickness direction of the substrate.
  • FIG. 2 is an enlarged cross-sectional view when the line segment II-II in FIG. 1 is cut.
  • FIG. 3 is
  • FIG. 7 is a schematic plan view of a part of the semiconductor device according to the fifth embodiment as viewed in the thickness direction of the substrate.
  • FIG. 8 is a schematic perspective view showing the appearance of the semiconductor device according to the fifth embodiment.
  • FIG. 9 is an enlarged view showing a part of the semiconductor device shown in FIG.
  • FIG. 10 is a schematic plan view of a part of the semiconductor device according to the sixth embodiment as viewed in the thickness direction of the substrate.
  • FIG. 11 is a schematic plan view of a part of the semiconductor device according to the seventh embodiment as viewed in the thickness direction of the substrate.
  • FIG. 12 is a schematic plan view of a part of the semiconductor device according to the eighth embodiment as viewed in the thickness direction of the substrate.
  • FIG. 13 is an equivalent circuit diagram of a part of the semiconductor device according to the ninth embodiment.
  • one of the purposes is to provide a semiconductor device capable of reducing the inductance while suppressing damage to the device connected to the semiconductor device.
  • the semiconductor device is a substrate having a circuit pattern including a first circuit board and a second circuit board arranged at intervals from the first circuit board, and is arranged on the first circuit board in the thickness direction.
  • a semiconductor chip through which a current flows and a capacitor connecting the first circuit board and the second circuit board are provided.
  • the semiconductor chip has a semiconductor layer, a first electrode pad arranged on one side in the thickness direction of the semiconductor layer so as to face the first circuit board, and a second electrode pad arranged on the other side in the thickness direction of the semiconductor layer. Including electrode pads.
  • the semiconductor device further includes a first wire connecting the second electrode pad and the second circuit board.
  • the capacitor is connected to the first circuit board and the second circuit board. Therefore, the surge voltage can be absorbed by the snubber circuit configured by electrically connecting the capacitor in parallel to the semiconductor chip.
  • the capacitor can be arranged near the semiconductor chip, and the inductance can be reduced.
  • the semiconductor device includes a first wire connecting the second electrode pad and the second circuit board. Therefore, the first wire and the capacitor can be electrically connected in series, and the first wire can function as a fuse. Then, when an excessive current flows in the circuit of the semiconductor device and the capacitor is short-circuited, the first wire connected in series with the capacitor is blown.
  • the circuit including the capacitor can be opened, and it is possible to suppress the excessive current from flowing to the device connected to the semiconductor device. As a result, damage to the device connected to the semiconductor device can be suppressed. From the above, according to the above-mentioned semiconductor device, it is possible to reduce the inductance while suppressing damage to the device connected to the semiconductor device.
  • the semiconductor device may include a plurality of capacitors. By doing so, the total capacitance of the capacitor can be increased, and the effect of absorbing the surge voltage can be further enhanced.
  • the capacitor may be a monolithic ceramic capacitor.
  • Multilayer ceramic capacitors have excellent heat resistance. Therefore, it is particularly effective when the heat generated from the semiconductor chip is large.
  • the semiconductor chip may include a semiconductor layer made of SiC or GaN.
  • a semiconductor chip is capable of high-speed switching, but generates a large surge voltage. Since the semiconductor device can absorb the surge voltage while reducing the inductance, the semiconductor chip is suitably used for the semiconductor device.
  • the semiconductor device may include a plurality of semiconductor chips.
  • a plurality of semiconductor chips may be electrically arranged in series. By doing so, it is possible to efficiently absorb the surge voltage in a circuit including a plurality of semiconductor chips.
  • the semiconductor device may further include a first resistor electrically connected in series with the capacitor.
  • a semiconductor device includes an RC snubber circuit composed of a capacitor and a first resistor in the circuit, and can absorb a surge voltage.
  • the semiconductor chip may be a transistor chip.
  • the second electrode pad may be a source electrode pad.
  • the circuit pattern may further include a third circuit board that is spaced apart from each of the first circuit board and the second circuit board.
  • the semiconductor device may further include a second wire connecting the source electrode pad and the third circuit board, and a third wire connected to the gate electrode pad of the semiconductor chip.
  • the diameter of the first wire may be the same as the diameter of at least one of the second wire and the third wire.
  • the semiconductor device has a housing including a frame surrounding the substrate, a first terminal electrically connected to either the first circuit board or the third circuit board, and arranged outside the housing, and a second circuit.
  • a second terminal which is electrically connected to the board and is arranged outside the housing, may be further provided.
  • the user who uses the semiconductor device may not be able to grasp that the first wire is in a blown state, and may continue to use the semiconductor device. Then, since the circuit including the capacitor is open, the semiconductor device continues to operate in a state where the surge voltage cannot be absorbed. As a result, when a surge voltage is generated, the surge voltage cannot be absorbed by the capacitor, and the reliability of the semiconductor device is lowered.
  • the semiconductor device having the above configuration includes a first terminal electrically connected to either the first circuit board or the third circuit board, and a second terminal electrically connected to the second circuit board. ..
  • the first terminal is electrically connected to the source electrode side or the drain electrode side.
  • the second terminal is electrically connected to the source electrode side before the first wire is blown, and is electrically connected to the drain electrode side after the first wire is blown. It will be. Therefore, the potential difference between the first terminal and the second terminal changes before and after the fusing of the first wire. Therefore, if the potential difference between the first terminal and the second terminal is monitored and it is detected that the potential difference between the first terminal and the second terminal has changed, it is possible to know that the first wire has been blown.
  • the first terminal and the second terminal are respectively arranged outside the housing, it is easy to electrically connect each of the first terminal and the second terminal to the device for measuring the potential difference to monitor the potential difference. Can be done. Therefore, according to such a semiconductor device, it is possible to easily grasp whether or not the first wire is blown, and it is possible to determine whether or not to continue the operation of the semiconductor device. As a result, reliability can be improved.
  • the first terminal may be either an independent terminal or a source terminal. By doing so, any terminal can be used as the first terminal. Therefore, a simpler configuration can be obtained.
  • the semiconductor device may further include a second resistor that is electrically connected to the second terminal. By doing so, the resistance value in the second resistor can be adjusted, and the potential difference between the first terminal and the second terminal can be detected as a more appropriate potential difference.
  • the second resistor may be formed in the circuit constituting the second circuit board. By doing so, it becomes easy to manufacture the semiconductor device including the second resistor.
  • the semiconductor device may further include a detection unit that detects a potential difference between the first terminal and the second terminal. By doing so, it is possible to grasp whether or not the first wire has been blown according to the detection result by the detection unit. Therefore, it is possible to more reliably determine whether or not the first wire has been blown.
  • the semiconductor device of the present disclosure has a first circuit board, a second circuit board arranged at a distance from the first circuit board, and a second circuit board arranged at a distance from each of the first circuit board and the second circuit board. It includes a board having a circuit pattern including three circuit boards, a semiconductor chip arranged on the first circuit board and a current flowing in the thickness direction, and a capacitor connecting the first circuit board and the second circuit board. ..
  • the semiconductor chip is a domainista chip, which is a drain electrode pad arranged on one side in the thickness direction of the semiconductor layer so as to face the first circuit board, and the other side in the thickness direction of the semiconductor layer. Includes a source electrode pad, which is placed in.
  • the semiconductor device includes a first wire connecting the source electrode pad and the second circuit board, a second wire connecting the source electrode pad and the third circuit board, a housing including a frame surrounding the substrate, and a first wire.
  • a first terminal electrically connected to either one of the 1 circuit board or the third circuit board and arranged outside the housing, and a second terminal electrically connected to the second circuit board and arranged outside the housing. And further prepare.
  • Such a semiconductor device includes a first terminal electrically connected to either the first circuit board or the third circuit board, and a second terminal electrically connected to the second circuit board. ..
  • the first terminal is electrically connected to the source electrode side or the drain electrode side.
  • the second terminal is electrically connected to the source electrode side before the first wire is blown, and is electrically connected to the drain electrode side after the first wire is blown. It will be. Then, before and after the fusing of the first wire, the potential difference between the first terminal and the second terminal changes. Therefore, if the potential difference between the first terminal and the second terminal is monitored and it is detected that the potential difference between the first terminal and the second terminal has changed, it is possible to know that the first wire has been blown.
  • the first terminal and the second terminal are respectively arranged outside the housing, it is easy to electrically connect each of the first terminal and the second terminal to the device for measuring the potential difference to monitor the potential difference. Can be done. Therefore, according to such a semiconductor device, it is possible to easily grasp whether or not the first wire is blown, and it is possible to determine whether or not to continue the operation of the semiconductor device. As a result, reliability can be improved.
  • FIG. 1 is a schematic plan view of a part of the semiconductor device according to the first embodiment as viewed in the thickness direction of the substrate.
  • FIG. 2 is an enlarged cross-sectional view when the line segment II-II in FIG. 1 is cut.
  • FIG. 3 is an enlarged cross-sectional view when the line segment III-III in FIG. 1 is cut. From the viewpoint of easy understanding, the capacitor and the first wire are shown in FIG.
  • the semiconductor device 11a includes a heat sink 12, a first bonding material 13a, a substrate 14a, a second bonding material 13b, and a transistor chip 23a. , A capacitor 31a, a first wire 29a, a second wire 29b, and a third wire 29c.
  • the heat sink 12 is made of metal.
  • the heat sink 12 is made of, for example, copper.
  • the surface of the heat radiating plate 12 may be nickel-plated.
  • the first joining material 13a is arranged on one surface 12a of the heat radiating plate 12 in the thickness direction.
  • solder specifically, Sn—Ag—Cu-based solder or Sn—Sb-based solder is used.
  • the substrate 14a is joined to the heat radiating plate 12 by the first joining material 13a.
  • the substrate 14a includes a circuit pattern 15a having conductivity, an insulating plate 21 having insulating properties, and a metal plate 22.
  • the circuit pattern 15a is arranged on one surface of the insulating plate 21 in the thickness direction, and the metal plate 22 is arranged on the other surface of the insulating plate 21 in the thickness direction. That is, the substrate 14a has a structure in which a metal plate 22, an insulating plate 21, and a circuit pattern 15a are laminated.
  • the metal plate 22 is made of copper, for example.
  • the insulating plate 21 is made of, for example, ceramic. Examples of the material of the insulating plate 21 include Al 2 O 3 , Al N, and Si 3 N 4 .
  • the circuit pattern 15a is copper wiring.
  • the thickness direction of the heat radiating plate 12 and the thickness direction of the substrate 14a are both in the Z direction.
  • the circuit pattern 15a includes a first circuit board 16a, a second circuit board 16b, and a third circuit board 16c, which are arranged at intervals.
  • the first circuit board 16a and the third circuit board 16c, and the second circuit board 16b and the third circuit board 16c are arranged at intervals in the Y direction, respectively.
  • the first circuit board 16a is electrically connected to, for example, a P terminal (not shown) included in the semiconductor device 11a
  • the third circuit board 16c is connected to an O terminal (not shown) included in the semiconductor device 11a. It is electrically connected.
  • the transistor chip 23a is a wide bandgap semiconductor chip. Specifically, the transistor chip 23a includes a semiconductor layer made of SiC.
  • the transistor chip 23a is, for example, a metal-oxide-semiconductor field effect transistor (MOSFET).
  • MOSFET metal-oxide-semiconductor field effect transistor
  • the transistor chip 23a is a vertical transistor chip. That is, the transistor chip 23a is a transistor chip in which a current flows in the thickness direction (Z direction).
  • the transistor chip 23a includes a semiconductor layer 24a, a drain electrode pad 25a (particularly see FIG. 2) as a first electrode pad arranged on one side of the semiconductor layer 24a in the thickness direction, and a semiconductor layer 24a in the thickness direction. It includes a source electrode pad 26a as a second electrode pad arranged on the other side, and a gate electrode pad 27a as a third electrode pad arranged on the other side in the thickness direction of the semiconductor layer 24a. The source electrode pad 26a and the gate electrode pad 27a are arranged at different positions when viewed in the thickness direction of the substrate 14a.
  • the drain electrode pad 25a of the transistor chip 23a and the first circuit plate 16a are bonded by the second bonding material 13b.
  • the source electrode pad 26a of the transistor chip 23a is electrically connected to the third circuit board 16c by a second wire 29b, which is also called a source wire.
  • a plurality of second wires 29b are provided.
  • the gate electrode pad 27a of the transistor chip 23a is electrically connected to a gate terminal (not shown) included in the semiconductor device 11a by a third wire 29c, which is also called a gate wire.
  • the semiconductor device 11a includes a resin portion 19 that fills a space surrounded by a frame (not shown).
  • a resin portion 19 that fills a space surrounded by a frame (not shown).
  • an epoxy resin is used as the material of the resin portion 19, for example.
  • the frame is attached to the heat radiating plate 12 and is arranged so as to surround the substrate 14a.
  • the frame body and the heat sink 12 constitute a housing (not shown) of the semiconductor device 11a. That is, the housing includes a frame body and a heat sink 12.
  • the capacitor 31a is arranged in a space surrounded by a frame.
  • a monolithic ceramic capacitor is used as the capacitor 31a.
  • the heat resistant temperature of the multilayer ceramic capacitor is 150 ° C. or lower.
  • Multilayer ceramic capacitors have good heat resistance.
  • the capacitor 31a includes a plurality of layered ceramic inner layers 32a, a plurality of internal electrodes 33a, and a pair of external electrodes 34a and 35a.
  • the plurality of inner layers 32a are laminated in the Z direction.
  • a plurality of internal electrodes 33a connected to either one of the external electrodes 34a and 35a are alternately arranged in the Z direction between the layered internal layers 32a.
  • the external electrode 34a and the first circuit plate 16a of the circuit pattern 15a are electrically connected. Specifically, for example, the external electrode 34a and the first circuit board 16a are joined by a third joining material 13c made of solder.
  • the external electrode 35a and the second circuit board 16b of the circuit pattern 15a are electrically connected. Specifically, the external electrode 35a and the second circuit board 16b are joined by the third joining material 13c.
  • the capacitor 31a is electrically connected in parallel with the transistor chip 23a. Specifically, the capacitor 31a is connected to the circuit pattern 15a so that the external electrode 34a is on the drain side of the transistor chip 23a and the external electrode 35a is on the source side of the transistor chip 23a.
  • the semiconductor device 11a includes a first wire 29a that connects the source electrode pad 26a, which is the second electrode pad, and the second circuit board 16b of the circuit pattern 15a.
  • the source electrode pad 26a, which is the second electrode pad, and the second circuit board 16b of the circuit pattern 15a are electrically connected by the first wire 29a. That is, the second circuit board 16b to which the external electrode 35a is connected has the same potential as the source electrode pad 26a.
  • the capacitor 31a is electrically connected in parallel with the transistor chip 23a with the external electrode 34a on the drain side and the external electrode 35a on the source side. Further, the capacitor 31a and the first wire 29a are electrically connected in series.
  • the diameter of the first wire 29a is the same as the diameter of at least one of the second wire 29b and the third wire 29c.
  • the first wire 29a, the second wire 29b, and the third wire 29c all have the same diameter.
  • the materials of the first wire 29a, the second wire 29b, and the third wire 29c are the same. That is, the same wire is used for the first wire 29a, the second wire 29b, and the third wire 29c.
  • the diameter of the first wire 29a is selected according to the requirement because the rated current of the transistor chip 23a and the current for fusing differ depending on the material of the resin portion 19.
  • the current flow during operation of the semiconductor device 11a When the transistor chip 23a is turned on, the current flows from the P terminal through the first circuit plate 16a of the circuit pattern 15a, the transistor chip 23a in the on state, the second wire 29b, and the third circuit plate 16c of the circuit pattern 15a. It flows to the terminal.
  • the capacitor 31a is connected to the first circuit board 16a and the second circuit board 16b. Therefore, the surge voltage can be absorbed by the snubber circuit configured by electrically connecting the capacitor 31a to the transistor chip 23a in parallel. In the semiconductor device 11a, the capacitor 31a can be arranged near the transistor chip 23a, and the inductance can be reduced.
  • the semiconductor device 11a includes a first wire 29a that connects a source electrode pad 26a, which is a second electrode pad, and a second circuit board 16b. Therefore, the first wire 29a and the capacitor 31a can be electrically connected in series, and the first wire 29a can function as a fuse.
  • the capacitor 31a is a monolithic ceramic capacitor. Multilayer ceramic capacitors have excellent heat resistance. Therefore, it is particularly effective when the heat generated from the transistor chip 23a is large. In the present embodiment, since the transistor chip 23a includes a semiconductor layer made of SiC, a large amount of heat is generated during operation. Therefore, the monolithic ceramic capacitor is preferably used in the semiconductor device 11a.
  • the transistor chip 23a includes a semiconductor layer made of SiC. That is, the transistor chip 23a is a SiC transistor chip. Such a SiC transistor chip is capable of high-speed switching, but a large surge voltage is generated. Since the semiconductor device 11a can absorb the surge voltage while reducing the inductance, the transistor chip 23a is suitably used for the semiconductor device 11a.
  • the diameter of the first wire 29a is the same as the diameter of the second wire 29b and the diameter of the third wire 29c. Therefore, when connecting each portion using the second wire 29b and the third wire 29c, the connection by the first wire 29a can also be performed. Therefore, the semiconductor device 11a is a semiconductor device that can reduce the types of wires and can be efficiently manufactured.
  • the double pulse switching effect was verified by simulation when and was not directly connected.
  • LTspice was used as software.
  • the simulation conditions were a voltage of 850V, a current of 150A, and a resistance of 3.3 ohms.
  • FIG. 4 is a schematic plan view of a part of the semiconductor device according to the second embodiment as viewed in the thickness direction of the substrate.
  • the semiconductor device of the second embodiment is different from the case of the first embodiment in that it includes two capacitors.
  • the semiconductor device 11b in the second embodiment includes a plurality of semiconductor devices 11b, and in the present embodiment, the two capacitors 31a and 31b are included.
  • the configuration of the capacitor 31b is the same as the configuration of the capacitor 31a.
  • the capacitor 31b is electrically connected in parallel with both the transistor chip 23a and the capacitor 31a. That is, the external electrode 34b is connected to the first circuit board 16a, and the external electrode 35b is connected to the second circuit board 16b.
  • the semiconductor device 11b of the present embodiment can increase the total capacitance of the capacitors 31a and 31b. Therefore, the semiconductor device 11b is a semiconductor device capable of further enhancing the effect of absorbing the surge voltage.
  • the semiconductor device 11b when multilayer ceramic capacitors are used as the capacitors 31a and 31b, they are advantageous from the viewpoint of heat resistance, but disadvantageous from the viewpoint of capacitance. Therefore, the number of capacitors 31a and 31b electrically connected in parallel with the transistor chip 23a can be increased according to the required characteristics of the semiconductor device 11b, particularly the capacitance.
  • the semiconductor device 11b may include three or more capacitors.
  • FIG. 5 is an equivalent circuit diagram of a part of the semiconductor device according to the third embodiment.
  • the semiconductor device of the third embodiment is different from the case of the first embodiment in that it includes two transistor chips and a resistor in the circuit.
  • the semiconductor device 11c in the third embodiment includes a plurality of semiconductor devices 11c, and in the present embodiment, the two transistor chips 23a and 23b, the capacitor 31a, and the first resistor 36a are included.
  • the first resistor 36a is electrically connected in series with the capacitor 31a.
  • the transistor chips 23a and 23b are electrically connected in series.
  • the capacitor 31a and the first resistor 36a are electrically connected in series to form an RC snubber circuit.
  • Such a semiconductor device 11c can efficiently absorb a surge voltage by including an RC snubber circuit composed of a capacitor 31a and a first resistor 36a in a circuit including a plurality of transistor chips 23a and 23b. can.
  • the semiconductor device 11b may include three or more transistor chips.
  • FIG. 6 is a schematic plan view of a part of the semiconductor device according to the fourth embodiment as viewed in the thickness direction of the substrate.
  • the semiconductor device of the fourth embodiment is different from the case of the first embodiment in that one power supply line includes two transistor chips.
  • the circuit pattern 15b included in the semiconductor device 11d includes the fourth circuit board 16d.
  • the fourth circuit board 16d is arranged at a distance from each of the first circuit board 16a, the second circuit board 16b, and the third circuit board 16c.
  • the semiconductor device 11d according to the fourth embodiment includes two transistor chips 23a and 23c.
  • the transistor chip 23c has a semiconductor layer, a drain electrode arranged on one side in the thickness direction of the semiconductor layer so as to face the fourth circuit plate 16d, and a source arranged on the other side in the thickness direction of the semiconductor layer. It includes an electrode pad 26b and a gate electrode pad 27b arranged on the other side in the thickness direction of the semiconductor layer and to which a gate wire, which is a third wire 29e, is connected.
  • the external electrode 34a of the capacitor 31a is connected to the fourth circuit board 16d.
  • the source wire 26b, which is the second wire 29d connects the source electrode pad 26b of the transistor chip 23c and the first circuit board 16a.
  • a snubber circuit that is collectively attached to a power supply line composed of transistor chips 23a and 23c can be configured.
  • FIG. 7 is a schematic plan view of a part of the semiconductor device according to the fifth embodiment as viewed in the thickness direction of the substrate.
  • FIG. 8 is a schematic perspective view showing the appearance of the semiconductor device according to the fifth embodiment.
  • FIG. 9 is an enlarged view showing a part of the semiconductor device shown in FIG.
  • a one-dot chain line schematically shows the boundary between the inside and the outside of the housing, which will be described later.
  • the illustration of the first end portion and the second end portion described later in FIG. 7 is schematic, and the positions of the first end portion and the second end portion are shown by FIGS. 8 and 9.
  • the resin portion 19 is not shown in FIG.
  • the semiconductor device of the fifth embodiment is different from the case of the first embodiment in that the semiconductor device includes the first terminal and the second terminal described later.
  • the semiconductor device 11e includes a housing 39 including a heat dissipation plate 12 and a frame 38, a first circuit board 16a, a second circuit board 16b, and a first circuit board.
  • a substrate 14a having a circuit pattern 15a including a circuit board 16c, a transistor chip 23a, a capacitor 31a, a resin portion 19, a first wire 29a, a second wire 29b, and a third wire 29c are provided.
  • the frame body 38 is attached to the heat radiating plate 12 and is arranged so as to surround the substrate 14a.
  • the frame body 38 and the heat sink 12 form a housing 39 of the semiconductor device 11a.
  • the resin portion 19 fills the space surrounded by the frame body 38.
  • the first wire 29a connects the source electrode pad 26a, which is the second electrode pad of the transistor chip 23a, and the second circuit board 16b.
  • the second wire 29b connects the source electrode pad 26a and the third circuit board 16c.
  • a plurality of second wires 29b are provided.
  • the third wire 29c connects the gate electrode pad 27a, which is the third electrode pad of the transistor chip 23a, to the gate terminal.
  • the semiconductor device 11e includes a first terminal 41e and a second terminal 42e.
  • the first terminal 41e and the second terminal 42e are respectively arranged outside the housing 39.
  • the first terminal 41e and the second terminal 42e are arranged so as to protrude from the upper end surface 40 of the frame body 38 at intervals in the X direction.
  • the first terminal 41e is electrically connected to the third circuit board 16c.
  • the connection portion 43e which is electrically connected to the first terminal 41e and is arranged in the housing 39, and the third circuit board 16c are electrically connected by the wire 44e.
  • the first terminal 41e is an independent terminal.
  • the first terminal 41e may be a source terminal.
  • the second terminal 42e is an independent terminal, and the second terminal 42e is electrically connected to the second circuit board 16b.
  • the connection portion 45e which is electrically connected to the second terminal 42e and is arranged in the housing 39, and the second circuit board 16b are electrically connected by the wire 46e.
  • the first terminal 41e is electrically connected to the source electrode side.
  • the second terminal 42e is electrically connected to the source electrode side before the first wire 29a is blown. Further, the second terminal 42e is electrically connected to the drain electrode side after the first wire 29a is blown. Therefore, before and after the fusing of the first wire 29a, the potential difference between the first terminal 41e and the second terminal 42e changes.
  • the user of the semiconductor device 11e constantly or periodically measures the potential difference between the first terminal 41e and the second terminal 42e with a tester or the like for measuring the potential difference, and obtains the first terminal 41e and the second terminal 42e. Detect the potential difference between.
  • the semiconductor device 11a having such a configuration, if the potential difference between the first terminal 41e and the second terminal 42e is monitored and it is detected that the potential difference between the first terminal 41e and the second terminal 42e has changed, the first terminal is used. It can be grasped that the wire 29a has been blown.
  • the first terminal 41e is electrically connected to the third circuit board 16c on the source electrode side, and the second terminal 42e is on the source electrode side before the first wire 29a is blown. It is electrically connected to the second circuit board 16b. Therefore, before the first wire 29a is blown, the potential difference between the first terminal 41e and the second terminal 42e is in a state of nothing (0V).
  • the second circuit plate 16b is electrically connected to the drain electrode side, so that the potential difference between the first terminal 41e and the second terminal 42e is the source. -The potential difference applied between the drains. Therefore, if it is detected that the potential difference between the first terminal 41e and the second terminal 42e is the potential difference applied between the source and the drain from the state where there is no potential difference, it can be determined that the first wire 29a is blown. .. Further, since the first terminal 41e and the second terminal 42e are respectively arranged outside the housing 39, each of the first terminal 41e and the second terminal 42e can be easily electrically connected to the device for measuring the potential difference. Then, the potential difference can be monitored.
  • the potential difference between the first terminal 41e and the second terminal 42e can be easily monitored. Therefore, according to such a semiconductor device 11e, it is possible to easily grasp whether or not the first wire 29a is blown, and it is possible to determine whether or not the operation of the semiconductor device 11e is continued. As a result, reliability can be improved.
  • the first terminal 41e may be a source terminal.
  • the source terminal can be used as the first terminal 41e. Therefore, a simpler configuration can be made.
  • FIG. 10 is a schematic plan view of a part of the semiconductor device according to the sixth embodiment as viewed in the thickness direction of the substrate.
  • the semiconductor device of the sixth embodiment is different from the case of the fifth embodiment in that the first terminal 41e is electrically connected to the first circuit board 16a. That is, in the semiconductor device of the present disclosure, the first terminal 41e may be electrically connected to either the first circuit board 16a or the third circuit board 16c.
  • the first terminal 41e arranged outside the housing 39 is electrically connected to the first circuit board 16a instead of the third circuit board 16c.
  • the semiconductor device 11f having such a configuration, if the potential difference between the first terminal 41e and the second terminal 42e is monitored and it is detected that the potential difference between the first terminal 41e and the second terminal 42e has changed, the first terminal is used. It can be grasped that the wire 29a has been blown.
  • the first terminal 41e is electrically connected to the first circuit board 16a on the drain electrode side.
  • the second terminal 42e is electrically connected to the second circuit board 16b on the source electrode side before the first wire 29a is blown.
  • the potential difference between the first terminal 41e and the second terminal 42e is the potential difference applied between the source and the drain.
  • the second circuit plate 16b is electrically connected to the drain electrode side. Therefore, there is no potential difference between the first terminal 41e and the second terminal 42e (0V). Therefore, if it is detected that the potential difference between the first terminal 41e and the second terminal 42e is in a state where there is no potential difference from the potential difference applied between the source and the drain, it is determined that the first wire 29a has been blown. Can be done. Therefore, according to such a semiconductor device 11f, it is possible to easily grasp whether or not the first wire 29a is blown, and it is possible to determine whether or not the operation of the semiconductor device 11f is continued. As a result, reliability can be improved.
  • FIG. 11 is a schematic plan view of a part of the semiconductor device according to the seventh embodiment as viewed in the thickness direction of the substrate.
  • the semiconductor device of the seventh embodiment is different from the case of the fifth embodiment in that it includes a detection unit for detecting a potential difference between the first terminal 41e and the second terminal 42e.
  • the semiconductor device 11g of the seventh embodiment has a first terminal 41e electrically connected to the third circuit board 16c and a second terminal electrically connected to the second circuit board 16b.
  • a detection unit 49 for detecting a potential difference between the 42e and the first terminal 41e and the second terminal 42e is included.
  • the detection unit 49 is connected to the first terminal 41e by the wiring 47e, and is connected to the second terminal 42e by the wiring 48e.
  • the detection unit 49 is, for example, a tester capable of measuring a voltage. By doing so, it is possible to grasp whether or not the first wire 29a has been blown according to the detection result by the detection unit 49.
  • the first wire 29a is said to have been blown. You can judge. Therefore, it is possible to more reliably determine whether or not the first wire 29a has been blown.
  • FIG. 12 is a schematic plan view of a part of the semiconductor device according to the eighth embodiment as viewed in the thickness direction of the substrate.
  • the semiconductor device of the eighth embodiment is different from the case of the fifth embodiment in that it includes a second resistor.
  • the semiconductor device 11h of the eighth embodiment includes a second resistor 51 that is electrically connected to the second terminal 42e.
  • the second resistor 51 is arranged between the second circuit board 16b and the fifth circuit board 16e included in the circuit pattern 15a of the semiconductor device 11h, and is electrically connected to the second circuit board 16b and the fifth circuit board 16e, respectively. Is connected.
  • the fifth circuit board 16e is electrically connected to the second terminal 42e by the fourth wire 29f. That is, the second circuit board 16b is electrically connected to the second terminal 42e via the second resistor 51.
  • the potential difference between the first terminal 41e and the second terminal 42e can be made smaller than the potential difference applied between the source and the drain. Therefore, even when the potential difference applied between the source and the drain is large, for example, even if it exceeds several hundred V to 1000 V, it can be detected as an appropriate potential difference, for example, several V.
  • the value of the second resistance 51 is preferably 10 to 10000 times the internal resistance of the tester for measuring the potential difference between the first terminal 41e and the second terminal 42e, for example. Alternatively, it is more preferable to set the value to 100 times to 1000 times.
  • FIG. 13 is an equivalent circuit diagram of a part of the semiconductor device according to the ninth embodiment.
  • the first circuit board 16a, the second circuit board 16b, and the third circuit board 16c are schematically shown by broken lines.
  • the semiconductor device of the ninth embodiment is different from the case of the eighth embodiment in that the second resistor is formed in the circuit constituting the second circuit board.
  • the semiconductor device 11i of the ninth embodiment includes a power supply 53 that applies a potential difference between the source and the drain. Further, the semiconductor device 11i includes a second resistor 52 electrically connected to the second terminal 42e.
  • the second resistor 52 is formed in the circuit constituting the second circuit board 16b. That is, the second circuit board 16b is configured to include the second resistor 52. By doing so, it becomes easy to form the second resistor 52. That is, when forming the wiring in the second circuit board 16b, it can be formed with a configuration including the second resistor 52. Then, at the time of manufacturing the semiconductor device 11i, it is not necessary to provide a resistor between the second terminal 42e and the second circuit board 16b. Therefore, it becomes easy to manufacture the semiconductor device 11i including the second resistor 52.
  • the capacitor is a monolithic ceramic capacitor in the semiconductor device, but the capacitor is not limited to this, and other capacitors, for example, a film capacitor may be used.
  • the semiconductor chip included in the semiconductor device is a transistor chip, but the semiconductor chip is not limited to this, and the semiconductor chip is, for example, a diode chip, specifically, a Schottky barrier diode chip. It may be (SBD). In this case, for example, the first electrode pad becomes a cathode pad, and the second electrode pad becomes an anode pad. Further, the semiconductor chip included in the semiconductor device may be an insulated gate bipolar transistor (IGBT).
  • IGBT insulated gate bipolar transistor
  • the semiconductor chip includes a semiconductor layer made of SiC, but the present invention is not limited to this, and the semiconductor chip may include a semiconductor layer made of GaN. That is, the semiconductor chip may include a semiconductor layer made of SiC or GaN. Since the semiconductor device can absorb the surge voltage while reducing the inductance, the semiconductor chip is suitably used for the semiconductor device.
  • the diameter of the first wire is the same as the diameter of the second wire and the diameter of the third wire, but the diameter is not limited to this.
  • the diameter of the second wire and the diameter of the third wire are different, they may be the same as either one. That is, the diameter of the first wire may be the same as the diameter of at least one of the second wire and the third wire.
  • the first terminal 41e is an independent terminal, but the present invention is not limited to this, and the first terminal 41e may be either an independent terminal or a source terminal.
  • the source terminal By using the source terminal as the first terminal, a simpler configuration can be obtained.
  • the first terminal 41e and the second terminal 42e as independent terminals, the distance between the terminals can be easily shortened, and the circuit configuration for detecting the potential difference can be reduced. Therefore, the configuration can be simple.
  • the terminal provided as an independent terminal may be limited to the first terminal 41e, and the second terminal 42e may be shared with the drain terminal or the source terminal of the main terminal. As a result, the number of required terminals can be reduced, so that the configuration can be made simpler.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

L'invention concerne un dispositif à semi-conducteurs pourvu : d'un substrat comportant un motif de circuit et comprenant une première carte de circuit imprimé et une seconde carte de circuit imprimé positionnée à une certaine distance de la première carte de circuit imprimé ; une puce semi-conductrice qui est positionnée sur la première carte de circuit imprimé et dans laquelle un courant circule dans la direction de l'épaisseur ; un condensateur connectant la première carte de circuit imprimé et la seconde carte de circuit imprimé. La puce semi-conductrice comprend : une couche semi-conductrice ; une première pastille d'électrode positionnée d'un côté, par rapport à la direction de l'épaisseur, de la couche semi-conductrice de manière à faire face à la première carte de circuit imprimé ; et une seconde pastille d'électrode positionnée de l'autre côté, par rapport à la direction de l'épaisseur, de la couche semi-conductrice. Le dispositif à semi-conducteurs comprend en outre un premier fil connectant la seconde pastille d'électrode et la seconde carte de circuit imprimé.
PCT/JP2020/034571 2020-05-12 2020-09-11 Dispositif à semi-conducteurs WO2021229837A1 (fr)

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Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011238906A (ja) * 2010-04-14 2011-11-24 Denso Corp 半導体モジュール
JP2012210153A (ja) * 2012-08-03 2012-10-25 Daikin Ind Ltd 電力変換装置
WO2016084241A1 (fr) * 2014-11-28 2016-06-02 日産自動車株式会社 Module à semi-conducteur de puissance en demi-pont et procédé pour sa fabrication
WO2018186353A1 (fr) * 2017-04-05 2018-10-11 ローム株式会社 Module de puissance
WO2018194153A1 (fr) * 2017-04-21 2018-10-25 三菱電機株式会社 Module semi-conducteur de puissance, composant électronique et procédé de production de module semi-conducteur de puissance
JP2018200918A (ja) * 2017-05-25 2018-12-20 三菱電機株式会社 パワーモジュール
JP2019017112A (ja) * 2018-10-22 2019-01-31 ローム株式会社 パワー回路
JP2019080417A (ja) * 2017-10-24 2019-05-23 三菱電機株式会社 パワーモジュール
WO2019163205A1 (fr) * 2018-02-20 2019-08-29 三菱電機株式会社 Module de semi-conducteur de puissance et dispositif de conversion d'énergie l'utilisant

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011238906A (ja) * 2010-04-14 2011-11-24 Denso Corp 半導体モジュール
JP2012210153A (ja) * 2012-08-03 2012-10-25 Daikin Ind Ltd 電力変換装置
WO2016084241A1 (fr) * 2014-11-28 2016-06-02 日産自動車株式会社 Module à semi-conducteur de puissance en demi-pont et procédé pour sa fabrication
WO2018186353A1 (fr) * 2017-04-05 2018-10-11 ローム株式会社 Module de puissance
WO2018194153A1 (fr) * 2017-04-21 2018-10-25 三菱電機株式会社 Module semi-conducteur de puissance, composant électronique et procédé de production de module semi-conducteur de puissance
JP2018200918A (ja) * 2017-05-25 2018-12-20 三菱電機株式会社 パワーモジュール
JP2019080417A (ja) * 2017-10-24 2019-05-23 三菱電機株式会社 パワーモジュール
WO2019163205A1 (fr) * 2018-02-20 2019-08-29 三菱電機株式会社 Module de semi-conducteur de puissance et dispositif de conversion d'énergie l'utilisant
JP2019017112A (ja) * 2018-10-22 2019-01-31 ローム株式会社 パワー回路

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