WO2021227208A1 - 用于mems器件的空腔加工工艺、体声波谐振器及其制造工艺 - Google Patents

用于mems器件的空腔加工工艺、体声波谐振器及其制造工艺 Download PDF

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WO2021227208A1
WO2021227208A1 PCT/CN2020/097807 CN2020097807W WO2021227208A1 WO 2021227208 A1 WO2021227208 A1 WO 2021227208A1 CN 2020097807 W CN2020097807 W CN 2020097807W WO 2021227208 A1 WO2021227208 A1 WO 2021227208A1
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cavity
substrate
oxide
mask layer
acoustic wave
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PCT/CN2020/097807
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French (fr)
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郭海峰
盛荆浩
江舟
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杭州见闻录科技有限公司
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/02244—Details of microelectro-mechanical resonators
    • H03H9/02433—Means for compensation or elimination of undesired effects
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00023—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems without movable or flexible elements
    • B81C1/00047—Cavities
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00436—Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
    • B81C1/00444—Surface micromachining, i.e. structuring layers on the substrate
    • B81C1/00468—Releasing structures
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00436—Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
    • B81C1/00523—Etching material
    • B81C1/00531—Dry etching
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00436—Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
    • B81C1/00523—Etching material
    • B81C1/00539—Wet etching
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/0072—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks of microelectro-mechanical resonators or networks

Definitions

  • This application relates to the field of communication devices, and mainly relates to cavity processing technology, bulk acoustic wave resonator and manufacturing technology for MEMS devices.
  • the filter is one of the radio frequency front-end modules, which can improve the transmission and reception of signals. It is mainly composed of multiple resonators connected through a topological network structure. Fbar (Film bulk acoustic resonator) is a bulk acoustic wave resonator.
  • the filter composed of it has the advantages of small size, strong integration capability, high quality during high-frequency operation, and strong power tolerance. It is used as the core device of the RF front-end .
  • Air Cavity (cavity structure bottom electrode) is the most significant feature of FBAR, the FBAR is one of the key technology, over the cavity using SiO 2 doped with phosphorus or boron or SiO 2 (PSG / BSG) as a sacrificial layer material, After the device is processed, HF or BOE (Buffered Oxide Etch) is used to release the sacrificial layer material to form a cavity structure.
  • HF or BOE Bouffered Oxide Etch
  • the cavity structure is divided into two types: underground (Air Cavity on ground) and above ground (Air Cavity on ground).
  • the production process of the underground type Air Cavity generally includes the production process represented by Avago of the United States; the production process of the ground type Air Cavity generally includes the production process represented by Taiyo of Japan and Samsung of South Korea.
  • the manufacturing process of Avago in the United States is specifically: making a cavity on a substrate (usually a Si wafer) through photolithography and dry etching processes; after removing the glue, performing oxide (SiO 2 or doped phosphorus or Boron SiO 2 ) growth; the surface is planarized by CMP; after CMP is completed, the bottom electrode-the electric film layer-the upper electrode are grown sequentially, and finally the oxide in the cavity is released by HF to obtain the Air Cavity structure Fbar.
  • the difference between the manufacturing process of Taiyo of Japan and Samsung of South Korea and Avago of the United States lies in the use of photolithography and dry etching, and the oxide is higher than the surface of the substrate.
  • the oxide and Si substrate are two different materials in the manufacturing process of Avago Company in the United States.
  • the flattening of the entire surface of the CMP will cause the step at the junction of the oxide and the substrate to be about 50-70nm.
  • the oxide is in the middle. The area becomes the lowest point. The sides near the Air Cavity are about 50nm higher than the middle area.
  • the cost of CMP equipment is higher.
  • the mainstream CMP equipment is about 5 million US dollars, and the cost of abrasive consumables is higher.
  • the bombardment of plasma during dry etching will cause the surface of the substrate on both sides of the Air Cavity to be rough, and the rough surface will affect the film quality of the electrode and the piezoelectric layer, thereby affecting the performance of the device.
  • the oxide deposition productivity UPH is low, and the single-cavity PECVD deposition of 2um (industry common thickness) oxide is less than 3pcs/Hour.
  • the present invention proposes a cavity processing technology, bulk acoustic wave resonator and its manufacturing technology for MEMS devices to solve the problem of relatively large roughness of oxide and substrate, and relatively high UPH of oxide deposition productivity.
  • a cavity processing technology for MEMS devices which includes the following steps:
  • the APCVD thermal oxidation process is used to etch the region where the cavity will be formed while growing and forming an oxide.
  • step c) includes: first using a dry process to etch the area on the substrate where the cavity is to be formed to form a part of the cavity, and then using the APCVD thermal oxidation process to etch out the remaining part of the cavity while growing and oxidizing in the cavity Things.
  • APCVD thermal oxidation process can improve the efficiency of oxide growth, thereby greatly improving productivity.
  • the mask layer is made of silicon nitride material.
  • silicon nitride as the mask layer can avoid the problem of poor surface roughness caused by direct photolithography or dry etching.
  • the process further includes the following steps:
  • the oxide is released.
  • the surface quality after removal by the wet process is much better than the surface quality after the CMP planarization treatment.
  • the wet process in step d) includes using H 3 PO 4 for etching.
  • H 3 PO 4 does not react with oxides and substrates, and can make the surface roughness smaller.
  • a manufacturing process of a bulk acoustic wave resonator is proposed.
  • the cavity processing technology described above is used to manufacture a cavity in a substrate, wherein the device functional layer is an electrode layer and a piezoelectric layer.
  • a bulk acoustic wave resonator is proposed, which is manufactured by the above-mentioned process.
  • a layer of silicon nitride is deposited on the substrate as a mask layer in advance, and the Air Cavity trench is etched by photolithography and wet etching technology and dry technology.
  • APCVD thermal oxidation process replaces PECVD for oxide growth, which improves productivity and reduces the cost of equipment and consumables.
  • a wet process is used to remove the silicon nitride mask layer. Compared with CMP planarization, it will not damage the liner.
  • the bottom surface ensures the surface roughness of the substrate.
  • the cavity processing technology can be applied to the production of bulk acoustic wave resonators in large quantities, and can greatly reduce production costs and consumables while ensuring quality, and greatly increase production capacity.
  • Fig. 1 is a flowchart of a cavity processing process for a MEMS device according to an embodiment of the present invention
  • Fig. 2 is a process flow chart of a cavity processing process for a MEMS device according to another embodiment of the present invention.
  • Fig. 3 is a manufacturing process flow chart of a bulk acoustic wave resonator according to an embodiment of the present invention
  • Fig. 4 is a schematic structural diagram of a bulk acoustic wave resonator according to an embodiment of the present invention.
  • Fig. 1 shows a flow chart of a cavity processing process for a MEMS device according to an embodiment of the present invention.
  • the cavity processing process for a MEMS device includes the following processes:
  • a mask layer 102 is pre-deposited on the silicon substrate 101, and the mask layer 102 is used to protect the upper surface of the silicon substrate 101 from damage during processing.
  • the mask layer 102 is silicon nitride. Using silicon nitride as the mask layer 102 can protect the surface of the silicon substrate 101, and a wet process can be used when removing it. Phosphoric acid H 3 PO 4 does not interact with the silicon substrate. The characteristics of the reaction 101 further ensure the surface roughness of the silicon substrate 101.
  • a layer of photoresist 103 is coated on the upper surface of the mask layer 102, and Air Cavity is formed on the photoresist 103 and the mask layer 102 by photolithography and wet etching processes.
  • the prototype of the trench It should be noted that the etching solution selected for the wet etching process should not react with the silicon substrate 101 to avoid damage to the silicon substrate 101 and affect the subsequent processing of the Air Cavity trench depth control on the silicon substrate 101 .
  • the photoresist 103 is removed and the Air Cavity is etched on the silicon substrate 101 by a dry process. Groove.
  • the oxide 104 is grown by a thermal oxidation process, where the growth of the oxide 104 should satisfy the requirement that the Air Cavity trench on the silicon substrate 101 can be just filled after the growth, and the oxide 104 grows
  • FIG. 1d The structure diagram afterwards is shown in Figure 1d.
  • an APCVD thermal oxidation (dry oxygen or wet oxygen) process is used to grow the oxide 104, where the oxide 104 is specifically silicon oxide.
  • APCVD thermal oxidation (dry oxygen or wet oxygen) process to grow silicon oxide, the silicon in the Air Cavity trench on the silicon substrate 101 is correspondingly consumed.
  • the growth ratio of silicon oxide can be compared to the silicon substrate 101
  • the Air Cavity trench depth is controlled so that the height of the silicon oxide grown on the surface of the silicon substrate 101 is consistent.
  • the reactor structure required by the APCVD thermal oxidation process is simpler and the deposition rate is faster, which can increase productivity and reduce production costs.
  • the growth of silicon oxide based on the thermal oxidation process and the consumption ratio of the silicon substrate 101 2 ⁇ m silicon oxide will consume 0.92 ⁇ m silicon, so etching is required A trench with a depth of 1.08 ⁇ m is formed, and at this time, the trench is just filled up after the growth of silicon oxide is completed.
  • the mask layer 102 is removed by a wet process.
  • the mask layer 102 is silicon nitride, a wet process is used, and phosphoric acid H 3 PO 4 is used instead of silicon lining.
  • the reaction characteristics of the substrate 101 will not affect the surface roughness of the silicon substrate 101, and the surface quality of the silicon substrate 101 processed by a wet process is much better than the surface quality processed by CMP planarization in the prior art.
  • the above-mentioned cavity processing technology solves the problem that the use of CMP to planarize the entire surface in the prior art will cause a step difference of about 50-70nm at the interface between the oxide 104 and the silicon substrate 101, and the cost of the CMP equipment is relatively high.
  • the mainstream CMP equipment About 5 million US dollars, the technical problem of the high cost of abrasive consumable slurry.
  • the surface roughness of the oxide 104 and the silicon substrate 101 can be reduced from about 10 nm to within 3 nm, which greatly improves the surface quality of the silicon substrate 101.
  • FIG. 2 shows a flowchart of a cavity processing process for a MEMS device according to another embodiment of the present invention.
  • the cavity processing process for a MEMS device includes the following process :
  • a mask layer 202 is pre-deposited on the silicon substrate 201.
  • the mask layer 202 is used to protect the surface of the silicon substrate 201 from damage during processing.
  • the mask layer 202 is made of silicon nitride, and the use of silicon nitride as the mask layer 202 can protect the surface of the silicon substrate 201, and a wet process can be used when removing it.
  • Phosphoric acid H 3 PO 4 does not interact with the silicon substrate
  • the reaction characteristic of 201 further ensures the surface roughness of the silicon substrate 201.
  • a layer of photoresist 203 is coated on the upper surface of the mask layer 202, and Air Cavity is formed on the photoresist 203 and the mask layer 202 by photolithography and wet etching processes.
  • the prototype of the trench It should be noted that the etching solution selected for the wet etching process should not react with the silicon substrate 201 to avoid damage to the silicon substrate 201 and affect the subsequent processing of the Air Cavity trench depth control on the silicon substrate 201 .
  • the APCVD thermal oxidation process is used to directly grow the oxide 204, and the mask layer 202 is removed by a wet process.
  • the mask layer 202 is silicon nitride
  • the wet process utilizes the characteristic that phosphoric acid H 3 PO 4 does not react with the silicon substrate 201, and does not cause the surface of the silicon substrate 201 to be rough.
  • the surface quality of the silicon substrate 201 processed by the wet process is much better than that of the prior art.
  • the ratio of the growth of silicon oxide based on the thermal oxidation process to the consumption of the silicon substrate 201 is such that the silicon substrate 201 is processed with a required depth of Air Cavity trenches.
  • the ratio of the growth of silicon oxide in the thermal oxidation process to the consumption of the silicon substrate 201 is 1:0.46.
  • the process flow chart of the cavity processing process for MEMS devices shown in Fig. 2 omits the process of using dry etching of part of the trench, and directly uses the APCVD thermal oxidation process to perform oxide 204 The growth simplifies the process and further improves production efficiency.
  • Figure 1 and Figure 2 both use APCVD instead of PECVD for the growth of oxide 104 and 204.
  • the general equipment of APCVD can grow at least 150pcs Wafer each time, and the growth time of 2 ⁇ m oxide 104 and 204 is about 6 hours.
  • the calculation formula is: x 0 2 ⁇ Bt, where x 0 is the thickness, B is the parabolic constant of oxidation (approximately 0.012 ⁇ m 2 /min for wet oxidation at 1200°C), and t is the time.
  • the new Air Cavity manufacturing process discards CMP equipment and adopts wet and APCVD equipment.
  • the mainstream Single Wafer wet process equipment costs about 800,000 US dollars
  • the APCVD equipment costs approximately 600,000 US dollars.
  • the total is about 1.4 million U.S. dollars
  • the cost of CMP equipment is about 5 million U.S. dollars. It can be seen that the cost of the new air cavity manufacturing process equipment is reduced by about 72%.
  • a device functional layer covering oxides 104, 204 can also be fabricated on the silicon substrates 101, 201, and finally hydrofluoric acid, etc.
  • the chemical agent releases the oxides 104 and 204 to obtain the required products for communication modules, such as bulk acoustic wave resonators.
  • Fig. 3 shows a manufacturing process flow chart of a bulk acoustic wave resonator according to an embodiment of the present invention.
  • the bottom electrode 302, the piezoelectric layer 303, and the top electrode 304 are grown on the upper surface of the silicon substrate 301 in order to obtain the result shown in FIG. 3a.
  • Fig. 4 shows a schematic structural diagram of a bulk acoustic wave resonator according to an embodiment of the present invention.
  • the bulk acoustic wave resonator includes a silicon substrate 401 and a functional layer grown on the upper surface of the silicon substrate 401.
  • the functional layer includes a bottom electrode 402, a piezoelectric layer 403, and a top electrode 404 from bottom to top.
  • the bulk acoustic wave resonator has the advantages of small size, strong integration capability, high quality during high-frequency operation, and strong power tolerance. It is widely used in the core components of the RF front-end.
  • the embodiments of the present invention can be applied to the production of bulk acoustic wave resonators in large quantities, can greatly reduce production costs and consumables while ensuring quality, and greatly increase production capacity.
  • the manufacturing process is simple, the manufacturing cost is low, and it is convenient for large-scale industrial production.

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Abstract

一种用于MEMS器件的空腔（405）加工工艺，包括以下步骤：在衬底（101、201、301、401）上沉积一层掩膜层（102、202）；利用光刻蚀刻工艺将衬底（101、201、301、401）上将要形成空腔（405）的区域上的掩膜层（102、202）蚀刻掉；借助APCVD热氧化工艺在将要形成空腔（405）的区域进行蚀刻同时生长形成氧化物（104、204、305）；利用湿法工艺将掩膜层（102、202）去除；在衬底（101、201、301、401）上制作覆盖氧化物（104、204、305）的器件功能层后，将氧化物（104、204、305）释放。一种体声波谐振器的制造工艺，采用上述空腔（405）加工工艺在衬底（101、201、301、401）中制造空腔（405），其中器件功能层为电极层（302、304、402、404）和压电层（303、403）。一种体声波谐振器，其采用上述工艺制造而成。利用上述工艺可以改善衬底（101、201、301、401）表面粗糙度，并大幅提高产能，适于大批量生产。

Description

用于MEMS器件的空腔加工工艺、体声波谐振器及其制造工艺 技术领域
本申请涉及通信器件领域，主要涉及用于MEMS器件的空腔加工工艺、体声波谐振器及其制造工艺。
背景技术
随着电磁频谱的日益拥挤、无线通讯设备的频段与功能增多，无线通讯使用的电磁频谱从500MHz到5GHz以上高速增长，也对性能高、成本低、功耗低、体积小的射频前端模块需求日益增长。滤波器是射频前端模块之一，可改善发射和接收信号，主要由多个谐振器通过拓扑网络结构连接而成。Fbar(Film bulk acoustic resonator)是一种体声波谐振器，由它组成的滤波器具有体积小、集成能力强、高频工作时保证高品质、功率承受能力强等优势而作为射频前端的核心器件。
Air Cavity(电极底部的空腔结构)是Fbar最为显著的特征，也是Fbar的关键工艺之一，空腔上方使用SiO 2或者掺杂磷或硼的SiO 2(PSG/BSG)作为牺牲层材料，在器件加工完成之后使用HF或BOE(Buffered氧化物Etch)释放牺牲层材料形成空腔结构。
相对硅衬底的初始面，空腔结构分为地下型(Air Cavity under ground)和地上型(Air Cavity on ground)两种。
地下型Air Cavity的制作工艺一般包括以美国Avago公司为代表的制作工艺；地上型Air Cavity的制作工艺一般包括以日本Taiyo、韩国三星为代表的制作工艺。其中，美国Avago公司的制作工艺具体为：通过光刻和干法刻蚀工艺在衬底(一般为Si片)上制作空腔；去胶过后通过PECVD进行氧化物(SiO 2或者掺杂磷或硼的SiO 2)生长；通过CMP来进行表面平坦化；CMP完成后开始依次生长底电极-电膜层-上电极，最后通过HF对空腔内的氧化物进行释放，从而得到Air Cavity结构的Fbar。日本Taiyo、韩国三星的制作工艺与美国Avago公司的区别在于采用光刻和干刻刻蚀，氧化物高出衬底表面。
但是，美国Avago公司的制作工艺中氧化物和Si衬底是两种不同材料，CMP整面平坦化会造成氧化物和衬底交界处的台阶在50-70nm左右，在CMP完成之后氧化物中间区域变成最低点，靠近Air Cavity两侧比中间区域高出50nm左右，CMP设备成本较高，主流CMP设备大约500万美金，研磨料耗材slurry成本较高。日本Taiyo、韩国三星的制作工艺中干刻刻蚀时等离子体的轰击会造成Air Cavity两侧衬底表面粗糙，而表面粗糙会影响电极和压电层成膜质量，从而影响器件性能。氧化物沉积产能UPH较低，单腔PECVD沉积2um(行业通用厚度)氧化物小于3pcs/Hour。
发明内容
为了解决现有技术中因氧化物和硅衬底是两种不同材料，导致CMP整面平坦化时会造成氧化物和衬底的表面粗糙度过大、CMP设备成本及研磨料耗材过高、产能较低的技术问题，本发明提出了用于MEMS器件的空腔加工工艺、体声波谐振器及其制造工艺，用以解决氧化物和衬底的粗糙度较大、氧化物沉积产能UPH较低、生产设备和材料成本太高的技术问题。
根据本发明的第一方面，提出了一种用于MEMS器件的空腔加工工艺，包括以下步骤：
a)在衬底上沉积一层掩膜层；
b)利用光刻蚀刻工艺将衬底上将要形成空腔的区域上的掩膜层蚀刻掉；以及
c)借助APCVD热氧化工艺在将要形成空腔的区域进行蚀刻同时生长形成氧化物。
优选的，步骤c)包括：先利用干法工艺蚀刻衬底上将要形成空腔的区域以形成一部分空腔，然后将利用APCVD热氧化工艺蚀刻出空腔的剩余部分同时在空腔内生长氧化物。利用APCVD热氧化工艺可以提高氧化物生长的效率，进而极大地提升产能。
优选的，掩膜层为氮化硅材料。利用氮化硅材料作为掩膜层，可 以避免直接利用光刻或干刻造成的表面粗糙度不良的问题。
进一步优选的，工艺还包括以下步骤：
d)利用湿法工艺将掩膜层去除；以及
e)在衬底上制作覆盖氧化物的器件功能层后，将氧化物释放。利用湿法工艺去除后的表面质量大大优于CMP平坦化处理后的表面质量。
进一步优选的，步骤d)中的湿法工艺包括利用H 3PO 4进行腐蚀。H 3PO 4不会与氧化物和衬底反应，能够使得表面粗糙度更小。
根据本发明的第二方面，提出了一种体声波谐振器的制造工艺，采用上述空腔加工工艺在衬底中制造空腔，其中器件功能层为电极层和压电层。
根据本发明的第三方面，提出了一种体声波谐振器，其采用上述的工艺制造而成。
本发明公开的用于MEMS器件的空腔加工工艺，事先在衬底上沉积一层氮化硅作为掩膜层，利用光刻和湿法腐蚀工艺及干法工艺刻蚀Air Cavity沟槽，采用APCVD热氧化工艺替代PECVD进行氧化物生长，在提升产能的同时也降低了设备及耗材成本，最后利用湿法工艺去除氮化硅掩膜层，相比于CMP平坦化处理，不仅不会破坏衬底表面，保证衬底表面粗糙度。该空腔加工工艺可以大批量应用于体声波谐振器的生产，能够在保证质量的同时大幅度缩减生产成本和耗材，且使得产能大幅提升。
附图说明
包括附图以提供对实施例的进一步理解并且附图被并入本说明书中并且构成本说明书的一部分。附图图示了实施例并且与描述一起用于解释本发明的原理。将容易认识到其它实施例和实施例的很多预期优点，因为通过引用以下详细描述，它们变得被更好地理解。附图的元件不一定是相互按照比例的。同样的附图标记指代对应的类似部件。
图1是根据本发明的一个实施例的用于MEMS器件的空腔加工工 艺流程图；
图2是根据本发明的另一个实施例的用于MEMS器件的空腔加工工艺流程图；
图3是根据本发明的实施例的体声波谐振器的制造工艺流程图；
图4是根据本发明的实施例的体声波谐振器结构示意图。
具体实施方式
下面结合附图和实施例对本申请作进一步的详细说明。可以理解的是，此处所描述的具体实施例仅仅用于解释相关发明，而非对该发明的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与有关发明相关的部分。
需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。下面将参考附图并结合实施例来详细说明本申请。
图1示出了根据本发明的一个实施例的用于MEMS器件的空腔加工工艺流程图，如图1所示，该用于MEMS器件的空腔加工工艺包括以下流程：
首先如图1a所示，在硅衬底101上预先沉积一层掩膜层102，掩膜层102用于保护硅衬底101的上表面，使其在加工过程中免受破坏。优选的，掩膜层102选择氮化硅，采用氮化硅作为掩膜层102能够保护硅衬底101的表面，且在去除时可以采用湿法工艺利用磷酸H 3PO 4不与硅衬底101反应的特性，进一步保证硅衬底101的表面粗糙度。应当认识到，掩膜层102除了采用氮化硅之外，还可以选择其他的硅化物或氮化物作为掩膜层102的材料，并且湿法工艺去除掩膜层102时采用对应不与硅衬底101反应的化学药剂，同样能够实现本发明的技术效果。
继续参考图1b，如图1b所示，在掩膜层102的上表面涂布一层光刻胶103，利用光刻以及湿法腐蚀工艺在光刻胶103和掩膜层102上形成Air Cavity沟槽的雏形，应当注意的是，湿法腐蚀工艺选用的腐蚀液应当不与硅衬底101反应，避免破坏硅衬底101而影响后续在 硅衬底101上加工Air Cavity沟槽深度的控制。
如图1c所示，在图1b中光刻胶103和掩膜层102上形成Air Cavity沟槽雏形的基础上，去除光刻胶103并利用干法工艺在硅衬底101上刻蚀Air Cavity沟槽。完成Air Cavity沟槽的刻蚀后，通过热氧化工艺进行氧化物104的生长，其中氧化物104的生长应当满足生长后能够刚好填满硅衬底101上的Air Cavity沟槽，氧化物104生长后的结构示意图如图1d所示。
在优选的实施例中，采用APCVD热氧化(干氧或湿氧)工艺进行氧化物104的生长，其中，氧化物104具体为氧化硅。采用APCVD热氧化(干氧或湿氧)工艺在生长氧化硅的同时，硅衬底101上的Air Cavity沟槽中的硅相应被消耗，可以通过氧化硅的生长比例对硅衬底101上的Air Cavity沟槽深度进行控制，使氧化硅生长后和硅衬底101表面的高度保持一致性。利用APCVD热氧化工艺所需的反应器结构更为简单，沉积速率更快，能够提升产能并减少生产成本。
在具体的实施例中，根据本发明申请人的多次试验，基于热氧化工艺的氧化硅的生长与硅衬底101的消耗比例，2μm的氧化硅会消耗0.92μm的硅，所以需要刻蚀出1.08μm深的沟槽，此时氧化硅生长完成后刚好填满沟槽。
继续参考图1e，如图1e所示，利用湿法工艺去除掩膜层102，具体的，在掩膜层102为氮化硅时，采用湿法工艺，利用磷酸H 3PO 4不与硅衬底101反应的特性，不会影响硅衬底101表面粗糙度，利用湿法工艺处理的硅衬底101的表面质量，大大优于现有技术中通过CMP平坦化处理的表面质量。
上述空腔加工工艺解决了现有技术中利用CMP整面平坦化会造成氧化物104和硅衬底101交界处的存在50-70nm左右的段差，且CMP设备成本较高，目前一般主流CMP设备大约500万美金，研磨料耗材slurry成本较高的技术问题。利用该空腔加工工艺可以将氧化物104和硅衬底101的表面粗糙度由10nm左右降低至3nm以内，极大提升了硅衬底101的表面质量。
继续参考图2，图2示出了根据本发明的另一个实施例的用于 MEMS器件的空腔加工工艺流程图，如图2所示，该用于MEMS器件的空腔加工工艺包括以下流程：
首先参考图2a，在硅衬底201上预先沉积一层掩膜层202，掩膜层202用于保护硅衬底201的表面，使其在加工过程中的免受破坏。优选的，掩膜层202选择氮化硅，采用氮化硅作为掩膜层202能够保护硅衬底201的表面，且在去除时可以采用湿法工艺利用磷酸H 3PO 4不与硅衬底201反应的特性，进一步保证硅衬底201的表面粗糙度。应当认识到，掩膜层202除了采用氮化硅之外，还可以选择其他的硅化物或氮化物作为掩膜层202，并且湿法工艺去除掩膜层202时采用对应不与硅衬底201反应的化学药剂，同样能够实现本发明的技术效果。
继续参考图2b，如图2b所示，在掩膜层202的上表面涂布一层光刻胶203，利用光刻以及湿法腐蚀工艺在光刻胶203和掩膜层202上形成Air Cavity沟槽的雏形，应当注意的是，湿法腐蚀工艺选用的腐蚀液应当不与硅衬底201反应，避免破坏硅衬底201以及影响后续在硅衬底201上加工Air Cavity沟槽深度的控制。
参考图2c和2d，去除光刻胶203后直接利用APCVD热氧化工艺进行氧化物204的生长，利用湿法工艺去除掩膜层202，具体的，在掩膜层202为氮化硅时，采用湿法工艺利用磷酸H 3PO 4不与硅衬底201反应的特性，不会造成硅衬底201表面粗糙，利用湿法工艺处理的硅衬底201的表面质量大大优于现有技术中通过CMP平坦化处理的表面质量。
在具体的实施例中，基于热氧化工艺的氧化硅的生长与硅衬底201的消耗比例，使得硅衬底201上加工出所需深度的Air Cavity沟槽。其中，根据本发明申请人的多次试验，热氧化工艺的氧化硅的生长与硅衬底201的消耗比例为1:0.46。
图2示出的用于MEMS器件的空腔加工工艺流程图相较于图1中的空腔加工工艺省略了利用干法刻蚀部分沟槽的工艺，直接利用APCVD热氧化工艺进行氧化物204的生长，简化了工艺，进一步提高生产效率。
图1和图2两种加工工艺都采用APCVD来替代PECVD来进行氧化物104、204的生长，APCVD的通用设备每次至少可生长150pcs Wafer，2μm的氧化物104、204生长时间大约为6小时，计算公式为：x 0 2≈Bt，其中，x 0为厚度，B为氧化抛物线常数(1200℃湿法氧化大约为0.012μm 2/min)，t为时间，由此推算，t≈x 0 2/B≈2μm 2/0.012μm 2/min≈333min，所以，以6小时计算，APCVD的产能UPH大约为25pcs/Hour，相对于PECVD的3pcs/Hour，产量提升800％以上。
相对于目前的Air Cavity制作工艺，新的Air Cavity制作工艺舍弃了CMP设备，采用湿法和APCVD设备，目前主流一台Single Wafer湿法设备成本大约80万美金，APCVD设备成本大约60万美金，合计约140万美金，而CMP设备成本约为500万美金，由此可见，新的Air cavity制作工艺设备成本降低约72％。
在优选的实施例中，在图1和图2的空腔加工工艺的基础上，还可以在硅衬底101、201上制作覆盖氧化物104、204的器件功能层，最终利用氢氟酸等化学药剂将氧化物104、204释放获得所需的用于通信模块的产品，例如用于体声波谐振器等。
图3示出了根据本发明的一个实施例的体声波谐振器的制造工艺流程图。在图1和图2的空腔加工工艺中湿法腐蚀完成后的基础上，在硅衬底301的上表面依次生长底电极302、压电层303和顶电极304，获得如图3a所示的结构；利用氢氟酸对氧化物305进行释放，最终获得如图3b所示的具有Air Cavity结构的体声波谐振器。
图4示出了根据本发明的一个实施例的体声波谐振器的结构示意图。如图4所示，该体声波谐振器包括硅衬底401以及生长于硅衬底401上表面的功能层，该功能层自下而上依次包括底电极402、压电层403和顶电极404，其中，硅衬底401与底电极402之间存在有Air cavity的空腔405，该体声波谐振器具有体积小、集成能力强、高频工作时保证高品质、功率承受能力强等优势，被广泛应用于射频前端的核心器件中。
以上描述了本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内， 可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为准。
在本申请的描述中，需要理解的是，术语“上”、“下”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。措词‘包括’并不排除在权利要求未列出的元件或步骤的存在。元件前面的措词‘一’或‘一个’并不排除多个这样的元件的存在。在相互不同从属权利要求中记载某些措施的简单事实不表明这些措施的组合不能被用于改进。在权利要求中的任何参考符号不应当被解释为限制范围。
工业实用性
本发明实施例可以大批量应用于体声波谐振器的生产，能够在保证质量的同时大幅度缩减生产成本和耗材，且使得产能大幅提升。制造工艺简单、制造成本低，便于大规模工业化生产。

Claims (7)

  1. 一种用于MEMS器件的空腔加工工艺，包括以下步骤：
    a)在衬底上沉积一层掩膜层；
    b)利用光刻蚀刻工艺将所述衬底上将要形成空腔的区域上的掩膜层蚀刻掉；以及
    c)借助APCVD热氧化工艺在将要形成空腔的区域进行蚀刻同时生长形成氧化物。
  2. 根据权利要求1所述的空腔加工工艺，其特征在于，
    所述步骤c)包括：先利用干法工艺蚀刻所述衬底上将要形成空腔的区域以形成一部分空腔，然后将利用APCVD热氧化工艺蚀刻出空腔的剩余部分同时在所述空腔内生长氧化物。
  3. 根据权利要求1所述的空腔加工工艺，其特征在于，
    所述掩膜层为氮化硅材料。
  4. 根据权利要求1-3中任一项所述的空腔加工工艺，其特征在于，所述工艺还包括以下步骤：
    d)利用湿法工艺将所述掩膜层去除；以及
    e)在所述衬底上制作覆盖所述氧化物的器件功能层后，将所述氧化物释放。
  5. 根据权利要求4所述的空腔加工工艺，其特征在于，所述步骤d)中的湿法工艺包括利用H 3PO 4进行腐蚀。
  6. 一种体声波谐振器的制造工艺，其特征在于，采用权利要求4或5所述的空腔加工工艺在衬底中制造空腔，其中所述器件功能层为电极层和压电层。
  7. 一种体声波谐振器，其特征在于，其采用权利要求6所述的工艺制造而成。
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