WO2021218607A1 - 半导体结构及其形成方法、存储器及其形成方法 - Google Patents

半导体结构及其形成方法、存储器及其形成方法 Download PDF

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WO2021218607A1
WO2021218607A1 PCT/CN2021/086467 CN2021086467W WO2021218607A1 WO 2021218607 A1 WO2021218607 A1 WO 2021218607A1 CN 2021086467 W CN2021086467 W CN 2021086467W WO 2021218607 A1 WO2021218607 A1 WO 2021218607A1
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active
layer
forming
semiconductor
pillar
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PCT/CN2021/086467
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English (en)
French (fr)
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朱一明
平尔萱
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长鑫存储技术有限公司
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Priority to EP21797863.4A priority Critical patent/EP3975253B1/en
Publication of WO2021218607A1 publication Critical patent/WO2021218607A1/zh
Priority to US17/575,806 priority patent/US20220139431A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B51/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
    • H10B51/40—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/40—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
    • H10B61/22—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors of the field-effect transistor [FET] type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
    • H10B63/34—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors of the vertical channel field-effect transistor type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region

Definitions

  • This application relates to the field of semiconductor technology, in particular to a semiconductor structure and its forming method, a memory and its forming method.
  • the memory usually includes a data storage unit and a control transistor that controls the data storage unit.
  • the integration of transistors restricts the storage density of the memory.
  • the channel size of the transistor is reduced to reduce the size of the transistor, thereby increasing the storage density of the memory.
  • the transistor performance is reduced due to the narrow channel effect and the short channel effect, which affects the performance of the memory and restricts the further improvement of the transistor size and the storage density of the memory.
  • the technical problem to be solved by this application is to provide a semiconductor structure and a method for forming the same, a memory and a method for forming the same, so as to further improve the storage density of the memory.
  • the present application provides a method for forming a semiconductor structure, including: providing a substrate on which a sacrificial layer and an active layer located on the sacrificial layer are formed; Patterning with the sacrificial layer to form a groove, the groove divides the active layer and the sacrificial layer into a plurality of active regions; filling the groove to form an area surrounding the active region
  • the first isolation layer; the active layer in the active area is patterned to form a number of discrete active patterns, the active pattern has at least one sidewall or end connected to the first isolation layer;
  • the sacrificial layer is removed along the opening between the adjacent active patterns to form a gap between the bottom of the active pattern and the substrate; a bit line is formed in the gap;
  • a semiconductor pillar is formed on the top of the source pattern.
  • an isolation dielectric layer filling the adjacent active patterns is formed.
  • the active pattern is an active line arranged in parallel and extending along a first direction, and at least one sidewall or end of the active line is connected to the first isolation layer; further including: After the bit line, the active line is patterned to form a plurality of active pillars arranged in an array along the first direction and the second direction; the semiconductor pillar is formed on the top of the active pillar.
  • the method for forming the semiconductor pillar includes: forming a protective layer on the surface of the first isolation layer and the isolation dielectric layer; forming an epitaxial via in the protective layer; and exposing the bottom of the epitaxial via The top surface of the active column; epitaxially grow a semiconductor material on the top surface of the active column to form a semiconductor column located in the epitaxial through hole; and remove the protective layer.
  • a semiconductor material is formed on the top surface of the active pillar; then the semiconductor material is etched and trimmed to form a semiconductor pillar on the top of the active pillar.
  • the method further includes: forming a first doped region located in the active pillar; forming a channel region located in the semiconductor pillar and a second doped region located above the channel region; forming a surrounding area The gate structure of the channel region.
  • the method for forming the first doped region includes: ion implanting the active line or the active column; the method for forming the second doped region includes: implanting the top region of the semiconductor column Ion implantation is performed to form the second doped region at the top of the semiconductor pillar.
  • the method for forming the first doped region includes: after forming the active line or the active pillar, forming a doped area on the surface of the substrate between adjacent active lines or adjacent active pillars. A transition layer of impurity elements; through diffusion treatment, at least part of the doping elements in the transition layer are diffused into the active line or the active column to form the first doped region.
  • the method for forming the first doped region includes: adopting an in-situ doping process, and in the process of forming the active layer by an epitaxial growth process, doping the active layer to form a second doped region.
  • the method for forming the region includes: adopting an in-situ doping process, in the process of forming the semiconductor column by an epitaxial growth process, performing in-situ doping to sequentially form the channel region and the second doped region.
  • the method for forming the bit line further includes: forming a conductive material layer filling the gap and the opening; patterning the conductive material layer, leaving only the edge at the bottom of the active pattern Part of the conductive material layer extending in the first direction serves as a bit line.
  • the method further includes: etching the first isolation layer or the active pattern to form a through hole; filling the through hole with a conductive material to form a bit line connection line, and the bottom of the bit line connection line Connect with the bit line.
  • the through hole is located at the edge of the active area.
  • the method for forming the gate structure includes: sequentially forming a gate dielectric layer and a gate layer on the surfaces of the first isolation layer, the isolation dielectric layer, and the semiconductor pillar; The layer is patterned to form a gate structure surrounding the channel region of the semiconductor pillar and expose the top area of the semiconductor pillar.
  • the gate structures on the surfaces of the semiconductor pillars on the same column arranged in the second direction are connected.
  • the method further includes: forming a second isolation layer covering the gate structure and the second doped region, and the second isolation layer exposes the top surface of the second doped region.
  • the technical solution of the present application also provides a semiconductor structure, including: forming by the above-mentioned method.
  • the technical solution of the present application also provides a memory, including: the above-mentioned semiconductor structure; a memory cell located above the semiconductor structure, and the memory cell is connected to the semiconductor pillar.
  • the storage unit includes a capacitive storage unit, a magnetic storage unit, a ferroelectric storage unit, a phase change storage unit, or a resistance storage unit.
  • the technical solution of the present application also provides a method for forming a memory, including: providing a semiconductor structure formed by the above method; forming a memory cell on the semiconductor structure, and the memory cell is connected to the semiconductor pillar.
  • the storage unit includes a capacitive storage unit, a magnetic storage unit, a ferroelectric storage unit, a phase change storage unit, or a resistance storage unit.
  • a sacrificial layer and an active layer on the surface of the sacrificial layer are formed on a substrate, and a bit line is used to replace the position of the sacrificial layer, thereby forming a buried bit line, thereby facilitating subsequent formation of vertical
  • the source/drain of the bottom of the vertical transistor is led out through the bit line of the transistor.
  • the active layer is divided into a plurality of active regions through the first isolation layer, and then the active layer in each active region is patterned into active patterns At least one side of each active pattern is connected to the first isolation layer, so that after removing the sacrificial layer under the active pattern, the active pattern can remain suspended.
  • the thickness of the active layer is relatively low, and then the semiconductor pillars are formed by epitaxially forming the top of the active pillars formed by the patterned active layer, which can reduce the patterning of the active layer. There is a risk of collapse.
  • vertical transistors occupy a smaller layout size, and the channel width is determined by the thickness of the active layer.
  • the area of the transistor can be reduced without reducing the channel width, thereby improving the semiconductor structure.
  • the degree of integration is the reason for manufacturing the transistor.
  • the memory of the present application includes a semiconductor structure with a vertical transistor array, which can increase the storage density of the memory when the size of the transistor is small.
  • 1 to 13C are schematic structural diagrams of a semiconductor forming process according to an embodiment of the application.
  • FIG. 14 is a schematic structural diagram of a memory according to an embodiment of the application.
  • FIG. 15 is a schematic structural diagram of a memory according to an embodiment of the application.
  • FIG. 1 to FIG. 13C are schematic diagrams of the semiconductor formation process of an embodiment of the application.
  • a substrate 110 is provided, and a sacrificial layer 120 and an active layer 130 on the surface of the sacrificial layer 120 are formed on the surface of the substrate 110.
  • the substrate 110 may be single crystal silicon, germanium, SiC, etc., various semiconductor materials, and may be a single-layer structure or a composite structure.
  • the substrate 110 includes a semiconductor base and a dielectric layer formed on the surface of the semiconductor base. Etc., it is not limited here.
  • the sacrificial layer 120 and the active layer 130 may be sequentially formed on the surface of the substrate 110 through a deposition process.
  • the active layer 130 is made of semiconductor materials, such as Si, Ge, SiC, or SiGe, etc., which may be one or more of semiconductor materials.
  • the material of the sacrificial layer 120 is different from the material of the substrate 110 and the active layer 120, so that the subsequent process of removing the sacrificial layer 120 reduces the influence on the substrate 110 and the active layer 120.
  • the substrate 110 is a silicon substrate
  • the sacrificial layer 120 is a SiGe layer
  • the active layer is a silicon layer.
  • an epitaxial growth process after the sacrificial layer 120 is epitaxially formed on the surface of the substrate 110, an active layer 130 is formed on the surface of the sacrificial layer 120 through an epitaxial process.
  • the sacrificial layer 120 is made of a different material from the substrate 110 and the active layer 130, in the process of removing the sacrificial layer 120, the gap between the sacrificial layer 120 and the substrate 110 and the active layer 130 It suffices to have a higher etching selection ratio.
  • the substrate 110, the sacrificial layer 120, and the active layer 130 may be an SOI substrate, wherein the buried oxide layer in the SOI substrate serves as the sacrificial layer 120.
  • ion implantation may be performed on a bulk silicon substrate to form a doped layer inside the bulk silicon substrate as the sacrificial layer 120.
  • Ge implantation is performed on bulk silicon, and by controlling the depth of Ge implantation, a SiGe layer is formed inside the bulk silicon as the sacrificial layer 120, the silicon layer below the doped layer is the substrate 110, and the silicon layer above the doped layer is used as the active layer .
  • the doped layer may also be formed by implanting other elements, such as C, O, N, etc., so that the etching rate of the doped layer is different from the material layers above and below, so as to form the doped layer.
  • the sacrificial layer 120 is described.
  • the material of the sacrificial layer 120 may be silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, or the like.
  • the active layer 130 is used to form the bottom doped region of the vertical transistor, that is, the source/drain.
  • the sacrificial layer 120 is used for subsequent replacement to form bit lines.
  • the thickness of the sacrificial layer 120 and the active layer 130 are set reasonably.
  • the thickness of the sacrificial layer 120 may be 35 nm-50 nm.
  • the bottom doped region of the transistor is formed separately from the upper channel region and the top doped region, which can reduce the thickness of the active layer 130, thereby reducing subsequent patterning of the active layer 130 Later, the formed active pattern has a probability of collapse.
  • the active layer 130 and the sacrificial layer 120 are patterned to form a groove, and the groove connects the active layer 130 (please refer to FIG. 1) and the sacrificial layer 120
  • the layer 120 (please refer to FIG. 1) is divided into a plurality of active regions 130a; a first isolation layer 200 surrounding the active region 130a is formed in the groove.
  • the active layer 130 and the sacrificial layer 120 are etched to the surface of the substrate 110 to form the grooves, and the active layer 130 is divided into a number of active regions 130a; then the grooves are filled
  • the dielectric material is flattened to form the first isolation layer 200 to realize the lateral electrical isolation between the active regions 130a.
  • FIG. 2A shows a schematic structural diagram of an active region 130 a surrounded by the first isolation layer 200.
  • FIG. 2B shows a schematic top view of a plurality of active regions 130 a and the first isolation layer 200.
  • the size of the active region 130a can be designed as required. In some embodiments, if the active region 130a is used to form a control transistor of a memory, the active region 130a can correspond to a memory block.
  • the active layer in the active region 130a is patterned to form a number of discrete active patterns, the active pattern has at least one sidewall or end portion and the first isolation
  • the layer 200 is connected.
  • Fig. 3B is a schematic cross-sectional view along the line A-A' in Fig. 3A;
  • Fig. 3C is a schematic cross-sectional view along the line B-B' in Fig. 3A.
  • the active layer in the active region 130a is patterned to form a plurality of elongated active lines 131 arranged in parallel and extending along the first direction (y direction).
  • the adjacent active lines There are openings 301 between 131.
  • the ends of the active lines 131 are all connected to the first isolation layer 200, and the sidewalls of the active lines 131 located at the edge of the active region 130a are also connected to the first isolation layer 200.
  • the sacrificial layer 120 may be further etched to remove the sacrificial layer 120 at the bottom of the opening 301.
  • the method of forming the active line 131 includes: forming a patterned mask layer (not shown in the figure) on the surface of the active region 130a, and the patterned mask layer has a first edge A pattern of openings extending in the direction; using the patterned mask layer as a mask, the active layer 130 is etched into long strip-shaped active lines 131 and openings 301.
  • the active pillars may also be formed by patterning the active layer in the active area, for example, forming a plurality of active pillars arranged in 2 rows or 2 columns, so that the active pillars have at least one
  • the sidewalls are connected to the first isolation layer 200; in other embodiments, more rows or more columns of active pillars may be formed, and a dielectric layer may be deposited between the active pillars to ensure that the active pillars At least one sidewall is connected to the dielectric layer, so that after the sacrificial layer 120 at the bottom of the active column is subsequently removed, the active column can remain in a suspended state.
  • the sacrificial layer 120 is removed along the opening 301, and a gap 600 is formed between the bottom of the active line 131 and the substrate 110.
  • the sacrificial layer 120 is removed by a wet etching process.
  • a suitable etching solution according to the material of the sacrificial layer 120, so that during the wet etching process, the sacrificial layer 120 and the sacrificial layer 120
  • the active line 131 and the first isolation layer 200 have a higher etching selection ratio, so as to reduce the impact on the active line 131 and the first isolation layer 200 during the process of removing the sacrificial layer 120 .
  • the active line 131 is supported by the first isolation layer 200 and suspended above the substrate 110 to form a gap 600 with the substrate 110.
  • a conductive material is filled in the gap 600 to form a bit line 701 extending in the first direction.
  • a conductive material such as polysilicon or a metal material such as Cu, Ag, or Al, may be deposited in the gap 600 by a chemical vapor deposition or physical vapor deposition process.
  • the conductive material fills the gap 600 to form a bit line 701 located at the bottom of the active line 131; the conductive material also fills the opening 301 and covers the first isolation layer 200 and the active line At the top of 131, the conductive material on the top of the first isolation layer 200 and the top of the active line 131 is removed by subsequent etching back or planarization, and the conductive material of the opening 301 is removed by etching, so as to avoid adjacent active
  • the bit lines 701 at the bottom of the line 131 are connected to each other.
  • an isolation dielectric layer 500 is formed on the surface of the substrate 110 to fill the spacing between the active lines 131, and is planarized; at the ends of the active lines 131, exposed parts are formed.
  • the through hole 801 on the surface of the substrate 110 is described.
  • Fig. 6B is a schematic cross-sectional view taken along the cut line A-A' in Fig. 6A
  • Fig. 6C is a schematic cross-sectional view taken along the cut line B-B' in Fig. 6A.
  • the material of the isolation dielectric layer 500 is a dielectric material, which is used to provide electrical isolation between the active lines 131.
  • the material of the isolation dielectric layer 500 is silicon oxide.
  • the method of forming the isolation dielectric layer 500 is a chemical vapor deposition process, and the surface of the substrate 110 is formed to fill the space between adjacent active lines 131 and cover the top of the active lines 131. After the isolation material layer, the isolation material layer is planarized to form the isolation dielectric layer 500.
  • the top of the isolation dielectric layer 500 is flush with the top of the active line 131; in other embodiments, the top of the active line 131 is reserved for patterning the active layer.
  • the isolation dielectric layer 500 is flush with the patterned mask layer; in other embodiments, before the isolation dielectric layer 500 is formed, the patterned mask layer Having been removed, the isolation dielectric layer 500 also covers the top of the active line 131. In the subsequent process, the top of the active line 131 can be protected.
  • the isolation dielectric layer 500 may provide a flat surface to form a mask layer for etching the active lines 131 to form via holes. In other embodiments, the isolation dielectric layer 500 may not be formed. In the process of etching the active line 131, the opening 301 is filled with the material of the mask layer, such as the bottom anti-reflection layer, etc. Form a flat surface.
  • the through hole 801 is formed by etching the first isolation layer 200 located at the end of the active line 131, and the bottom sidewall of the through hole 801 exposes the bit line 701.
  • the through hole 801 may also be formed at other positions of the active line 131.
  • the bit line connection line 702 is formed by filling conductive material in the through hole 801 and planarizing it.
  • the bottom of the bit line connection line 702 is connected to the bit line 701 and is used to lead out the bit line 701 buried under the active line 131 to facilitate the application of control signals to the bit line 701.
  • the bit line 701 is located below the active line 131, forms an electrical connection with the first doped region 1311 at the bottom of the active line 131, and extends along the extending direction of the active line 131.
  • a bit line connection line may be formed.
  • FIGS. 8A to 8C Please refer to FIGS. 8A to 8C to pattern the active line 131 to form a number of discrete active pillars 132.
  • an active pillar 132 is formed.
  • the active pillars 132 are arranged in an array along a first direction (y direction) and a second direction (x direction).
  • the isolation dielectric layer 500 is also etched at the same time.
  • the first direction is perpendicular to the second direction; in other embodiments, the included angle between the first direction and the second direction may be 60° to 120°.
  • a selective etching process can also be used to pattern only the active lines 131.
  • the isolation dielectric layer 501 is filled in the openings between adjacent active pillars 132; ion implantation is performed on the active pillars 132 to form a first doped region 1311.
  • the first doped region 1311 can also be formed by diffusion treatment.
  • a transition layer with doping elements is formed on the surface of the substrate 110 between adjacent active lines 131 (please refer to FIG. 3A); at least part of the transition layer with doping atoms is doped by diffusion treatment The elements diffuse into the active line 131 to form a doped active line, which is patterned to form a first doped region 1311.
  • a transition layer with doped elements may be formed on the surface of the substrate between the active pillars 132 (please refer to FIG. 8A), and then the doped elements may be diffused into the active pillars 132 through diffusion treatment. , The first doped region 1311 is formed.
  • the transition layer material can be deposited on the surface of the substrate 110 and then etched back to form a transition layer with a certain thickness.
  • the thickness of the transition layer can be adjusted according to the size requirements of the source/drain regions of the transistor to be formed. In some embodiments, the thickness of the transition layer is consistent with the height of the active line 131 or the active pillar 132. In some embodiments, the transition layer may also cover the top of the active line 131 or the active pillar 132 to ensure that the entire active line 131 or all areas of the active pillar 132 are doped.
  • the material of the transition layer is different from the material of the active line, and may be a material that facilitates the diffusion of impurities, such as polysilicon, or other materials such as dielectric materials such as silicon oxide, silicon nitride, and silicon oxynitride.
  • the method for forming the transition layer with doping elements includes: after forming an undoped transition layer with a certain thickness on the surface of the semiconductor component 110, doping the transition layer by ion implantation. At this time, the top of the active line 131 or the active pillar 132 is covered with a patterned mask layer, and the energy of the ion implantation is controlled so that the ion implantation can only dope the transition layer.
  • N-type or P-type ions, or atomic clusters with N-type or P-type ions are implanted into the transition layer.
  • the doping elements in the transition layer may exist in the form of ions, atoms, compound molecules or clusters.
  • an in-situ doping process can be used to directly form a transition layer with a doping element by adding a doping gas with a doping element to the deposition process gas. .
  • the diffusion treatment may be a thermal annealing process. According to the diffusion efficiency of dopant atoms, an annealing process with appropriate parameters is selected so that the doping elements in the transition layer diffuse into the active line 131 or the active pillar 132, A first doped region 1311 is formed.
  • the doping concentration in the first doped region formed after the diffusion treatment can be adjusted by adjusting the concentration of the doping element in the transition layer, the diffusion treatment time, temperature and other parameters.
  • an in-situ doping process may also be used.
  • the active layer 130 is doped; After patterning, the first doped region 1311 is formed.
  • the method of diffusion or in-situ doping can reduce the damage to the surface of the active pillar 132 (the first doped region 1311).
  • a semiconductor pillar 133 is formed on the surface of the first doped region 1311.
  • a selective epitaxy process is used to epitaxial semiconductor material on the top surface of the active column to form a semiconductor column 133 on the top of the active column. Due to the selective epitaxial process, only the active pillar, that is, the semiconductor material is grown epitaxially on the top surface of the first doped region 1311, and the material of the semiconductor pillar 133 is the same as the material of the active pillar , Is Si. In other embodiments, the material of the semiconductor pillar 133 may also be other semiconductor materials such as SiGe. After the semiconductor material with a certain thickness is grown epitaxially, the semiconductor material can be further etched and trimmed to form a semiconductor pillar 133 with a flatter surface.
  • a chemical vapor deposition (CVD) process can also be used to form a surface covering the first isolation layer 200, isolation dielectric layers 500, 501, and the first doped region 1311 on the surface of the structure shown in FIG. 9A.
  • the method for forming the semiconductor pillar includes: forming a protective layer on the surface of the first isolation layer and the isolation dielectric layer; forming an epitaxial via in the protective layer; and the bottom of the epitaxial via Expose the top surface of the active column; epitaxially grow a semiconductor material on the top surface of the active column to form a semiconductor column located in the epitaxial via; remove the protective layer.
  • the epitaxial through hole Through the epitaxial through hole, the growth size and position of the semiconductor column are restricted, and no more morphology trimming is performed by etching. It is possible to avoid problems such as collapse of the semiconductor column during the growth process or the trimming process.
  • a channel region located on the surface of the first doped region 1311 and a gate structure 1000 surrounding the channel region are formed in the semiconductor pillar 133.
  • the semiconductor pillar 133 may be implanted by channel ion implantation to form a channel region on the first doped region 1311, and the channel to be formed can be adjusted by the channel ion implantation.
  • channel doping may be performed at the corresponding position of the channel region through an in-situ doping process.
  • a gate dielectric layer and a gate layer are sequentially formed on the surfaces of the semiconductor pillars 133, the first isolation layer 200, and the isolation dielectric layers 500 and 501; the gate dielectric layer and the gate layer are patterned to form a
  • the gate structure 1000 in the channel region of the semiconductor pillar 133 exposes the top area of the semiconductor pillar 133.
  • the gate structure 1000 includes a gate layer and a gate dielectric layer. In FIGS. 11A to 11B, only the gate layer is shown, and the gate dielectric layer is omitted.
  • the gate dielectric layer may be a gate dielectric material such as silicon oxide, hafnium oxide, or aluminum oxide; the material of the gate layer may be a conductive material such as polysilicon, tungsten, copper, or aluminum.
  • FIG. 11D to FIG. 11F are schematic structural diagrams of forming a gate structure 1000 according to an embodiment of the application.
  • a gate dielectric layer 1011 covering the surface of the structure of FIG. 10 and a gate layer 1012 can be sequentially formed through a deposition process.
  • the gate layer entirely covers the structure below, and the top is higher than the semiconductor pillar 133 The top; then, referring to FIG. 11E, the gate layer 1012 is etched through a planarization and etch-back process, so that the height of the etched gate layer 1012a is lower than the top of the semiconductor pillar 133; please refer to FIG.
  • the exposed gate dielectric layer covering the top of the semiconductor pillar 122 is removed, and the exposed gate dielectric layer is removed by a chemical dry etching process, leaving only the gate dielectric layer 1011a covered by the gate layer 1012.
  • the chemical dry etching process can fully remove the exposed gate dielectric layer due to its better isotropic etching advantage.
  • the gate layer 1012 a and the gate dielectric layer 1011 a form a gate structure 1000, and the gate structure 1000 surrounds the channel region of the semiconductor pillar 133.
  • the gate electrodes of the gate structures 1000 on the surface of the semiconductor pillars 133 on the same straight line arranged in the second direction (x direction) are connected to form a word line.
  • the gate structures 1000 on the surface of each semiconductor pillar 133 may also be independent of each other.
  • each gate structure 1000 After forming the gate structure 1000, it further includes filling an isolation dielectric layer 1001 between adjacent gate structures 1000.
  • the isolation dielectric layer 1001 may be formed first, and then the isolation dielectric layer 1001 may be patterned to form an opening, and then the gate structure 1000 may be formed in the opening.
  • ion implantation is performed on the top region of the semiconductor pillar 133 to form the second doped region 1321.
  • the doping type of the second doped region 1321 is the same as the doping type of the first doped region 1311, and the second doped region 1321 and the first doped region 1311 respectively serve as vertical transistors The source or drain.
  • the second doped region 1321 can also be formed in the aforementioned steps by using a suitable in-situ doping, diffusion or implantation method, which will not be repeated here.
  • a second isolation layer 1200 covering the gate structure 1000 and the second doped region 1321 is formed.
  • the second isolation layer 1200 exposes the top surface of the second doped region 1321.
  • the material of the second isolation layer 1200 may be an insulating dielectric material such as silicon oxide, silicon oxynitride, etc., and the first isolation layer 200, the isolation dielectric layer 500, 501, and the isolation dielectric layer 1001 form a space between the vertical transistors. And provide a flat surface for forming other semiconductor structures or material layers above the vertical transistor.
  • an interconnection structure that penetrates the second isolation layer 1200 and is connected to the bit line connection line 702 may also be formed.
  • a bit line connection line that penetrates the second isolation layer 1200 and the first isolation layer 110 and is connected to the bit line 701 may also be formed.
  • the above forming method forms a vertical transistor on a substrate, and forms a buried bit line between the first doped region at the bottom of the vertical transistor and the substrate, so that the area of the transistor can be reduced, and At the same time, the problem of how to apply the bit line signal is solved.
  • the above forming method forms a vertical transistor on a substrate, and forms a buried bit line between the first doped region at the bottom of the vertical transistor and the substrate, so that the area of the transistor can be reduced, and At the same time, the problem of how to apply the bit line signal to the vertical transistor is solved.
  • the embodiment of the present application also provides a semiconductor structure.
  • FIGS. 13A to 13C are schematic diagrams of a semiconductor structure according to an embodiment of the application.
  • the semiconductor structure includes: a substrate 110; a vertical transistor located on the substrate 110; connected to the bottom of the vertical transistor and located between the bottom of the vertical transistor and the substrate 110 ⁇ 701 ⁇ The bit line 701. In this specific manner, the semiconductor structure is shown in FIGS. 13A to 13C.
  • the semiconductor structure may be formed by the method in the above-mentioned embodiments, or other methods may be used. All semiconductor structures with vertical transistors and buried bit lines located at the bottom of the vertical transistors can be used as the semiconductor structures claimed in this application.
  • the vertical transistor includes a first doped region 1311, a channel region 1322, a second doped region 1321, and a surrounding channel region 1322 that are sequentially arranged in an upward direction from the surface of the substrate 110.
  • the gate structure 1000 is set.
  • a plurality of the vertical transistors are formed on the semiconductor structure, which are arranged in an array along a first direction (y direction) and a second direction (x direction), and the bottoms of the vertical transistors on the same straight line arranged in the first direction
  • the first doped region 1311 is connected to the same bit line 701; the gate structures 1000 of the vertical transistors on the same straight line arranged in the second direction are connected.
  • the semiconductor structure further includes an isolation layer formed between the vertical transistors on the substrate 110, and the isolation layer includes an isolation dielectric layer 500 located between the bit line 701 and the first doped region 1311 , 501, the isolation dielectric layer 1001 between adjacent gate structures 1000, and the second isolation layer 1200 located on the surface of the isolation dielectric layer 1001, between adjacent second doped regions 1321, and located at the periphery of the vertical transistor The first isolation layer 200a.
  • the semiconductor structure further includes a through hole located in the isolation layer, a bit line connection line 702 is formed in the through hole, and the bottom of the bit line connection line 702 is connected to the bit line 701.
  • the bit line connection line 702 is located at one side edge of the transistor array, and on one side of each row of transistors arranged in the y direction, a bit line connection line 702 is formed to connect to the bit line 701 under the row of transistors.
  • the channel region 1322 and the second doped region 1321 of the vertical transistor are formed in the semiconductor pillar on the surface of the first doped region 1311, and the channel region 1322 and the second doped region
  • the semiconductor layer where 1321 is located and the semiconductor pillar are not an integral structure, but are formed separately.
  • the first doped region 1311, the channel region 1322, and the second doped region 1321 of the vertical transistor are located in the same active column, and the active column is an integral structure formed by doping The first doped region 1311, the channel region 1322, and the second doped region 1321.
  • the doped ions in the first doped region 1311 and/or the second doped region 1321 are formed by diffusion, in-situ doping or ion implantation.
  • the embodiment of the present application also provides a memory and a method of forming the same.
  • the semiconductor structure includes: a substrate; a vertical transistor located on the substrate; connected to the bottom of the vertical transistor and located at the bottom of the vertical transistor and the substrate The bit line between the bottoms.
  • the semiconductor structure is shown in FIGS. 13A to 13C.
  • the semiconductor structure may be formed by the method in the above-mentioned embodiments, or other methods may be used. All semiconductor structures with vertical transistors and buried bit lines located at the bottom of the vertical transistors can be used as the semiconductor structures claimed in this application.
  • a memory cell 1300 is formed above the vertical transistor, and the memory cell 1300 is connected to the second doped region 1321 of the vertical transistor.
  • the memory is a DRAM memory
  • the memory unit 1300 is a metal capacitor, which includes an upper electrode, a lower electrode, and a capacitor dielectric layer located between the upper and lower electrodes.
  • the structure of the capacitor may be a planar capacitor, a cylindrical capacitor, etc., and those skilled in the art can select a capacitor with a suitable structure as the storage unit according to requirements.
  • the storage unit 1300 is only an example, and does not represent the actual structure of the capacitor.
  • the second doped region 1321 of each transistor is connected to a memory cell to form a 1T1C memory structure.
  • the storage unit may include one capacitor, or two or more capacitors connected in parallel.
  • a metal contact layer may be formed on the surface of the second doped region 1321, and then a metal contact layer may be formed on the surface of the second doped region 1321.
  • the surface of the metal contact layer forms the memory cell.
  • the memory cell 1300 is formed in a dielectric layer (not shown in the figure), and an interconnection structure connecting the bit line connecting line 702 and the gate structure 1000 may also be formed in the dielectric layer to connect the The bit line and the word line are connected to an external circuit.
  • the storage unit may also be a magnetic storage unit, a ferroelectric storage unit, a phase change storage unit, or a resistance storage unit.
  • FIG. 15 is a schematic structural diagram of a memory according to an embodiment of the application.
  • the memory is a FeRAM memory, and a ferroelectric memory cell 1400 is formed above the second doped region 1321 of the vertical transistor of the semiconductor structure shown in FIG. 13A.
  • the ferroelectric memory cell includes a lower electrode connected to the second doped region 1321, an upper electrode located above the lower electrode, and a layer of ferroelectric material between the upper and lower electrodes. Ferroelectric capacitors.
  • the material of the ferroelectric material layer may be PZT (lead zirconate titanate) or SBT (barium strontium titanate).
  • the ferroelectric memory cell 1400 in FIG. 15 is only for illustration, and does not represent the actual structure of the ferroelectric memory cell. Those skilled in the art should be able to combine as needed to form a ferroelectric memory cell 1400 with a corresponding structure, which is not limited here.
  • the ferroelectric memory cell 1400 it is also necessary to form a plate line 1401 connected to the upper electrode above the ferroelectric memory cell 1400.
  • the ferroelectric memory cells arranged in the second direction (x direction) and located on the same bottom are connected to the same plate line 1401. Through the plate line 1401 and the vertical transistors below, the pairing can be realized.
  • the bidirectional pressure of the ferroelectric storage unit 1400 can utilize the properties of the ferroelectric material layer for data storage.
  • a magnetic memory cell may be formed on the second doped region 1321 of the vertical transistor.
  • the magnetic memory cell includes a magnetic tunnel junction, and the magnetic tunnel junction includes a fixed layer, a free layer, and a magnetic tunnel junction.
  • the dielectric layer between the fixed layer and the free layer.
  • the fixed layer is connected to the second doped region 1321.
  • memory cells may also be formed, such as magnetic memory cells, ferroelectric memory cells, phase change memory cells, or resistive memory cells, etc., to form corresponding memories.
  • vertical transistors are used as the control transistors connected to the memory cell, and the buried bit lines connected to the control transistors can increase the storage density of the memory.

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Abstract

提供一种半导体结构、存储器及其形成方法。半导体结构的形成方法包括：提供衬底（110），衬底表面形成有牺牲层（120）和位于牺牲层表面的有源层（130）；对有源层和牺牲层进行图形化，形成凹槽，凹槽将有源层和牺牲层分割为若干有源区（130a）；在凹槽内形成包围有源区的第一隔离层（200）；对有源区内的有源层进行图形化，形成若干分立的有源图形；沿相邻的有源图形之间的开口（301）去除牺牲层，形成位于有源图形底部与衬底之间的间隙（600）；在间隙内形成位线（701）；在部分有源图形顶部形成半导体柱（133）。上述方法能够减小晶体管的平面尺寸，提高存储器的存储密度。

Description

半导体结构及其形成方法、存储器及其形成方法
相关申请引用说明
本申请要求于2020年04月27日递交的中国专利申请号202010343514.2，申请名为“半导体结构及其形成方法、存储器及其形成方法”的优先权，其全部内容以引用的形式附录于此。
技术领域
本申请涉及半导体技术领域，尤其涉及一种半导体结构及其形成方法、存储器及其形成方法。
背景技术
存储器通常包括数据存储单元以及控制所述数据存储单元的控制晶体管。晶体管的集成度制约了存储器的存储密度。对于平面晶体管，通过缩小晶体管的沟道尺寸来减小晶体管的尺寸，从而提高存储器的存储密度。
但是随着晶体管沟道尺寸的减小，窄沟道效应以及短沟道效应所导致晶体管性能下降，使得存储器的性能受到影响，制约了晶体管尺寸以及存储器存储密度的进一步提高。
如何在不降低晶体管性能的前提下，减小晶体管的平面尺寸，提高存储器的存储密度是目前亟待解决的问题。
发明内容
本申请所要解决的技术问题是，提供一种半导体结构及其形成方法、存储器及其形成方法，进一步提高存储器的存储密度。
为了解决上述问题，本申请提供了一种半导体结构的形成方法，包括：提供衬底，所述衬底上形成有牺牲层和位于所述牺牲层上的有源层；对所述有源层和所述牺牲层进行图形化，形成凹槽，所述凹槽将所述有源层和所述牺牲层分割为若干有源区；在所述凹槽内填充以形成包围所述有源区的第一隔离层；对所述有源区内的有源层进行图形化，形成若干分立的有源图形，所述有源图形至少有一侧壁或端部与所述第一隔离层连接；沿相邻所述有源图形之间的开口去除所述牺牲层，形成位于所述有源图形底部与所述衬底之间的间隙；在所述间隙内形成位线；在部分所述有源图形顶部形成半导体柱。
可选的，在形成所述位线后，形成填充满相邻有源图形之间的隔离介质层。
可选的，所述有源图形为平行排列且沿第一方向延伸的有源线，所述有源线的至少一个侧壁或端部与所述第一隔离层连接；还包括：在形成所述位线后，对所述有源线进行图形化，形成若干沿第一方向和第二方向阵列排布的有源柱；在所述有源柱顶部形成所述半导体柱。
可选的，所述半导体柱的形成方法包括：在所述第一隔离层和所述隔离介质层表面形成保护层；在所述保护层内形成外延通孔；所述外延通孔底部暴露出所述有源柱顶部表面；在所述有源柱顶部表面外延生长半导体材料，形成位于所述外延通孔内的半导体柱；去除所述保护层。
可选的，在所述有源柱顶部表面形成半导体材料；然后对所述半导体材料进行刻蚀修整，形成位于所述有源柱顶部的半导体柱。
可选的，还包括：形成位于所述有源柱内的第一掺杂区；形成位于所述半导体柱内的沟道区和位于所述沟道区上方的第二掺杂区；形成环绕所述沟道区的栅极结构。
可选的，所述第一掺杂区的形成方法包括：对所述有源线或有源柱进行离子注入；所述第二掺杂区的形成方法包括：对所述半导体柱的顶部区域进行离子注入，形成位于所述半导体柱顶部的所述第二掺杂区。
可选的，所述第一掺杂区的形成方法包括：在形成所述有源线或有源柱之后，在相邻有源线或相邻有源柱之间的衬底表面形成具有掺杂元素的过渡层；通过扩散处理，将过渡层内的至少部分掺杂元素扩散进入有源线或有源柱内，形成所述第一掺杂区。
可选的，所述第一掺杂区的形成方法包括：采用原位掺杂工艺，在采用外延生长工艺形成所述有源层的过程中，对所述有源层进行掺杂，形成第一掺杂层；在图形化所述有源层形成所述有源柱后，所述第一掺杂层被图形化为第一掺杂区；所述沟道区、所述第二掺杂区的形成方法包括：采用原位掺杂工艺，在采用外延生长工艺形成所述半导体柱的过程中，进行原位掺杂，依次形成所述沟道区和所述第二掺杂区。
可选的，所述位线的形成方法进一步包括：形成填充满所述间隙以及所述开口的导电材料层；对所述导电材料层进行图形化，仅保留位于所述有源图形底部的沿第一方向延伸的部分导电材料层作为位线。
可选的，还包括：刻蚀所述第一隔离层或所述有源图形，形成通孔；在所述通孔内填充导电材料，形成位线连接线，所述位线连接线的底部与所述位线连接。
可选的，所述通孔位于有源区边缘。
可选的，所述栅极结构的形成方法包括：在所述第一隔离层、隔离介质层以及半导体柱表面依次形成栅介质层以及栅极层；对所述栅介质层和所述栅极层进行图形化，形成环绕所述半导体柱的沟道区的栅极结构，并暴露出所述半导体柱的顶部区域。
可选的，位于第二方向排列的同一列上的半导体柱表面的栅极结构相连。
可选的，还包括：形成覆盖所述栅极结构、第二掺杂区的第二隔离层，所述第二隔离层暴露出所述第二掺杂区的顶部表面。
本申请的技术方案还提供一种半导体结构，包括：采用上述方法形成。
本申请的技术方案还提供一种存储器，包括：上述半导体结构；位于所述半导体结构上方的存储单元，所述存储单元连接至所述半导体柱。
可选的，所述存储单元包括电容存储单元、磁性存储单元、铁电存储单元、相变存储单元或电阻存储单元。
本申请的技术方案还提供一种存储器的形成方法，包括：提供上述方法所形成的半导体结构；在所述半导体结构上形成存储单元，所述存储单元连接至所述半导体柱。
可选的，所述存储单元包括电容存储单元、磁性存储单元、铁电存储单元、相变存储单元或电阻存储单元。
本申请的半导体结构的形成方法，在衬底上形成牺牲层以及位于牺牲层表面的有源层，利用位线替代牺牲层的位置，从而形成埋入式的位线，从而便于后续形成竖直型的晶体管，通过位线将竖直型的晶体管底部的源/漏极引出。并且，在对有源层进行图形化形成有源线之前，通过第一隔离层将有源层分割为多个有源区，再将各有源区内的有源层图形化为有源图形，各有源图形至少一侧与第一隔离层连接，从而使得去除有源图形下方的牺牲层后，所述有源图形能够保持悬空。并且，本申请的半导体结构的形成方法中，有源层的厚度较低，后续再通过对图形化有源层形成的有源柱顶部外延形成半导体柱，可以降低有源层被图形化后图形发生倒塌的风险。
进一步的，竖直型的晶体管占据的版图尺寸较小，且沟道宽度由有源层的厚度来决定，可以在不减小沟道宽度等情况下，减小晶体管的面积，从而提高半导体结构的集成度。
本申请的存储器包括具有竖直型晶体管阵列的半导体结构，在晶体管尺寸较小的情况下，能够提高存储器的存储密度。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对本申请实施例中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1至图13C为本申请一实施例的半导体形成过程的结构示意图；
图14为本申请一实施例的存储器的结构示意图；
图15为本申请一实施例的存储器的结构示意图。
具体实施方式
为了使本申请的目的、技术手段及其效果更加清楚明确，以下将结合附图对本申请作进一步地阐述。应当理解，此处所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例，并不用于限定本申请。基于本申请中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
请参考图1至图13C，为本申请一实施例的半导体形成过程的结构示意图。
请参考图1，提供衬底110，所述衬底110表面形成有牺牲层120和位于所述牺牲层120表面的有源层130。
所述衬底110可以为单晶硅、锗、SiC等，各种半导体材料，可以为单层结构也可以为复合结构，例如所述衬底110包括半导体基底以及形成于半导体基底表面的介质层等，在此不作限定。
可以通过沉积工艺在所述衬底110表面依次形成所述牺牲层120和所述有源层130。所述有源层130采用半导体材料，例如Si、Ge、SiC或SiGe等，可以是其中的一种或多种半导体材料。所述牺牲层120的材料与所述衬底110、有源层120的材料不同，使得后续在去除所述牺牲层120的过程中，减少对所述衬底110、有源层120的影响。
该实施例中，所述衬底110为硅衬底，所述牺牲层120为SiGe层，所述有源层为硅层。 采用外延生长工艺，在所述衬底110表面外延形成所述牺牲层120之后，再通过外延工艺，在所述牺牲层120表面形成有源层130。
实际上，所述牺牲层120只要与所述衬底110以及有源层130采用不同的材料，在去除牺牲层120的过程中，牺牲层120与所述衬底110以及有源层130之间有较高的刻蚀选择比即可。
在一些实施例中，所述衬底110、牺牲层120以及有源层130可以为SOI衬底，其中SOI衬底中的埋氧层作为牺牲层120。
在其他实施例中，可以通过对体硅衬底进行离子注入，在所述体硅衬底内部形成掺杂层作为所述牺牲层120。例如对体硅进行Ge注入，通过控制Ge的注入深度，在体硅内部形成SiGe层作为牺牲层120，掺杂层下方的硅层为衬底110，掺杂层上方的硅层作为有源层。在其他实施例中，也可以通过注入其他元素形成所述掺杂层，例如C、O、N等，使得所述掺杂层的刻蚀速率与其上方及下方的材料层均不同，从而形成所述牺牲层120。较佳的，所述牺牲层120的材料可以为氧化硅、氮化硅、氮氧化硅、碳氧化硅等。
所述有源层130用于形成竖直晶体管的底部掺杂区，即源/漏极。所述牺牲层120用于后续被替代形成位线。根据待形成的竖直晶体管的尺寸以及位线的尺寸，合理设置所述牺牲层120和所述有源层130的厚度。在一个实施例中，所述牺牲层120的厚度可以为35nm～50nm。该实施例中，晶体管的底部掺杂区与上方的沟道区及顶部掺杂区分开形成，可以降低所述有源层130的厚度，从而可以降低后续对所述有源层130进行图形化后，形成的有源图形发生倒塌的几率。
请参考图2A和图2B，对所述有源层130和所述牺牲层120进行图形化，形成凹槽，所述凹槽将所述有源层130(请参考图1)和所述牺牲层120(请参考图1)分割为若干有源区130a；在所述凹槽内形成包围所述有源区130a的第一隔离层200。
刻蚀所述有源层130以及牺牲层120至所述衬底110表面，形成所述凹槽，将所述有源层130分割为若干有源区130a；然后再在所述凹槽内填充介质材料，并进行平坦化处理，形成所述第一隔离层200，实现各有源区130a之间的横向的电学隔离。
图2A中示出了被所述第一隔离层200包围的一个有源区130a的结构示意图。图2B示出了多个有源区130a以及第一隔离层200的俯视示意图。
所述有源区130a的尺寸可以根据需要进行设计，在一些实施例中，若所述有源区130a内用于形成存储器的控制晶体管，所述有源区130a可以对应于一个存储块。
请参考图3A至图3C，对所述有源区130a内的有源层进行图形化，形成若干分立的有源图形，所述有源图形至少有一侧壁或端部与所述第一隔离层200连接。图3B为沿图3A中A-A’线的剖面示意图；图3C为沿图3A中B-B’线的剖面示意图。
该实施例中，对所述有源区130a内的有源层进行图形化，形成若干平行排列且沿第一方向(y方向)延伸的长条状的有源线131，相邻有源线131之间具有开口301。所述有源线131的端部均与所述第一隔离层200连接，且位于所述有源区130a边缘的有源线131的侧壁也与所述第一隔离层200连接。
该实施例中，仅对所述有源层进行图形化。在其他实施例中，也可以进一步刻蚀所述牺牲层120，去除所述开口301底部的牺牲层120。
该实施例中，形成所述有源线131的方法包括：在所述有源区130a表面形成图形化掩膜层(图中未示出)，所述图形化掩膜层内具有沿第一方向延伸的开口图形；以所述图形化掩膜层为掩膜，刻蚀所述有源层130成长条状的有源线131以及开口301。
在其他实施例中，也可以通过对所述有源区内的有源层进行图形化形成有源柱，例如形成2行或2列排列的若干有源柱，使得所述有源柱至少有一侧侧壁与所述第一隔离层200相连；在其他实施例中，也可以形成更多行或更多列的有源柱，可以通过在有源柱之间沉积介质层，确保有源柱至少有一侧壁与介质层连接，从而使得后续去除所述有源柱底部的牺牲层120之后，所述有源柱能够保持悬空状态。
请参考图4A和图4B，沿所述开口301去除所述牺牲层120，在所述有源线131底部与所述衬底110之间形成间隙600。
采用湿法刻蚀工艺去除所述牺牲层120，本领域技术人员可以根据所述牺牲层120的材料选择合适的刻蚀溶液，使得所述湿法刻蚀过程中，所述牺牲层120和所述有源线131、第一隔离层200有较高的刻蚀选择比，以在去除所述牺牲层120的过程中，减少对所述有源线131和所述第一隔离层200的影响。
在去除所述牺牲层120之后，所述有源线131由所述第一隔离层200支撑，悬空于所述衬底110上方，与衬底110之间形成间隙600。
请参考图5A至图5B，在所述间隙600内填充导电材料，形成沿第一方向延伸的位线701。
可以通过化学气相沉积或物理气相沉积工艺在所述间隙600内沉积导电材料，例如多晶硅或者Cu、Ag或Al等金属材料。
所述导电材料填充满所述间隙600，形成位于所述有源线131底部的位线701；所述导电材料还填充满所述开口301，并覆盖所述第一隔离层200以及有源线131顶部，后续通过回刻蚀或者平坦化处理，去除所述第一隔离层200顶部以及有源线131顶部的导电材料以及通过刻蚀处理去除所述开口301的导电材料，避免相邻有源线131底部的位线701之间相互连接。
请参考图6A至图6C，在所述衬底110表面形成填充满各有源线131之间间距的隔离介质层500，并进行平坦化；在所述有源线131端部形成暴露出所述衬底110表面的通孔801。图6B为沿图6A中割线A-A’的剖面示意图；图6C为沿图6A中割线B-B’的剖面示意图。
所述隔离介质层500的材料为介电材料，用于在各有源线131之间提供电学隔离。该实施例中，所述隔离介质层500的材料为氧化硅。该实施例中，形成所述隔离介质层500的方法为化学气相沉积工艺，在所述衬底110表面形成填充满相邻有源线131之间的间距以及覆盖所述有源线131顶部的隔离材料层之后，对隔离材料层进行平坦化，形成所述隔离介质层500。该实施例中，所述隔离介质层500的顶部与所述有源线131的顶部齐平；在 其他实施例中，所述有源线131顶部还保留有用于对有源层进行图形化形成有源线的图形化掩膜层，所述隔离介质层500与所述图形化掩膜层齐平；在其他实施例中，在形成所述隔离介质层500之前，所述图形化掩膜层已被去除，所述隔离介质层500还覆盖所述有源线131的顶部，在后续工艺中，可以对所述有源线131顶部进行保护。
所述隔离介质层500可以提供平坦表面，以形成用于刻蚀有源线131形成通孔的掩膜层。在其他实施例中，也可以不形成所述隔离介质层500，在刻蚀有源线131的过程中，通过掩膜层的材料，例如底部抗反射层等将所述开口301填满，以形成平坦表面。
该实施例中，通过刻蚀位于所述有源线131的端部的第一隔离层200形成所述通孔801，所述通孔801底部侧壁暴露出所述位线701。在其他实施例中，也可以在所述有源线131的其他位置处形成所述通孔801。
请参考图7A至图7C，通过在所述通孔801内填充导电材料，并进行平坦化，形成所述位线连接线702。
所述位线连接线702的底部与所述位线701连接，用于将埋入所述有源线131下方的位线701引出，便于向所述位线701施加控制信号。所述位线701位于所述有源线131下方，与所述有源线131底部的第一掺杂区1311之间形成电连接，沿所述有源线131的延伸方向延伸。
在其他实施例中，也可以在形成所述第二隔离层1200(图13A)之后，再形成位线连接线。
请参考图8A至图8C，对所述有源线131进行图形化，形成若干分立的有源柱132。
通过对所述有源线131进行图形化，形成有源柱132。所述有源柱132沿第一方向(y方向)和第二方向(x方向)阵列排布。该实施例中，在对所述有源线131进行图形化的过程中，对所述隔离介质层500也同时进行刻蚀。该实施例中，所述第一方向垂直于所述第二方向；在其他实施例中，所述第一方向和第二方向之间的夹角可以为60°～120°。
在其他实施例中，还可以采用选择性刻蚀工艺，仅对所述有源线131进行图形化。
请参考图9A至图9C，在相邻有源柱132之间的开口内填充隔离介质层501；对所述有源柱132进行离子注入，形成第一掺杂区1311。
在其他实施例中，还可以通过扩散处理，形成所述第一掺杂区1311。具体的，在相邻有源线131(请参考图3A)之间的衬底110表面形成具有掺杂元素的过渡层；通过扩散处理，将具有掺杂原子的过渡层内的至少部分掺杂元素扩散进入有源线131内，形成掺杂的有源线，被图形化后形成第一掺杂区1311。在其他实施例中，还可以在有源柱132(请参考图8A)之间的衬底表面形成具有掺杂元素的过渡层，再通过扩散处理，将掺杂元素扩散进入有源柱132内，形成所述第一掺杂区1311。
可以通过在衬底110表面沉积过渡层材料后，进行回刻蚀，形成一定厚度的过渡层，所述过渡层的厚度可以根据待形成的晶体管的源/漏区的尺寸要求调整。在一些实施例中，所述过渡层的厚度与所述有源线131或有源柱132的高度一致。在一些实施例中，所述过渡层还可以覆盖所述有源线131或有源柱132的顶部，以确保将整个有源线131或有源柱 132所有区域均实现掺杂。
所述过渡层的材料与所述有源线的材料不同，可以为利于杂质扩散的材料，例如多晶硅，还可以为其他材料例如氧化硅、氮化硅、氮氧化硅等介质材料。形成具有掺杂元素的所述过渡层的形成方法包括：在所述半导体成110表面形成一定厚度未被掺杂的过渡层之后，通过离子注入，对所述过渡层进行掺杂。此时，在所述有源线131或有源柱132顶部覆盖有图形化掩膜层，通过控制所述离子注入的能量，使得所述离子注入仅能对所述过渡层进行掺杂。根据待形成的晶体管的类型，向所述过渡层内注入N型或P型离子，或者具有N型或P型离子的原子团簇。所述过渡层内的掺杂元素可以以离子、原子、化合物分子或者团簇形式存在。在其他实施例中，也可以在形成所述过渡层的过程中，通过原位掺杂工艺，通过在沉积工艺气体中加入具有掺杂元素的掺杂气体，直接形成具有掺杂元素的过渡层。
所述扩散处理可以为热退火工艺，根据掺杂原子的扩散效率，选择合适参数的退火工艺，使得所述过渡层内的掺杂元素扩散进入所述有源线131或有源柱132内，形成第一掺杂区1311。可以通过调整所述过渡层内的掺杂元素的浓度，扩散处理时间、温度等参数，调整扩散处理后形成的第一掺杂区内的掺杂浓度。
在其他实施例中，还可以采用原位掺杂工艺，在通过外延工艺沉积形成所述有源层130的过程中，对所述有源层130进行掺杂；在对所述有源层130进行图形化后，形成所述第一掺杂区1311。
与采用离子注入形成所述第一掺杂区1311相比，采用扩散或者原位掺杂的方式，能够减少对有源柱132(第一掺杂区1311)表面的损伤。
请参考图10，在所述第一掺杂区1311表面形成半导体柱133。
该实施例中，采用选择性外延工艺，在所述有源柱顶部表面外延半导体材料，形成位于所述有源柱顶部的半导体柱133。由于采用选择性外延工艺，仅会在所述有源柱，即在所述第一掺杂区1311的顶部表面外延生长半导体材料，所述半导体柱133的材料与所述有源柱的材料相同，为Si。在其他实施例中，所述半导体柱133的材料还可以为SiGe等其他半导体材料。在外延生长一定厚度的半导体材料后，还可以进一步对所述半导体材料进行刻蚀修整，以形成表面形貌更为平整的半导体柱133。
在其他实施例中，还可以采用化学气相沉积(CVD)工艺，在图9A所示的结构表面形成覆盖所述第一隔离层200、隔离介质层500、501以及第一掺杂区1311表面的半导体材料；然后对所述半导体材料进行图形化，形成位于所述第一掺杂区1311顶部的半导体柱。
在其他实施例中，所述半导体柱的形成方法包括：在所述第一隔离层和所述隔离介质层表面形成保护层；在所述保护层内形成外延通孔；所述外延通孔底部暴露出所述有源柱顶部表面；在所述有源柱顶部表面外延生长半导体材料，形成位于所述外延通孔内的半导体柱；去除所述保护层。通过所述外延通孔，限制半导体柱的生长尺寸和位置，无需再通过刻蚀进行形貌的修整。可以避免所述半导体柱在生长过程或修整过程中发生倒塌等问题。
请参考图11A至图11C，在所述半导体柱133内形成位于所述第一掺杂区1311表面的 沟道区，以及环绕所述沟道区的栅极结构1000。
本申请的实施例中，可以通过离子注入，对所述半导体柱133进行沟道离子注入，在所述第一掺杂区1311上形成沟道区，通过所述沟道离子注入，调整待形成的晶体管的阈值电压等参数。
在其他实施例中，可以在形成所述半导体柱133的过程中，通过原位掺杂工艺在沟道区对应位置处进行沟道掺杂。
在所述半导体柱133、第一隔离层200以及隔离介质层500、501表面依次形成栅介质层以及栅极层；对所述栅介质层和所述栅极层进行图形化，形成环绕所述半导体柱133的沟道区的栅极结构1000，并暴露出所述半导体柱133的顶部区域。所述栅极结构1000包括栅极层和栅介质层，图11A至图11B中，仅示出了栅极层，省略了栅介质层。
所述栅介质层可以为氧化硅、氧化铪、氧化铝等栅介质材料；所述栅极层的材料可以为多晶硅、钨、铜或铝等导电材料。
请参考图11D至图11F，为本申请一实施例，形成栅极结构1000的结构示意图。请参考图11D，可以通过沉积工艺，依次形成覆盖所述图10结构表面的栅介质层1011，以及栅极层1012，所述栅极层整体覆盖下方的结构，顶部高于所述半导体柱133顶部；然后，请参考图11E，通过平坦化及回刻蚀工艺，刻蚀所述栅极层1012，使得刻蚀后的栅极层1012a的高度低于半导体柱133的顶部；请参考图11F，去除覆盖所述半导体柱122顶部裸露的栅介质层，刻蚀通过化学干法刻蚀工艺去除所述裸露的栅介质层，仅保留被所述栅极层1012覆盖的栅介质层1011a。化学干法刻蚀工艺由于具有较好的各向同性刻蚀优势，能充分去除所述裸露的栅介质层。所述栅极层1012a和所述栅介质层1011a构成栅极结构1000，所述栅极结构1000环绕半导体柱133的沟道区。
该实施例中，沿第二方向(x方向)排列的同一直线上的半导体柱133表面的栅极结构1000的栅电极相连，构成字线。
在其他实施例中，各个半导体柱133表面的栅极结构1000之间也可以是相互独立的。
为了使得各栅极结构1000之间进行电学隔离，在形成所述栅极结构1000之后，还包括在相邻栅极结构1000之间填充隔离介质层1001。在其他实施例中，也可以先形成所述隔离介质层1001，然后对所述隔离介质层1001进行图形化，形成开口，再在所述开口内形成所述栅极结构1000。
请参考图12A至图12C，形成所述栅极结构1000之后，对所述半导体柱133的顶部区域进行离子注入，形成所述第二掺杂区1321。
所述第二掺杂区1321的掺杂类型与所述第一掺杂区1311的掺杂类型一致，所述第二掺杂区1321和所述第一掺杂区1311分别作为竖直型晶体管的源极或漏极。在其他实施例中，所述第二掺杂区1321还可以在前述的步骤中，采用合适的原位掺杂、扩散或者注入方式形成，在此不再赘述。
请参考图13A至图13C，形成覆盖所述栅极结构1000、第二掺杂区1321的第二隔离层1200。所述第二隔离层1200暴露出所述第二掺杂区1321的顶部表面。
所述第二隔离层1200的材料可以为氧化硅、氮氧化硅等绝缘介质材料，与所述第一隔离层200、隔离介质层500、501以及隔离介质层1001形成各竖直型晶体管之间的隔离层，并且为在所述竖直型晶体管上方形成其他半导体结构或材料层提供平坦表面。
在其他实施例中，还可以形成贯穿所述第二隔离层1200与所述位线连接线702连接的互连结构。在其他实施例中，也可以在该步骤中，形成贯穿所述第二隔离层1200、第一隔离层110且与所述位线701连接的位线连接线。
上述形成方法在衬底上形成竖直型晶体管，且在所述竖直型晶体管底部的第一掺杂区下方与衬底之间形成埋入式的位线，从而可以减少晶体管的面积，并同时解决了如何施加位线信号的问题。
上述形成方法在衬底上形成竖直型晶体管，且在所述竖直型晶体管底部的第一掺杂区下方与衬底之间形成埋入式的位线，从而可以减少晶体管的面积，并同时解决了如何对竖直晶体管的施加位线信号的问题。
本申请的实施例还提供一种半导体结构。
请参考图13A至图13C，为本申请一实施例的半导体结构的结构示意图。
所述半导体结构包括：衬底110；位于所述衬底110上的竖直型晶体管；与所述竖直型晶体管底部连接，且位于所述竖直型晶体管底部与所述衬底110之间的位线701。该具体方式中，所述半导体结构如图13A至13C所示。
在本申请的其他实施例中，所述半导体结构可以采用上述实施例中的方法形成，也可以采用其他方法。所有具有竖直晶体管，以及位于竖直晶体管底部的埋入式位线的半导体结构，均可以作为本申请所要求保护的半导体结构。
该实施例中，所述竖直型晶体管包括自衬底110表面向上的方向上依次设置的第一掺杂区1311、沟道区1322、第二掺杂区1321以及环绕所述沟道区1322设置的栅极结构1000。
所述半导体结构上形成有多个所述竖直型晶体管，沿第一方向(y方向)和第二方向(x方向)阵列分布，沿第一方向排列的同一直线上的竖直型晶体管底部的第一掺杂区1311连接至同一位线701；沿第二方向排列的同一直线上的竖直型晶体管的栅极结构1000相连接。
所述半导体结构还包括：位于所述衬底110上形成于各竖直型晶体管之间的隔离层，所述隔离层包括位于位线701、第一掺杂区1311之间的隔离介质层500、501、相邻栅极结构1000之间的隔离介质层1001，以及位于所述隔离介质层1001表面，相邻第二掺杂区1321之间的第二隔离层1200、位于竖直晶体管外围的第一隔离层200a。
所述半导体结构还包括：位于所述隔离层内的通孔，所述通孔内形成有位线连接线702，所述位线连接线702底部连接至所述位线701。该实施例中，所述位线连接线702位于晶体管阵列的一侧边缘，沿y方向排列的每一行晶体管的一侧，均形成有一位线连接线702与该行晶体管下方的位线701连接，相邻位线连接线702之间具有第一隔离层200。
该实施例中，所述竖直晶体管的沟道区1322和第二掺杂区1321形成于所述第一掺杂区1311表面的半导体柱内，所述沟道区1322和第二掺杂区1321所在的半导体层和所述半导体柱非一体结构，而是分开形成的。在一些实施例中，所述竖直晶体管的第一掺杂区1311、 沟道区1322、第二掺杂区1321位于同一有源柱内，所述有源柱为一体结构，通过掺杂形成了所述第一掺杂区1311、沟道区1322、第二掺杂区1321。
所述第一掺杂区1311和/或所述第二掺杂区1321内的掺杂离子通过扩散、原位掺杂或离子注入方式形成。
本申请的实施例还提供一种存储器及其形成方法。
首先提供一半导体结构，所述半导体结构包括：衬底；位于所述衬底上的竖直型晶体管；与所述竖直型晶体管底部连，且位于所述竖直型晶体管底部与所述衬底之间的位线。该具体方式中，所述半导体结构如图13A至13C所示。所述半导体结构可以采用上述实施例中的方法形成，也可以采用其他方法。所有具有竖直晶体管，以及位于竖直晶体管底部的埋入式位线的半导体结构，均可以作为本申请所要求保护的半导体结构。
请参考图14，在所述竖直型晶体管上方形成存储单元1300，所述存储单元1300连接至所述竖直型晶体管的第二掺杂区1321。
在一个实施例中，所述存储器为DRAM存储器，所述存储单元1300为金属电容器，包括上电极、下电极以及位于上、下电极之间的电容介质层。所述电容器的结构可以为平面电容器、柱形电容器等，本领域技术人员可以根据需求，选择合适结构的电容器作为存储单元。图14中，所述存储单元1300仅为示例，并不代表电容器的实际结构。该实施例中，每个晶体管的第二掺杂区1321连接至一个存储单元，构成1T1C的存储结构。所述存储单元可以包括一个电容器，或两个以上并联的电容器。
在其他实施例中，为了降低所述第二掺杂区1321与所述存储单元1300之间的连接电阻，还可以在所述第二掺杂区1321表面形成金属接触层，然后再在所述金属接触层表面形成所述存储单元。
所述存储单元1300形成与介质层(图中未示出)内，还可以在所述介质层内形成连接所述位线连接线702以及栅极结构1000的互连结构，用于将所述位线以及字线连接至外部电路。
在本申请的其他实施例中，所述存储单元还可以为磁性存储单元、铁电存储单元、相变存储单元或电阻存储单元。
请参考图15，为本申请一实施例的存储器的结构示意图。
所述存储器为FeRAM存储器，在图13A所示的半导体结构的竖直型晶体管的第二掺杂区1321上方形成铁电存储单元1400。
所述铁电存储单元包括与所述的第二掺杂区1321连接的下电极、位于所述下电极上方的上电极、以及位于所述上、下电极之间的铁电材料层所构成的铁电电容。所述铁电材料层的材料可以为PZT(锆钛酸铅)或SBT(钛酸钡锶)。图15中的铁电存储单元1400仅为示意，并不代表实际的铁电存储单元的结构。本领域技术人员，应当能够根据需要结合，形成相应结构的铁电存储单元1400，在此不作限制。
对于铁电存储单元1400，还需要在所述铁电存储单元1400上方，形成与上电极连接的板线1401。该实施例中，沿第二方向(x方向)上排列的位于同一之下上的铁电存储单元 连接至同一根板线1401，通过所述板线1401和下方的竖直晶体管，可以实现对所述铁电存储单元1400的双向加压，从而利用铁电材料层的性质进行数据存储。
在其他实施例中，还可以在所述竖直晶体管的第二掺杂区1321上形成磁性存储单元，所述磁性存储单元包括磁性隧道结，所述磁性隧道结包括固定层、自由层以及位于所述固定层和自由层之间的介质层。所述固定层连接至所述第二掺杂区1321。
在其他实施例中，还可以形成其他结构或类型的存储单元，例如磁性存储单元、铁电存储单元、相变存储单元或电阻存储单元等，以形成对应的存储器。
上述存储器及其形成方法，采用竖直型晶体管作为与存储单元连接的控制晶体管，以及与所述控制晶体管连接的埋入型的位线，可以提高存储器的存储密度。
以上所述仅是本申请的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本申请的保护范围。

Claims (20)

  1. 一种半导体结构的形成方法，其中，包括：
    提供衬底，所述衬底上形成有牺牲层和位于所述牺牲层上的有源层；
    对所述有源层和所述牺牲层进行图形化，形成凹槽，所述凹槽将所述有源层和所述牺牲层分割为若干有源区；
    在所述凹槽内填充以形成包围所述有源区的第一隔离层；
    对所述有源区内的有源层进行图形化，形成若干分立的有源图形，所述有源图形至少有一侧壁或端部与所述第一隔离层连接；
    沿相邻的所述有源图形之间的开口去除所述牺牲层，形成位于所述有源图形底部与所述衬底之间的间隙；
    在所述间隙内形成位线；
    在部分所述有源图形顶部形成半导体柱。
  2. 根据权利要求1所述的半导体结构的形成方法，其中，在形成所述位线后，形成填充满相邻有源图形之间的隔离介质层。
  3. 根据权利要求2所述的半导体结构的形成方法，其中，所述有源图形为平行排列且沿第一方向延伸的有源线，所述有源线的至少一个侧壁或端部与所述第一隔离层连接；还包括：在形成所述位线后，对所述有源线进行图形化，形成若干沿第一方向和第二方向阵列排布的有源柱；在所述有源柱顶部形成所述半导体柱。
  4. 根据权利要求3所述的半导体结构的形成方法，其中，所述半导体柱的形成方法包括：在所述第一隔离层和所述隔离介质层表面形成保护层；在所述保护层内形成外延通孔；所述外延通孔底部暴露出所述有源柱顶部表面；在所述有源柱顶部表面外延生长半导体材料，形成位于所述外延通孔内的半导体柱；去除所述保护层。
  5. 根据权利要求3所述的半导体结构的形成方法，其中，在所述有源柱顶部表面形成半导体材料；然后对所述半导体材料进行刻蚀修整，形成位于所述有源柱顶部的半导体柱。
  6. 根据权利要求3所述的半导体结构的形成方法，其中，还包括：形成位于所述有源柱内的第一掺杂区；形成位于所述半导体柱内的沟道区和位于所述沟道区上方的第二掺杂区；形成环绕所述沟道区的栅极结构。
  7. 根据权利要求6所述的半导体结构的形成方法，其中，所述第一掺杂区形成方法包括：对所述有源线或有源柱进行离子注入；所述第二掺杂区的形成方法包括：对所述半导体柱的顶部区域进行离子注入，形成位于所述半导体柱顶部的所述第二掺杂区。
  8. 根据权利要求6所述的半导体结构的形成方法，其中，所述第一掺杂区的形成方法包括：在形成所述有源线或有源柱之后，在相邻有源线或相邻有源柱之间的衬底表面形成具有掺杂元素的过渡层；通过扩散处理，将过渡层内的至少部分掺杂元素扩散进入有源线或有源柱内，形成所述第一掺杂区。
  9. 根据权利要求6所述的半导体结构的形成方法，其中，所述第一掺杂区的形成方法包括：采用原位掺杂工艺，在采用外延生长工艺形成所述有源层的过程中，对所述有源层进行掺杂，形成第一掺杂层；在图形化所述有源层形成所述有源柱后，所述第一掺杂层被图 形化为第一掺杂区；所述沟道区、所述第二掺杂区的形成方法包括：采用原位掺杂工艺，在采用外延生长工艺形成所述半导体柱的过程中，进行原位掺杂，依次形成所述沟道区和所述第二掺杂区。
  10. 根据权利要求1所述的半导体结构的形成方法，其中，所述位线的形成方法进一步包括：形成填充满所述间隙以及所述开口的导电材料层；对所述导电材料层进行图形化，仅保留位于所述有源图形底部的沿第一方向延伸的部分导电材料层作为位线。
  11. 根据权利要求10所述的半导体结构的形成方法，其中，还包括：刻蚀所述第一隔离层或所述有源图形，形成通孔；在所述通孔内填充导电材料，形成位线连接线，所述位线连接线的底部与所述位线连接。
  12. 根据权利要求11所述的半导体结构的形成方法，其中，所述通孔位于有源区边缘。
  13. 根据权利要求6所述的半导体结构的形成方法，其中，所述栅极结构的形成方法包括：在所述第一隔离层、隔离介质层以及半导体柱表面依次形成栅介质层以及栅极层；对所述栅介质层和所述栅极层进行图形化，形成环绕所述半导体柱的沟道区的栅极结构，并暴露出所述半导体柱的顶部区域。
  14. 根据权利要求13所述的半导体结构的形成方法，其中，位于第二方向排列的同一列上的半导体柱表面的栅极结构相连。
  15. 根据权利要求6所述的半导体结构的形成方法，其中，还包括：形成覆盖所述栅极结构、第二掺杂区的第二隔离层，所述第二隔离层暴露出所述第二掺杂区的顶部表面。
  16. 一种半导体结构，其中，包括：采用权利要求1所述的方法形成。
  17. 一种存储器，其中，包括：
    如权利要求1所述方法所形成的半导体结构；
    位于所述半导体结构上方的存储单元，所述存储单元连接至所述半导体柱。
  18. 根据权利要求17所述的存储器，其中，所述存储单元包括电容存储单元、磁性存储单元、铁电存储单元、相变存储单元或电阻存储单元。
  19. 一种存储器的形成方法，其中，包括：
    提供如权利要求1所述方法所形成的半导体结构；
    在所述半导体结构上形成存储单元，所述存储单元连接至所述半导体柱的。
  20. 根据权利要求19所述的存储器的形成方法，其中，所述存储单元包括电容存储单元、磁性存储单元、铁电存储单元、相变存储单元或电阻存储单元。
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