WO2021218438A1 - 显示基板及显示装置 - Google Patents

显示基板及显示装置 Download PDF

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Publication number
WO2021218438A1
WO2021218438A1 PCT/CN2021/080390 CN2021080390W WO2021218438A1 WO 2021218438 A1 WO2021218438 A1 WO 2021218438A1 CN 2021080390 W CN2021080390 W CN 2021080390W WO 2021218438 A1 WO2021218438 A1 WO 2021218438A1
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sub
line
layer
gate
same
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PCT/CN2021/080390
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English (en)
French (fr)
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袁粲
李蒙
李永谦
袁志东
张大成
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京东方科技集团股份有限公司
合肥京东方卓印科技有限公司
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Priority to US17/773,501 priority Critical patent/US20230006023A1/en
Publication of WO2021218438A1 publication Critical patent/WO2021218438A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/86—Arrangements for improving contrast, e.g. preventing reflection of ambient light
    • H10K50/865—Arrangements for improving contrast, e.g. preventing reflection of ambient light comprising light absorbing layers, e.g. light-blocking layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/351—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels comprising more than three subpixels, e.g. red-green-blue-white [RGBW]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/8791—Arrangements for improving contrast, e.g. preventing reflection of ambient light
    • H10K59/8792—Arrangements for improving contrast, e.g. preventing reflection of ambient light comprising light absorbing layers, e.g. black layers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0452—Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/029—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel
    • G09G2320/0295—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel by monitoring each display pixel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the invention belongs to the field of display technology, and specifically relates to a display substrate and a display device.
  • the organic light-emitting diode (Organic Light-Emitting Device, referred to as OLED) display substrate is a display substrate different from the traditional liquid crystal display (Liquid Crystal Display, referred to as LCD). It has active light emission, good temperature characteristics, low power consumption, and response. Fast, flexible, ultra-thin and low cost. Therefore, it has become one of the important development discoveries of a new generation of display devices, and has attracted more and more attention.
  • the present invention aims to solve at least one of the technical problems existing in the prior art and provide a display substrate and a display device.
  • an embodiment of the present disclosure provides a display substrate, which includes a base, a plurality of gate lines extending in a first direction and a plurality of data lines extending in a second direction, and a plurality of Pixel unit, the first direction and the second direction intersect;
  • Each of the plurality of pixel units includes a plurality of sub-pixels, each of the plurality of sub-pixels includes a pixel circuit; the pixel circuit includes at least a switching transistor, a driving transistor, a sensing transistor, and a storage capacitor; in,
  • the switch transistor, the drive transistor, and the sensing transistor are all located on the same side of the storage capacitor; the switch transistor is located on the same side of the storage capacitor connected to the gate line and the The crossing position of the data line, and the switch transistor and the sensing transistor are arranged adjacently in the first direction, and the driving transistor is arranged adjacently in the second direction.
  • the plurality of pixel units are arranged in multiple columns along the first direction and in multiple rows along the second direction; the multiple sub-pixels in each pixel unit are arranged in two rows along the second direction , The sub-pixels in each row are arranged along the first direction;
  • the gates of the switching transistors of the pixel circuits are connected to the same gate line;
  • the switching transistors of the pixel circuits with the same light-emitting color of the organic electroluminescent diodes are connected to the same data line.
  • the gate line corresponding to each row of pixel units is located between the two rows of sub-pixels of the row of pixel units.
  • the gates of the switching transistors of the sub-pixels in one row are connected to the gate lines through the first gate connection line, and the sub-pixels in the other row
  • the gate of the switching transistor is connected to the gate line through a second gate connection line;
  • the first gate connection line is arranged in the same layer and the same material as the gate line, and the second gate connection line is the same as the data line.
  • Layer arrangement and the same material; a first insulating layer is arranged between the gate line and the layer where the data line is located; connect.
  • the data line connected to the pixel unit of each column is located between the two columns of the sub-pixels of the pixel unit of the column.
  • the drain of the driving transistor of each pixel circuit in each column of the pixel unit is connected to a first power line, and the first power line is located between the two columns of the sub-pixels of the pixel unit corresponding to it. between.
  • the first power line includes a first sub-power line and a second sub-power line that are electrically connected; the first sub-power line and the gate line are arranged in the same layer and have the same material; the second sub-power line is connected to the data
  • the lines are set on the same layer and have the same material.
  • control signal lines are further included, and the gates of the sensing transistors in the pixel units located in the same row are connected to the same control signal line.
  • control signal line connected to the pixel unit of each row is located between the two rows of sub-pixels of the pixel unit.
  • control signal line and the gate line are arranged in the same layer and made of the same material; for the two rows of the sub-pixels of the pixel unit in each row, the gates of the sensing-off transistors of one row of the sub-pixels pass through
  • the first control signal connection line is connected to the control signal line, and the gates of the sensing transistors of the sub-pixels in the other row are connected to the control signal through a second control signal connection line;
  • the first control signal connection line is connected to The control signal line is arranged in the same layer and the same material, the second control signal connection line is arranged in the same layer and the same material as the data line; a first control signal connection line is arranged between the gate line and the layer where the data line is located.
  • An insulating layer, the second control signal connecting line is connected to the control signal line through a via hole penetrating the first insulating layer.
  • the display substrate further includes a plurality of sensing signal lines, and the drains of the sensing transistors in the pixel units located in the same column are connected to the same sensing line.
  • the sensing line and the data line are arranged in the same layer and have the same material.
  • each of the pixel units includes two rows of the sub-pixels arranged along the first direction and two rows of the sub-pixels arranged along the second row direction.
  • the light-emitting colors of the organic electroluminescent diodes of the sub-pixels in each pixel unit are red, green, blue, and white, respectively.
  • it further includes a plurality of light-transmitting units; the light-transmitting units and the pixel units are alternately arranged in the first direction or the second direction.
  • the switching transistor, the driving transistor, and the sensing transistor all include a source electrode and a drain electrode arranged on the semiconductor active layer, the gate electrode, and the same layer in sequence;
  • a light shielding layer and a buffer layer are sequentially arranged between the substrates;
  • a gate insulating layer is arranged between the layer where the gate is located and the layer where the semiconductor active layer is located; the layer where the gate is located is connected to the source
  • An interlayer insulating layer is arranged between the electrode and the layer where the drain electrode is located.
  • the storage capacitor includes a first electrode and a second electrode; the second electrode includes a first sub-plate and a second sub-plate; the first electrode and the semiconductor active layer are arranged in the same layer and made of material The same; the light-shielding layer is used as the first sub-plate; the second sub-plate and the source of the driving transistor are arranged in the same layer and have the same material; the first sub-plate and the second The sub-electrodes are connected by via holes penetrating the buffer layer, the gate insulating layer, and the interlayer insulating layer.
  • the gate of the driving transistor in the pixel circuit and the source of the switching transistor are connected through a first wiring; the source of the driving transistor and the source of the sensing transistor are connected through a second wiring ;
  • the first wiring and the second wiring are both arranged in the same layer and made of the same material as the source of the driving transistor.
  • the auxiliary cathode includes a first substructure and a second substructure sequentially arranged on the substrate; the first substructure and the gate of the driving transistor are arranged in the same layer and have the same material The second substructure and the source of the driving transistor are arranged in the same layer and have the same material, and the first substructure and the second substructure are connected by a via hole penetrating the interlayer insulating layer.
  • the auxiliary cathodes extend along the second direction, the auxiliary cathodes are arranged on one side of the sub-pixels in each row, and the auxiliary cathodes in adjacent rows are separated by one row of the sub-pixels.
  • a passivation layer, a transfer electrode, and a planarization layer are sequentially arranged; the transfer electrode passes through the The via hole of the passivation layer is connected to the drain of the driving transistor, and the anode of the organic electroluminescent diode is connected to the switching electrode through the via hole penetrating the planarization layer.
  • the organic electroluminescence diode is a top emission type organic electroluminescence diode.
  • embodiments of the present disclosure provide a display device, which includes the above-mentioned display substrate.
  • Fig. 1 is an exemplary pixel arrangement diagram of a display substrate
  • Fig. 2 is an exemplary pixel circuit diagram
  • FIG. 3 is a pixel layout of a sub-pixel of a display substrate according to an embodiment of the present invention.
  • FIG. 4 is a schematic diagram of a pixel arrangement of a display substrate according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of a pixel circuit of a pixel unit according to an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of another pixel arrangement of a display substrate according to an embodiment of the present invention.
  • FIG. 7 is a cross-sectional view of a driving transistor and an organic electroluminescent diode of a display substrate according to an embodiment of the present invention.
  • FIG 8 is another cross-sectional view of the driving transistor and the organic electroluminescent diode of the display substrate according to the embodiment of the present invention.
  • FIG. 9 is a layout of a pixel unit of a display substrate according to an embodiment of the present invention.
  • FIG. 10 is the layout of the layer where the light-shielding layer in FIG. 9 is located;
  • FIG. 11 is a layout of the layer where the semiconductor active layer in FIG. 9 is located;
  • FIG. 12 is a layout of the layer where the gate is located in FIG. 9;
  • FIG. 13 is the layout of the layer where the source and drain electrodes in FIG. 9 are located.
  • FIG. 1 illustrates the structure of a display substrate.
  • the display substrate includes a base 10 on which a plurality of gate lines 1, a plurality of data lines 7, a plurality of control signal lines 13, and a plurality of sensing lines 2 are arranged on the base 10.
  • a plurality of pixel units A wherein the gate line 1 and the control signal line 13 extend in a first direction, the data line 7 and the sensing line 2 extend in a second direction, and the first direction and the second direction intersect, that is, the gate line 1 And data line 7 cross set.
  • Each pixel unit A includes a plurality of sub-pixels a located at the intersection of the gate line 1 and the data line 7.
  • each pixel unit A includes a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B. Wherein, each sub-pixel a is provided with a pixel circuit.
  • the pixel circuit includes a switching transistor 4, a driving transistor 5, a sensing transistor 6, a storage capacitor 3, and an organic electroluminescent diode OLED; wherein the gate 42 of the switching transistor 4 is connected to the gate Line 1, the source 42 of the switching transistor 4 is connected to the gate 52 of the driving transistor 5, and the drain 43 of the switching transistor 4 is connected to the data line 7; the gate 52 of the driving transistor 5 is connected to the first electrode of the storage capacitor 3, and the driving transistor 5
  • the source 53 of the driving transistor 5 is connected to the second electrode 32 of the storage capacitor 3, the source 63 of the sensing transistor 6 and the anode 401 of the organic electroluminescent diode OLED, and the drain 54 of the driving transistor 5 is connected to the first power line 8;
  • the gate 62 of 6 is connected to the control signal line 13, and the drain 64 of the sensing transistor 6 is connected to the sensing signal; the cathode 403 of the organic electroluminescent diode OLED is connected to the second power line (or ground).
  • the pixel circuit When only external compensation is required for the pixel circuit, the pixel circuit includes at least the following two stages in the working process: the display stage (including the data voltage Vdata writing process) and the sensing stage (including the current reading process).
  • Display stage Write a high level signal to the gate line 1, the switch transistor 4 is turned on, the data voltage Vdata in the data line 7 is written to the gate of the driving transistor, and the storage capacitor 3 is charged, which is driven by the driving transistor 5.
  • the organic electroluminescent diode OLED emits light.
  • Sensing phase Write high-level signals to the gate line 1 and the signal control line, the sensing body transistor and the driving transistor are turned on, and a test voltage Vsense is written to the gate of the driving transistor through the data line 7, and passes The sensing transistor 6 reads the electrical signal at the source 53 of the drive transistor 5 and outputs it through sensing, so that the external compensation circuit compensates the mobility of the drive transistor 5 through the output electrical signal.
  • the gate line 1 and the signal control line are usually arranged in parallel, and they are located on the upper and lower sides of the sub-pixel a.
  • the switching transistor 4 is the crossing position of the gate line 1 and the data line 7 to facilitate the switching transistor 4
  • the gate 42 is connected to the gate line 1, and the drain is connected to the data line 7;
  • the sensing transistor 6 is located at the intersection of the control signal line 13 and the sensing line 2;
  • the driving transistor 5 and the switching transistor 4 are along the first direction (gate line 1) are arranged side by side, and the storage capacitor 3 is located in the middle area of the sub-pixel a.
  • the following technical solutions are provided in the embodiment of the present invention.
  • the first direction and the second direction are perpendicular to each other as an example for description.
  • the first direction is the row direction
  • the second direction is the column direction.
  • the perpendicularity of the first direction and the second direction does not constitute a limitation to the embodiment of the present disclosure, as long as the first direction and the second direction intersect.
  • each pixel unit A is arranged in an array as an example for description.
  • each pixel unit A can also be arranged according to a certain rule. .
  • an embodiment of the present disclosure provides a display substrate.
  • the display substrate includes a base 10, multiple rows of gate lines 1 and multiple columns of data lines 7 on the base 10, and arrays arranged in an array.
  • Multiple pixel units A Each pixel unit A includes a plurality of sub-pixels a, and each sub-pixel a includes a pixel circuit; the pixel circuit includes at least a switching transistor 4, a driving transistor 5, a sensing transistor 6, and a storage capacitor 3 (for example, as shown in FIG.
  • the pixel circuit shown wherein, for each pixel circuit, the switching transistor 4, the driving transistor 5, and the sensing transistor 6 are all located on the same side of the storage capacitor 3; the switching transistor 4 is located on the gate line 1 and the The intersection of the data line 7 and the switching transistor 4 and the sensing transistor 6 are arranged adjacently in the row direction, and the driving transistor 5 is arranged adjacently in the column direction.
  • the switching transistor 4, the driving transistor 5, the sensing transistor 6, and the storage capacitor 3 in the pixel circuit of each sub-pixel a are reasonably arranged so that the switching transistor in each pixel circuit 4.
  • the driving transistor 5 and the sensing transistor 6 are all located on the same side of the storage capacitor 3, and the switching transistor 4 and the sensing transistor 6 are arranged adjacently in the row direction, and the driving transistor 5 is arranged adjacently in the column direction, so as to be effective.
  • the use of the row space of each sub-pixel a saves the column-direction space of each sub-pixel a, thereby effectively reducing the space occupied by each sub-pixel a to ensure that the pixel circuit layout space is limited, greatly improving The resolution of the display panel to which the display substrate of the embodiment of the present disclosure is applied.
  • the thin film transistors (switching transistor 4, driving transistor 5, and sensing transistor 6) in each sub-pixel a are collectively arranged, that is, arranged in the storage capacitor 3 On the same side, it effectively solves the grating effect in related technologies.
  • each pixel unit A includes two rows of sub-pixels a, and the pixel circuits in the two rows of sub-pixels a are controlled by the same gate line 1, located in the same column of sub-pixels a, and have organic electroluminescent diodes. Pixel circuits with the same light-emitting color of the OLED are provided with data voltage signals from the same data line 7.
  • the gate 42 of the switching transistor 4 in each pixel circuit is connected to the same gate line 1.
  • the organic electroluminescent diode OLED emits light in the same pixel circuit
  • the drain 43 of the switching transistor 4 is connected to the same data line 7.
  • each pixel unit A includes two rows, two columns, and four sub-pixels a, and the light-emitting colors of the organic electroluminescent diodes OLED in the pixel circuits of the four sub-pixels a are all different.
  • the gate 42 of the switching transistor 4 of the pixel circuit in the four sub-pixels a in the pixel unit A in the same row is connected to a gate line 1, and is connected to the four sub-pixels in the pixel unit A in the same column.
  • the drain 43 of the switching transistor 4 of the pixel circuit in a is respectively connected to the corresponding data line 7, that is, the four sub-pixels located in a row of pixel units A are controlled by a gate line 1, and located in four sub-pixels of a column of pixel units A.
  • the four sub-pixels a of each pixel unit A are provided with data voltage signals by the four data lines 7.
  • the gate line 1 used to control the two rows of sub-pixels a of the pixel unit A is located between the two rows of sub-pixels a, so as to facilitate
  • the gate 42 of the switching transistor 4 of the pixel circuit in the two rows of sub-pixels a is connected to the gate line 1, and the gate 42 of the switching transistor 4 and the gate line 1 connected to it can be prepared in a single process during preparation. It is a one-piece structure, so the preparation process is simple and easy to realize.
  • the gate 42 of the switching transistor 4 of one row of sub-pixel a is connected to the gate through the first gate connecting line 11
  • the gate 42 of the switching transistor 4 of the other row of sub-pixel a is connected to the gate line 1 through the second gate connection line 12;
  • the first gate connection line 11 and the gate line 1 are arranged in the same layer and have the same material, and the second gate
  • the connecting line 12 and the data line 7 are arranged in the same layer and made of the same material; a first insulating layer is arranged between the layer where the gate line 1 and the data line 7 are located, and the second gate connecting line 12 passes through the via hole penetrating the first insulating layer and the gate. Line 1 connection.
  • the switching transistor 4, the driving transistor 5, and the sensing transistor 6 are all top-gate thin film transistors as an example for description. Among them, the respective film layers of the switching transistor 4, the driving transistor 5, and the sensing transistor 6 are arranged in the same layer.
  • the driving transistor 5 includes a semiconductor active layer 51, a gate insulating layer 302, a gate 52, an interlayer insulating layer 303, a source electrode 53 and a drain electrode 54 sequentially disposed on the substrate 10.
  • the above-mentioned gate line 1 is usually arranged in the same layer as the gate 52 of the driving transistor 5, and the data line 7 is usually arranged in the same layer as the source 53 and drain 54 of the driving transistor 5.
  • the first insulating layer in between refers to the two-layer structure of the gate insulating layer 302 and the interlayer insulating layer 303, and the vias that penetrate the first insulating layer are the vias that penetrate the gate insulating layer 302 and the interlayer insulating layer.
  • the 303 via hole consists of a sleeved via hole.
  • the data line 7 used to provide data voltage signals for the two columns of sub-pixels a of the pixel unit A is located between the two columns of sub-pixels a, In this way, the drains 43 of the switching transistors 4 of the two columns of sub-pixels a are connected, and the drain 43 of the switching transistor 4 and the data line 7 can be prepared in a single process during the preparation, and the drain of the switching transistor 4 can be connected. 43 and the data line 7 connected therewith are prepared into an integrated structure, so that the preparation process is simple and easy to implement.
  • the drain 54 of the driving transistor 5 of the pixel circuit of each sub-pixel a in each column of pixel unit A is connected to the first power supply line 8, and when each pixel unit A includes two columns of sub-pixel a, The first power line 8 is located between the two rows of sub-pixels a of the pixel unit A corresponding thereto.
  • the reason for this arrangement is that the driving transistor 5 and the switching transistor 4 are arranged side by side in the column direction, so that the connection between the first power line 8 and the drain 54 of the driving transistor 5 is more convenient.
  • the first power line 8 may include a first sub-power line 81 and a second sub-power line 82 electrically connected; wherein the first sub-power line and the gate line 1 are arranged in the same layer and have the same material; and the second sub-power line 82 and The data line 7 is arranged in the same layer and made of the same material, and the data line 7 is usually arranged in the same layer as the drain electrode 54 of the driving transistor 5, and the same material is used. Therefore, the second sub-power supply line 82 can be the same as the drain electrode of the driving transistor 5. 54 are arranged in the same layer and have the same material; therefore, the first power line 8 and the drain 54 of the driving transistor 5 can be prepared by a patterning process, so that the preparation process is simple and easy to implement.
  • the first power line 8 and the data line 7 corresponding to each column of pixel unit A are located between the two columns of sub-pixel a.
  • the extension directions of the first power line 8 and the data line 7 are set to be parallel, so that the wiring space of the first power line 8 and the data line 7 can be reduced, and the pixel resolution can be improved.
  • the gate 62 of the sensing transistor 6 of each pixel circuit is connected to the corresponding control signal line 13.
  • the gate 62 of the sensing transistor 6 in each pixel circuit in the pixel unit A in the same row may be connected to the same control signal line 13.
  • the control signal line 13 for controlling the row of pixel units A is located between the two rows of sub-pixels a.
  • the control signal line 13 can also be set parallel to the extending direction of the gate line 1. In this way, when the gate line 1 is located between the two rows of sub-pixels a connected to it, the gate line 1 and the control signal can be reduced.
  • the wiring space of the line 13 improves the pixel resolution.
  • the gate line 1 and the control signal line 13 can be arranged in the same layer, and the same material can be used, so that the two can be prepared by one patterning process, which can simplify the process steps and reduce the process cost.
  • control signal line 13 and the gate line 1 are arranged in the same layer and made of the same material; for the two rows of sub-pixels a of each row of pixel units A, the gate 62 of the sensing off transistor 6 of one row of the sub-pixel A is
  • the first control signal connection line 14 is connected to the control signal line 13, and the gate 62 of the sensing transistor 6 of the other row of sub-pixel a is connected to the control signal connection 13 through the second control signal connection line 15; the first control signal connection line 14
  • the second control signal connection line 15 and the data line 7 are provided in the same layer and the same material; a first insulating layer is provided between the layer where the gate line 1 and the data line 7 are located.
  • the two control signal connection lines are connected to the control signal line through a via hole penetrating the first insulating layer.
  • the explanation of the first insulating layer is the same as the above-mentioned first insulating layer, and the description will not be repeated here.
  • the gate 42 of the switching transistor 4 in the first row of sub-pixel a is connected to the gate line 1 through the first gate connection line 12, then the sensing transistor in the second row of sub-pixel a
  • the gate 62 of 6 is connected to the control signal line 13 through the first control signal connection 14. In this way, it is avoided that the gate line 1 and the control signal line 13 are arranged in the same layer, and the problem of cross wiring between each connection line is avoided.
  • the gate line 1, the control signal line 13, and the switching transistor 4 and the driving transistor 5 of a in each sub-pixel in each pixel unit A are connected.
  • the sensing transistors 6 are centrally arranged (located in the middle area of the two rows of sub-pixels a), which reduces the area of the display area of the display panel and increases the area of the transparent area, thereby eliminating the grating effect.
  • the display substrate further includes a plurality of sensing signal lines, and the drain 64 of the sensing transistor 6 of each pixel circuit in the pixel unit A in the same column is connected to the same sensing line 2. Further, each sensing line 2 is located in the same column of the corresponding pixel unit A, that is, there is a row of pixel units A between adjacent sensing lines 2. In this way, it can be avoided that the sensing lines 2 are arranged in a concentrated manner to cause the coupling of the signals between the sensing lines 2, resulting in the inaccuracy of the transmitted electrical signals.
  • each pixel unit A adopts four sub-pixels a arranged in a square form, that is, each pixel unit A includes two rows, two columns, and four sub-pixels a, which are located in one pixel unit at this time.
  • the four sub-pixels a in A share a gate line 1. If the light-emitting colors of the four organic electroluminescent diodes OLED in the four sub-pixels a are different, the four sub-pixels a are connected to the four data lines 7 respectively.
  • the gate line 1, the data line 7, the control signal line 13, the first power line 8, and the sensing line 2 of the display substrate can all adopt any of the above-mentioned arrangements. The description will not be repeated here.
  • the light-emitting color of the organic electroluminescent diode OLED of the sub-pixel a in each pixel unit A is red (red, R), green (green, G), and blue (blue).
  • each pixel unit A is not limited to only including four sub-pixels a, for example, each pixel unit A includes three sub-pixels a, such as red, green, and blue sub-pixel a, this sub-pixel a
  • the pixels a may be arranged in a fringe shape.
  • the display substrate in the embodiment of the present disclosure can be applied to a transparent display.
  • the display substrate not only includes the above structure but also includes a light-transmitting unit Q, where the light-transmitting unit Q is connected to the pixel Unit A is set alternately.
  • the pixel unit A displays according to the picture to be displayed, and the light-transmitting unit Q, as the name implies, can transmit light at the position where the light-transmitting unit Q is located. Observe the scene behind the display panel (the side facing away from the display surface).
  • each sub-pixel a obtains a scan signal through the electrically connected gate line 1 and a data voltage signal through the data line 7. Under the action of the scan signal and the data voltage signal, the sub-pixel a is driven The organic electroluminescent diode OLED emits light.
  • the sub-pixels a with the same light-emitting color of the organic electroluminescent diode OLED are connected to the same data line 7.
  • the data line 7 passes through the light-transmitting unit Q and needs to be shielded by a black matrix (not shown in the figure).
  • the switching transistor 4, the driving transistor 5, and the sensing transistor 6 in the display substrate all include a source and a drain arranged on the semiconductor active layer, the gate, and the same layer;
  • a light-shielding layer and a buffer layer 301 are arranged between the layer and the substrate 10;
  • a gate insulating layer 302 is arranged between the layer where the gate is located and the layer where the semiconductor active layer is located; the layer where the gate is located is connected to the source and drain
  • An interlayer insulating layer 303 is provided between the layers.
  • the switching transistor 4, the driving transistor 5, and the sensing transistor 6 in the embodiments of the present disclosure may all be oxide thin film transistors, or may be polysilicon or amorphous silicon thin film transistors.
  • each transistor is An oxide transistor will be described as an example.
  • the switching transistor 4, the driving transistor 5, and the sensing transistor 6 may all be top-gate transistors or bottom-gate transistors.
  • the transistors in the embodiments of the present disclosure are all top-gate transistors as an example Be explained.
  • the switching transistor 4, the driving transistor 5, and the sensing transistor 6 all include a semiconductor active layer, a gate, and a source and a drain arranged in the same layer in sequence, the following is a description of each of the driving transistor 5 and the organic electroluminescent diode OLED.
  • the layer structure describes each film layer on the display substrate.
  • the driving transistor 5 is a top-gate oxide thin film transistor to prevent light from affecting the electron mobility of the semiconductor active layer, a light shielding layer and a buffer layer 301 are sequentially formed on the substrate 10 before forming the transistor.
  • the driving transistor 5 may be a top gate type, and the driving transistor 5 may include a semiconductor active layer, a gate insulating layer 302, a gate, an interlayer insulating layer 303, a source, and Drain.
  • the source and drain are respectively located on opposite sides of the gate, and the source and drain can respectively pass through via holes (for example, metal vias) to respectively contact the source contact regions and drain regions on opposite sides of the active layer. Polar contact area contact.
  • the driving transistor 5 may also be a bottom gate type.
  • the storage capacitor 3 includes a first electrode and a second electrode 32; the second electrode 32 includes a first sub-plate 311 and a second sub-plate 312; among them, the first electrode, the first sub-plate 311 and the second sub-plate
  • the orthographic projection of the electrode plate 312 on the substrate 10 at least partially overlaps.
  • the first electrode and the semiconductor active layer are arranged in the same layer and have the same material; the first sub-plate 311 is arranged in the same layer and the light-shielding layer and the material is the same; the second sub-plate 312 is in the same layer as the source 53 of the driving transistor 5 The arrangement and the material are the same; the first sub-plate 311 and the second sub-plate 312 are connected by a via hole penetrating the buffer layer 301, the gate insulating layer 302, and the interlayer insulating layer 303.
  • the first via hole includes a via hole penetrating the buffer layer 301, a via hole penetrating the gate insulating layer 302, and a via hole penetrating the interlayer insulating layer 303, and these three via holes are sleeved together.
  • the materials of the gate and the light shielding layer may include metal materials or alloy materials, such as molybdenum, aluminum, and titanium.
  • the source and drain electrodes may include metal materials or alloy materials, such as a metal single-layer or multi-layer structure formed of molybdenum, aluminum, and titanium.
  • the multi-layer structure is a multi-metal laminated layer, such as titanium, aluminum, and titanium. Layer metal stack (Al/Ti/Al), etc.
  • the material of the semiconductor active layer may include an oxide semiconductor material, such as indium gallium zinc oxide, indium gallium tin oxide, and the like.
  • a planarization layer 304 is provided on the side of the driving transistor 5 away from the substrate 10.
  • the planarization layer 304 is usually made of organic materials, such as photoresist, acrylic-based polymer, silicon-based polymer and other materials.
  • the organic electroluminescent diode OLED may include an anode 401 and a pixel defining layer 306 of the organic electroluminescent diode OLED sequentially formed on the planarization layer 304. It should be understood that the organic electroluminescent diode OLED The light-emitting layer 402 and the cathode 403 may also be included.
  • the first anode of the organic electroluminescent diode OLED can be electrically connected to the source 53 of the driving transistor 5 through the via hole penetrating the planarization layer 304, and the anode can be ITO (Indium Tin Oxide). ), indium zinc oxide (IZO), zinc oxide (ZnO) and other materials; the pixel defining layer 306 can cover the planarization layer 304, the pixel defining layer 306 can be made of organic materials, such as photoresist, etc.
  • the pixel defining layer 306 may have an accommodating part exposing the first electrode; the light-emitting layer is located in the accommodating part and is formed on the anode.
  • the light-emitting layer may include small molecular organic materials or polymer molecular organic materials, and may be fluorescent light-emitting materials. Or phosphorescent light-emitting materials, which can emit red light, green light, blue light, or white light, etc.; and, according to different actual needs, in different examples, the light-emitting layer may further include an electron injection layer, an electron transport layer, and a hole Functional layers such as injection layer and hole transport layer; the cathode covers the light-emitting layer, and the cathode can be made of metal materials such as lithium (Li), aluminum (Al), magnesium (Mg), and silver (Ag).
  • metal materials such as lithium (Li), aluminum (Al), magnesium (Mg), and silver (Ag).
  • the anode 401, the light-emitting layer 402 and the cathode 403 can constitute an organic electroluminescent diode OLED.
  • the display substrate includes organic electroluminescent diodes OLED arranged in an array.
  • the anode 401 of each organic electroluminescent diode OLED is independent of each other, and the cathode 403 of each organic electroluminescent diode OLED can be connected on the entire surface; that is, the cathode is a whole surface structure arranged on the display substrate, which is Common electrode for multiple organic electroluminescent diodes OLED.
  • the anode 401 of the organic electroluminescent diode OLED can also be electrically connected to the source 53 of the driving transistor 5 through the switching electrode 501.
  • a passivation (PVX) layer may also be formed between the planarization layer 304 and the layer where the source electrode 53 and the drain electrode of the interlayer driving transistor 5 are located.
  • the passivation layer 305 can be formed of materials such as silicon oxide, silicon nitride, or silicon oxynitride; the passivation layer 305 covers the layer where the source and drain electrodes are located; and the transfer electrode 501 is formed on the planarization layer 304 and the passivation layer 305 Between the passivation layer 305 and the source 53 of the driving transistor 5 through vias (such as metal vias) in turn; and the first pole can pass through the vias (such as metal vias) on the planarization layer 304 The hole) is electrically connected to the transfer electrode 501, thereby completing the connection between the anode 401 of the organic electroluminescent diode OLED and the source 53 of the driving transistor 5.
  • vias such as metal vias
  • the organic electroluminescent diode OLED may also include an encapsulation layer and other structures, where the encapsulation layer includes a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer that are stacked in sequence.
  • the first encapsulation layer and the third encapsulation layer are used to prevent water and oxygen from entering the light-emitting layer;
  • the first encapsulation layer and the third encapsulation layer can be made of inorganic materials such as silicon nitride and silicon oxide.
  • the second encapsulation layer is used to achieve planarization to facilitate the production of the third encapsulation film layer.
  • the second encapsulation layer can be made of acrylic-based polymer, silicon-based polymer, or other materials.
  • the gate 52 of the driving transistor 5 and the source 42 of the switching transistor 4 in the pixel circuit are connected through the first wiring 201; the source 53 of the driving transistor 5 and the source 63 of the sensing transistor 6 pass through The second wiring 202 is connected; the first wiring 201 and the second wiring 202 are arranged in the same layer as the source 53 of the driving transistor 5 and have the same material.
  • the data line 7, the sensing line 2, the first power line 8 and other structures can also be arranged in the same layer as the source 53 and the drain of the driving transistor 5. In this way, the formed display substrate can be made lighter and thinner. .
  • the cathodes 403 of the plurality of organic electroluminescent diodes OLED in the display substrate are of a whole-surface structure, the input signal of the organic electroluminescent diode OLED farther from the signal input terminal has a larger voltage drop.
  • the display substrate of the embodiment of the present disclosure is further provided with an auxiliary cathode 9;
  • the auxiliary cathode 9 includes a first substructure 91 and a second substructure 92 sequentially arranged on the base 10;
  • the first substructure 91 and The gate 52 of the driving transistor 5 is arranged in the same layer and the same material, the second sub-structure 92 and the source 53 of the driving transistor 5 are arranged in the same layer and the same material, the first sub-structure 91 and the second sub-structure 92 pass through the interlayer The second via connection.
  • the number of the second via holes is multiple, and the multiple second via holes are arranged in a row along the extension direction of the auxiliary cathode 9. .
  • auxiliary cathodes 9 extend along the column direction, an auxiliary cathode 9 is provided on one side of each column of sub-pixels a, and adjacent columns of auxiliary cathodes 9 are separated by a column of sub-pixels a.
  • the organic electroluminescent diode OLED is a top-emitting organic electroluminescent diode OLED.
  • the structure of the display substrate will be described in conjunction with the following display substrate method.
  • the following method is only an example structure of the display substrate. It does not constitute a limitation to the protection scope of the embodiments of the present disclosure.
  • the pixel unit A in the display substrate includes four sub-pixels a arranged in a square form, and the connected data lines corresponding to the four sub-pixels are respectively 7(R), 7(G), 7(B). ) And 7(W) indicate that the method for preparing the display substrate according to the embodiment of the present disclosure with reference to FIGS. 5 and 9-13 specifically includes the following steps.
  • the substrate 10 is a transparent substrate 10, such as a glass substrate 10 and the like.
  • the light shielding layer may be used as the first sub-plate 311 of the first electrode of the storage capacitor 3.
  • each light-shielding layer encircles a small box, denoted by 101, these four positions are the positions where the light-shielding layer is connected to the second sub-plate 312 of the first electrode of the storage capacitor 3.
  • the insulating layer located between the light-shielding layer and the layer where the second sub-plate 312 is located will form a via hole in the corresponding small box 101.
  • the three small boxes circled on the sensing connection line are used to indicate 102a, 102b, and 102c, respectively, where the positions of 102a and 102b are the drains of the sensing transistors 6 located in the upper and lower sub-pixels a.
  • the position where the pole 64 is connected to the connecting line of the first sensing line 2, and the position 102c is the position where the first sensing connecting line 21 is connected to the sensing line 2;
  • the insulating layer between the drain 64 of the transistor 6 and the sensing line 2 is provided with via holes at positions 102a, 102b, and 102c.
  • the position of the small square on the second electrode 32 of the storage capacitor 3 shown in FIG. 11 is indicated by 103, which is the second electrode 32 of the storage capacitor 3 and the driving transistor in the sub-pixel a.
  • the gate 52 of 5 is connected to the position, so the insulating layer between the gate 52 of the driving transistor 5 and the second electrode 32 of the storage capacitor 3 is formed with a via hole at the position 103, so that the second electrode 32 of the storage capacitor 3 and The gate 52 of the driving transistor 5 is connected.
  • the two small squares on the active layer of the switching transistor 4 in each sub-pixel a are 104a and 104b, and the two small squares on the active layer of the driving transistor 5 are 104c and 104d, respectively.
  • the sensing transistor The two small boxes on the active layer of 6 are 104e and 104f, respectively; 104a and 104b respectively correspond to the position where the source 42 and drain of the switching transistor 4 are connected to its semiconductor active layer; 104c and 104d correspond to the driving transistor 5, respectively The position where the source 53 and drain of the sensor are connected to its semiconductor active layer; 104e and 104f respectively correspond to the position where the source 63 and drain of the sensing transistor 6 are connected to its semiconductor active layer; 5.
  • the insulating layer between the layer where the semiconductor active layer 61 of the sensing transistor 6 is located and the layer where the source and drain are located has via holes formed at positions corresponding to 104a, 104b, 104c, 104d, 104e, and 104f.
  • a gate insulating layer 302 is formed, and the gate insulating layer 302 corresponds to 101, 102a, 102b, 102c, Via holes are formed at positions 103, 104a, 104b, 104c, 104d, 104e, and 104f.
  • the gate 62 of the switching transistor 4 On the substrate 10 on which the gate insulating layer 302 is formed, the gate 62 of the switching transistor 4, the driving transistor 5, the sensing transistor 6, the gate line 1, the signal control line, the first gate connecting line 11, the first The control signal connection line 14, the first sub-power supply line 81 of the first power supply line 8, the power supply connection line, the first sub-structure 91 of the auxiliary cathode 9, and the data connection line 71; wherein the gate 52 of each drive transistor 5 passes The via hole at position 103 is connected to the second electrode 32 of the storage capacitor 3; the gate 42 of the switching transistor 4 of the first row of sub-pixel a in the pixel unit A is connected to the gate line 1 through the first gate connection line 11, and the second The gate 62 of the sensing transistor 6 of the row sub-pixel a is connected to the control signal line 13 through the first control signal connection line 14; two sub-pixels a located in the same row correspond to a first sub-power supply line 81, and these two The sub-pixels
  • the gate 42 of the switching transistor 4 of the first row of sub-pixel a in the pixel unit A, the first gate connection line 11 and the gate line 1 may be an integral structure; the measurement in the second row of sub-pixel a
  • the gate of the transistor, the first control signal connection line 14 and the control signal line 13 may be an integral structure.
  • the small box on the first structure of the auxiliary cathode 9 of each sub-pixel a is represented by 105.
  • the position of 105 is the connection position of the first substructure 91 and the second substructure 92 of the auxiliary cathode 9, so A via hole is provided at a position corresponding to 105 in the insulating layer between the first substructure 91 and the second substructure 92 of the auxiliary cathode 9.
  • Each first sub power line 81 and the small boxes on the power connection line are represented by 106a and 106b, respectively; where 106a is located between the first sub power line 81 of the first power line 8 and the second sub power line 82 Connection position; the position of 106b is the connection position of the power connection line and the source 53 of the driving transistor 5, so the insulating layer between the first sub-power line 81 and the power connection line corresponds to 106a and 106b formed with vias .
  • the small squares on the gate line 1 are denoted by 107a and 107b, respectively, and the small squares on the gate 42 of the switching transistor 4 of the sub-pixel a in the second row are denoted by 107c and 107d, respectively; where the positions of 107a and 107c are The gate 42 of the switching transistor 4 of the sub-pixel a in the second row and the first column of the pixel unit A is connected to the gate line 1 through the second gate connection line 12; the positions of 107b and 107d are the positions of the pixel unit A.
  • the gate 42 of the switching transistor 4 of the sub-pixel a in the second row and the second column is connected to the gate line 1 through the second gate connecting line 12, so the gate 42 of the switching transistor 4 and the gate line 1 are located in the layer and the second Via holes are formed at positions corresponding to 107a, 107b, 107c, and 107d in the insulating layer between the layers where the gate connection line 12 is located.
  • the small square on the gate 52 of each driving transistor 5 is used to indicate 108, and the position of 108 is the connection position between the gate 52 of the driving transistor 5 and the source 42 of the switching transistor 4 in each sub-pixel a, so A via hole is formed at a position corresponding to 108 in the insulating layer between the gate 52 of the driving transistor 5 and the layer where the source 42 of the switching transistor 4 is located.
  • the small squares on the control signal line 13 are denoted by 109a and 109b, respectively; the small squares on the gate 62 of the sensing transistor 6 of the first row of sub-pixel a in the pixel unit A are denoted by 109c and 109d, respectively;
  • the positions of 109a and 109c are the connection positions of the gate 62 of the sensing transistor 6 of the sub-pixel a in the first row and the first column of the pixel unit A through the second sensing connection line 22 and the control signal line 13;
  • the position is the connection position of the gate 62 of the sensing transistor 6 of the sub-pixel a in the first row and the second column of the pixel unit A through the second sensing connection line 22 and the control signal line 13, so it is located at the gate of the sensing transistor 6
  • the insulating layer between the electrode 62 and the layer where the control signal line 13 is located and the layer where the second sensing connection line 22 is located has via holes formed at positions corresponding to 109a, 109b,
  • the data connection line 71 in the second row of sub-pixel a in the pixel unit A is to prevent the four data lines 7 located between the two columns of sub-pixel a from being short-circuited when they are connected. It should be understood that the two data connection lines 71 in the pixel unit A can be respectively arranged in any two of the four sub-pixels a. In the embodiment of the present disclosure, the data connection lines 71 are respectively located in the first pixel unit A. Take the second row of sub-pixel a as an example.
  • the two small boxes at both ends of the data connection line 71 in the second row and first column of sub-pixel a in the pixel unit A are denoted by 110a and 110b respectively, and the data connection line in the second row and second column of sub-pixel a
  • the two small boxes at both ends of 71 are denoted by 110c and 110d respectively; among them, 110a and 110c are the connection positions of the drain 43 of the switching transistor 4 in each sub-pixel a and the data connection line 71; 110b and 110d are respectively
  • the connection position of the data line 7 connected to the sub-pixel a and the data connection line 71, so the insulating layer located between the layer where the data connection line 71 is located and the drain 43 of the switching transistor 4 and the layer where the data line 7 is located corresponds to 110a, 110b, Via holes are formed at positions 110c and 110d.
  • the gate 62 of the switching transistor 4, the driving transistor 5, the sensing transistor 6, the gate line 1, the signal control line, the first gate connection line 11, the first control signal connection line 14, and the first power supply line 8 are formed.
  • An interlayer insulating layer 303 is formed on the first sub-power line 81, the power connection line, the first substructure 91 of the auxiliary cathode 9, and the data connection line 71 on the substrate 10, and the interlayer insulating layer 303 corresponds to 101, 102a, 102b, 102c, 104a, 104b, 104c, 104d, 104e, 104f, 105, 106a, 106b, 107a, 107b, 107c, 107d, 108, 109a, 109b, 109c, 109d, 110a, 110b, 110c, 110d. hole.
  • the first wiring 201, and the second wiring are formed 202.
  • the second sub-plate 312 of the first electrode of the storage capacitor 3, the second grid connection line 12, the second control signal connection line 15, the second sensing connection line 22, the second sub-power supply of the first power line 8 The line 82, the second substructure 92 of the auxiliary cathode 9, the data line 7, the second sensing connection line 22, and the sensing line 2, as shown in FIG. 13.
  • the first sub-plate 311 and the second sub-plate 312 of the first electrode of the storage capacitor 3 are connected through the via hole at the position 101.
  • the drains 64 of the sensing transistors 6 in the same column in the pixel unit A are respectively connected to and correspondingly connected to the second sensing connecting lines 22, and the second sensing connecting lines 22 respectively pass through the via holes at positions 102a and 102b and
  • the first sensing connection line 21 is connected, and the sensing line 2 is connected to the first sensing connection line 21 through the via 102c; wherein, the second sensing connection line 22 and the drain 64 of the sensing transistor 6 connected to it can be As a one-piece structure.
  • the source 42 and the drain of the switching transistor 4 in each sub-pixel a are respectively connected to the semiconductor active layer 41 of the switching transistor 4 through vias at positions 104a and 104b; the source 53 and the drain of the driving transistor 5 It is connected to the semiconductor active layer 51 of the driving transistor 5 through the via holes at positions 104c and 104d, respectively; the source 63 and the drain electrode of the sensing transistor 6 are connected to the sensing transistor 6 through the via holes at positions 104e and 104f, respectively.
  • the semiconductor active layer 61 is connected.
  • the source 53 of the driving transistor 5 is also connected to the second sub-plate 312 of the first electrode of the storage capacitor 3, as shown in FIG.
  • the electrode plate 312 is formed as an integral structure.
  • the first sub-structure 91 and the second sub-structure 92 of the auxiliary cathode 9 are connected by the via hole at position 105.
  • the 105 position is more That is, a plurality of via holes are formed to connect the first substructure 91 and the second substructure 92.
  • the second sub-power line 82 of the first power line 8 is connected to the first sub-power line 81 through a via at 106a.
  • the drain 54 of the driving transistor 5 is connected to the power connection line through the via at 106b, and the power connection line is connected to the first sub-power connection line.
  • the connection between the drain 54 of the driving transistor 5 and the first power line 8 is completed.
  • the gate 42 of the switching transistor 4 in the sub-pixel a in the second row and the first column of the pixel unit A is connected to the second gate connection line 12, and the second gate connection line 12 is connected to the gate line 1 through the via hole at 107a.
  • the second gate connection line 12 can be an integral structure with the gate of the switch tube; in the same way, the gate 42 of the switching transistor 4 and the second gate connection line in the sub-pixel a in the second row and second column 12 is connected, the second gate connection line 12 is connected to the gate line 1 through the via at 107b, and the second gate connection line 12 may be an integral structure with the gate of the switch tube.
  • the source 42 of the switching transistor 4 in each sub-pixel a is connected to the first wiring 201, and the first wiring 201 is connected to the gate 52 of the driving transistor 5 through the via hole at position 108, that is, the driving transistor 5 is completed.
  • the gate 52 of the switch and the source 42 of the switching transistor 4 are connected.
  • the source 63 of the sensing transistor 6 is connected to the source 53 of the driving transistor 5 through the first wiring 201, and for the convenience of the process, the source 63 of the sensing transistor 6, the source 53 of the driving transistor 5, and the first wiring 201 Can be a one-piece structure.
  • One end of the second control signal connection line 15 is connected to the control signal line 13 through the via hole at the position 109a, and the other end is connected to the sub-pixel a in the first row and the first column of the pixel unit A through the via hole at the position 109c.
  • the gate 62 of the sensing transistor 6 is used to complete the connection between the gate 62 of the sensing transistor 6 in the sub-pixel a in the first row and the first column of the pixel unit A and the control signal; similarly, the second control signal is connected One end of the line 15 is connected to the control signal line 13 through the via at the position 109b, and the other end is connected to the sensing transistor 6 in the sub-pixel a in the first row and second column of the pixel unit A through the via at the position 109d.
  • the gate 62 is used to complete the connection between the gate 62 of the sensing transistor 6 in the sub-pixel a in the first row and the second column in the pixel unit A and the control signal.
  • the drain 43 of the switching transistor 4 in the sub-pixel a in the second row and the first column of the pixel unit A is connected to one end of the data connection line 71 through the via hole at position 110a, and the other end of the data connection line 71 passes through the position 110b.
  • the via hole at is connected to the data line 7 corresponding to the sub-pixel a to complete the connection between the drain 43 of the switching transistor 4 and the data line 7; in the same way, the switch in the sub-pixel a in the second row and second column
  • the drain 43 of the transistor 4 is connected to one end of the data connection line 71 through the via hole at position 110c, and the other end of the data connection line 71 is connected to the data line 7 corresponding to the sub-pixel a through the via hole at position 110d to The connection between the drain 43 of the switching transistor 4 and the data line 7 is completed.
  • the small box on the second sub-plate 312 of the first electrode of the storage capacitor 3 is represented by 111, where the position of 111 is the second sub-plate 312 of the storage capacitor 3 and the organic electro-optic
  • the connection position of the anode 401 of the light-emitting diode OLED is such that the insulating layer between the second sub-plate 312 of the storage capacitor 3 and the anode 401 of the organic electroluminescent diode OLED is formed with a via hole corresponding to the position 111.
  • the switching transistor 4, the driving transistor 5, the source 63 and the drain of the sensing transistor 6 in the pixel unit A, the first wiring 201, the second wiring 202, and the first electrode of the storage capacitor 3 are formed.
  • a passivation layer 305 is formed, and a via hole is formed at the position of the passivation layer 305 corresponding to 111.
  • a transfer electrode is formed on the substrate 10 on which the passivation layer 305 is formed.
  • the transfer electrode is connected to the first sub-plate 311 of the storage capacitor 3 through the via hole at position 111.
  • the source 53 of the transistor 5 and the source 63 of the sensing transistor 6 are an integral structure, so the switching electrode is simultaneously connected to the source 53 of the driving transistor 5 and the source 63 of the sensing transistor 6 through the via hole at the position 111.
  • an anode 401 of the organic electroluminescent diode OLED is formed, and the anode is connected to the transfer electrode through a via hole at 111.
  • a pixel defining layer 306, the light emitting layer 403 of the organic electroluminescent diode OLED and a cathode are sequentially formed, and the cathode is connected to the second substructure 92 of the auxiliary cathode 9 .
  • embodiments of the present disclosure also provide a display device, which includes the above-mentioned display substrate.
  • the display panel can be, for example, an electronic device with a display panel such as a mobile phone, a tablet computer, an electronic watch, a sports bracelet, or a notebook computer.
  • a display panel such as a mobile phone, a tablet computer, an electronic watch, a sports bracelet, or a notebook computer.

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Abstract

本发明提供一种显示基板及显示装置，属于显示技术领域。本发明的显示基板，其包括基底，设置在所述基底上、沿第一方向延伸的多条栅线和沿第二方向延伸的多条数据线，以及多个像素单元，所述第一方向和所述第二方向相交；所述多个像素单元中的每个包括多个亚像素，所述多个亚像素中的每个包括像素电路；所述像素电路至少包括开关晶体管、驱动晶体管、感测晶体管，以及存储电容；其中，对于每一个所述像素电路，其中的所述开关晶体管、所述驱动晶体管、所述感测晶体管均位于所述存储电容的同一侧；所述开关晶体管位于与之连接所述栅线和所述数据线的交叉位置，且所述开关晶体管与所述感测晶体管在所述第一方向上相邻设置，与所述驱动晶体管在所述第二方向上相邻设置。

Description

显示基板及显示装置 技术领域
本发明属于显示技术领域，具体涉及一种显示基板及显示装置。
背景技术
有机发光二极管(Organic Light-Emitting Device，简称OLED)显示基板，是一种与传统的液晶显示(Liquid Crystal Display，简称LCD)不同的显示基板，具备主动发光、温度特性好、功耗小、响应快、可弯曲、超轻薄和成本低等优点。因此已经成为新一代显示装置的重要发展发现之一，并且受到越来越多的关注。
发明内容
本发明旨在至少解决现有技术中存在的技术问题之一，提供一种显示基板及显示装置。
第一方面，本公开实施例提供一种显示基板，其包括基底，设置在所述基底上、沿第一方向延伸的多条栅线和沿第二方向延伸的多条数据线，以及多个像素单元，所述第一方向和所述第二方向相交；
所述多个像素单元中的每个包括多个亚像素，所述多个亚像素中的每个包括像素电路；所述像素电路至少包括开关晶体管、驱动晶体管、感测晶体管，以及存储电容；其中，
对于每一个所述像素电路，其中的所述开关晶体管、所述驱动晶体管、所述感测晶体管均位于所述存储电容的同一侧；所述开关晶体管位于与之连接所述栅线和所述数据线的交叉位置，且所述开关晶体管与所述感测晶体管在所述第一方向上相邻设置，与所述驱动晶体管在所述第二方向上相邻设置。
其中，所述多个像素单元沿所述第一方向排成多列，沿所述第二方向排成多行；每个所述像素单元中的多个亚像素沿第二方向排成两行，每一行所述亚像素沿第一方向排布；
对于位于同一行的所述像素单元，各个所述像素电路的开关晶体管的栅极连接同一所述栅线；
对于位于同一列的所述像素单元，有机电致发光二极管发光颜色相同的所述像素电路的开关晶体管的连接同一所述数据线。
其中，每行像素单元所对应的所述栅线位于该行像素单元的两行所述亚像素之间。
其中，对于每行所述像素单元的两行所述亚像素，其中的一行所述亚像素的开关晶体管的栅极通过第一栅连接线与所述栅线连接，另一行所述亚像素的开关晶体管的栅极通过第二栅连接线与所述栅线连接；所述第一栅连接线与所述栅线同层设置且材料相同，所述第二栅连接线与所述数据线同层设置且材料相同；在所述栅线和所述数据线所在层之间设置有第一绝缘层，所述第二栅连接线通过贯穿所述第一绝缘层的过孔与所述栅线连接。
其中，每列所述像素单元所连接的所述数据线位于该列像素单元的两列所述亚像素之间。
其中，每列所述像素单元中的各个所述像素电路的驱动晶体管的漏极连接第一电源线，且该第一电源线位于与之对应的所述像素单元的两列所述亚像素之间。
其中，所述第一电源线包括电连接的第一子电源线和第二子电源线；所述第一子电源线与栅线同层设置且材料相同；第二子电源线与所述数据线同层设置且材料相同。
其中，还包括多条控制信号线，且位于同一行的所述像素单元中的各所述感测晶体管的栅极连接同一所述控制信号线。
其中，每行所述像素单元所连接的控制信号线位于该像素单元的两行所述亚像素之间。
其中，所述控制信号线与所述栅线同层设置且材料相同；对于每行所述像素单元的两行所述亚像素，其中的一行所述亚像素的感测关晶体管的栅极通过第一控制信号连接线与所述控制信号线连接，另一行所述亚像素的感测 晶体管的栅极通过第二控制信号连接线与所述控制信号连接；所述第一控制信号连接线与所述控制信号线同层设置且材料相同，所述第二控制信号连接线与所述数据线同层设置且材料相同；在所述栅线和所述数据线所在层之间设置有第一绝缘层，所述第二控制信号连接线通过贯穿所述第一绝缘层的过孔与所述控制信号线连接。
其中，所述显示基板还包括多条感测信号线，且位于同一列的所述像素单元中的各所述感测晶体管的漏极连接同一所述感测线。
其中，所述感测线与所述数据线同层设置且材料相同。
其中，每个所述像素单元均包括沿所述第一方向排布的两列、沿所述第二排向排布的两行所述亚像素。
其中，每个所述像素单元中的所述亚像素的有机电致发光二极管的发光颜色分别为红色、绿色、蓝色、白色。
其中，还包括多个透光单元；在所述第一方向或所述第二方向上所述透光单元和所述像素单元交替设置。
其中，所述开关晶体管、所述驱动晶体管、所述感测晶体管均包括依次设置在半导体有源层、栅极、同层设置的源极和漏极；在所述半导体有源层所在层与所述基底之间依次设置有遮光层和缓冲层；在所述栅极所在层与所述半导体有源层所在层之间设置有栅极绝缘层；所在所述栅极所在层与所述源极、所述漏极所在层之间设置有层间绝缘层。
其中，所述存储电容包括第一电极和第二电极；所述第二电极包括第一子极板和第二子极板；所述第一电极与所述半导体有源层同层设置且材料相同；所述遮光层用作所述第一子极板；所述第二子极板与所述驱动晶体管的源极同层设置且材料相同；所述第一子极板和所述第二子极板通过贯穿所述缓冲层、所述栅极绝缘层、所述层间绝缘层的过孔连接。
其中，所述像素电路中的驱动晶体管的栅极与所述开关晶体管的源极通过第一走线连接；所述驱动晶体管的源极与所述感测晶体管的源极通过第二走线连接；
所述第一走线和所述第二走线均与所述驱动晶体管的源极同层设置且材料相同。
其中，还包括辅助阴极；所述辅助阴极包括依次设置在所述基底上的第一子结构和第二子结构；所述第一子结构与所述驱动晶体管的栅极同层设置且材料相同，所述第二子结构与所述驱动晶体管的源极同层设置且材料相同，所述第一子结构和所述第二子结构通过贯穿层间层绝缘层的过孔连接。
其中，所述辅助阴极沿所述第二方向延伸，在每一列所述亚像素的一侧设置有一所述辅助阴极，且相邻列所述辅助阴极间隔一列所述亚像素。
其中，在所述驱动晶体管的源极和漏极与所述有机电致发光二极管的阳极所在层之间依次设置有钝化层、转接电极、平坦化层；所述转接电极通过贯穿所述钝化层的过孔与所述驱动晶体管的漏极连接，所述有机电致发光二极管的阳极通过贯穿所述平坦化层的过孔与所述转接电极连接。
其中，所述有机电致发光二极管为顶发射型有机电致发光二极管。
第二方面，本公开实施例提供一种显示装置，其包括上述的显示基板。
附图说明
图1为一种示例性的显示基板的像素排布图；
图2为一种示例性的像素电路图；
图3为本发明实施例的显示基板的一个亚像素的像素版图；
图4为本发明实施例的显示基板的一种像素排布示意图；
图5为本发明实施例的一种像素单元的像素电路示意图；
图6为本发明实施例的显示基板的另一种像素排布示意图；
图7为本发明实施例的显示基板的驱动晶体管和有机电致发光二极管的一种截面图；
图8为本发明实施例的显示基板的驱动晶体管和有机电致发光二极管的另一种截面图；
图9为本发明实施例的显示基板的一个像素单元的版图；
图10为图9中的遮光层所在层的版图的；
图11为图9中半导体有源层所在层的版图；
图12为图9中栅极所在层的版图；
图13为图9中源极和漏极所在层的版图。
具体实施方式
为使本领域技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对本发明作进一步详细描述。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
图1示意出一种显示基板的结构，该显示基板包括基底10，设置基底10上的多条栅线1、多条数据线7、多条控制信号线13、多条感测线2，以及多个像素单元A；其中，栅线1和控制信号线13沿第一方向延伸，数据线7和感测线2沿第二方向延伸，第一方向和第二方向相交，也即栅线1和数据线7交叉设置。每个像素单元A包括位于栅线1和数据线7交叉位置处的多个亚像素a。在图1中，以每个像素单元A包括红色亚像素R、绿色亚像素G、蓝色亚像素B。其中，每个亚像素a中设置有像素电路。
图2为一种示意性的像素电路，该像素电路包括开关晶体管4、驱动晶体管5、感测晶体管6、存储电容3、有机电致发光二极管OLED；其中，开关晶体管4的栅极42连接栅线1，开关晶体管4的源极42连接驱动晶体管 5的栅极52，开关晶体管4的漏极43连接数据线7；驱动晶体管5的栅极52连接存储电容3的第一电极，驱动晶体管5的源极53连接存储电容3的第二电极32、感测晶体管6的源极63和有机电致发光二极管OLED的阳极401，驱动晶体管5的漏极54连接第一电源线8；感测晶体管6的栅极62连接控制信号线13，感测晶体管6的漏极64连接感测信号；有机电致发光二极管OLED的阴极403连接第二电源线(或者接地)。
在需要对该像素电路仅需外部补偿时，该像素电路在工作过程中至少包括如下两个阶段：显示阶段(包括数据电压Vdata写入过程)和感测阶段(包括电流读取过程)。
显示阶段：给栅线1写入高电平信号，开关晶体管4打开，将数据线7中的数据电压Vdata写入至驱动晶体晶体管的栅极，并给存储电容3充电，通过驱动晶体管5驱动有机电致发光二极管OLED发光。
感测阶段：给栅线1和信号控制线写入高电平信号，感测体晶体管和驱动晶体晶体管打开，通过数据线7将一个测试电压Vsense写入至驱动晶体晶体管的栅极，并通过感测晶体管6将驱动晶体管5的源极53处的电信号读取，并通过感测输出，以使外界补偿电路通过输出的电信号对驱动晶体管5的迁移率进行补偿。
其中，通常栅线1和信号控制线平行设置，且二者位于亚像素a的上、下两相对侧，其中，开关晶体管4为栅线1和数据线7的交叉位置，以便于开关晶体管4的栅极42与栅线1连接，漏极与数据线7连接；感测晶体管6位于控制信号线13和感测线2的交叉位置；驱动晶体管5与开关晶体管4沿第一方向(栅线1的延伸方向)并排设置，存储电容3则位于亚像素a的中间区域。
发明人发现，由于感测晶体管6的源极63与驱动晶体管5的源极53连接，在驱动晶体管5和感测晶体管6之间存在存储电容3，故导致感测晶体管6的源极63与驱动晶体管5的源极53的连接不便，为解决前述问题，在本发明实施例中提供如下技术方案。
在此需要说明的是，本公开实施例中，以第一方向和第二方向相互垂直为例进行说明，此时，第一方向为行方向，第二方向为列方向。当然，应当理解的是的，第一方向和第二方向垂直并不构成对本公开实施例的限制，只要是第一方向和第二方向相交即可。相应的，当第一方向和第二方向垂直时，在本公开实施例中，以各个像素单元A呈阵列排布为例进行说明，当然，各个像素单元A也可以是按照一定规律进行排布。
第一方面，如图3所示，本公开实施例提供一种显示基板，该显示基板包括基底10，位于基底10上的多行栅线1和多列数据线7，以及呈阵列排布的多个像素单元A。每个像素单元A包括多个亚像素a，每个亚像素a中均包括像素电路；该像素电路至少包括开关晶体管4、驱动晶体管5、感测晶体管6，以及存储电容3(例如图2所示的像素电路)；其中，对于每一个像素电路，其中的开关晶体管4、驱动晶体管5、感测晶体管6均位于存储电容3的同一侧；开关晶体管4位于与之连接栅线1和所述数据线7的交叉位置，且开关晶体管4与感测晶体管6在行方向上相邻设置，与驱动晶体管5在列方向上相邻设置。
由于在本公开实施例中，将每个亚像素a的像素电路中的开关晶体管4、驱动晶体管5、感测晶体管6，以及存储电容3进行合理布局，以使每个像素电路中的开关晶体管4、驱动晶体管5、感测晶体管6均位于存储电容3的同一侧，且开关晶体管4与感测晶体管6在行方向上相邻设置，与驱动晶体管5在列方向上相邻设置，从而可以有效的利用每个亚像素a的行方向空间，节约了每个亚像素a的列方向空间，进而有效缩小每个亚像素a的所占空间，以保证像素电路版图空间有限的情况下，大大提高应用本公开实施例的显示基板的显示面板的分辨率。同时，相较相关技术中每个亚像素a中存储电容3的两侧存在非发光区域的薄膜晶体管(例如：开关晶体管4和感测晶体管6位于存储电容3的两相对侧)，存在光栅效应，导致显示重影等不良效果，而在本公开实施例中将每个亚像素a中薄膜晶体管(开关晶体管4、驱动晶体管5、感测晶体管6)集中设置，也即设置在存储电容3的同一侧，有效的解决了相关技术中所出现的光栅效应。
在一些实施例中，每个像素单元A包括两行亚像素a，且两行亚像素a中的像素电路由同一条栅线1控制，位于同一列的亚像素a中且有机电致发光二极管OLED发光颜色相同的像素电路由同一条数据线7提供数据电压信号。
也就是说，对于每一行像素单元A，各个像素电路中的开关晶体管4的栅极42连接同一条栅线1，对于每列像素单元A，有机电致发光二极管OLED发光颜色相同的像素电路中的开关晶体管4的漏极43连接同一条数据线7。
具体的，若每个像素单元A包括两行两列四个亚像素a，且四个亚像素a中的像素电路中的有机电致发光二极管OLED的发光颜色均不相同。此时，位于同一行的像素单元A中的四个亚像素a中的像素电路的开关晶体管4的栅极42的连接一条栅线1，且与同一列的像素单元A中的四个亚像素a中的像素电路的开关晶体管4的漏极43分别连接与之对应的数据线7，也即位于一行像素单元A的四个亚像素a由一条栅线1控制，位于一列像素单元A的四个像素单元A的四个亚像素a由四条数据线7提供数据电压信号。
在本公实施例由于位于同一行的像素单元A的多个亚像素a由一条栅线1控制，故在给该行栅线1输入扫描信号时，则可以对多行亚像素a进行扫描，因此可以大大提高应用本公开实施例的显示面板的刷新频率。
在一些实施例中，当每个像素单元A包括两行亚像素a时，用以控制该像素单元A的两行亚像素a的栅线1位于这两行亚像素a之间，这样以便于两行亚像素a中的像素电路的开关晶体管4的栅极42与栅线1连接，且在制备时可以将开关晶体管4的栅极42和与之连接的栅线1采用一次工艺制备，形成为一体结构，这样制备工艺简单，且易于实现。
在一些实施例中，如图12和13所示，对于每行像素单元A的两行亚像素a，其中的一行亚像素a的开关晶体管4的栅极42通过第一栅连接线11与栅线1连接，另一行亚像素a的开关晶体管4的栅极42通过第二栅连接线12与栅线1连接；第一栅连接线11与栅线1同层设置且材料相同，第二栅连接线12与数据线7同层设置且材料相同；在栅线1和数据线7所在层 之间设置有第一绝缘层，第二栅连接线12通过贯穿第一绝缘层的过孔与栅线1连接。
在此需要说明的是，在本公开实施例中以开关晶体管4、驱动晶体管5、感测晶体管6均为顶栅型薄膜晶体管为例进行说明的。其中，开关晶体管4、驱动晶体管5、感测晶体管6的各个膜层均同层设置。以驱动晶体管5为例，其包括依次设置在基底10上半导体有源层51、栅极绝缘层302、栅极52、层间绝缘层303、源极53和漏极54。上述的栅线1通常与驱动晶体管5的栅极52同层设置，数据线7通常与驱动晶体管5的源极53和漏极54同层设置，因此上述的栅极1和数据线7所在层之间第一绝缘层则是指栅极绝缘层302和层间绝缘层303两层结构，其中贯穿第一绝缘层的过孔则是贯穿栅极绝缘层302的过孔和贯穿层间绝缘层303的过孔组成的套设过孔。
在一些实施例中，当每个像素单元A包括两列亚像素a时，用以为该像素单元A的两列亚像素a提供数据电压信号的数据线7位于这两列亚像素a之间，这样以便于这两列亚像素a的开关晶体管4的漏极43连接，且在制备时可以将开关晶体管4的漏极43与数据线7采用一次工艺制备，且可以将开关晶体管4的漏极43和与之连接数据线7制备成为一体结构，这样制备工艺简单，且易于实现。
在一些实施例中，每列像素单元A中的各个亚像素a的像素电路的驱动晶体管5的漏极54连接第一电源线8，且当每个像素单元A包括两列亚像素a时，该第一电源线8位于与之对应的像素单元A的两列亚像素a之间。之所以如此设置是，驱动晶体管5与开关晶体管4沿列方向并排设置，这样一来，第一电源线8与驱动晶体管5的漏极54的连接更加便利。
进一步的，可以将第一电源线8包括电连接第一子电源线81和第二子电源线82；其中第子电源线与栅线1同层设置且材料同；第二子电源线82与数据线7同层设置且材料相同，而数据线7通常与和驱动晶体管5的漏极54同层设置，且采用相同的材料，因此，第二子电源线82可以与驱动晶体管5的漏极54同层设置且材料相同；故可以将第一电源线8和驱动晶体管5的漏极54采用一次构图工艺制备，这样制备工艺简单，且易于实现。
在一些实施例中，当每个像素单元A包括两列亚像素a时，与每一列像素单元A对应的第一电源线8和数据线7均位于两列亚像素a之间，此时可以将第一电源线8和数据线7的延伸方向设置为平行，从而可以缩小第一电源线8和数据线7的布线空间，提高像素分辨率。
在一些实施例中，每个像素电路的感测晶体管6的栅极62均连接与之对应的控制信号线13。在本公开实施例中可以将位于同一行的像素单元A中的各个像素电路中的感测晶体管6的栅极62连接同一控制信号线13。优选的，当每个像素单元A包括两行亚像素a时，控制该行像素单元A的控制信号线13位于这两行亚像素a之间。进一步的，还可以将控制信号线13设置为与栅线1的延伸方向平行，这样一来，当栅线1位于其所连接两行亚像素a之间时，可以缩小栅线1和控制信号线13的布线空间，提高像素分辨率。而且还可以将栅线1和控制信号线13同层设置，并采用相同的材料，这样一来二者可以采用一次构图工艺制备，可以简化工艺步骤，降低工艺成本。
在一些实施例中，控制信号线13与栅线1同层设置且材料相同；对于每行像素单元A的两行亚像素a，其中的一行亚像素A的感测关晶体管6的栅极62通过第一控制信号连接线14与控制信号线13连接，另一行亚像素a的感测晶体管6的栅极62通过第二控制信号连接线15与控制信号连接13；第一控制信号连接线14与控制信号线13同层设置且材料相同，第二控制信号连接线15与数据线7同层设置且材料相同；在栅线1和数据线7所在层之间设置有第一绝缘层，第二控制信号连接线通过贯穿第一绝缘层的过孔与控制信号线连接。
在此需要说明的是，该第一绝缘层与上述的第一绝缘层解释相同，在此不再重复说明。其中，对于每一行像素单元A，若第一行亚像素a中的开关晶体管4的栅极42通过第一栅连接线12与栅线1连接，那么第二行亚像素a中的感测晶体管6的栅极62则通过第一控制信号连接14与控制信号线13连接。这样一来，避免栅线1与控制信号线13同层设置，各个连接线之间存在交叉布线的问题。
在本公开实施例中，对于每一行像素单元A而言其所连接的将栅线1、控制信号线13，以及每个像素单元A中的各个亚像素中a的开关晶体管4、驱动晶体管5、感测晶体管6集中设置(位于两行亚像素a的中间区域)，减小了显示面板显示区域的面积，增大了透明区域的面积，从而可以消除光栅效应。
在一些实施例中，显示基板还包括多条感测信号线，且位于同一列的像素单元A中的各像素电路的感测晶体管6的漏极64连接同一感测线2。进一步的，每一条感测线2位于其所对应的像素单元A的同一列，也即相邻的感测线2之间间隔一列像素单元A。这样一来，可以避免感测线2集中设置而导致感测线2之间信号发生耦合，导致所传输的电信号不准确。
在一些实施例中，每个像素单元A均采用正方形(square)形式排布的四个亚像素a，即每个像素单元A包括两行两列四个亚像素a，此时位于一个像素单元A中的四个亚像素a共用一条栅线1，若四个亚像素a中的四个有机电致发光二极管OLED的发光颜色不同，该四个亚像素a则分别连接四条数据线7。在该种情况下，显示基板的栅线1、数据线7、控制信号线13、第一电源线8、感测线2均可以采用上述任意一种设置方式。在此不再重复描述。
在一些实施例中，每个所述像素单元A中的所述亚像素a的有机电致发光二极管OLED的发光颜色分别为红色(red，R)、绿色(green，G)、蓝色(blue，B)、白色(white，W)，也即包括红色亚像素R、绿色亚像素G、蓝色亚像素B、白色亚像素W，四个亚像素分别对应连接的数据线分别用7(R)、7(G)、7(B)、7(W)表示。如图4和5所示，在本公开实施例中以每个像素单元A中的第一行亚像素a的有机电致发光二极管OLED的发光颜色为红色和蓝色，第二行亚像素a的有机电致发光二极管OLED的发光颜色为绿色和白色为例进行说明。当然，每个像素单元A也不局限于仅包括四个亚像素a，例如，每个像素单元A包括三个亚像素a，例如由红色、绿色、蓝色三种颜色亚像素a，这个亚像素a可以呈品字形排布。
如图6所示，本公开实施例中的显示基板可以应用至透明显示中，此时 显示基板不仅包括上述结构还包括透光单元Q，其中透光单元Q在行方向或者列方向上与像素单元A交替设置。其中，像素单元A则根据待显示画面进行显示，而透光单元Q顾名思义，该透光单元Q所在位置可以透光，观看者在观看应用该显示基板的显示面板时，可以通过透光单元Q观看到显示面板背后(背离显示面的一侧)的景象。
在此需要说明的是，每个亚像素a均通过电连接的栅线1获取扫描信号，通过数据线7获取数据电压信号，在扫描信号和数据电压信号的作用下，驱动该亚像素a中的有机电致发光二极管OLED发光。每列亚像素a中有机电致发光二极管OLED发光颜色相同的亚像素a连接同一条数据线7，该数据线7穿过透光单元Q，并且需要黑矩阵(图中未示)进行遮挡。
在一些实施例中，显示基板中的开关晶体管4、驱动晶体管5、感测晶体管6均包括依次设置在半导体有源层、栅极、同层设置的源极和漏极；在半导体有源层所在层与基底10之间依次设置有遮光层和缓冲层301；在栅极所在层与半导体有源层所在层之间设置有栅极绝缘层302；所在栅极所在层与源极、漏极所在层之间设置有层间绝缘层303。
其中，在本公开实施例中的开关晶体管4、驱动晶体管5、感测晶体管6均可以为氧化物薄膜晶体管，也可以为多晶硅、非晶硅薄膜晶体管，在本公开实施例中以各个晶体管为氧化物晶体管为例进行说明。对于开关晶体管4、驱动晶体管5、感测晶体管6均可以为顶栅型晶体管，也可以为底栅型晶体管，在下述描述中以本公开实施例中的晶体管为均为顶栅型晶体管为例进行说明。由于开关晶体管4、驱动晶体管5、感测晶体管6均包括依次设置在半导体有源层、栅极、同层设置的源极和漏极，以下对驱动晶体管5和有机电致发光二极管OLED的各层结构对显示基板上的各膜层进行说明。
在一个示例中，由于驱动晶体管5为顶栅型氧化物薄膜晶体管，以避免光照影响半导体有源层的电子迁移率，故形成晶体管之前在基底10依次上形成有遮光层和缓冲层301。驱动晶体管5可为顶栅型，此驱动晶体管5可包括依次设置在基底10背离缓冲层301一侧的半导体有源层、栅极绝缘层302、栅极、层间绝缘层303、源极和漏极。其中，源极和漏极分别位于栅 极的相对两侧，该源极和漏极可分别通过过孔(例如：金属过孔)分别与有源层的相对两侧的源极接触区和漏极接触区接触。应当理解的是，此驱动晶体管5也可为底栅型。
其中，存储电容3包括第一电极和第二电极32；第二电极32包括第一子极板311和第二子极板312；其中，第一电极、第一子极板311和第二子极板312在基底10上的正投影至少部分重叠。
具体的，第一电极与半导体有源层同层设置且材料相同；第一子极板311与遮光层同层设置且材料相同；第二子极板312与驱动晶体管5的源极53同层设置且材料相同；第一子极板311和第二子极板312通过贯穿所述缓冲层301、栅极绝缘层302、层间绝缘层303的过孔连接。其中，第一过孔包括贯穿缓冲层301的过孔、贯穿栅极绝缘层302的过孔，以及贯穿层间绝缘层303的过孔，且这三个过孔套设在一起。
举例而言，栅极和遮光层的材料可以包括金属材料或者合金材料，例如包括钼、铝及钛等。源极和漏极可以包括金属材料或者合金材料，例如由钼、铝及钛等形成的金属单层或多层结构，例如，该多层结构为多金属层叠层，例如钛、铝、钛三层金属叠层(Al/Ti/Al)等。半导体有源层的材料可以包括氧化物半导体材料，例如氧化铟镓锌、氧化铟镓锡等。
如图7所示，在驱动晶体管5背离基底10的一侧设置有平坦化层304。其中，平坦化层304通常采用有机材料制作而成，例如：光刻胶、丙烯酸基聚合物、硅基聚合物等材料。
如图7所示，有机电致发光二极管OLED可以包括依次形成在平坦化层304上的有机电致发光二极管OLED的阳极401和像素限定层306，应当理解的是，该有机电致发光二极管OLED还可包括发光层402和阴极403。
其中，如图7所示，有机电致发光二极管OLED的第一极阳极可通过贯穿平坦化层304的过孔与驱动晶体管5的源极53电性连接，此阳极可为ITO(氧化铟锡)、氧化铟锌(IZO)、氧化锌(ZnO)等材料制作而成；像素限定层306可覆盖平坦化层304，此像素限定层306可为有机材料制作而成， 例如：光刻胶等有机材料，且像素限定层306可具有露出第一电极的容纳部；发光层位于容纳部内并形成在阳极上，该发光层可包括小分子有机材料或聚合物分子有机材料，可以为荧光发光材料或磷光发光材料，可以发红光、绿光、蓝光，或可以发白光等；并且，根据实际不同需要，在不同的示例中，发光层还可以进一步包括电子注入层、电子传输层、空穴注入层、空穴传输层等功能层；阴极覆盖发光层，此阴极可为锂(Li)、铝(Al)、镁(Mg)、银(Ag)等金属材料制作而成。
需要说明的是，阳极401、发光层402和阴极403可构成一个有机电致发光二极管OLED。其中，显示基板中包括呈阵列排布的有机电致发光二极管OLED。此外，还需说明的是，各有机电致发光二极管OLED的阳极401相互独立，各有机电致发光二极管OLED的阴极403可整面连接；即阴极为设置在显示基板上的整面结构，为用于多个有机电致发光二极管OLED的公共电极。
在一些实施例中，如图8所示，有机电致发光二极管OLED的阳极401还可通过转接电极501与驱动晶体管5的源极53电性连接。当阳极401通过转接电极501与驱动晶体管5的电性连接时，在平坦化层304与层间驱动晶体管5的源极53和漏极所在层之间还可形成钝化(PVX)层，该钝化层305可由氧化硅、氮化硅或者氮氧化硅等材料形成；该钝化层305覆盖源极和漏极所在层；而转接电极501形成在平坦化层304与钝化层305之间，并依次通过钝化层305上的过孔(例如金属过孔)与驱动晶体管5的源极53电性连接；而第一极可通过平坦化层304上的过孔(例如金属过孔)与转接电极501电性连接，以此完成有机电致发光二极管OLED的阳极401与驱动晶体管5的源极53的连接。
当然，在有机电致发光二极管OLED之上还可以包括封装层等结构，其中，封装层包括依次层叠设置的第一封装层、第二封装层和第三封装层。第一封装层、第三封装层用于防止水、氧进入到发光层中；该第一封装层、第三封装层可采用氮化硅、氧化硅等无机材料制作而成。第二封装层用于实现平坦化作用，以便于第三封装薄膜层层的制作，此第二封装层可采用丙烯酸 基聚合物、硅基聚合物等材料制作而成。
在一些实施例中，像素电路中的驱动晶体管5的栅极52与开关晶体管4的源极42通过第一走线201连接；驱动晶体管5的源极53与感测晶体管6的源极63通过第二走线202连接；第一走线201和所述第二走线202均与驱动晶体管5的源极53同层设置且材料相同。当然，与驱动晶体管5的源极53和漏极同层设置还可以有数据线7、感测线2、第一电源线8等结构，这样一来，可以使得所形成的显示基板的较为轻薄。
在一些实施例中，由于显示基板中多个有机电致发光二极管OLED的阴极403为一整面结构，故较信号入端较远的有机电致发光二极管OLED的输入信号存在较大的压降(IR drop)，因此在本公开实施例的显示基板还设置有辅助阴极9；辅助阴极9包括依次设置在基底10上的第一子结构91和第二子结构92；第一子结构91与驱动晶体管5的栅极52同层设置且材料相同，第二子结构92与驱动晶体管5的源极53同层设置且材料相同，第一子结构91和第二子结构92通过贯穿层间层的第二过孔连接。在此需要说明的是，以便于第一子结构91和第二子结构92的连接，第二过孔的数量为多个，且多个第二过孔沿辅助阴极9的延伸方向排成一列。
其中，辅助阴极9沿列方向延伸，在每一列亚像素a的一侧设置有一辅助阴极9，且相邻列辅助阴极9间隔一列亚像素a。
在一些实施例中，由于在本公开实施例中的基底10上设置有遮光层，故有机电致发光二极管OLED选用顶发射型有机电致发光二极管OLED。
为了更清楚本公开实施例显示基板的结构，结合下述显示基板的方法对该显示基板的结构进行说明，另外，需要说明的是，下述方法只是给出一种显示基板的示例结构，并不构成对本公开实施例保护范围的限制。其中，显示基板中的像素单元A包括四个按照square形式排布的四个亚像素a，四个亚像素所对应的连接的数据线分别用7(R)、7(G)、7(B)、7(W)表示，结合图5、9-13本公开实施例的显示基板的制备方法具体包括如下步骤。
S01、提供一基底10。该基底10为透明基底10，例如玻璃基底10等。
S02、在基底10上形成遮光层，以及用于将各个像素电路中的感测晶体管6的漏极64与感测线2连接的感测连接线，如图10所示。
在本公开实施例中，如图10所示，遮光层可以用作存储电容3的第一电极的第一子极板311。在此需要说明的是，每个遮光层分别圈出一个小方框，用101表示，这四个位置为遮光层与的存储电容3的第一电极的第二子极板312连接的位置，位于遮光层和第二子极板312所在层之间的绝缘层在对应小方框101将形成过孔。感测连接线上圈出的三个小方框，分别用于102a、102b、102c表示，其中，102a、102b的位置分别为位于该位置上下两个亚像素a中的感测晶体管6的漏极64与第一感测线2连接线连接的位置，102c的位置为第一感测连接线21与感测线2连接的位置；其中，位于第一感测连接线21所在层与感测晶体管6的漏极64和感测线2之间的绝缘层在102a、102b、102c在所在位置设置有过孔。
S03、在形成有遮光层的基底10上形成缓冲层301，且在缓冲层301对应101、102a、102b、102c的位置形成过孔。
S04、在形成缓冲层301的基底10上形成每个亚像素a中的开关晶体管4、驱动晶体管5、感测晶体管6的半导体有源层61和存储电容3的第二电极32，如图11所示。
在此需要说明的是，图11中所示存储电容3的第二电极32上的小方框的位置用103表示，该位置为该亚像素a中存储电容3的第二电极32与驱动晶体管5的栅极52连接位置，故位于驱动晶体管5的栅极52和存储电容3的第二电极32之间的绝缘层在103所在位置形成有过孔，以便存储电容3的第二电极32与驱动晶体管5的栅极52连接。每个亚像素a中的开关晶体管4的有源层上的两个小方框分别为104a和104b，驱动晶体管5的有源层上的两个小方框分别为104c和104d，感测晶体管6的有源层上的两个小方框分别为104e和104f；104a和104b分别对应开关晶体管4的源极42和漏极与其半导体有源层连接的位置；104c和104d分别对应驱动晶体管5的源极53和漏极与其半导体有源层连接的位置；104e和104f分别对应感测晶体管6的源极63和漏极与其半导体有源层连接的位置；故在位于开关晶体管 4、驱动晶体管5、感测晶体管6的半导体有源层61所在层和源极、漏极所在层之间的绝缘层对应104a、104b、104c、104d、104e和104f的位置形成有过孔。
S05、在形成有开关晶体管4、驱动晶体管5、感测晶体管6的半导体有源层61的基底10上，形成栅极绝缘层302，在栅极绝缘层302对应101、102a、102b、102c、103、104a、104b、104c、104d、104e和104f的位置形成过孔。
S06、在形成有栅极绝缘层302的基底10上，形成开关晶体管4、驱动晶体管5、感测晶体管6的栅极62、栅线1、信号控制线、第一栅连接线11、第一控制信号连接线14、第一电源线8的第一子电源线81、电源连接线、辅助阴极9的第一子结构91、数据连接线71；其中，每个驱动晶体管5的栅极52通过103位置的过孔与存储电容3的第二电极32连接；像素单元A中的第一行亚像素a的开关晶体管4的栅极42通过第一栅连接线11与栅线1连接，第二行亚像素a的感测晶体管6的栅极62通过第一控制信号连接线14与控制信号线13连接；两个位于同一行的亚像素a对应一条第一子电源线81，且这两个亚像素a分别通过对应的电源连接线与第一子电源线81连接；如图12所示。
在此需要说明的是，像素单元A中第一行亚像素a的开关晶体管4的栅极42、第一栅连接线11和栅线1可以为一体结构；第二行亚像素a中的测晶体管的栅极、第一控制信号连接线14和控制信号线13可以为一体结构。如图12中每个亚像素a的辅助阴极9的第一结构上的小方框用105表示，105的位置为辅助阴极9的第一子结构91和第二子结构92的连接位置，故在辅助阴极9的第一子结构91和第二子结构92所在层之间的绝缘层对应105的位置设置有过孔。每条第一子电源线81和电源连接线上的小方框分别用106a和106b表示；其中，106a的位置为第一电源线8的第一子电源线81与其第二子电源线82的连接位置；106b的位置为电源连接线与驱动晶体管5的源极53的连接位置，故位于第一子电源线81所在层和电源连接线之间绝缘层对应106a和106b的位置形成有过孔。栅线1上的小方框分别用 107a和107b表示，在第二行亚像素a的开关晶体管4的栅极42上的小方框分别用107c和107d表示；其中，107a和107c的位置为像素单元A中的第二行第一列的亚像素a的开关晶体管4的栅极42通过第二栅连接线12与栅线1连接的位置；107b和107d的位置为像素单元A中的第二行第二列的亚像素a的开关晶体管4的栅极42通过第二栅连接线12与栅线1连接的位置，故在开关晶体管4的栅极42和栅线1所在层与第二栅连接线12所在层之间绝缘层对应107a、107b、107c、107d的位置形成有过孔。每个驱动晶体管5的栅极52上的小方框用于108表示，108的位置为每个亚像素a中的驱动晶体管5的栅极52与开关晶体管4的源极42的连接位置，故在驱动晶体管5的栅极52所在与开关晶体管4的源极42所在层之间的绝缘层对应108的位置形成有过孔。控制信号线13上的小方框分别用109a和109b表示；像素单元A中第一行亚像素a的感测晶体管6的栅极62上的小方框分别用于109c和109d表示；其中，109a和109c的位置为像素单元A中第一行第一列的亚像素a的感测晶体管6的栅极62通过第二感测连接线22与控制信号线13的连接位置；109b和109d的位置为像素单元A中第一行第二列的亚像素a的感测晶体管6的栅极62通过第二感测连接线22与控制信号线13的连接位置，故位于感测晶体管6的栅极62和控制信号线13所在层与第二感测连接线22所在层之间的绝缘层在对应109a、109b、109c、109d的位置形成有过孔。像素单元A中第二行亚像素a中的数据连接线71是为了避免位于两列亚像素a之间的四条数据线7在连接时发生短路。应当理解的是，像素单元A中的两条数据连接线71可以分别设置在四个亚像素a的任意两个之中，在本公开实施例中以数据连接线71分别位于像素单元A中第二行亚像素a中为例。其中，像素单元A中的第二行第一列亚像素a中的数据连接线71两端的两个小方框分别用110a和110b表示，第二行第二列亚像素a中的数据连接线71两端的两个小方框分别用110c和110d表示；其中，110a和110c分别为各亚像素a中的开关晶体管4的漏极43与数据连接线71的连接位置；110b和110d分别为各亚像素a所连接的数据线7与数据连接线71的连接位置，故位于数据连接线71所在层与开关晶体管4的漏极43和 数据线7所在层之间的绝缘层对应110a、110b、110c、110d的位置形成有过孔。
S07、在形成有开关晶体管4、驱动晶体管5、感测晶体管6的栅极62、栅线1、信号控制线、第一栅连接线11、第一控制信号连接线14、第一电源线8的第一子电源线81、电源连接线、辅助阴极9的第一子结构91、数据连接线71的基底10上，形成层间绝缘层303，并在层间绝缘层303对应101、102a、102b、102c、104a、104b、104c、104d、104e、104f、105、106a、106b、107a、107b、107c、107d、108、109a、109b、109c、109d、110a、110b、110c、110d位置形成过孔。
S08、在形成层间绝缘层303的基底10上，形成像素单元A中的开关晶体管4、驱动晶体管5、感测晶体管6的源极63和漏极、第一走线201、第二走线202、存储电容3的第一电极的第二子极板312、第二栅连接线12、第二控制信号连接线15、第二感测连接线22、第一电源线8的第二子电源线82、辅助阴极9的第二子结构92、数据线7、第二感测连接线22、感测线2，如图13所示。其中，存储电容3的第一电极的第一子极板311和第二子极板312通过101位置处的过孔连接。像素单元A中的位于同一列的感测晶体管6的漏极64分别连接与各自对应连接第二感测连接线22，第二感测连接线22分别并通过102a和102b位置处的过孔与第一感测连接线21连接，感测线2通过过孔102c与第一感测连接线21连接；其中，第二感测连接线22和与之连接的感测晶体管6的漏极64可以为一体结构。每个亚像素a中的开关晶体管4的源极42和漏极分别通过104a和104b位置处的过孔与该开关晶体管4的半导体有源层41连接；驱动晶体管5的源极53和漏极分别通过104c和104d位置处的过孔与该驱动晶体管5的半导体有源层51连接；感测晶体管6的源极63和漏极分别通过104e和104f位置处的过孔与该感测晶体管6的半导体有源层61连接。驱动晶体管5的源极53还与存储电容3的第一电极的第二子极板312连接，如图13所示，为了制备工艺简单，可以将驱动晶体管5的源极53与存第二子极板312形成为一体结构。辅助阴极9的第一子结构91和第二子结构92通过105位置出处的过孔连接，为 了使得辅助阴极9的第一子结构91和第二子结构92可以连接可靠，故105位置为多个，也即形成多个过孔，以使第一子结构91和第二子结构92连接。第一电源线8的第二子电源线82通过106a处的过孔与第一子电源线81连接。为了使得第一子电源线81和第二子电源线82连接可靠，故106a位置为多个，也即形成多个过孔，以使第一子电源线81和第二子电源线82连接。驱动晶体管5的漏极54通过106b处的过孔与电源连接线连接，电源连接线与第一子电源连接线连接，此时完成驱动晶体管5的漏极54与第一电源线8的连接。像素单元A中位于第二行第一列的亚像素a中的开关晶体管4的栅极42与第二栅连接线12连接，该第二栅连接线12通过107a处的过孔与栅线1连接，且该第二栅连接线12可以与该开关管的栅极为一体结构；同理，位于第二行第二列的亚像素a中的开关晶体管4的栅极42与第二栅连接线12连接，该第二栅连接线12通过107b处的过孔与栅线1连接，且该第二栅连接线12可以与该开关管的栅极为一体结构。每个亚像素a中的开关晶体管4的源极42与第一走线201连接，第一走线201通过108位置处的过孔与驱动晶体管5的栅极52连接，也即完成驱动晶体管5的栅极52和开关晶体管4的源极42的连接。感测晶体管6的源极63通过第一走线201与驱动晶体管5的源极53连接，且为了工艺简便感测晶体管6的源极63、驱动晶体管5的源极53、第一走线201可以为一体结构。第二控制信号连接线15的一端通过109a位置处的过孔与控制信号线13连接，另一端通过109c位置处的过孔与像素单元A中位于第一行第一列的亚像素a中的感测晶体管6的栅极62，以完成像素单元A中位于第一行第一列的亚像素a中的感测晶体管6的栅极62和控制信号连接连接；同理，第二控制信号连接线15的一端通过109b位置处的过孔与控制信号线13连接，另一端通过109d位置处的过孔与像素单元A中位于第一行第二列的亚像素a中的感测晶体管6的栅极62，以完成像素单元A中位于第一行第二列的亚像素a中的感测晶体管6的栅极62和控制信号连接连接。像素单元A中位于第二行第一列的亚像素a中的开关晶体管4的漏极43与数据连接线71的一端通过110a位置处的过孔连接，数据连接线71的另一端通过110b位置处的过孔和与该亚 像素a对应的数据线7连接，以完成开关晶体管4的漏极43与数据线7的连接；同理，位于第二行第二列的亚像素a中的开关晶体管4的漏极43与数据连接线71的一端通过110c位置处的过孔连接，数据连接线71的另一端通过110d位置处的过孔和与该亚像素a对应的数据线7连接，以完成开关晶体管4的漏极43与数据线7的连接。
在此需要说明的是，存储电容3的第一电极的第二子极板312上的小方框用111表示，其中，111的位置为存储电容3的第二子极板312与有机电致发光二极管OLED的阳极401的连接位置，故位于存储电容3的第二子极板312与有机电致发光二极管OLED的阳极401之间的绝缘层对应111的位置形成有过孔。
S09、在形成有像素单元A中的开关晶体管4、驱动晶体管5、感测晶体管6的源极63和漏极、第一走线201、第二走线202、存储电容3的第一电极的第二子极板312、第二栅连接线12、第二控制信号连接线15、第二感测连接线22、第一电源线8的第二子电源线82、辅助阴极9的第二子结构92、数据线7、第二感测连接线22、感测线2的基底10上，形成钝化层305，并在钝化层305对应111的位置形成过孔。
S10、在形成钝化层305的基底10上，形成转接电极，转接电极通过111位置处的过孔与存储电容3的第一子极板311连接，由于第一子极板311与驱动晶体管5的源极53和感测晶体管6的源极63为一体结构，故转接电极通过111位置处的过孔同时与驱动晶体管5的源极53和感测晶体管6的源极63连接。
S11、在形成转接电极的基底10上，形成平坦化层304，并在平坦化层304对应111的位置处形成过孔。
S12、在形成平坦化层304的基底10上，形成有机电致发光二极管OLED的阳极401，该阳极通过111处的过孔与转接电极连接。
S13、在形成有机电致发光二极管OLED的阳极401的基底10上依次形成像素限定层306、有机电致发光二极管OLED的发光层403和阴极，该阴 极与辅助阴极9的第二子结构92连接。
至此完成显示基板的制备。
第二方面，本公开实施例还提供一种显示装置，该显示装置包括上述的显示基板。该显示面板例如可为手机、平板电脑、电子手表、运动手环、笔记本电脑等具有显示面板的电子设备。该显示装置具有的技术效果可参考上述对显示面板的技术效果的论述，在此不再赘述。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (23)

  1. 一种显示基板，其包括基底，设置在所述基底上、沿第一方向延伸的多条栅线和沿第二方向延伸的多条数据线，以及多个像素单元，所述第一方向和所述第二方向相交；
    所述多个像素单元中的每个包括多个亚像素，所述多个亚像素中的每个包括像素电路；所述像素电路至少包括开关晶体管、驱动晶体管、感测晶体管，以及存储电容；其中，
    对于每一个所述像素电路，其中的所述开关晶体管、所述驱动晶体管、所述感测晶体管均位于所述存储电容的同一侧；所述开关晶体管位于与之连接所述栅线和所述数据线的交叉位置，且所述开关晶体管与所述感测晶体管在所述第一方向上相邻设置，与所述驱动晶体管在所述第二方向上相邻设置。
  2. 根据权利要求1所述的显示基板，其中，所述多个像素单元沿所述第一方向排成多列，沿所述第二方向排成多行；每个所述像素单元中的多个亚像素沿第二方向排成两行，每一行所述亚像素沿第一方向排布；
    对于位于同一行的所述像素单元，各个所述像素电路的开关晶体管的栅极连接同一所述栅线；
    对于位于同一列的所述像素单元，有机电致发光二极管发光颜色相同的所述像素电路的开关晶体管的连接同一所述数据线。
  3. 根据权利要求2所述的显示基板，其中，每行像素单元所连接的所述栅线位于该行像素单元的两行所述亚像素之间。
  4. 根据权利要求3所述的显示基板，其中，对于每行所述像素单元的两行所述亚像素，其中的一行所述亚像素的开关晶体管的栅极通过第一栅连接线与所述栅线连接，另一行所述亚像素的开关晶体管的栅极通过第二栅连接线与所述栅线连接；所述第一栅连接线与所述栅线同层设置且材料相同，所述第二栅连接线与所述数据线同层设置且材料相同；在所述栅线和所述数据线所在层之间设置有第一绝缘层，所述第二栅连接线通过贯穿所述第一绝 缘层的过孔与所述栅线连接。
  5. 根据权利要求2所述的显示基板，其中，每列所述像素单元所连接的所述数据线位于该列像素单元的两列所述亚像素之间。
  6. 根据权利要求2所述的显示基板，其中，每列所述像素单元中的各个所述像素电路的驱动晶体管的漏极连接第一电源线，且该第一电源线位于与之对应的所述像素单元的两列所述亚像素之间。
  7. 根据权利要求6所述的显示基板，其中，所述第一电源线包括电连接的第一子电源线和第二子电源线；所述第一子电源线与栅线同层设置且材料相同；第二子电源线与所述数据线同层设置且材料相同。
  8. 根据权利要求2所述的显示基板，其中，还包括多条控制信号线，且位于同一行的所述像素单元中的各所述感测晶体管的栅极连接同一所述控制信号线。
  9. 根据权利要求8所述的显示基板，其中，每行所述像素单元所连接的控制信号线位于该像素单元的两行所述亚像素之间。
  10. 根据权利要求9所述的显示基板，其中，所述控制信号线与所述栅线同层设置且材料相同；对于每行所述像素单元的两行所述亚像素，其中的一行所述亚像素的感测关晶体管的栅极通过第一控制信号连接线与所述控制信号线连接，另一行所述亚像素的感测晶体管的栅极通过第二控制信号连接线与所述控制信号连接；所述第一控制信号连接线与所述控制信号线同层设置且材料相同，所述第二控制信号连接线与所述数据线同层设置且材料相同；在所述栅线和所述数据线所在层之间设置有第一绝缘层，所述第二控制信号连接线通过贯穿所述第一绝缘层的过孔与所述控制信号线连接。
  11. 根据权利要求2所述的显示基板，其中，还包括多条感测信号线，且位于同一列的所述像素单元中的各所述感测晶体管的漏极连接同一所述感测线。
  12. 根据权利要求11所述的显示基板，其中，所述感测线与所述数据线同层设置且材料相同。
  13. 根据权利要求1-12中任一项所述的显示基板，其中，每个所述像素单元均包括沿所述第一方向排布的两列、沿所述第二排向排布的两行所述亚像素。
  14. 根据权利要求13所述的显示基板，其中，每个所述像素单元中的所述亚像素的有机电致发光二极管的发光颜色分别为红色、绿色、蓝色、白色。
  15. 根据权利要求1-12中任一项所述的显示基板，其中，还包括多个透光单元；在所述第一方向或所述第二方向上所述透光单元和所述像素单元交替设置。
  16. 根据权利要求1-12所述的显示基板，其中，所述开关晶体管、所述驱动晶体管、所述感测晶体管均包括依次设置在半导体有源层、栅极、同层设置的源极和漏极；在所述半导体有源层所在层与所述基底之间依次设置有遮光层和缓冲层；在所述栅极所在层与所述半导体有源层所在层之间设置有栅极绝缘层；所在所述栅极所在层与所述源极、所述漏极所在层之间设置有层间绝缘层。
  17. 根据权利要求16所述的显示基板，其中，所述存储电容包括第一电极和第二电极；所述第二电极包括第一子极板和第二子极板；所述第一电极与所述半导体有源层同层设置且材料相同；所述遮光层用作所述第一子极板；所述第二子极板与所述驱动晶体管的源极同层设置且材料相同；所述第一子极板和所述第二子极板通过贯穿所述缓冲层、所述栅极绝缘层、所述层间绝缘层的过孔连接。
  18. 根据权利要求16所述的显示基板，其中，所述像素电路中的驱动晶体管的栅极与所述开关晶体管的源极通过第一走线连接；所述驱动晶体管的源极与所述感测晶体管的源极通过第二走线连接；
    所述第一走线和所述第二走线均与所述驱动晶体管的源极同层设置且材料相同。
  19. 根据权利要求16所述的显示基板，其中，还包括辅助阴极；所述 辅助阴极包括依次设置在所述基底上的第一子结构和第二子结构；所述第一子结构与所述驱动晶体管的栅极同层设置且材料相同，所述第二子结构与所述驱动晶体管的源极同层设置且材料相同，所述第一子结构和所述第二子结构通过贯穿层间层绝缘层的过孔连接。
  20. 根据权利要求19所述的显示基板，其中，所述辅助阴极沿所述第二方向延伸，在每一列所述亚像素的一侧设置有一所述辅助阴极，且相邻列所述辅助阴极间隔一列所述亚像素。
  21. 根据权利要求16所述的显示基板，其中，在所述驱动晶体管的源极和漏极与所述有机电致发光二极管的阳极所在层之间依次设置有钝化层、转接电极、平坦化层；所述转接电极通过贯穿所述钝化层的过孔与所述驱动晶体管的漏极连接，所述有机电致发光二极管的阳极通过贯穿所述平坦化层的过孔与所述转接电极连接。
  22. 根据权利要求1-12中任一项所述的显示基板，其中，所述有机电致发光二极管为顶发射型有机电致发光二极管。
  23. 一种显示装置，其包括权利要求1-22中任一项所述的显示基板。
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