WO2021213219A1 - 编码、译码方法、装置及设备 - Google Patents

编码、译码方法、装置及设备 Download PDF

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Publication number
WO2021213219A1
WO2021213219A1 PCT/CN2021/086960 CN2021086960W WO2021213219A1 WO 2021213219 A1 WO2021213219 A1 WO 2021213219A1 CN 2021086960 W CN2021086960 W CN 2021086960W WO 2021213219 A1 WO2021213219 A1 WO 2021213219A1
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matrix
block
sub
generator
generator matrix
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PCT/CN2021/086960
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English (en)
French (fr)
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张华滋
童佳杰
王献斌
戴胜辰
李榕
王俊
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华为技术有限公司
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Priority to EP21791667.5A priority Critical patent/EP4131785A4/en
Priority to JP2022564458A priority patent/JP2023523254A/ja
Publication of WO2021213219A1 publication Critical patent/WO2021213219A1/zh
Priority to US17/969,736 priority patent/US20230058149A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/118—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/033—Theoretical methods to calculate these checking codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H03M13/1111—Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms
    • H03M13/1125—Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms using different domains for check node and bit node processing, wherein the different domains include probabilities, likelihood ratios, likelihood differences, log-likelihood ratios or log-likelihood difference pairs
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H03M13/1131—Scheduling of bit node or check node processing
    • H03M13/1137—Partly parallel processing, i.e. sub-blocks or sub-groups of nodes being processed in parallel
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit

Definitions

  • This application relates to the field of communication technology, and in particular to an encoding and decoding method, device and equipment.
  • communication equipment such as terminal equipment, base stations, etc.
  • the complexity of the codec is usually related to the code length.
  • the code length is very long (for example, the code length is greater than 16384), the complexity of encoding and decoding through polarized codes is high, resulting in poor encoding and decoding performance.
  • the embodiments of the present application provide an encoding and decoding method, device, and equipment, which reduce the complexity of encoding and decoding.
  • an embodiment of the present application provides an encoding method.
  • the method includes: obtaining K bits to be encoded, where K is a positive integer; and determining a first generator matrix, the first generator matrix including at least Two sub-blocks, the sub-blocks include multiple first generator matrix cores; according to the first generator matrix, the second generator matrix is generated, and the second generator matrix includes T sub-blocks.
  • the positional relationship is determined according to the preset positional relationship, and T is a positive integer; the K bits to be encoded are polarized encoding according to the second generating matrix to obtain the encoded bits.
  • the first generator matrix is determined first, and then the second generator matrix is generated according to the first generator matrix, and the K bits to be coded are maximized according to the second generator matrix. ⁇ coding. Since the first generator matrix includes at least two sub-blocks distributed according to a preset positional relationship, each sub-block includes a plurality of first generator matrix cores, the second generator matrix includes T sub-blocks, and adjacent ones of the T sub-blocks The positional relationship between the two sub-blocks is determined according to the preset positional relationship.
  • the second generating matrix includes a plurality of sub-blocks arranged according to the above-mentioned preset positional relationship, and each sub-block includes Multiple first generator matrix cores. Therefore, when the K bits to be encoded are polarized encoding according to the second generator matrix, it is equivalent to polar encoding multiple short codes first, and then coupling multiple short codes to obtain the encoding result, thereby reducing the encoding complexity .
  • the positional relationship between two adjacent sub-blocks among the T sub-blocks is the same as the preset positional relationship.
  • the positional relationship between the two adjacent sub-blocks in the T sub-blocks is the same as the preset positional relationship, so that the coupling mode between the short codes is the same, making the coding complexity relatively high. Low.
  • the first diagonal of the sub-block includes the first generator matrix core.
  • the multiple first generator matrix cores in the sub-block are distributed in a triangle below.
  • the distribution of the first generator matrix core in the sub-block is the same as the distribution of the first element in the second generator matrix core, and the number of elements included in the second generator matrix core is the same as that in the sub-block.
  • the number of matrix units is the same, and the matrix units included in the sub-block are the first generator matrix core or the 0 matrix.
  • the coupling method of the short code is similar to the existing coding method, which makes the coding complexity Lower.
  • the first generator matrix includes two sub-blocks.
  • the second generator matrix includes fewer sub-blocks, which makes the process of constructing the second generator matrix easier.
  • the number of matrix units included in the sub-block is 2*2, and the matrix units included in the sub-block are the first generator matrix core or the 0 matrix.
  • the first generator matrix includes a first sub-block and a second sub-block, and the first matrix unit in the first sub-block coincides with the second matrix unit in the second sub-block; wherein, The coordinates of the first matrix unit in the first sub-block are (2, 2), and the coordinates of the second matrix unit in the second sub-block are (1, 1).
  • the second generator matrix is symmetric, so that the coding complexity is low, and the decoding complexity is also low.
  • the number of matrix units included in the sub-block is 4*4, and the matrix units included in the sub-block are the first generator matrix core or the 0 matrix.
  • the first generator matrix includes a first sub-block and a second sub-block, four first matrix units in the first sub-block and four second matrix units in the second sub-block Coincidence; among them, the coordinates of the 4 first matrix units in the first sub-block are: (3,3), (3,4), (4,3), (4,4); 4 second matrices The coordinates of the unit in the second sub-block are: (1,1), (1,2), (2,1), (2,2).
  • the second generator matrix is symmetric, so that the coding complexity is low, and the decoding complexity is also low.
  • the K bits to be encoded are information bits; the K bits to be encoded are polarized encoding according to the second generating matrix to obtain the encoded bits, including: Determine the K subchannels with the highest reliability among multiple subchannels; determine the positions of K bits to be coded according to the K subchannels with the highest reliability; determine the sequence to be coded according to the positions of the K bits to be coded, and the sequence to be coded includes K Bits to be coded and frozen bits; according to the second generating matrix, polarization coding is performed on the sequence to be coded to obtain the coded bits.
  • the sub-channel with the highest reliability is selected to transmit the information bits, so that the coding performance is higher.
  • the multiple sub-channels include P groups of sub-channels, and P is a positive integer; determining the K sub-channels with the highest reliability among the multiple sub-channels corresponding to the K bits to be coded includes: set of subchannels reliability determined in the i-th set of subchannels in the first subchannel X i, X i is the i th first group of subchannels in the subchannel highest reliability subchannel X i, i is an integer, 1 ⁇ i ⁇ P, X i is a positive integer, The K sub-channels with the highest reliability include the first sub-channel.
  • an embodiment of the present application provides a decoding method, including: receiving polarization-encoded bit information; performing polarization decoding on the bit information according to a second generating matrix to obtain polarization-decoded bits; wherein , The second generator matrix is generated according to the first generator matrix, the first generator matrix includes at least two sub-blocks distributed according to a preset position relationship, the sub-block includes a plurality of first generator matrix cores, and the second generator matrix includes T Sub-blocks, the positional relationship between two adjacent sub-blocks in the T sub-blocks is determined according to the preset positional relationship, and T is a positive integer.
  • each sub-block includes multiple first generator matrix cores
  • the second generator matrix includes T sub-blocks
  • the positional relationship between two adjacent sub-blocks in the T sub-blocks is determined according to the preset positional relationship. Therefore, it can be concluded that the second generating matrix includes a plurality of sub-blocks arranged according to the above-mentioned preset positional relationship.
  • each sub-block includes multiple first generator matrix cores. Therefore, the polarization decoding of the bit information according to the second generator matrix is equivalent to decoupling multiple short codes first, and decoding the short codes after the decoupling.
  • the complexity of decoding the short codes is relatively low. Therefore, the complexity of the above-mentioned decoding is lower.
  • the positional relationship between two adjacent sub-blocks among the T sub-blocks is the same as the preset positional relationship.
  • the positional relationship between two adjacent sub-blocks in the T sub-blocks is the same as the preset positional relationship, so that the coupling mode between the short codes is the same, which makes the decoding complexity Lower.
  • the first diagonal of the sub-block includes the first generator matrix core.
  • the multiple first generator matrix cores in the sub-block are distributed in a triangle below.
  • the distribution of the first generator matrix core in the sub-block is the same as the distribution of the first element in the second generator matrix core, and the number of elements included in the second generator matrix core is the same as that in the sub-block.
  • the number of matrix units is the same, and the matrix units included in the sub-block are the first generator matrix core or the 0 matrix.
  • the coupling method of the short code is similar to the existing decoding method, making the decoding The complexity is low.
  • the first generator matrix includes two sub-blocks.
  • the second generator matrix includes fewer sub-blocks, which makes the process of constructing the second generator matrix easier.
  • the number of matrix units included in the sub-block is 2*2, and the matrix units included in the sub-block are the first generator matrix core or the 0 matrix.
  • the first generator matrix includes a first sub-block and a second sub-block, and the first matrix unit in the first sub-block coincides with the second matrix unit in the second sub-block; wherein, The coordinates of the first matrix unit in the first sub-block are (2, 2), and the coordinates of the second matrix unit in the second sub-block are (1, 1).
  • the second generator matrix is symmetric, so that the complexity of decoding is lower.
  • the number of matrix units included in the sub-block is 4*4, and the matrix units included in the sub-block are the first generator matrix core or the 0 matrix.
  • the first generator matrix includes a first sub-block and a second sub-block, four first matrix units in the first sub-block and four second matrix units in the second sub-block Coincidence; among them, the coordinates of the 4 first matrix units in the first sub-block are: (3,3), (3,4), (4,3), (4,4); 4 second matrices The coordinates of the unit in the second sub-block are: (1,1), (1,2), (2,1), (2,2).
  • the second generator matrix is symmetric, so that the complexity of decoding is lower.
  • the bit information includes N′ first log-likelihood ratio LLR sequences, and N′ is a positive integer.
  • the N′ first LLRs include T first LLR sequences, and the first LLR sequences include at least two first LLRs; polarization decoding includes: determining T first LLR sequences Corresponding to T second LLR sequences, a first LLR sequence corresponds to one or more groups of bits before encoding, and a second LLR sequence corresponds to a group of bits before encoding; polarization decoding is performed according to T second LLR sequences .
  • determining the T second LLR sequences corresponding to the T first LLR sequences includes: according to at least one of the i-th first LLR sequence and the first i-1 second LLR sequence The second LLR sequence determines the i-th second LLR sequence, where i is an integer between 2 and T.
  • the pairing is then realized.
  • the first LLR sequence is decoupled to obtain the i-th second LLR sequence.
  • the coupling degree of the code block is 2; according to the i-th first LLR sequence and at least one second LLR sequence among the first i-1 second LLR sequences, the i-th LLR sequence is determined
  • the second LLR sequence includes: determining the i-th second LLR sequence according to the i-th first LLR sequence and the i-1th second LLR sequence.
  • the first second LLR sequence is the same as the first first LLR sequence.
  • the coupling degree of the code block is 4; according to the i-th first LLR sequence and at least one second LLR sequence of the first i-1 second LLR sequences, the i-th LLR sequence is determined
  • the second LLR sequence includes: determining the i-th second LLR sequence according to the i-th first LLR sequence and the i-2th second LLR sequence, where i is an integer between 3 and T.
  • the first second LLR sequence is the same as the first first LLR sequence; the second second LLR sequence is the same as the second first LLR sequence.
  • polarization decoding can be performed according to the T second LLR sequence in the following manner: according to the T second LLR sequence, it is determined to obtain the Tth decoding result; according to the i+1th LLR sequence; At least one decoding result from the decoding result to the T-th decoding result and the i-th second LLR sequence determine the i-th decoding result, where i is an integer between 1 and T-1.
  • the decoding result can be obtained, so that the decoding complexity is low.
  • the coupling degree of the code block is 2, according to at least one decoding result from the (i+1)th decoding result to the T-th decoding result, and the i-th second LLR sequence
  • Determining the i-th decoding result includes: determining the i-th decoding result according to the i+1-th decoding result, the i+1-th first LLR sequence, and the i-th second LLR sequence.
  • an embodiment of the present application provides an encoding method.
  • the method includes: obtaining K bits to be encoded, where K is a positive integer; determining a first generator matrix, the first generator matrix including a first matrix block and a second matrix block , The first matrix block is located at the upper left corner of the first generator matrix, the second matrix block is located at the lower right corner of the first generator matrix, the first matrix block and the second matrix block are the same, along the diagonal direction of the first generator matrix, the first The distance between the first element in one matrix block and the second element in the second matrix block is u, where u is an integer greater than or equal to 1, and the second generator matrix is determined according to the coding length and the first generator matrix.
  • the second generator matrix includes T first generator matrices, the T first generator matrices are distributed along the diagonal of the second generator matrix, and the first matrix of the a+1 first generator matrix among the T first generator matrices
  • the block coincides with the second matrix block of the a-th first generator matrix, a is an integer greater than or equal to 1, and T is an integer greater than or equal to 2; according to the second generator matrix, K bits to be encoded are polarized encoding , Get the encoded bits.
  • the first generator matrix is determined first, and then the second generator matrix is generated according to the first generator matrix, and the K bits to be coded are maximized according to the second generator matrix. ⁇ coding. Since the first generator matrix has self-similarity, the second generator matrix includes multiple first matrix blocks. Therefore, when the K bits to be encoded are polarized encoding according to the second generator matrix, it is equivalent to performing multiple short codes first. Perform polarization coding, and then couple multiple short codes to obtain coding results, thereby reducing coding complexity.
  • the size of the first generator matrix is v*v
  • encoding it is equivalent to first performing polarization encoding on multiple short codes, and then coupling multiple short codes to obtain an encoding result, thereby reducing encoding complexity.
  • the elements in the first generator matrix are symmetrical along the subdiagonal line of the first generator matrix.
  • T is the smallest integer that enables the first condition to be satisfied, and the first condition is: the size of the second generator matrix is greater than or equal to the code length.
  • T satisfies the following relationship: v+(T-1)*u ⁇ N′ ⁇ v+T*u; where v is the size of the first generator matrix, N′ is the coding length, and N 'Is an integer greater than 1.
  • the size of the second generator matrix can be avoided to be too large or too small, so that the coding complexity is low.
  • an embodiment of the present application provides a decoding method, which may include: receiving polarization-encoded bit information; performing polarization decoding on the bit information according to a second generating matrix to obtain polarization-decoded bit information Bit, the second generator matrix is generated according to the first generator matrix; wherein, the first generator matrix includes a first matrix block and a second matrix block, the first matrix block is located at the upper left corner of the first generator matrix, and the second matrix block is located In the lower right corner of the first generator matrix, the first matrix block and the second matrix block are the same.
  • the second generator matrix includes T first generator matrices, and the T first generator matrices are distributed along the diagonal of the second generator matrix.
  • the first matrix block of the a+1 first generator matrix in a generator matrix coincides with the second matrix block of the a-th first generator matrix, a is an integer greater than or equal to 1, and T is greater than or equal to 2. Integer.
  • the second generator matrix since the first generator matrix has self-similarity, the second generator matrix includes a plurality of first matrix blocks, therefore. Therefore, the polarization decoding of the bit information according to the second generator matrix is equivalent to decoupling multiple short codes first, and decoding the short codes after the decoupling.
  • the complexity of decoding the short codes is relatively low. Therefore, the complexity of the above-mentioned decoding is lower.
  • the size of the first generator matrix is v*v
  • decoding decoding it is equivalent to performing polarization decoding on multiple short codes first, and then coupling multiple short codes to obtain the decoding result, thereby reducing the decoding complexity.
  • the elements in the first generator matrix are symmetrical along the subdiagonal line of the first generator matrix.
  • the decoding complexity is relatively low.
  • T is the smallest integer that enables the first condition to be satisfied, and the first condition is: the size of the second generator matrix is greater than or equal to the decoding length.
  • T satisfies the following relationship: v+(T-1)*u ⁇ N′ ⁇ v+T*u; where v is the size of the first generator matrix, and N′ is the decoding length, N'is an integer greater than 1.
  • the size of the second generator matrix can be prevented from being too large or too small, so that the decoding complexity is low.
  • the bit information includes N′ first log-likelihood ratio LLR sequences, and N′ is a positive integer.
  • the N′ first LLRs include T first LLR sequences, and the first LLR sequences include at least two first LLRs; polarization decoding includes: determining T first LLR sequences Corresponding to T second LLR sequences, a first LLR sequence corresponds to one or more groups of bits before encoding, and a second LLR sequence corresponds to a group of bits before encoding; polarization decoding is performed according to T second LLR sequences .
  • determining the T second LLR sequences corresponding to the T first LLR sequences includes: according to at least one of the i-th first LLR sequence and the first i-1 second LLR sequence The second LLR sequence determines the i-th second LLR sequence, where i is an integer between 2 and T.
  • the pairing is then realized.
  • the first LLR sequence is decoupled to obtain the i-th second LLR sequence.
  • the coupling degree of the code block is 2; according to the i-th first LLR sequence and at least one second LLR sequence among the first i-1 second LLR sequences, the i-th LLR sequence is determined
  • the second LLR sequence includes: determining the i-th second LLR sequence according to the i-th first LLR sequence and the i-1th second LLR sequence.
  • the first second LLR sequence is the same as the first first LLR sequence.
  • the coupling degree of the code block is 4; according to the i-th first LLR sequence and at least one second LLR sequence of the first i-1 second LLR sequences, the i-th LLR sequence is determined
  • the second LLR sequence includes: determining the i-th second LLR sequence according to the i-th first LLR sequence and the i-2th second LLR sequence, where i is an integer between 3 and T.
  • the first second LLR sequence is the same as the first first LLR sequence; the second second LLR sequence is the same as the second first LLR sequence.
  • polarization decoding can be performed according to the T second LLR sequence in the following manner: according to the T second LLR sequence, it is determined to obtain the Tth decoding result; according to the i+1th LLR sequence; At least one decoding result from the decoding result to the T-th decoding result and the i-th second LLR sequence determine the i-th decoding result, where i is an integer between 1 and T-1.
  • the decoding result can be obtained, so that the decoding complexity is low.
  • the coupling degree of the code block is 2, according to at least one decoding result from the (i+1)th decoding result to the T-th decoding result, and the i-th second LLR sequence
  • Determining the i-th decoding result includes: determining the i-th decoding result according to the i+1-th decoding result, the i+1-th first LLR sequence, and the i-th second LLR sequence.
  • an embodiment of the present application provides an encoding device, including an acquisition module, a determination module, a generation module, and an encoding module, where:
  • the obtaining module is configured to obtain K bits to be coded, where K is a positive integer
  • the determining module is configured to determine a first generator matrix, where the first generator matrix includes at least two sub-blocks distributed according to a preset position relationship, and the sub-block includes a plurality of first generator matrix cores;
  • the generating module is configured to generate a second generating matrix according to the first generating matrix, the second generating matrix including T sub-blocks, and the positional relationship between two adjacent sub-blocks in the T sub-blocks is Determined according to the preset positional relationship, the T is a positive integer;
  • the encoding module is configured to perform polarization encoding on the K to-be-encoded bits according to the second generating matrix to obtain encoded bits.
  • the positional relationship between two adjacent sub-blocks in the T sub-blocks is the same as the preset positional relationship.
  • the first diagonal of the sub-block includes the first generator matrix core.
  • the multiple first generator matrix cores in the sub-block are distributed in a triangle below.
  • the distribution of the first generator matrix core in the sub-block is the same as the distribution of the first element in the second generator matrix core, and the number of elements included in the second generator matrix core is equal to The number of matrix units included in the sub-blocks is the same, and the matrix units included in the sub-blocks are the first generator matrix core or the 0 matrix.
  • the first generator matrix includes two sub-blocks.
  • the number of matrix units included in the sub-block is 2*2, and the matrix units included in the sub-block are the first generator matrix core or the 0 matrix.
  • the first generator matrix includes a first sub-block and a second sub-block, and the first matrix unit in the first sub-block and the second sub-block in the second sub-block are The matrix units coincide;
  • the coordinates of the first matrix unit in the first sub-block are (2, 2), and the coordinates of the second matrix unit in the second sub-block are (1, 1).
  • the number of matrix units included in the sub-block is 4*4, and the matrix units included in the sub-block are the first generator matrix core or the 0 matrix.
  • the first generator matrix includes a first sub-block and a second sub-block, and the four first matrix units in the first sub-block and the second sub-block in the The 4 second matrix units overlap; among them,
  • the coordinates of the four first matrix units in the first sub-block are: (3,3), (3,4), (4,3), (4,4);
  • the coordinates of the four second matrix units in the second sub-block are respectively: (1,1), (1,2), (2,1), (2,2).
  • the K bits to be encoded are information bits; the encoding module is specifically configured to:
  • the multiple sub-channels include P groups of sub-channels, and the P is a positive integer;
  • the encoding module is specifically configured to:
  • the reliability of the sub-group i, determining X i in the i-th first sub-set of subchannels in the first subchannel X i is the i-th set of subchannels highest reliability X i subchannels ,
  • the i is an integer, 1 ⁇ i ⁇ P, the X i is a positive integer,
  • the K subchannels with the highest reliability include the first subchannel.
  • an embodiment of the present application provides a decoding device, including a receiving module and a decoding module, where:
  • the receiving module is configured to receive polarization-encoded bit information
  • the decoding module is configured to perform polarization decoding on the bit information according to a second generating matrix to obtain polarization decoded bits
  • the second generator matrix is generated according to the first generator matrix
  • the first generator matrix includes at least two sub-blocks distributed according to a preset position relationship
  • the sub-block includes a plurality of first generator matrix cores
  • the second generating matrix includes T sub-blocks, the positional relationship between two adjacent sub-blocks in the T sub-blocks is determined according to the preset positional relationship, and the T is a positive integer.
  • the positional relationship between two adjacent sub-blocks in the T sub-blocks is the same as the preset positional relationship.
  • the first diagonal of the sub-block includes the first generator matrix core.
  • the multiple first generator matrix cores in the sub-block are distributed in a triangle below.
  • the distribution of the first generator matrix core in the sub-block is the same as the distribution of the first element in the second generator matrix core, and the number of elements included in the second generator matrix core is equal to The number of elements included in the sub-blocks is the same, and the elements included in the sub-blocks are the first generator matrix core or the 0 matrix.
  • the first generator matrix includes two sub-blocks.
  • the number of elements included in the sub-block is 2*2, and the elements included in the sub-block are the first generator matrix core or the 0 matrix.
  • the first generator matrix includes a first sub-block and a second sub-block, and the first element in the first sub-block and the second element in the second sub-block are coincide;
  • the coordinates of the first element in the first sub-block are (2, 2), and the coordinates of the second element in the second sub-block are (1, 1).
  • the number of elements included in the sub-block is 4*4, and the elements included in the sub-block are the first generator matrix core or the 0 matrix.
  • the first generating matrix includes a first sub-block and a second sub-block, and the four first elements in the first sub-block and the four in the second sub-block are Two second elements coincide; among them,
  • the coordinates of the four first elements in the first sub-block are: (3,3), (3,4), (4,3), (4,4);
  • the coordinates of the four second elements in the second sub-block are respectively: (1,1), (1,2), (2,1), (2,2).
  • the bit information includes N′ first log-likelihood ratio LLR sequences, and the N′ is a positive integer.
  • the N′ first LLRs include T first LLR sequences, and the first LLR sequences include at least two first LLRs; the decoding module is specifically configured to:
  • T second LLR sequences corresponding to the T first LLR sequences one of the first LLR sequences corresponds to one or more sets of bits before encoding, and one of the second LLR sequences corresponds to a set of bits before encoding ;
  • the decoding module is specifically configured to:
  • the coupling degree of the code block is 2; the decoding module is specifically configured to:
  • the i-th second LLR sequence is determined according to the i-th first LLR sequence and the i-1th second LLR sequence.
  • the first second LLR sequence is the same as the first first LLR sequence.
  • the coupling degree of the code block is 4; the decoding module is specifically configured to:
  • the i-th second LLR sequence is determined according to the i-th first LLR sequence and the i-2th second LLR sequence, and the i is an integer between 3 and T.
  • the first second LLR sequence is the same as the first first LLR sequence
  • the second second LLR sequence is the same as the second first LLR sequence.
  • the decoding module is specifically configured to:
  • the coupling degree of the code block is 2; the decoding module is specifically configured to:
  • the i-th decoding result is determined according to the i+1-th decoding result, the i+1-th first LLR sequence, and the i-th second LLR sequence.
  • an embodiment of the present application provides an encoding device, including an acquisition module, a determination module, a generation module, and an encoding module, where:
  • the obtaining module is configured to obtain K bits to be coded, where K is a positive integer
  • the determining module is configured to determine a first generator matrix.
  • the first generator matrix includes a first matrix block and a second matrix block.
  • the first matrix block is located at the upper left corner of the first generator matrix.
  • the two matrix blocks are located at the lower right corner of the first generator matrix.
  • the first matrix block and the second matrix block are the same.
  • the distance between the first element and the second element in the second matrix block is u, and the u is an integer greater than or equal to 1;
  • the generating module is configured to generate a second generator matrix according to the coding length and the first generator matrix.
  • the second generator matrix includes T first generator matrices, and the T first generator matrices are The diagonal distribution of the second generator matrix, the first matrix block of the a+1-th first generator matrix in the T first generator matrices coincides with the second matrix block of the a-th first generator matrix ,
  • the a is an integer greater than or equal to 1
  • the T is an integer greater than or equal to 2;
  • the encoding module is configured to perform polarization encoding on the K to-be-encoded bits according to the second generating matrix to obtain encoded bits.
  • the i is an integer
  • the j is an integer
  • the v is a positive integer
  • the u is an integer, 1 ⁇ i ⁇ v, 1 ⁇ j ⁇ v, 1 ⁇ i+u ⁇ v, 1 ⁇ j+u ⁇ v.
  • the elements in the first generator matrix are symmetrical along a subdiagonal line of the first generator matrix.
  • T is the smallest integer that enables the first condition to be satisfied, and the first condition is: the size of the second generator matrix is greater than or equal to the code length.
  • the T satisfies the following relationship:
  • the v is the size of the first generator matrix
  • the N′ is the coding length
  • the N′ is an integer greater than 1.
  • an embodiment of the present application provides a decoding device, including a receiving module and a decoding module, where:
  • the receiving module is configured to receive polarization-encoded bit information
  • the decoding module is configured to perform polarization decoding on the bit information according to a second generating matrix to obtain polarized decoded bits, and the second generating matrix is generated according to the first generating matrix;
  • the first generator matrix includes a first matrix block and a second matrix block, the first matrix block is located at the upper left corner of the first generator matrix, and the second matrix block is located at the upper left corner of the first generator matrix.
  • the first matrix block and the second matrix block are the same, and along the diagonal direction of the first generator matrix, the first element in the first matrix block is the same as that in the second matrix block.
  • the distance between the second elements of is u, and the u is an integer greater than or equal to 1;
  • the second generator matrix includes T first generator matrices, the T first generator matrices are distributed along the diagonal of the second generator matrix, and the T first generator matrices are The first matrix block of the a+1th first generator matrix coincides with the second matrix block of the ath first generator matrix, where a is an integer greater than or equal to 1, and the T is an integer greater than or equal to 2 .
  • the i is an integer
  • the j is an integer
  • the v is a positive integer
  • the u is an integer, 1 ⁇ i ⁇ v, 1 ⁇ j ⁇ v, 1 ⁇ i+u ⁇ v, 1 ⁇ j+u ⁇ v.
  • the elements in the first generator matrix are symmetrical along a subdiagonal line of the first generator matrix.
  • T is the smallest integer that enables the first condition to be satisfied, and the first condition is: the size of the second generator matrix is greater than or equal to the code length.
  • the T satisfies the following relationship:
  • the v is the size of the first generator matrix
  • the N′ is the coding length
  • the N′ is an integer greater than 1.
  • the bit information includes N′ first log-likelihood ratio LLR sequences, and the N′ is a positive integer.
  • the N′ first LLRs include T first LLR sequences, and the first LLR sequences include at least two first LLRs; the decoding module is specifically configured to:
  • T second LLR sequences corresponding to the T first LLR sequences one of the first LLR sequences corresponds to one or more sets of bits before encoding, and one of the second LLR sequences corresponds to a set of bits before encoding ;
  • the decoding module is specifically configured to:
  • the coupling degree of the code block is 2; the decoding module is specifically configured to:
  • the i-th second LLR sequence is determined according to the i-th first LLR sequence and the i-1th second LLR sequence.
  • the first second LLR sequence is the same as the first first LLR sequence.
  • the coupling degree of the code block is 4; the decoding module is specifically configured to:
  • the i-th second LLR sequence is determined according to the i-th first LLR sequence and the i-2th second LLR sequence, and the i is an integer between 3 and T.
  • the first second LLR sequence is the same as the first first LLR sequence
  • the second second LLR sequence is the same as the second first LLR sequence.
  • the decoding module is specifically configured to:
  • the coupling degree of the code block is 2; the decoding module is specifically configured to:
  • the i-th decoding result is determined according to the i+1-th decoding result, the i+1-th first LLR sequence, and the i-th second LLR sequence.
  • an embodiment of the present application provides an encoding device, including: a memory, a processor, and a computer program.
  • the computer program is stored in the memory, and the processor runs the computer program to execute any of the computer programs as in the first aspect.
  • an embodiment of the present application provides an encoding device, including: a memory, a processor, and a computer program.
  • the computer program is stored in the memory, and the processor runs the computer program to execute any of the operations as in the second aspect.
  • an embodiment of the present application provides an encoding device, including: a memory, a processor, and a computer program.
  • the computer program is stored in the memory, and the processor runs the computer program to execute the computer program as in the third aspect. Any one of the encoding methods.
  • an embodiment of the present application provides an encoding device, including: a memory, a processor, and a computer program, the computer program is stored in the memory, and the processor runs the computer program to execute as in the fourth aspect Any one of the decoding methods.
  • an embodiment of the present application provides a storage medium, where the storage medium includes a computer program, and the computer program is used to implement the encoding method according to any one of the first aspect.
  • an embodiment of the present application provides a storage medium, where the storage medium includes a computer program, and the computer program is used to implement the decoding method according to any one of the second aspects.
  • an embodiment of the present application provides a storage medium, the storage medium includes a computer program, and the computer program is used to implement the encoding method according to any one of the third aspect.
  • an embodiment of the present application provides a storage medium, where the storage medium includes a computer program, and the computer program is used to implement the decoding method according to any one of the fourth aspect.
  • an embodiment of the present application provides an encoding device, which may include an input interface and a logic circuit, where:
  • the input interface is used to obtain K bits to be encoded, where K is a positive integer;
  • the logic circuit is configured to determine a first generator matrix, the first generator matrix includes at least two sub-blocks distributed according to a preset positional relationship, and the sub-block includes a plurality of first generator matrix cores;
  • a first generator matrix generates a second generator matrix, the second generator matrix includes T sub-blocks, and the positional relationship between two adjacent sub-blocks in the T sub-blocks is determined according to the preset positional relationship,
  • the T is a positive integer;
  • the K bits to be encoded are polarized encoding according to the second generating matrix to obtain encoded bits.
  • the logic circuit may also execute the encoding method described in any one of the first aspect.
  • an embodiment of the present application provides a decoding device.
  • the decoding device may include an input interface and a logic circuit, where:
  • the input interface is used to receive polarization-encoded bit information
  • the logic circuit is configured to perform polarization decoding on the bit information according to a second generating matrix to obtain polarization decoded bits; wherein, the second generating matrix is generated according to the first generating matrix, so
  • the first generator matrix includes at least two sub-blocks distributed according to a preset position relationship, the sub-block includes a plurality of first generator matrix cores, the second generator matrix includes T sub-blocks, and in the T sub-blocks The positional relationship between two adjacent sub-blocks is determined according to the preset positional relationship, and the T is a positive integer.
  • the logic circuit may also execute the decoding method described in any one of the second aspect.
  • an embodiment of the present application provides a schematic structural diagram of an encoding device.
  • the encoding device may include an input interface and a logic circuit, where:
  • the input interface is used to obtain K bits to be encoded, where K is a positive integer;
  • the logic circuit is configured to determine a first generator matrix.
  • the first generator matrix includes a first matrix block and a second matrix block.
  • the first matrix block is located at the upper left corner of the first generator matrix.
  • the two matrix blocks are located at the lower right corner of the first generator matrix.
  • the first matrix block and the second matrix block are the same.
  • the distance between the first element and the second element in the second matrix block is u, where u is an integer greater than or equal to 1, and the second generator matrix is determined according to the coding length and the first generator matrix
  • the second generator matrix includes T first generator matrices, the T first generator matrices are distributed along the diagonal of the second generator matrix, and the ath of the T first generator matrices
  • the first matrix block of the +1 first generator matrix coincides with the second matrix block of the a-th first generator matrix, where a is an integer greater than or equal to 1, and the T is an integer greater than or equal to 2; according to The second generating matrix performs polarization encoding on the K to-be-encoded bits to obtain encoded bits.
  • the logic circuit may also execute the encoding method described in any one of the third aspect.
  • an embodiment of the present application provides a decoding device.
  • the decoding device may include an input interface and a logic circuit, where:
  • the input interface is used to receive polarization-encoded bit information
  • the logic circuit is configured to perform polarization decoding on the bit information according to a second generator matrix to obtain polarized decoded bits, and the second generator matrix is generated according to the first generator matrix; wherein,
  • the first generator matrix includes a first matrix block and a second matrix block, the first matrix block is located at the upper left corner of the first generator matrix, and the second matrix block is located at the lower right corner of the first generator matrix,
  • the first matrix block and the second matrix block are the same, and along the diagonal direction of the first generator matrix, the first element in the first matrix block is the same as the second element in the second matrix block.
  • the distance between the elements is u, and the u is an integer greater than or equal to 1; wherein, the second generating matrix includes T first generating matrices, and the T first generating matrices are along the first generating matrix.
  • the diagonal distribution of the second generator matrix, the first matrix block of the a+1-th first generator matrix in the T first generator matrices coincides with the second matrix block of the a-th first generator matrix, the a is an integer greater than or equal to 1, and the T is an integer greater than or equal to 2.
  • the logic circuit may also execute the decoding method described in any one of the fourth aspect.
  • the embodiments of the application provide an encoding and decoding method, device, and equipment method.
  • a first generator matrix is determined first, and then a second generator matrix is generated according to the first generator matrix, and Perform polarization coding on the K bits to be coded according to the second generating matrix.
  • the first generator matrix includes at least two sub-blocks distributed according to a preset positional relationship, each sub-block includes a plurality of first generator matrix cores, the second generator matrix includes T sub-blocks, and adjacent ones of the T sub-blocks The positional relationship between the two sub-blocks is determined according to the preset positional relationship.
  • the second generating matrix includes a plurality of sub-blocks arranged according to the above-mentioned preset positional relationship, and each sub-block includes Multiple first generator matrix cores. Therefore, when the K bits to be encoded are polarized encoding according to the second generator matrix, it is equivalent to polar encoding multiple short codes first, and then coupling multiple short codes to obtain the encoding result, thereby reducing the encoding complexity .
  • the complexity of decoding can be reduced.
  • Figure 1 is an architecture diagram of the communication system provided by this application.
  • Figure 2 is a coding diagram provided by an embodiment of the application.
  • FIG. 3 is a schematic flowchart of an encoding method provided by an embodiment of the application.
  • FIG. 4 is a schematic diagram of sub-blocks provided by an embodiment of the application.
  • FIG. 5A is a schematic diagram of a first generating matrix provided by an embodiment of this application.
  • FIG. 5B is a schematic diagram of another first generating matrix provided by an embodiment of this application.
  • FIG. 5C is a schematic diagram of yet another first generating matrix provided by an embodiment of this application.
  • FIG. 6A is a schematic diagram of a second generating matrix provided by an embodiment of this application.
  • 6B is a schematic diagram of another second generating matrix provided by an embodiment of this application.
  • FIG. 6C is a schematic diagram of still another second generating matrix provided by an embodiment of this application.
  • FIG. 7A is a schematic diagram of a third generating matrix provided by an embodiment of this application.
  • FIG. 7B is a schematic diagram of a third generating matrix provided by an embodiment of this application.
  • FIG. 8A is a schematic diagram of a decoding process provided by an embodiment of this application.
  • FIG. 8B is a schematic diagram of another decoding process provided by an embodiment of this application.
  • FIG. 9A is another encoding diagram provided by an embodiment of this application.
  • FIG. 9B is another encoding diagram provided by an embodiment of this application.
  • FIG. 9C is another encoding diagram provided by an embodiment of this application.
  • FIG. 10 is a schematic flowchart of another encoding method provided by an embodiment of this application.
  • FIG. 11A is a schematic diagram of a first generating matrix provided by an embodiment of this application.
  • FIG. 11B is a schematic diagram of still another first generating matrix provided by an embodiment of this application.
  • FIG. 11C is a schematic diagram of another first generating matrix provided by an embodiment of this application.
  • FIG. 12A is a schematic diagram of still another first generating matrix provided by an embodiment of this application.
  • FIG. 12B is a schematic diagram of still another first generating matrix provided by an embodiment of this application.
  • FIG. 13 is a schematic diagram of another second generating matrix provided by an embodiment of this application.
  • FIG. 14 is a schematic diagram of a process of generating a second generator matrix according to an embodiment of the application.
  • FIG. 15A is a schematic diagram of a second generating matrix provided by an embodiment of this application.
  • 15B is a schematic diagram of another second generating matrix provided by an embodiment of this application.
  • 15C is a schematic diagram of a second generating matrix provided by an embodiment of this application.
  • FIG. 16 is a schematic diagram of decoding provided by an embodiment of this application.
  • FIG. 17 is a schematic diagram of a decoding process provided by an embodiment of this application.
  • FIG. 18 is a schematic diagram of a decoding process provided by an embodiment of this application.
  • FIG. 19 is a schematic diagram of decoding performance provided by an embodiment of this application.
  • 20A is a schematic diagram of another decoding performance provided by an embodiment of this application.
  • 20B is a schematic diagram of another decoding performance provided by an embodiment of this application.
  • FIG. 21 is a schematic structural diagram of an encoding device provided by an embodiment of this application.
  • FIG. 22 is a schematic structural diagram of a decoding device provided by an embodiment of this application.
  • FIG. 23 is a schematic structural diagram of another encoding device provided by an embodiment of this application.
  • FIG. 24 is a schematic structural diagram of another decoding device provided by an embodiment of this application.
  • 25 is a schematic diagram of the hardware structure of an encoding device provided by an embodiment of the application.
  • FIG. 26 is a schematic diagram of the hardware structure of a decoding device provided by an embodiment of the application.
  • FIG. 27 is a schematic structural diagram of another encoding device provided by an embodiment of this application.
  • FIG. 28 is a schematic structural diagram of another decoding device provided by an embodiment of this application.
  • FIG. 29 is a schematic structural diagram of another encoding device provided by an embodiment of this application.
  • FIG. 30 is a schematic structural diagram of another decoding device provided by an embodiment of this application.
  • the embodiments of the present application can be applied to various fields that adopt Polar coding, such as: data storage field, optical network communication field, wireless communication field, and so on.
  • the wireless communication systems mentioned in the embodiments of this application include but are not limited to: narrowband-internet of things (NB-IoT), Wimax, long-term evolution (LTE), and next-generation 5G Three application scenarios of the new radio (NR) of the mobile communication system Enhanced mobile broadband (eMBB), ultra-reliable and low-latency communication (URLLC), and large-scale machines Communications (massive machine-type communications, mMTC).
  • NB-IoT narrowband-internet of things
  • LTE long-term evolution
  • 5G Three application scenarios of the new radio (NR) of the mobile communication system Enhanced mobile broadband (eMBB), ultra-reliable and low-latency communication (URLLC), and large-scale machines Communications (massive machine-type communications, mMTC).
  • eMBB new radio
  • URLLC ultra-reliable and low-late
  • the embodiments of this application are suitable for communication scenarios with a long code length, for example, including but not limited to large-throughput business scenarios, high-definition video business scenarios, large file transmission business scenarios, virtual reality (VR)/augmented reality ( Multimedia services such as augmented reality (AR for short), and automatic hybrid repeat request (HARQ) of wireless communication, etc.
  • large-throughput business scenarios high-definition video business scenarios
  • high-definition video business scenarios large file transmission business scenarios
  • VR virtual reality
  • augmented reality Multimedia services such as augmented reality (AR for short)
  • HARQ automatic hybrid repeat request
  • Figure 1 is an architecture diagram of the communication system provided by this application. Please refer to Fig. 1, which includes a sending device 101 and a receiving device 102.
  • the receiving device 102 is a network device.
  • the sending device 101 is a network device
  • the receiving device 102 is a terminal device.
  • the sending device 101 includes an encoder, so that the sending device 101 can perform polar encoding and output an encoded sequence.
  • the encoded sequence is transmitted to the receiving device 102 on the channel after rate matching, interleaving, and modulation.
  • the receiving device 102 includes a decoder, and the receiving device 102 can receive a signal sent by the sending device 101 and decode the received signal.
  • FIG. 1 merely illustrates an architecture diagram of a communication system in the form of an example, and is not a limitation on the architecture diagram of the communication system.
  • Terminal equipment including but not limited to mobile station (MS), mobile terminal (MT), mobile phone (mobile telephone, MT), mobile phone (handset) and portable equipment (portable equipment), etc., the terminal equipment It can communicate with one or more core networks via a radio access network (RAN).
  • RAN radio access network
  • the terminal device may be a mobile phone (or called a "cellular" phone), a computer with wireless communication function, etc.
  • the terminal device may also be a portable, pocket-sized, handheld, built-in computer or vehicle-mounted mobile device or device.
  • Network equipment It can be an evolutional node B (eNB or eNodeB) in the LTE system, or it can be a gNB or a transmission and reception point (TRP) in a 5G communication system, a micro base station, etc. , Or the network equipment can be relay stations, access points, in-vehicle equipment, wearable devices, and network equipment in the public land mobile network (PLMN) that will evolve in the future, or in a network where multiple technologies are converged, Or base stations in various other evolved networks, etc.
  • eNB evolutional node B
  • TRP transmission and reception point
  • PLMN public land mobile network
  • Polarization coding can also become polar coding. Polar coding can be described in the following two ways:
  • the encoding process can be represented by a generator matrix, that is,
  • N is the code length, and N is an integer greater than or equal to 1.
  • u i is the bit before encoding, i is an integer between 1 and N. It includes information bits and/or frozen bits, that is, u i can be information bits or frozen bits.
  • Information bits are bits used to carry information, and the information bits may include Cyclic Redundancy Check (CRC) bits and/or Parity Check (PC) bits.
  • CRC Cyclic Redundancy Check
  • PC Parity Check
  • G N is the generator matrix
  • G N is the N*N matrix
  • B N is an N*N transposed matrix
  • B N may be a bit reversal matrix
  • the above mentioned addition and multiplication are all operations on the binary Galois field (galois field).
  • G N can also be referred to as a generator matrix core.
  • the coding process can be represented by a coding diagram.
  • Figure 2 is a coding diagram provided by an embodiment of the application.
  • the encoding code length corresponding to the encoding diagram is 8, each circle in the first column represents an information bit or a frozen bit, and u 1 , u 2 ,..., u 8 in the first column are before encoding Of bits (information bits or frozen bits), where u 4 , u 6 , u 7 , and u 8 are information bits, and u 1 , u 2 , u 3 , and u 5 are frozen bits.
  • Each circle in the columns except the first column represents a partial sum bit.
  • the x 1 , x 2 ,..., x 8 in the last column are the encoded bits.
  • Each butterfly diagram (shown on the right in the figure) represents a polarization of 2 bits, that is,
  • an embodiment of the present application provides an encoding method.
  • the generator matrix corresponding to the short code can be processed to obtain the final generator matrix, and polarization encoding is performed according to the final generator matrix. Yu firstly performs polarization coding on multiple short codes, and then couples multiple short codes to obtain coding results, thereby reducing coding complexity.
  • the starting coordinates in the matrix are (1, 1) as an example for description.
  • the starting coordinates in the matrix can also be (0, 0), the embodiment of the present application does not specifically limit this.
  • FIG. 3 is a schematic flowchart of an encoding method provided by an embodiment of the application. See Figure 3. The method can include:
  • K is a positive integer.
  • the K bits to be encoded include information bits and frozen bits. Or, all the K bits to be encoded are information bits.
  • the first generator matrix includes at least two sub-blocks distributed according to a preset position relationship, and the sub-block includes a plurality of first generator matrix cores.
  • the first generator matrix core may be G N.
  • N 2 n , where n is a positive integer.
  • the size of N can be set according to actual needs, for example, N can be a preset value.
  • the sub-block may include the first generator matrix core and the 0 matrix (which can be expressed as 0 N ).
  • the size of the first generator matrix core is the same as the size of the 0 matrix. For example, if the size of the first generator matrix core is N*N, the size of the 0 matrix is also N*N.
  • the first generator matrix core or the 0 matrix is referred to as a matrix unit.
  • the size of the matrix refers to the number of rows and columns in the matrix.
  • the size of the matrix can be expressed by M*N (M is the number of rows in the matrix, and N is the number of columns in the matrix).
  • M is the number of rows in the matrix
  • N is the number of columns in the matrix.
  • the size of the matrix can be expressed by the number of rows or columns.
  • the size of the matrix can be expressed by N*N, or by N Indicates the size of the matrix.
  • Fig. 4 is a schematic diagram of sub-blocks provided by an embodiment of the application. Please refer to FIG. 4, the sub-block includes multiple matrix units, and FIG. 4 takes 16 matrix units as an example for illustration.
  • Each matrix unit includes N*N elements, for example, the elements can be 0 or 1.
  • the matrix unit can be G N or 0 N. Assuming that N is equal to 2, then
  • the first diagonal of the sub-block includes a first generator matrix kernel (G N ).
  • the first diagonal may be the main diagonal of the sub-block.
  • the matrix unit on the main diagonal of the sub-block is G N , such as the (1,1), (2,2), (3,3), (4,4)th matrix
  • the unit is G N.
  • the multiple first generator matrix cores in the sub-block are distributed in a triangle below.
  • multiple G N in the sub-block are distributed below the triangle.
  • the distribution of the first generator matrix core in the sub-block is the same as the distribution of the first element in the second generator matrix core, and the first element may be 1.
  • the element distribution in the core of the second generator matrix satisfies
  • the number of elements in the second generator matrix core and the number of elements in the first generator matrix core may be the same or different.
  • the distribution of G N in the sub-block is the same as the distribution of 1 in the second generator matrix core, and correspondingly, the distribution of 0 N in the sub-block is the same as the distribution of 0 in the second generator matrix core.
  • Example 1 assuming that the second generator matrix core is Then the sub-block can be The number of matrix units included in the sub-block is 2*2. Among them, the distribution of G N in the sub-block is the same as the distribution of element 1 in the second generator matrix core.
  • the sub-block can be obtained as:
  • the sub-block can be obtained as:
  • Example 2 Assuming that the second generator matrix core is Then the sub-block can be The distribution of G N in the sub-block is the same as the distribution of element 1 in the second generator matrix core.
  • the sub-block can be obtained as:
  • the first generating matrix includes at least two sub-blocks distributed according to a preset position relationship.
  • the number of sub-blocks included in the first generating matrix may be two.
  • overlapping parts in at least two sub-blocks in the first generator matrix there are overlapping parts in at least two sub-blocks in the first generator matrix.
  • every two adjacent sub-blocks in the first generator matrix have overlapping parts.
  • the two adjacent sub-blocks are sub-block 1 and sub-block 2, respectively.
  • the element in the lower right corner area of sub-block 1 is the same as sub-block 2.
  • the elements in the upper left corner of the area overlap.
  • the preset positional relationship may be: sub-block 1 is located in the upper left part of the first generator matrix, and sub-block 2 is located in the first In the lower right part of the generator matrix, the lower right corner area of sub-block 1 coincides with the upper left corner area of sub-block 2.
  • FIG. 5A is a schematic diagram of a first generating matrix provided by an embodiment of this application.
  • FIG. 5B is a schematic diagram of another first generating matrix provided by an embodiment of this application.
  • FIG. 5C is a schematic diagram of still another first generating matrix provided by an embodiment of this application.
  • the first generating matrix includes two sub-blocks, which are respectively denoted as the first sub-block and the second sub-block, and the first sub-block and the second sub-block are the same.
  • the first sub-block is located in the upper left part of the first generator matrix
  • the second sub-block is located in the lower right part of the first generator matrix.
  • the lower-right corner area of the first sub-block overlaps with the upper-left corner area of the second sub-block, and the elements in the lower-right corner area of the first sub-block have the same distribution of elements in the upper-left corner area of the second sub-block.
  • the first generator matrix includes the first sub-block and the second sub-block, and the first sub-block and the second sub-block are respectively Then the first generator matrix can be
  • the first sub-block is located in the upper left part of the first generator matrix
  • the second sub-block is located in the lower right part of the first generator matrix.
  • the first matrix unit in the first sub-block coincides with the second matrix unit in the second sub-block.
  • the coordinates of the first matrix unit in the first sub-block are (2, 2), and the coordinates of the second matrix unit in the second sub-block are (1, 1).
  • the first generator matrix includes the first sub-block and the second sub-block, and the first sub-block and the second sub-block are respectively Then the first generator matrix can be The first sub-block is located in the upper left part of the first generator matrix, and the second sub-block is located in the lower right part of the first generator matrix.
  • the four first matrix units in the first sub-block overlap with the four second matrix units in the second sub-block.
  • the coordinates of the 4 first matrix units in the first sub-block are: (3,3), (3,4), (4,3), (4,4); the 4 second matrix units are in the second
  • the coordinates in the sub-block are: (1,1), (1,2), (2,1), (2,2).
  • FIG labeled 0 N omitted i.e., the blank of FIG. 5B- FIG. 5C are 0 N unit matrix.
  • the second generating matrix includes T sub-blocks, the positional relationship between two adjacent sub-blocks in the T sub-blocks is determined according to a preset positional relationship, and T is a positive integer.
  • the positional relationship between two adjacent sub-blocks in the T sub-blocks is the same as the preset positional relationship.
  • the number T of sub-blocks included in the second generator matrix can be determined according to the first generator matrix, the size of the sub-block and the coding length N′, and the second generator matrix can be generated according to the first generator matrix and the number T.
  • T is the smallest integer that satisfies the first condition
  • the first condition is that the size of the second generator matrix is greater than or equal to the code length.
  • the second generator matrix is a square matrix, and the size of the second generator can be represented by the number of rows or columns included in the second generator matrix, that is, the size of the second generator matrix is the number of rows or columns included in the second generator matrix .
  • T satisfies the following relationship:
  • v is the size of the sub-block (the sub-block is a square matrix, and v represents the number of rows or columns of elements included in the sub-block).
  • N' is the code length, and N'is an integer greater than one.
  • u is the distance between two adjacent sub-blocks, which can pass through the distance between the first element in two adjacent sub-blocks (for example, the first element can be an element with coordinates (1,1) in the sub-block) (Difference of row number or difference of column number) represents the distance between two adjacent sub-blocks.
  • T 7.
  • T is 5.
  • FIG. 6A is a schematic diagram of a second generating matrix provided by an embodiment of this application.
  • the first generator matrix includes two sub-blocks, each sub-block includes 16 matrix units, some of the matrix units are G N , and some of the matrix units are 0 N.
  • the positional relationship of the two sub-blocks is shown in Figure 6A.
  • the second generator matrix includes 7 sub-blocks, which are respectively denoted as sub-block 1, sub-block 2, ..., sub-block 6, and sub-block 7.
  • the positional relationship between every two adjacent sub-blocks in the 7 sub-blocks is the same as the positional relationship between the two sub-blocks in the first generating matrix.
  • the size of the second generator matrix (the number of rows or columns included in the second generator matrix) is 2048.
  • FIG. 6B is a schematic diagram of another second generating matrix provided by an embodiment of this application. Referring to FIG. 6B, it is assumed that the first generator matrix includes two sub-blocks, each sub-block includes 16 matrix units, some of the matrix units are G N , and some of the matrix units are 0 N. The positional relationship of the two sub-blocks is shown in Figure 6B.
  • the second generating matrix includes 5 sub-blocks, which are respectively denoted as sub-block 1, sub-block 2, sub-block 3, sub-block 4, and sub-block 5.
  • the positional relationship between every two adjacent sub-blocks in the 5 sub-blocks It is the same as the positional relationship between the two sub-blocks in the first generator matrix.
  • the size of the second generator matrix (the number of rows or columns included in the second generator matrix) is 1536.
  • FIG. 6C is a schematic diagram of still another second generating matrix provided by an embodiment of this application.
  • the first generator matrix includes two sub-blocks, each sub-block includes 4 matrix units, some of the matrix units are G N , and some of the matrix units are 0 N.
  • the positional relationship of the two sub-blocks is shown in Figure 6C.
  • the second generator matrix includes 7 sub-blocks, which are respectively denoted as sub-block 1, sub-block 2, ..., sub-block 6, and sub-block 7.
  • the positional relationship between every two adjacent sub-blocks in the 7 sub-blocks is the same as the positional relationship between the two sub-blocks in the first generating matrix.
  • the size of the second generator matrix (the number of rows or columns included in the second generator matrix) is 1024.
  • the matrix units except G N are all 0 N.
  • the mark of 0 N is omitted in the figure, that is, the blanks in FIGS. 6A-6C
  • the matrix units are all 0 N.
  • FIGS. 6A-6C are only illustrative of the second generator matrix in the form of examples, and are not a limitation on the second generator matrix.
  • the second generator matrix may also be other. limited.
  • the K bits to be coded are subjected to polarization coding according to the second generating matrix to obtain the coded bits.
  • the third generator matrix is a matrix truncated in the upper left corner area of the second generator matrix, or the third generator matrix is a matrix truncated in the lower right corner area of the second generator matrix.
  • the third generator matrix is a square matrix.
  • FIG. 7A is a schematic diagram of a third generating matrix provided by an embodiment of this application. Referring to FIG. 7A, assuming that the coding level is 1500 and the size of the second generator matrix is 1536, a matrix with a size of 1500 can be intercepted in the upper left corner area of the second generator matrix as the third generator matrix.
  • FIG. 7B is a schematic diagram of a third generating matrix provided by an embodiment of this application. Referring to FIG. 7B, assuming that the coding level is 1500 and the size of the second generator matrix is 1536, a matrix with a size of 1500 can be intercepted in the lower right corner area of the second generator matrix as the third generator matrix.
  • the K sub-channels with the highest reliability can be determined among the multiple sub-channels corresponding to the K bits to be coded, and the K bits to be coded can be determined according to the K sub-channels with the highest reliability.
  • the sequence to be coded includes K bits to be coded and frozen bits. According to the second generating matrix, the coded sequence is polarized and coded to obtain the coded bits.
  • the positions of the K bits to be coded are positions corresponding to the K subchannels with the highest reliability.
  • fill information bits bits to be coded
  • the coded sequence includes N'bits, N The'bits include K information bits and N'-K frozen bits.
  • the code length is 8
  • the number of bits to be coded is 4, and the sub-channels with the highest reliability among the eight sub-channels are: sub-channel 4, sub-channel 6, sub-channel 7 and sub-channel 8, then sub-channel 4
  • the corresponding positions of subchannel 6, subchannel 7 and subchannel 8 are used to carry information bits, and the other subchannels are used to carry frozen bits.
  • the sequence to be coded may be 00010111, where 1 represents information bits, and 0 represents frozen bits.
  • the K sub-channels with the highest reliability can be determined in the following way:
  • P group of sub-channels is determined among multiple sub-channels, and P is a positive integer.
  • X i first sub-channels are determined in the i-th group of sub-channels
  • the K sub-channels with the highest reliability include the first sub-channels determined in each group of sub-channels.
  • the X i first sub-channels are the X i sub-channels with the highest reliability in the i-th group of sub-channels, i is an integer, 1 ⁇ i ⁇ P, and X i is a positive integer,
  • the number of sub-channels included in a group of sub-channels may be the same as the size of one matrix unit. For example, assuming that the size of the matrix unit is 16, a group of sub-channels includes 16 sub-channels.
  • the number of sub-channels included in a group of sub-channels may be the same as the size of one sub-block. For example, assuming that the size of a sub-block is 64, a group of sub-channels includes 64 sub-channels.
  • the reliability of each group of sub-channels can be pre-calculated, and the reliability of each group of sub-channels can be stored.
  • the following two methods can be used to store the reliability of each group of sub-channels:
  • the sequence numbers of the 8 sub-channels are: 1, 2, ..., 7, 8.
  • Sub-channel Reliability Subchannel 1 2.1 Subchannel 2 3 Subchannel 3 4.5 Subchannel 4 5 Subchannel 5 3.2 Subchannel 6 2 Subchannel 7 2.6 Subchannel 8 7
  • the reliability rankings of the sub-channels in different groups may be the same or different.
  • the reliability rankings of the sub-channels in different groups are the same, the reliability of only one group of sub-channels can be stored.
  • the reliability of all sub-channels corresponding to the coding code length may be calculated in advance, and the reliability sequence may be stored. Assuming that the maximum encoding code length supported by the protocol is N*T, where N is the size of a matrix unit, T reliability sequences can be pre-calculated and stored, and the lengths of the T reliability sequences are: T, 2T, 3T ,..., N*T.
  • the calculation of the reliability of the sub-channel shown in the embodiment of the present application includes: the reliability calculation within the short code and the reliability calculation between the short codes. Among them, the reliability calculation in the short code is the same as the existing calculation method.
  • the method of calculating the reliability of the sub-channel is also different.
  • the method of calculating the reliability of the sub-channel is introduced through specific examples.
  • Example 1 Assuming that the second generator matrix is the second generator matrix shown in FIG. 6C, the code corresponding to the second generator matrix may also be referred to as 2-coupled coding.
  • ⁇ -1 (x) is the inverse function of ⁇ (x).
  • FIG. 8B is a schematic diagram of another decoding process provided by an embodiment of this application. See Figure 8B, For the input first reliability of the i-th group of sub-channels, the f operation is the same as the f operation shown in FIG. 8A.
  • FIG. 9A is another encoding diagram provided by an embodiment of this application.
  • the second generator matrix corresponding to the coding image is the second generator matrix in FIG. 6C.
  • Figure 9A compared with the encoding diagram shown in Figure 2, the leftmost box in Figure 9A no longer represents an information bit or a frozen bit, and a box represents a short code encoding image, for example, short
  • the code length of the code can be the size N of a matrix unit.
  • the circles in each column except the first column no longer represent a part and bit, but a part and bit vector.
  • the number of polarizations (the number of columns of edges in the coding and decoding diagram) of each N-length short code is log 2 (N) times.
  • the short code is polarized twice to obtain a long code with a code length of N′. Therefore, the number of polarizations of a long code with a code length of N′ is log 2 (N)+2 times, and the total coding and decoding complexity is N′*(log 2 (N)+2). Since N can be set as a constant that does not change with N', when N'is very large, we can ignore the constant term, and the compilation complexity is O(N').
  • the polar code shown in this application can be referred to as a coupled polar code.
  • the coding diagram of the coupled polar code can be regarded as a recombination or cropping of the original long code coding diagram. 9C, a further detailed description of the coded picture.
  • FIG. 9B is another encoding diagram provided by an embodiment of this application. Referring to FIG. 9B, several columns can be extracted from the original Polar long code encoding diagram, and then combined to obtain an encoding diagram of the coupled Polar code.
  • FIG. 9C is another encoding diagram provided by an embodiment of this application. Referring to Fig. 9C, several rows and several columns can be extracted from the original Polar long code coding diagram, and then combined to obtain a coding diagram of the coupled Polar code.
  • the transmitting end obtains the coded bits
  • the coded bits are sent, and the coded bits are transmitted to the receiving end through the channel after rate matching, interleaving, and modulation.
  • the first generator matrix is determined first, and then the second generator matrix is generated according to the first generator matrix, and the K bits to be encoded are determined according to the second generator matrix.
  • the coded bits are polarized coded. Since the first generator matrix includes at least two sub-blocks distributed according to a preset positional relationship, each sub-block includes a plurality of first generator matrix cores, the second generator matrix includes T sub-blocks, and adjacent ones of the T sub-blocks The positional relationship between the two sub-blocks is determined according to the preset positional relationship.
  • the second generating matrix includes a plurality of sub-blocks arranged according to the above-mentioned preset positional relationship, and each sub-block includes Multiple first generator matrix cores. Therefore, when the K bits to be encoded are polarized encoding according to the second generator matrix, it is equivalent to polar encoding multiple short codes first, and then coupling multiple short codes to obtain the encoding result, thereby reducing the encoding complexity .
  • FIG. 10 is a schematic flowchart of another encoding method provided by an embodiment of this application. Referring to Figure 10, the method can include:
  • K is a positive integer.
  • first generator matrix in the embodiment in FIG. 10 is equivalent to the sub-block in the embodiment in FIG. 3, and the description of the sub-block in the embodiment in FIG. 3 can be applied to the first generator matrix in the embodiment in FIG. 10. I will not repeat them here.
  • the first generator matrix includes a first matrix block and a second matrix block
  • the first matrix block is located at the upper left corner of the first generator matrix
  • the second matrix block is located at the lower right corner of the first generator matrix
  • the first matrix block and the second matrix block The matrix blocks are the same, along the diagonal direction of the first generator matrix, the distance between the first element in the first matrix block and the second element in the second matrix block (hereinafter may also be referred to as the first matrix block and the second element for short)
  • the distance between the two matrix blocks) is u, and u is an integer greater than or equal to 1.
  • the first element may be an element in the upper left corner of the first matrix block
  • the second element may be an element in the upper left corner of the second generator matrix.
  • the distance between the first element and the second element refers to the difference between the row number or the column number of the first element and the second element.
  • the first element is 0 or 1.
  • first generator matrix other elements except the first matrix block and the second matrix block may all be 0 elements.
  • a first matrix and a second matrix block may comprise a block or a plurality of matrix cells, matrix cells, or may be a G N 0 N. Both the first matrix block and the second matrix block are square matrices. G N 0 N may be described and illustrated embodiment Referring to FIG. 3.
  • the first generator matrix satisfies self-similarity (or shifted self-similarity).
  • Self-similarity refers to the movement of the first matrix block in the first generator matrix (for example, along the main diagonal of the first generator matrix). After moving) the preset distance, the first matrix block can be moved to the position of the second matrix block, and the content in the first matrix block and the second matrix block are the same.
  • the elements in the first generator matrix satisfy: a i,j ⁇ a i+u,j+u , where i is an integer, j is an integer, and v is the first generator matrix
  • i is an integer
  • j is an integer
  • v is the first generator matrix
  • the size of u is an integer, 1 ⁇ i ⁇ v, 1 ⁇ j ⁇ v, 1 ⁇ i+u ⁇ v, 1 ⁇ j+u ⁇ v.
  • FIG. 11A is a schematic diagram of a first generating matrix provided by an embodiment of this application.
  • the first generator matrix includes a first matrix block and a second matrix block.
  • the first matrix block is located in the upper left corner (or called the upper left corner area) of the first generator matrix
  • the second matrix block is located in the first generator.
  • the bottom right corner of the matrix (or called the bottom right area).
  • the first matrix block is the same as the second matrix block.
  • the first generator matrix and the second generator matrix partially overlap.
  • FIG. 11B is a schematic diagram of still another first generating matrix provided by an embodiment of this application.
  • the first generator matrix includes a first matrix block and a second matrix block.
  • the first matrix block is located in the upper left corner (or called the upper left corner area) of the first generator matrix
  • the second matrix block is located in the first generator.
  • the bottom right corner of the matrix (or called the bottom right area).
  • the first matrix block is the same as the second matrix block.
  • first generator matrix and the second generator matrix there is a certain distance between the first generator matrix and the second generator matrix, that is, an element in the lower right corner of the first generator matrix (referred to as element 1) and an element in the upper left corner of the second generator matrix (referred to as element 2) There is a certain distance between them, for example, the difference between the row numbers of element 2 and element 1 is greater than 1.
  • FIG. 11C is a schematic diagram of another first generating matrix provided by an embodiment of this application.
  • the first generator matrix includes a first matrix block and a second matrix block.
  • the first matrix block is located in the upper left corner (or called the upper left corner area) of the first generator matrix
  • the second matrix block is located in the first generator.
  • the bottom right corner of the matrix (or called the bottom right area).
  • the first matrix block is the same as the second matrix block.
  • the first generator matrix and the second generator matrix are adjacent, that is, an element in the lower right corner of the first generator matrix (referred to as element 1) is adjacent to an element in the upper left corner of the second generator matrix (referred to as element 2),
  • element 1 an element in the lower right corner of the first generator matrix
  • element 2 an element in the upper left corner of the second generator matrix
  • the row number of element 2 is one greater than the row number of element 1
  • the column number of element 2 is one greater than the column number of element 1.
  • the elements in the first generator matrix are symmetrical along the subdiagonal line of the first generator matrix.
  • FIG. 12A is a schematic diagram of still another first generating matrix provided by an embodiment of this application.
  • the first generator matrix includes a first matrix block and a second matrix block, and the first matrix block and the second matrix block each include a G N. Assuming that N is 128, the distance between the first matrix block and the second matrix block is 128.
  • FIG. 12B is a schematic diagram of still another first generating matrix provided by an embodiment of this application.
  • the first generated matrix includes a first matrix block and a second matrix block, and the first matrix block and the second matrix block respectively include four matrix units. Assuming that N is 128, the distance between the first matrix block and the second matrix block is 256.
  • FIG 12A- FIG. 12B FIG labeled 0 N omitted, i.e., in FIG 12A- FIG. 12B are blank 0 N unit matrix.
  • Figures 12A to 12B illustrate the first generator matrix only by way of example, and do not limit the first generator matrix.
  • the second generator matrix includes T first generator matrices, the T first generator matrices are distributed along the diagonal of the second generator matrix (for example, the diagonal may be the main diagonal), and the T first generators
  • the first matrix block of the a+1 first generator matrix in the generator matrix coincides with the second matrix block of the a-th first generator matrix, a is an integer greater than or equal to 1, and T is an integer greater than or equal to 2 .
  • FIG. 13 is a schematic diagram of another second generating matrix provided by an embodiment of this application.
  • the second generator matrix includes five first generator matrices.
  • the five first generator matrices are distributed along the main diagonal of the second generator matrix, along the downward and rightward extension direction of the main diagonal of the second generator matrix.
  • the matrix in the upper left corner of the second generator matrix is the first first generator matrix.
  • the first generator matrix referred to by the number 1 is the first first generator matrix
  • the first generator matrix referred to by the number 2 is the second first generator matrix, and so on, as shown by the number 5.
  • the first generator matrix referred to is the fifth first generator matrix.
  • the second matrix block of the first first generator matrix coincides with the first matrix block of the second first generator matrix.
  • the second matrix block of the second first generator matrix coincides with the first matrix block of the third first generator matrix.
  • the second matrix block of the third first generator matrix coincides with the first matrix block of the fourth first generator matrix.
  • the second matrix block of the fourth first generator matrix coincides with the first matrix block of the fifth first generator matrix.
  • T is the smallest integer that enables the first condition to be satisfied, and the first condition is: the size of the second generator matrix is greater than or equal to the code length.
  • T satisfies the following relationship:
  • v is the size of the first generator matrix
  • N′ is the coding length
  • N′ is an integer greater than 1.
  • T 7.
  • T is 5.
  • the number T of the first generator matrix included in the second generator matrix may be determined according to the coding length and the first generator matrix, and then the second generator matrix is generated according to the first generator matrix and the number T. For example, you can copy and move the first generator matrix T-1 times along the main diagonal of the first generator matrix to obtain the second generator matrix.
  • Each movement distance is u, and the movement distance refers to the number of rows or columns moved. For example, if you move 3 rows, the moving distance is 3.
  • FIG. 14 is a schematic diagram of a process of generating a second generator matrix according to an embodiment of the application.
  • the first generator matrix includes 16 matrix units, some of which are G N and some of them are 0 N.
  • the first generator matrix satisfies self-similarity, and the distance (row or column distance) between the first matrix block and the second matrix block in the first generator matrix is u. Assuming that it is determined that the second generator matrix includes three first generator matrices, the first generator matrix needs to be copied and moved twice.
  • the second generator matrix includes the first generator matrix 1, the first generator matrix 2, and the first generator matrix 3.
  • FIG. 14 merely illustrates a way of generating a second generator matrix according to the first generator matrix by way of example, and is not a limitation on this way.
  • the matrix units except G N are all 0 N.
  • the mark of 0 N is omitted in the figure, that is, the blank matrix units in FIG. 14 are all 0 N.
  • FIG. 15A is a schematic diagram of a second generating matrix provided by an embodiment of this application.
  • the first generator matrix includes 16 matrix units, some of which are G N , and some of them are 0 N.
  • the first generator matrix satisfies self-similarity.
  • the second generator matrix includes 7 first generator matrices. In every two adjacent generator matrices of the 7 first generator matrices, the first matrix block of the latter generator matrix and the first matrix block of the previous first generator matrix The two matrices overlap.
  • the size of the second generator matrix (the number of rows or columns included in the second generator matrix) is 2048.
  • FIG. 15B is a schematic diagram of another second generating matrix provided by an embodiment of this application.
  • the first generator matrix includes 16 matrix units, some of which are G N , and some of them are 0 N.
  • the first generator matrix satisfies self-similarity.
  • the second generator matrix includes 5 first generator matrices. In every two adjacent generator matrices of the 5 first generator matrices, the first matrix block of the latter generator matrix and the first matrix block of the previous first generator matrix The two matrices overlap.
  • the size of the second generator matrix (the number of rows or columns included in the second generator matrix) is 1536.
  • FIG. 15C is a schematic diagram of a second generating matrix provided by an embodiment of this application.
  • the first generator matrix includes 16 matrix units, some of which are G N , and some of them are 0 N.
  • the first generator matrix satisfies self-similarity.
  • the second generator matrix includes 7 first generator matrices. In every two adjacent generator matrices of the 7 first generator matrices, the first matrix block of the latter generator matrix and the first matrix block of the previous first generator matrix The two matrices overlap.
  • the size of the second generator matrix (the number of rows or columns included in the second generator matrix) is 1024.
  • the matrix units except G N are all 0 N.
  • the mark of 0 N is omitted in the figure, that is, the blanks in FIGS. 15A-15C
  • the matrix units are all 0 N.
  • the first generator matrix is determined first, and then the second generator matrix is generated according to the first generator matrix, and the K bits to be encoded are determined according to the second generator matrix.
  • the coded bits are polarized coded. Since the first generator matrix has self-similarity, the second generator matrix includes multiple first matrix blocks. Therefore, when the K bits to be encoded are polarized encoding according to the second generator matrix, it is equivalent to performing multiple short codes first. Perform polarization coding, and then couple multiple short codes to obtain coding results, thereby reducing coding complexity.
  • FIG. 16 is a schematic diagram of decoding provided by an embodiment of this application. Referring to Figure 16, the method can include:
  • the bit information includes N′ first likelihood ratio (LLR) sequences, and N′ is a positive integer.
  • N′ is a positive integer.
  • the signal is demodulated and other processing to obtain N′ first LLRs, and Polar code decoding is performed according to the received N′ first LLRs.
  • the receiving end may misjudge.
  • b 0) that is correctly judged as 0 at the receiving end and the probability p(r
  • LLR log-likelihood ratio
  • S1602 Perform polarization decoding on the bit information according to the second generating matrix to obtain polarization decoded bits.
  • the second generating matrix is a matrix for performing polarization coding in the embodiment of FIG. 3.
  • the second generating matrix refers to the embodiment shown in FIG. 3, which will not be repeated here.
  • the second generator matrix is a matrix for polarization coding in the embodiment of FIG. 10.
  • the second generating matrix refer to the embodiment shown in FIG. 10, which will not be repeated here.
  • the coding sequence includes N′ bits before coding, and the N′ bits before coding include K information bits and N′-K frozen bits.
  • the N′ first LLRs include T first LLR sequences.
  • the N′ first LLRs can be divided into T first LLR sequences, and one first LLR sequence includes N LLRs.
  • a first LLR sequence can be combined with two or more sets of bits before encoding. For example, assuming that the coding sequence includes 8 groups of bits before coding, and the second generator matrix is shown in FIG. The relationship of the previous bit group is shown in Table 2:
  • the first LLR sequence 1 is related to the first group of bits before encoding and the second group of bits before encoding
  • the first LLR sequence 2 is related to the second group of bits before encoding and the third group of bits before encoding. ,And so on.
  • the first LLR sequence can be decoupled to obtain the second LLR sequence corresponding to each first LLR sequence, so that a second LLR sequence corresponds to a set of bits before encoding.
  • the first LLR sequence shown in Table 2 is decoupled to obtain 8 second LLR sequences.
  • the relationship between the 8 second LLR sequences and the bit group before encoding is shown in Table 3:
  • Identification of the first LLR sequence Bit group before encoding First LLR sequence 1 The first group of bits before encoding First LLR sequence 2 Group 2 bits before encoding First LLR sequence 3 3rd group of bits before encoding First LLR sequence 4 4th group of bits before encoding First LLR sequence 5 Group 5 bits before encoding First LLR sequence 6 Group 6 bits before encoding First LLR sequence 7 Group 7 bits before encoding First LLR sequence 8 Group 8 bits before encoding
  • the first LLR sequence 1 is related to the first group of bits before encoding
  • the first LLR sequence 2 is related to the second group of bits before encoding, and so on.
  • the second LLR sequence may be determined according to the first LLR sequence in the following manner: according to the i-th first LLR sequence and at least one second LLR sequence among the first i-1 second LLR sequences, the i-th LLR sequence is determined A second LLR sequence, the i is an integer between 2 and T.
  • the polarization decoding can be performed according to the T second LLR sequence in the following manner: according to the T second LLR sequence, it is determined to obtain the T-th decoding result; according to the i+1-th decoding result to the first At least one of the T decoding results and the i-th second LLR sequence determine the i-th decoding result, where i is an integer between 1 and T-1.
  • Example 1 Assuming that the second generator matrix is the second generator matrix shown in FIG. 6C, the code corresponding to the second generator matrix may also be referred to as 2-coupled coding.
  • the i-th second LLR sequence can be determined in the following manner: the i-th second LLR sequence is determined according to the i-th first LLR sequence and the i-1th second LLR sequence. Among them, the first second LLR sequence is the same as the first first LLR sequence.
  • the i-th decoding result may be determined in the following manner: the i-th decoding result is determined according to the i+1-th decoding result, the i+1-th first LLR sequence, and the i-th second LLR sequence.
  • FIG. 17 is a schematic diagram of a decoding process provided by an embodiment of this application.
  • l' i is the i-th first LLR sequence
  • l i is the i-th second LLR sequence
  • u i is the i-th bit sequence before encoding
  • c i is the i-th bit after encoding Sequence
  • i is an integer between 1 and 8.
  • g operation is: Encode c to get u.
  • the received N′ LLRs are divided into 8 first LLR sequences, which are respectively denoted as: l′ 1 , l′ 2 , l′ 3 , l' 4 , l' 5 , l' 6 , l' 7 , l' 8 .
  • the eight first LLR sequences corresponding to the second LLR sequences are respectively denoted as: l 1 , l 2 , l 3 , l 4 , l 5 , l 6 , l 7 , l 8 .
  • Fig. 17 first determine to obtain the first second LLR sequence l 1 . Then perform f operation on the first second LLR sequence l 1 and the second first LLR sequence l′ 2 to obtain the second second LLR sequence l 2 . Then perform f operation on the second second LLR sequence l 2 and the third first LLR sequence l′ 3 to obtain the third second LLR sequence l 3 , and so on, until the above 8 second LLR sequences are obtained .
  • first series of 8 l 8 second LLR input to the decoder for decoding to obtain a first decoding result of 8 u 8, wherein, u 8 includes the N decoded bits.
  • the result of g operation Input to the decoder for decoding and get the seventh decoding result u 7 .
  • Example 2 Assuming that the second generator matrix is the second generator matrix shown in FIG. 14, the encoding corresponding to the second generator matrix may also be referred to as 4-coupled encoding.
  • the i-th second LLR sequence can be determined in the following manner: the i-th second LLR sequence is determined according to the i-th first LLR sequence and the i-2 second LLR sequence, and the i is 3 to T Integer between.
  • the first second LLR sequence is the same as the first first LLR sequence; the second second LLR sequence is the same as the second first LLR sequence.
  • FIG. 18 is a schematic diagram of a decoding process provided by an embodiment of this application.
  • the f operation can be the same as the g operation in FIG. 17.
  • l' i is the i-th first LLR sequence.
  • the received N′ LLRs are divided into 8 first LLR sequences, which are respectively denoted as: l′ 1 , l′ 2 , l′ 3 , l' 4 , l' 5 , l' 6 , l' 7 , l' 8 .
  • decode according to the above-mentioned calculated parameters input l 8 into the decoder for decoding to obtain the eighth decoding result u 8 , where u 8 includes N decoding bits.
  • FIG. 19 is a schematic diagram of decoding performance provided by an embodiment of this application.
  • the horizontal axis represents the signal to noise ratio (SNR), and the vertical axis represents the block error rate (BLER).
  • SNR signal to noise ratio
  • BLER block error rate
  • the performance curve is shown as a dotted line.
  • the code length is 16384
  • the number K of information bits is 8129
  • two couplings are performed (for example, the second generator matrix is shown in FIG. 6C)
  • the performance curve is shown as a solid line. It can be seen from Fig. 19 that the method shown in this application can achieve a performance gain of about 1 dB.
  • the coupled Polar code has less complexity than the long Polar code without loss of performance.
  • the code length is increased to a certain length, the coupling in a larger range cannot bring significant performance gains.
  • FIG. 20A is a schematic diagram of another decoding performance provided by an embodiment of this application.
  • the performance curve is shown as a solid line.
  • the code length is 65536
  • the number of information bits K is 32768
  • two couplings are performed (for example, the second generator matrix is shown in FIG. 6C)
  • the performance curve is shown by one of the dashed lines.
  • the code length is 65536
  • the number of information bits K is 32768
  • 4-coupling for example, the second generator matrix is shown in FIG. 14
  • the performance curve is shown by the other dashed line.
  • FIG. 20B is a schematic diagram of another decoding performance provided by an embodiment of this application.
  • the performance curve is shown as a solid line.
  • the code length is 131072
  • the number K of information bits is 65536
  • two couplings for example, the second generator matrix is shown in FIG. 6C
  • the performance curve is shown by one of the dashed lines.
  • the code length is 131072
  • the number K of information bits is 65536
  • 4-coupling for example, the second generator matrix is shown in FIG. 14
  • the performance curve is shown by the other dashed line.
  • the coupling range or width can be limited to a certain extent, or an appropriate degree of coupling can be selected, so that performance can be achieved without loss of performance. Reduce the complexity of software and hardware implementation as much as possible.
  • FIG. 21 is a schematic structural diagram of an encoding device provided by an embodiment of this application.
  • the encoding device 10 may include an obtaining module 11, a determining module 12, a generating module 13, and an encoding module 14, where:
  • the obtaining module 11 is configured to obtain K bits to be coded, where K is a positive integer;
  • the determining module 12 is configured to determine a first generator matrix, where the first generator matrix includes at least two sub-blocks distributed according to a preset position relationship, and the sub-block includes a plurality of first generator matrix cores;
  • the generating module 13 is configured to generate a second generating matrix according to the first generating matrix, the second generating matrix including T sub-blocks, and the positional relationship between two adjacent sub-blocks in the T sub-blocks Is determined according to the preset position relationship, the T is a positive integer;
  • the encoding module 14 is configured to perform polarization encoding on the K to-be-encoded bits according to the second generating matrix to obtain encoded bits.
  • the obtaining module 11 may execute S301 in the embodiment of FIG. 3.
  • the determining module 12 may execute S302 in the embodiment of FIG. 3.
  • the generating module 13 may execute S303 in the embodiment of FIG. 3.
  • the encoding module 13 may perform S304 in the embodiment of FIG. 3.
  • the encoding device shown in the embodiment of the present application can execute the technical solution shown in the foregoing method embodiment, and its implementation principles and beneficial effects are similar, and will not be repeated this time.
  • the positional relationship between two adjacent sub-blocks in the T sub-blocks is the same as the preset positional relationship.
  • the first diagonal of the sub-block includes the first generator matrix core.
  • the multiple first generator matrix cores in the sub-block are distributed in a triangle below.
  • the distribution of the first generator matrix core in the sub-block is the same as the distribution of the first element in the second generator matrix core, and the number of elements included in the second generator matrix core is equal to The number of matrix units included in the sub-blocks is the same, and the matrix units included in the sub-blocks are the first generator matrix core or the 0 matrix.
  • the first generator matrix includes two sub-blocks.
  • the number of matrix units included in the sub-block is 2*2, and the matrix units included in the sub-block are the first generator matrix core or the 0 matrix.
  • the first generator matrix includes a first sub-block and a second sub-block, and the first matrix unit in the first sub-block and the second sub-block in the second sub-block are The matrix units coincide;
  • the coordinates of the first matrix unit in the first sub-block are (2, 2), and the coordinates of the second matrix unit in the second sub-block are (1, 1).
  • the number of matrix units included in the sub-block is 4*4, and the matrix units included in the sub-block are the first generator matrix core or the 0 matrix.
  • the first generator matrix includes a first sub-block and a second sub-block, and the four first matrix units in the first sub-block and the second sub-block in the The 4 second matrix units overlap; among them,
  • the coordinates of the four first matrix units in the first sub-block are: (3,3), (3,4), (4,3), (4,4);
  • the coordinates of the four second matrix units in the second sub-block are respectively: (1,1), (1,2), (2,1), (2,2).
  • the K bits to be encoded are information bits; the encoding module 14 is specifically configured to:
  • the multiple sub-channels include P groups of sub-channels, where P is a positive integer; the encoding module 14 is specifically configured to:
  • the reliability of the sub-group i, determining X i in the i-th first sub-set of subchannels in the first subchannel X i is the i-th set of subchannels highest reliability X i subchannels ,
  • the i is an integer, 1 ⁇ i ⁇ P, the X i is a positive integer,
  • the K subchannels with the highest reliability include the first subchannel.
  • the encoding device shown in the embodiment of the present application can execute the technical solution shown in the foregoing method embodiment, and its implementation principles and beneficial effects are similar, and will not be repeated this time.
  • FIG. 22 is a schematic structural diagram of a decoding device provided by an embodiment of this application.
  • the decoding device 20 may include a receiving module 21 and a decoding module 22, where:
  • the receiving module 21 is configured to receive polarization-encoded bit information
  • the decoding module 22 is configured to perform polarization decoding on the bit information according to the second generating matrix to obtain polarization decoded bits;
  • the second generator matrix is generated according to the first generator matrix
  • the first generator matrix includes at least two sub-blocks distributed according to a preset position relationship
  • the sub-block includes a plurality of first generator matrix cores
  • the second generating matrix includes T sub-blocks, the positional relationship between two adjacent sub-blocks in the T sub-blocks is determined according to the preset positional relationship, and the T is a positive integer.
  • the receiving module 21 may execute S1601 in the embodiment of FIG. 16.
  • the decoding module 22 may execute S1602 in the embodiment of FIG. 16.
  • the encoding device shown in the embodiment of the present application can execute the technical solution shown in the foregoing method embodiment, and its implementation principles and beneficial effects are similar, and will not be repeated this time.
  • the positional relationship between two adjacent sub-blocks in the T sub-blocks is the same as the preset positional relationship.
  • the first diagonal of the sub-block includes the first generator matrix core.
  • the multiple first generator matrix cores in the sub-block are distributed in a triangle below.
  • the distribution of the first generator matrix core in the sub-block is the same as the distribution of the first element in the second generator matrix core, and the number of elements included in the second generator matrix core is equal to The number of elements included in the sub-blocks is the same, and the elements included in the sub-blocks are the first generator matrix core or the 0 matrix.
  • the first generator matrix includes two sub-blocks.
  • the number of elements included in the sub-block is 2*2, and the elements included in the sub-block are the first generator matrix core or the 0 matrix.
  • the first generator matrix includes a first sub-block and a second sub-block, and the first element in the first sub-block and the second element in the second sub-block are coincide;
  • the coordinates of the first element in the first sub-block are (2, 2), and the coordinates of the second element in the second sub-block are (1, 1).
  • the number of elements included in the sub-block is 4*4, and the elements included in the sub-block are the first generator matrix core or the 0 matrix.
  • the first generating matrix includes a first sub-block and a second sub-block, and the four first elements in the first sub-block and the four in the second sub-block are Two second elements coincide; among them,
  • the coordinates of the four first elements in the first sub-block are: (3,3), (3,4), (4,3), (4,4);
  • the coordinates of the four second elements in the second sub-block are respectively: (1,1), (1,2), (2,1), (2,2).
  • the bit information includes N′ first log-likelihood ratio LLR sequences, and the N′ is a positive integer.
  • the N′ first LLRs include T first LLR sequences, and the first LLR sequences include at least two first LLRs; the decoding module 22 is specifically configured to :
  • T second LLR sequences corresponding to the T first LLR sequences one of the first LLR sequences corresponds to one or more sets of bits before encoding, and one of the second LLR sequences corresponds to a set of bits before encoding ;
  • the decoding module 22 is specifically configured to:
  • the coupling degree of the code block is 2; the decoding module 22 is specifically configured to:
  • the i-th second LLR sequence is determined according to the i-th first LLR sequence and the i-1th second LLR sequence.
  • the first second LLR sequence is the same as the first first LLR sequence.
  • the coupling degree of the code block is 4; the decoding module 22 is specifically configured to:
  • the i-th second LLR sequence is determined according to the i-th first LLR sequence and the i-2th second LLR sequence, and the i is an integer between 3 and T.
  • the first second LLR sequence is the same as the first first LLR sequence
  • the second second LLR sequence is the same as the second first LLR sequence.
  • the decoding module 22 is specifically configured to:
  • the coupling degree of the code block is 2; the decoding module 22 is specifically configured to:
  • the i-th decoding result is determined according to the i+1-th decoding result, the i+1-th first LLR sequence, and the i-th second LLR sequence.
  • the encoding device shown in the embodiment of the present application can execute the technical solution shown in the foregoing method embodiment, and its implementation principles and beneficial effects are similar, and will not be repeated this time.
  • FIG. 23 is a schematic structural diagram of another encoding device provided by an embodiment of this application.
  • the encoding device 30 may include an acquiring module 31, a determining module 32, a generating module 33, and an encoding module 34, where:
  • the obtaining module 31 is configured to obtain K bits to be coded, where K is a positive integer;
  • the determining module 32 is configured to determine a first generator matrix.
  • the first generator matrix includes a first matrix block and a second matrix block.
  • the first matrix block is located at the upper left corner of the first generator matrix.
  • the second matrix block is located at the lower right corner of the first generator matrix.
  • the first matrix block and the second matrix block are the same, along the diagonal direction of the first generator matrix, in the first matrix block
  • the distance between the first element of and the second element in the second matrix block is u, and the u is an integer greater than or equal to 1;
  • the generating module 33 is configured to generate a second generator matrix according to the coding length and the first generator matrix, the second generator matrix includes T first generator matrices, and the T first generator matrices Distributed along the diagonal of the second generator matrix, the first matrix block of the a+1-th first generator matrix and the second matrix block of the a-th first generator matrix among the T first generator matrices Coincident, said a is an integer greater than or equal to 1, and said T is an integer greater than or equal to 2;
  • the encoding module 34 is configured to perform polarization encoding on the K to-be-encoded bits according to the second generating matrix to obtain encoded bits.
  • the obtaining module 31 may execute S1001 in the embodiment of FIG. 10.
  • the determining module 32 may execute S1002 in the embodiment of FIG. 10.
  • the generating module 33 may execute S1003 in the embodiment of FIG. 10.
  • the encoding module 34 may execute S1004 in the embodiment in FIG. 10.
  • the encoding device shown in the embodiment of the present application can execute the technical solution shown in the foregoing method embodiment, and its implementation principles and beneficial effects are similar, and will not be repeated this time.
  • the i is an integer
  • the j is an integer
  • the v is a positive integer
  • the u is an integer, 1 ⁇ i ⁇ v, 1 ⁇ j ⁇ v, 1 ⁇ i+u ⁇ v, 1 ⁇ j+u ⁇ v.
  • the elements in the first generator matrix are symmetrical along a subdiagonal line of the first generator matrix.
  • T is the smallest integer that enables the first condition to be satisfied, and the first condition is: the size of the second generator matrix is greater than or equal to the code length.
  • the T satisfies the following relationship:
  • the v is the size of the first generator matrix
  • the N′ is the coding length
  • the N′ is an integer greater than 1.
  • the encoding device shown in the embodiment of the present application can execute the technical solution shown in the foregoing method embodiment, and its implementation principles and beneficial effects are similar, and will not be repeated this time.
  • FIG. 24 is a schematic structural diagram of another decoding device provided by an embodiment of this application.
  • the decoding device 40 may include a receiving module 41 and a decoding module 42, wherein,
  • the receiving module 41 is configured to receive polarization-encoded bit information
  • the decoding module 42 is configured to perform polarization decoding on the bit information according to a second generating matrix to obtain polarized decoded bits, and the second generating matrix is generated according to the first generating matrix;
  • the first generator matrix includes a first matrix block and a second matrix block, the first matrix block is located at the upper left corner of the first generator matrix, and the second matrix block is located at the upper left corner of the first generator matrix.
  • the first matrix block and the second matrix block are the same, and along the diagonal direction of the first generator matrix, the first element in the first matrix block is the same as that in the second matrix block.
  • the distance between the second elements of is u, and the u is an integer greater than or equal to 1;
  • the second generator matrix includes T first generator matrices, the T first generator matrices are distributed along the diagonal of the second generator matrix, and the T first generator matrices are The first matrix block of the a+1th first generator matrix coincides with the second matrix block of the ath first generator matrix, where a is an integer greater than or equal to 1, and the T is an integer greater than or equal to 2 .
  • the receiving module 41 may execute S1601 in the embodiment of FIG. 16.
  • the decoding module 42 may execute S1602 in the embodiment of FIG. 16.
  • the encoding device shown in the embodiment of the present application can execute the technical solution shown in the foregoing method embodiment, and its implementation principles and beneficial effects are similar, and will not be repeated this time.
  • the i is an integer
  • the j is an integer
  • the v is a positive integer
  • the u is an integer, 1 ⁇ i ⁇ v, 1 ⁇ j ⁇ v, 1 ⁇ i+u ⁇ v, 1 ⁇ j+u ⁇ v.
  • the elements in the first generator matrix are symmetrical along a subdiagonal line of the first generator matrix.
  • T is the smallest integer that enables the first condition to be satisfied, and the first condition is: the size of the second generator matrix is greater than or equal to the code length.
  • the T satisfies the following relationship:
  • the v is the size of the first generator matrix
  • the N′ is the coding length
  • the N′ is an integer greater than 1.
  • the bit information includes N′ first log-likelihood ratio LLR sequences, and the N′ is a positive integer.
  • the N′ first LLRs include T first LLR sequences, and the first LLR sequences include at least two first LLRs; the decoding module 42 is specifically configured to :
  • T second LLR sequences corresponding to the T first LLR sequences one of the first LLR sequences corresponds to one or more sets of bits before encoding, and one of the second LLR sequences corresponds to a set of bits before encoding ;
  • the decoding module 42 is specifically configured to:
  • the coupling degree of the code block is 2; the decoding module 42 is specifically configured to:
  • the i-th second LLR sequence is determined according to the i-th first LLR sequence and the i-1th second LLR sequence.
  • the first second LLR sequence is the same as the first first LLR sequence.
  • the coupling degree of the code block is 4; the decoding module 42 is specifically configured to:
  • the i-th second LLR sequence is determined according to the i-th first LLR sequence and the i-2th second LLR sequence, and the i is an integer between 3 and T.
  • the first second LLR sequence is the same as the first first LLR sequence
  • the second second LLR sequence is the same as the second first LLR sequence.
  • the decoding module 42 is specifically configured to:
  • the coupling degree of the code block is 2; the decoding module 42 is specifically configured to:
  • the i-th decoding result is determined according to the i+1-th decoding result, the i+1-th first LLR sequence, and the i-th second LLR sequence.
  • the encoding device shown in the embodiment of the present application can execute the technical solution shown in the foregoing method embodiment, and its implementation principles and beneficial effects are similar, and will not be repeated this time.
  • FIG. 25 is a schematic diagram of the hardware structure of an encoding device provided by an embodiment of the application.
  • the encoding device 50 may include: a processor 51 and a memory 52, where:
  • the memory 52 is used to store computer programs and can also be used to store intermediate data
  • the processor 51 is configured to execute a computer program stored in the memory to implement each step in the foregoing encoding method. For details, refer to the related description in the foregoing method embodiment.
  • the memory 52 may be independent or integrated with the processor 51. In some embodiments, the memory 52 may even be located outside the encoding device 50.
  • the encoding device 50 may further include a bus 53 for connecting the memory 52 and the processor 51.
  • the encoding device 50 may further include a transmitter.
  • the transmitter is used to transmit encoded bits.
  • the encoding device 50 provided in this embodiment may be a terminal device, or also a network device, and may be used to execute the above-mentioned encoding method, and its implementation and technical effects are similar, and will not be repeated here in this embodiment.
  • FIG. 26 is a schematic diagram of the hardware structure of a decoding device provided by an embodiment of the application.
  • the decoding device 60 may include: a processor 61 and a memory 62, where:
  • the memory 62 is used to store computer programs and can also be used to store intermediate data
  • the processor 61 is configured to execute a computer program stored in the memory to implement each step in the foregoing decoding method. For details, refer to the related description in the foregoing method embodiment.
  • the memory 62 may be independent or integrated with the processor 61. In some embodiments, the memory 62 may even be located outside the decoding device 60.
  • the decoding device 60 may further include a bus 63 for connecting the memory 62 and the processor 61.
  • the decoding device 60 may further include a receiver.
  • the receiver is used to receive polarization-encoded bit information.
  • the decoding device 60 provided in this embodiment may be a terminal device, or also a network device, and may be used to execute the above-mentioned decoding method.
  • the implementation manner and technical effect are similar, and the details are not described herein again in this embodiment.
  • FIG. 27 is a schematic structural diagram of another encoding device provided by an embodiment of this application. Please refer to FIG. 27.
  • the encoding device 70 may include an input interface 71 and a logic circuit 72, where:
  • the input interface 71 is used to obtain K bits to be coded, where K is a positive integer;
  • the logic circuit 72 is configured to determine a first generator matrix, the first generator matrix includes at least two sub-blocks distributed according to a preset position relationship, and the sub-block includes a plurality of first generator matrix cores;
  • the first generator matrix generates a second generator matrix, the second generator matrix includes T sub-blocks, and the positional relationship between two adjacent sub-blocks in the T sub-blocks is determined according to the preset positional relationship ,
  • the T is a positive integer; performing polarization coding on the K bits to be coded according to the second generating matrix to obtain the coded bits.
  • the input interface 71 may have the function of the acquisition module 11 in the embodiment of FIG. 21.
  • the logic circuit 72 may have the functions of the determining module 11, the generating module 13 and the encoding module 14 in the embodiment of FIG. 21.
  • the logic circuit 72 may have the function of the processor 61 in the embodiment of FIG. 25.
  • the logic circuit 72 can also perform other steps in the encoding method.
  • the encoding device 70 may further include an output interface.
  • the output interface can output encoded bits.
  • the encoding device 70 provided in the embodiment of the present application can execute the technical solutions shown in the foregoing method embodiments, and its implementation principles and beneficial effects are similar to those described herein.
  • FIG. 28 is a schematic structural diagram of another decoding device provided by an embodiment of this application.
  • the decoding device 80 may include an input interface 81 and a logic circuit 82, where:
  • the input interface 81 is used to receive polarization-encoded bit information
  • the logic circuit 82 is configured to perform polarization decoding on the bit information according to a second generating matrix to obtain polarized decoded bits; wherein, the second generating matrix is generated according to the first generating matrix,
  • the first generator matrix includes at least two sub-blocks distributed according to a preset position relationship, the sub-block includes a plurality of first generator matrix cores, the second generator matrix includes T sub-blocks, and the T sub-blocks
  • the positional relationship between two adjacent sub-blocks in is determined according to the preset positional relationship, and the T is a positive integer.
  • the input interface 81 may have the function of the receiving module 21 in the embodiment of FIG. 22.
  • the logic circuit 82 may have the function of the decoding module 22 in the embodiment of FIG. 22.
  • the input interface 81 may have the function of the receiver in the embodiment of FIG. 26.
  • the logic circuit 82 may have the function of the processor 61 in the embodiment of FIG. 26.
  • the logic circuit 82 can also perform other steps in the decoding method.
  • the decoding device 80 may also include an output interface.
  • the output interface can output the decoding result.
  • the decoding device 80 provided in the embodiment of the present application can execute the technical solutions shown in the foregoing method embodiments, and its implementation principles and beneficial effects are similar to those described herein.
  • FIG. 29 is a schematic structural diagram of another encoding device provided by an embodiment of this application.
  • the encoding device 90 may include an input interface 91 and a logic circuit 92, where:
  • the input interface 91 is used to obtain K bits to be encoded, where K is a positive integer;
  • the logic circuit 92 is configured to determine a first generator matrix.
  • the first generator matrix includes a first matrix block and a second matrix block.
  • the first matrix block is located at the upper left corner of the first generator matrix.
  • the second matrix block is located at the lower right corner of the first generator matrix.
  • the first matrix block and the second matrix block are the same, along the diagonal direction of the first generator matrix, in the first matrix block
  • the distance between the first element of and the second element in the second matrix block is u, where u is an integer greater than or equal to 1;
  • the second generator matrix is determined according to the coding length and the first generator matrix ,
  • the second generator matrix includes T first generator matrices, the T first generator matrices are distributed along the diagonal of the second generator matrix, and the first generator matrix in the T first generator matrix a+1 first matrix blocks of the first generator matrix overlap with the second matrix blocks of the a-th first generator matrix, where a is an integer greater than or equal to 1, and the T is an integer greater than or equal to 2;
  • According to the second generating matrix perform polarization encoding on the K to-be-encoded bits to obtain encoded bits.
  • the input interface 91 may have the function of the acquisition module 31 in the embodiment of FIG. 23.
  • the logic circuit 92 may have the functions of the determining module 32, the generating module 33, and the encoding module 34 in the embodiment of FIG. 23.
  • the logic circuit 92 may have the function of the processor 61 in the embodiment of FIG. 25.
  • the logic circuit 92 can also perform other steps in the encoding method.
  • the encoding device 90 may also include an output interface.
  • the output interface can output encoded bits.
  • the encoding device 90 provided in the embodiment of the present application can execute the technical solutions shown in the foregoing method embodiments, and its implementation principles and beneficial effects are similar to those described herein.
  • FIG. 30 is a schematic structural diagram of another decoding device provided by an embodiment of this application.
  • the decoding device 100 may include an input interface 101 and a logic circuit 102, where:
  • the input interface 101 is used to receive polarization-encoded bit information
  • the logic circuit 102 is configured to perform polarization decoding on the bit information according to a second generator matrix to obtain polarized decoded bits, and the second generator matrix is generated according to the first generator matrix; wherein,
  • the first generator matrix includes a first matrix block and a second matrix block, the first matrix block is located at the upper left corner of the first generator matrix, and the second matrix block is located at the lower right corner of the first generator matrix ,
  • the first matrix block and the second matrix block are the same, and along the diagonal direction of the first generator matrix, the first element in the first matrix block is the same as the first element in the second matrix block.
  • the distance between the two elements is u, and the u is an integer greater than or equal to 1; wherein, the second generating matrix includes T first generating matrices, and the T first generating matrices are along the The diagonal distribution of the second generator matrix, the first matrix block of the a+1-th first generator matrix in the T first generator matrices coincides with the second matrix block of the a-th first generator matrix, so The a is an integer greater than or equal to 1, and the T is an integer greater than or equal to 2.
  • the input interface 101 may have the function of the receiving module 41 in the embodiment of FIG. 24.
  • the logic circuit 102 may have the function of the decoding module 42 in the embodiment of FIG. 24.
  • the input interface 101 may have the function of the receiver in the embodiment of FIG. 26.
  • the logic circuit 102 may have the function of the processor 61 in the embodiment of FIG. 26.
  • the logic circuit 102 can also perform other steps in the decoding method.
  • the decoding device 100 may further include an output interface.
  • the output interface can output the decoding result.
  • the decoding device 100 provided in the embodiment of the present application can execute the technical solutions shown in the foregoing method embodiments, and its implementation principles and beneficial effects are similar to those described herein.
  • An embodiment of the present application further provides a storage medium, the storage medium includes a computer program, and the computer program is used to implement the encoding method described above.
  • An embodiment of the present application further provides a storage medium, the storage medium includes a computer program, and the computer program is used to implement the decoding method described above.
  • the embodiment of the present application also provides a chip or integrated circuit, including: a memory and a processor;
  • the memory is used to store program instructions and can also be used to store intermediate data
  • the processor is configured to call the program instructions stored in the memory to implement the encoding method described above.
  • the memory can be independent or integrated with the processor.
  • the memory may also be located outside the chip or integrated circuit.
  • the embodiment of the present application also provides a chip or integrated circuit, including: a memory and a processor;
  • the memory is used to store program instructions and can also be used to store intermediate data
  • the processor is configured to call the program instructions stored in the memory to implement the decoding method as described above.
  • the memory can be independent or integrated with the processor.
  • the memory may also be located outside the chip or integrated circuit.
  • An embodiment of the present application also provides a program product, the program product includes a computer program, the computer program is stored in a storage medium, and the computer program is used to implement the foregoing encoding method.
  • An embodiment of the present application also provides a program product, the program product includes a computer program, the computer program is stored in a storage medium, and the computer program is used to implement the above-mentioned decoding method.
  • the steps of the method or algorithm described in combination with the disclosure of the embodiment of the present invention may be implemented in a hardware manner, or may be implemented in a manner in which a processor executes software instructions.
  • Software instructions can be composed of corresponding software modules, which can be stored in random access memory (Random Access Memory, RAM), flash memory, read-only memory (Read Only Memory, ROM), and erasable programmable read-only memory ( Erasable Programmable ROM (EPROM), Electrically Erasable Programmable Read-Only Memory (Electrically EPROM, EEPROM), register, hard disk, mobile hard disk, CD-ROM or any other form of storage medium known in the art.
  • RAM Random Access Memory
  • ROM read-only memory
  • EPROM Erasable Programmable ROM
  • EPROM Electrically Erasable Programmable Read-Only Memory
  • register hard disk, mobile hard disk, CD-ROM or any other form of storage medium known in the art.
  • An exemplary storage medium is coupled to the processor, so that the processor can read information from the storage medium and write information to the storage medium.
  • the storage medium may also be an integral part of the processor.
  • the processor and the storage medium may be located in the ASIC.
  • the ASIC may be located in a base station or terminal.
  • the processor and the storage medium may also exist as discrete components in the receiving device.
  • processor may be a central processing unit (English: Central Processing Unit, abbreviated as: CPU), or other general-purpose processors, digital signal processors (English: Digital Signal Processor, abbreviated as: DSP), and application-specific integrated circuits. (English: Application Specific Integrated Circuit, referred to as ASIC) etc.
  • the general-purpose processor may be a microprocessor or the processor may also be any conventional processor or the like. The steps of the method disclosed in combination with the invention can be directly embodied as executed and completed by a hardware processor, or executed and completed by a combination of hardware and software modules in the processor.
  • the memory may include a high-speed RAM memory, or may also include a non-volatile storage NVM, such as at least one disk storage, and may also be a U disk, a mobile hard disk, a read-only memory, a magnetic disk, or an optical disk.
  • NVM non-volatile storage
  • the bus can be an Industry Standard Architecture (ISA) bus, Peripheral Component (PCI) bus, or Extended Industry Standard Architecture (EISA) bus, etc.
  • ISA Industry Standard Architecture
  • PCI Peripheral Component
  • EISA Extended Industry Standard Architecture
  • the bus can be divided into address bus, data bus, control bus and so on.
  • the buses in the drawings of this application are not limited to only one bus or one type of bus.
  • the above-mentioned storage medium can be realized by any type of volatile or non-volatile storage device or their combination, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable Except programmable read only memory (EPROM), programmable read only memory (PROM), read only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.
  • SRAM static random access memory
  • EEPROM electrically erasable programmable read-only memory
  • EPROM erasable except programmable read only memory
  • PROM programmable read only memory
  • ROM read only memory
  • magnetic memory flash memory
  • flash memory magnetic disk or optical disk.
  • optical disk any available medium that can be accessed by a general-purpose or special-purpose computer.
  • At least one refers to one or more, and “multiple” refers to two or more.
  • “And/or” describes the association relationship of the associated objects, indicating that there can be three relationships, for example, A and/or B, which can mean: A alone exists, A and B exist at the same time, and B exists alone, where A, B can be singular or plural.
  • the character “/” generally indicates that the associated objects before and after are in an “or” relationship.
  • the following at least one item (a)” or similar expressions refers to any combination of these items, including any combination of a single item (a) or a plurality of items (a).
  • at least one item (a) of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple .
  • the functions described in the embodiments of the present invention may be implemented by hardware, software, firmware, or any combination thereof.
  • these functions can be stored in a computer-readable medium or transmitted as one or more instructions or codes on the computer-readable medium.
  • the computer-readable medium includes a computer storage medium and a communication medium, where the communication medium includes any medium that facilitates the transfer of a computer program from one place to another.
  • the storage medium may be any available medium that can be accessed by a general-purpose or special-purpose computer.
  • the disclosed device and method may be implemented in other ways.
  • the device embodiments described above are merely illustrative.
  • the division of the modules is only a logical function division, and there may be other divisions in actual implementation, for example, multiple modules can be combined or integrated. To another system, or some features can be ignored, or not implemented.
  • the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or modules, and may be in electrical, mechanical or other forms.
  • modules described as separate components may or may not be physically separated, and the components displayed as modules may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules can be selected according to actual needs to achieve the objectives of the solutions of the embodiments.
  • the functional modules in the various embodiments of the present invention may be integrated into one processing unit, or each module may exist alone physically, or two or more modules may be integrated into one unit.
  • the units formed by the above-mentioned modules can be realized in the form of hardware, or in the form of hardware plus software functional units.

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Abstract

一种编码、译码方法、装置及设备，编码方法包括：获取K个待编码比特（S301），K为正整数；确定第一生成矩阵，第一生成矩阵中包括按照预设位置关系分布的至少两个子块，子块中包括多个第一生成矩阵核（S302）；根据第一生成矩阵，生成第二生成矩阵，第二生成矩阵包括T个子块，T个子块中相邻的两个子块之间的位置关系为根据预设位置关系确定的（S303），T为正整数；根据第二生成矩阵对K个待编码比特进行极化编码，得到编码后的比特（S304）。该方法降低了编码译码的复杂度。

Description

编码、译码方法、装置及设备
本申请要求于2020年04月22日提交中国专利局、申请号为202010323605.X、申请名称为“编码、译码方法、装置及设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及通信技术领域，尤其涉及一种编码、译码方法、装置及设备。
背景技术
在通信技术领域，通信设备(例如终端设备、基站等)可以通过极化码(Polar码)的方式进行信道编码和译码。
在通过极化码进行译码时，编译码(编码和/或译码)的复杂度通常与码长相关，码长越大，编译码的复杂度越大。当码长非常长(例如，码长大于16384)时，通过极化码进行编译码的复杂度很高，导致编译码的性能较差。
发明内容
本申请实施例提供一种编码、译码方法、装置及设备，降低了编码译码的复杂度。
第一方面，本申请实施例提供一种编码方法，该方法包括：获取K个待编码比特，K为正整数；确定第一生成矩阵，第一生成矩阵中包括按照预设位置关系分布的至少两个子块，子块中包括多个第一生成矩阵核；根据第一生成矩阵，生成第二生成矩阵，第二生成矩阵包括T个子块，T个子块中相邻的两个子块之间的位置关系为根据预设位置关系确定的，T为正整数；根据第二生成矩阵对K个待编码比特进行极化编码，得到编码后的比特。
在上述过程中，当需要对K个待编码比特进行编码时，先确定第一生成矩阵，再根据第一生成矩阵生成第二生成矩阵，并根据第二生成矩阵对K个待编码比特进行极化编码。由于第一生成矩阵中包括至少两个按照预设位置关系分布的子块，每个子块中包括多个第一生成矩阵核，第二生成矩阵中包括T个子块，T个子块中相邻的两个子块之间的位置关系为根据所述预设位置关系确定的，因此，可以得出第二生成矩阵中包括多个按照上述预设位置关系进行排布的子块，每个子块中包括多个第一生成矩阵核。因此，根据第二生成矩阵对K个待编码比特进行极化编码时，相当于先对多个短码进行极化编码，再对多个短码进行耦合，得到编码结果，进而降低编码复杂度。
在一种可能的实施方式中，T个子块中相邻的两个子块之间的位置关系与预设位置关系相同。
在上述过程中，在第二生成矩阵中，T个子块中相邻的两个子块之间的位置关系与预设位置关系相同，使得短码之间的耦合方式相同，使得编码的复杂度较低。
在一种可能的实施方式中，至少两个子块中存在重合部分。
在上述过程中，由于两个子块之间存在重合部分，使得可以实现对不同的短码进行耦合。
在一种可能的实施方式中，子块的第一对角线上包括第一生成矩阵核。
在一种可能的实施方式中，子块中的多个第一生成矩阵核以下三角形分布。
在一种可能的实施方式中，子块中的第一生成矩阵核的分布与第二生成矩阵核中第一元素的分布相同，第二生成矩阵核中的包括的元素数量与子块中包括的矩阵单元数量相同，子块中包括的矩阵单元为第一生成矩阵核或0矩阵。
在上述过程中，由于子块中的第一生成矩阵核的分布与第二生成矩阵核中第一元素的分布相同，使得对短码的耦合方式与已有编码方式类似，使得编码的复杂度较低。
在一种可能的实施方式中，第一生成矩阵中包括两个子块。
在上述过程中，第二生成矩阵中包括较少的子块，使得构造第二生成矩阵的过程较为容易。
在一种可能的实施方式中，子块中包括的矩阵单元数量为2*2，子块中包括的矩阵单元为第一生成矩阵核或0矩阵。
在一种可能的实施方式中，第一生成矩阵中包括第一子块和第二子块，第一子块中的第一矩阵单元与第二子块中的第二矩阵单元重合；其中，第一矩阵单元在第一子块中的坐标为(2,2)，第二矩阵单元在第二子块中的坐标为(1,1)。
在上述过程中，沿第二生成矩阵的副对角线方向，第二生成矩阵对称，使得编码的复杂性较低，同时也使得译码的复杂度较低。
在一种可能的实施方式中，子块中包括的矩阵单元数量为4*4，子块中包括的矩阵单元为第一生成矩阵核或0矩阵。
在一种可能的实施方式中，第一生成矩阵中包括第一子块和第二子块，第一子块中的4个第一矩阵单元与第二子块中的4个第二矩阵单元重合；其中，4个第一矩阵单元在第一子块中的坐标分别为：(3,3)、(3,4)、(4,3)、(4,4)；4个第二矩阵单元在第二子块中的坐标分别为：(1,1)、(1,2)、(2,1)、(2,2)。
在上述过程中，沿第二生成矩阵的副对角线方向，第二生成矩阵对称，使得编码的复杂性较低，同时也使得译码的复杂度较低。
在一种可能的实施方式中，K个待编码比特为信息比特；根据第二生成矩阵对K个待编码比特进行极化编码，得到编码后的比特，包括：在K个待编码比特对应的多个子信道中确定可靠度最高的K个子信道；根据可靠度最高的K个子信道，确定K个待编码比特的位置；根据K个待编码比特的位置确定待编码序列，待编码序列中包括K个待编码比特和冻结比特；根据第二生成矩阵对待编码序列进行极化编码，得到编码后的比特。
在上述过程中，选择可靠度最高的子信道传输信息比特，使得编码的性能较高。
在一种可能的实施方式中，多个子信道中包括P组子信道，P为正整数；在K个待编码比特对应的多个子信道中确定可靠度最高的K个子信道，包括：根据第i组子信道的可靠度，在第i组子信道中确定X i个第一子信道，X i个第一子信道为第i组子信道中可靠度最高的X i个子信道，i为整数，1≤i≤P，X i为正整数，
Figure PCTCN2021086960-appb-000001
可靠度最高的K个子信道包括第一子信道。
第二方面，本申请实施例提供一种译码方法，包括：接收极化编码后的比特信息；根据第二生成矩阵对比特信息进行极化译码，得到极化译码后的比特；其中，第二生成矩阵为根据第一生成矩阵生成的，第一生成矩阵中包括按照预设位置关系分布的至少两个子块， 子块中包括多个第一生成矩阵核，第二生成矩阵包括T个子块，T个子块中相邻的两个子块之间的位置关系为根据预设位置关系确定的，T为正整数。
在上述译码过程中，由于第一生成矩阵中包括至少两个按照预设位置关系分布的子块，每个子块中包括多个第一生成矩阵核，第二生成矩阵中包括T个子块，T个子块中相邻的两个子块之间的位置关系为根据所述预设位置关系确定的，因此，可以得出第二生成矩阵中包括多个按照上述预设位置关系进行排布的子块，每个子块中包括多个第一生成矩阵核。因此，根据第二生成矩阵对比特信息进行极化译码，相当于先对多个短码解耦合，在对解耦合后的短码进行译码，对短码进行译码的复杂度较低，因此，使得上述译码的复杂度较低。
在一种可能的实施方式中，T个子块中相邻的两个子块之间的位置关系与预设位置关系相同。
在上述过程中，在第二生成矩阵中，T个子块中相邻的两个子块之间的位置关系与预设位置关系相同，使得短码之间的耦合方式相同，使得译码的复杂度较低。
在一种可能的实施方式中，至少两个子块中存在重合部分。
在上述过程中，由于两个子块之间存在重合部分，使得可以实现对不同的短码进行耦合。
在一种可能的实施方式中，子块的第一对角线上包括第一生成矩阵核。
在一种可能的实施方式中，子块中的多个第一生成矩阵核以下三角形分布。
在一种可能的实施方式中，子块中的第一生成矩阵核的分布与第二生成矩阵核中第一元素的分布相同，第二生成矩阵核中的包括的元素数量与子块中包括的矩阵单元数量相同，子块中包括的矩阵单元为第一生成矩阵核或0矩阵。
在上述过程中，由于子块中的第一生成矩阵核的分布与第二生成矩阵核中第一元素的分布相同，使得对短码的耦合方式与已有译码方式类似，使得译码的复杂度较低。
在一种可能的实施方式中，第一生成矩阵中包括两个子块。
在上述过程中，第二生成矩阵中包括较少的子块，使得构造第二生成矩阵的过程较为容易。
在一种可能的实施方式中，子块中包括的矩阵单元数量为2*2，子块中包括的矩阵单元为第一生成矩阵核或0矩阵。
在一种可能的实施方式中，第一生成矩阵中包括第一子块和第二子块，第一子块中的第一矩阵单元与第二子块中的第二矩阵单元重合；其中，第一矩阵单元在第一子块中的坐标为(2,2)，第二矩阵单元在第二子块中的坐标为(1,1)。
在上述过程中，沿第二生成矩阵的副对角线方向，第二生成矩阵对称，使得译码的复杂性较低。
在一种可能的实施方式中，子块中包括的矩阵单元数量为4*4，子块中包括的矩阵单元为第一生成矩阵核或0矩阵。
在一种可能的实施方式中，第一生成矩阵中包括第一子块和第二子块，第一子块中的4个第一矩阵单元与第二子块中的4个第二矩阵单元重合；其中，4个第一矩阵单元在第一子块中的坐标分别为：(3,3)、(3,4)、(4,3)、(4,4)；4个第二矩阵单元在第二子块中的坐标分别为：(1,1)、(1,2)、(2,1)、(2,2)。
在上述过程中，沿第二生成矩阵的副对角线方向，第二生成矩阵对称，使得译码的复杂性较低。
在一种可能的实施方式中，比特信息包括N′个第一对数似然比LLR序列，N′为正整数。
在一种可能的实施方式中，N′个第一LLR中包括T个第一LLR序列，第一LLR序列中包括至少两个第一LLR；极化译码包括：确定T个第一LLR序列对应的T个第二LLR序列，一个第一LLR序列对应一组或多组编码前的比特，一个第二LLR序列对应一组编码前的比特；根据T个第二LLR序列进行极化译码。
在上述过程中，先对T个耦合的第一LLR序列进行解耦合，得到解耦合的T个第二LLR序列，再对解耦合的T个第二LLR序列进行译码，由于第二LLR序列的长度较短，使得对第二LLR序列进行译码的复杂度较低，进而使得译码复杂度较低。
在一种可能的实施方式中，确定T个第一LLR序列对应的T个第二LLR序列，包括：根据第i个第一LLR序列、以及前i-1个第二LLR序列中的至少一个第二LLR序列，确定第i个第二LLR序列，i为2至T之间的整数。
在上述过程中，在确定第i个第二LLR序列时，依据第i个第一LLR序列、以及已经解耦合的前i-1个第二LLR序列中至少一个第二LLR序列，进而实现对第一LLR序列进行解耦合，得到第i个第二LLR序列。
在一种可能的实施方式中，码块的耦合度为2；根据第i个第一LLR序列、以及前i-1个第二LLR序列中的至少一个第二LLR序列，确定第i个第二LLR序列，包括：根据第i个第一LLR序列和第i-1个第二LLR序列，确定第i个第二LLR序列。
在一种可能的实施方式中，第一个第二LLR序列与第一个第一LLR序列相同。
在一种可能的实施方式中，码块的耦合度为4；根据第i个第一LLR序列、以及前i-1个第二LLR序列中的至少一个第二LLR序列，确定第i个第二LLR序列，包括：根据第i个第一LLR序列和第i-2个第二LLR序列，确定第i个第二LLR序列，i为3至T之间的整数。
在一种可能的实施方式中，第一个第二LLR序列与第一个第一LLR序列相同；第二个第二LLR序列与第二个第一LLR序列相同。
在一种可能的实施方式中，可以通过如下方式根据T个第二LLR序列进行极化译码：根据第T个第二LLR序列，确定得到第T个译码结果；根据第i+1个译码结果至第T个译码结果中的至少一个译码结果、以及第i个第二LLR序列，确定第i个译码结果，i为1至T-1之间的整数。
在上述过程中，通过对第二LLR序列(短码)进行译码，可以实现得到译码结果，使得译码复杂度较低。
在一种可能的实施方式中，码块的耦合度为2，根据第i+1个译码结果至第T个译码结果中的至少一个译码结果、以及第i个第二LLR序列，确定第i个译码结果，包括：根据第i+1个译码结果、第i+1个第一LLR序列、第i个第二LLR序列，确定第i个译码结果。
第三方面，本申请实施例提供一种编码方法，该方法包括：获取K个待编码比特，K为正整数；确定第一生成矩阵，第一生成矩阵包括第一矩阵块和第二矩阵块，第一矩阵块位于第一生成矩阵的左上角，第二矩阵块位于第一生成矩阵的右下角，第一矩阵块和第二 矩阵块相同，沿第一生成矩阵的对角线方向，第一矩阵块中的第一元素与第二矩阵块中的第二元素之间的距离为u，u为大于或等于1的整数；根据编码长度和第一生成矩阵，确定第二生成矩阵，第二生成矩阵中包括T个第一生成矩阵，T个第一生成矩阵沿第二生成矩阵的对角线分布，T个第一生成矩阵中的第a+1个第一生成矩阵的第一矩阵块与第a个第一生成矩阵的第二矩阵块重合，a为大于或等于1的整数，T为大于或等于2的整数；根据第二生成矩阵，对K个待编码比特进行极化编码，得到编码后的比特。
在上述过程中，当需要对K个待编码比特进行编码时，先确定第一生成矩阵，再根据第一生成矩阵生成第二生成矩阵，并根据第二生成矩阵对K个待编码比特进行极化编码。由于第一生成矩阵具有自相似性，第二生成矩阵中包括多个第一矩阵块，因此，根据第二生成矩阵对K个待编码比特进行极化编码时，相当于先对多个短码进行极化编码，再对多个短码进行耦合，得到编码结果，进而降低编码复杂度。
在一种可能的实施方式中，第一矩阵块和第二矩阵块中不存在重叠的元素。
在一种可能的实施方式中，第一生成矩阵的尺寸为v*v，第一生成矩阵中的元素满足：a i,j＝a i+u,j+u，其中，i为整数，j为整数，v为正整数，u为整数，1≤i＜v，1≤j＜v，1＜i+u≤v，1＜j+u≤v。
在上述过程中，在第一生成矩阵满足a i,j＝a i+u,j+u时，使得第一生成矩阵满足自相似性，根据第二生成矩阵对K个待编码比特进行极化编码时，相当于先对多个短码进行极化编码，再对多个短码进行耦合，得到编码结果，进而降低编码复杂度。
在一种可能的实施方式中，第一生成矩阵中的元素沿第一生成矩阵的副对角线对称。
在上述过程中，由于第一生成矩阵中的元素沿第一生成矩阵的副对角线对称，使得编码的复杂度较低。
在一种可能的实施方式中，T为使得第一条件被满足的最小整数，第一条件为：第二生成矩阵的尺寸大于或等于编码长度。
在一种可能的实施方式中，T满足如下关系：v+(T-1)*u＜N′≤v+T*u；其中，v为第一生成矩阵的尺寸，N′为编码长度，N′为大于1的整数。
在上述过程中，可以避免第二生成矩阵的尺寸过大或者过小，使得编码的复杂度较低。
第四方面，本申请实施例提供一种译码方法，该方法可以包括：接收极化编码后的比特信息；根据第二生成矩阵对比特信息进行极化译码，得到极化译码后的比特，第二生成矩阵为根据第一生成矩阵生成的；其中，第一生成矩阵包括第一矩阵块和第二矩阵块，第一矩阵块位于第一生成矩阵的左上角，第二矩阵块位于第一生成矩阵的右下角，第一矩阵块和第二矩阵块相同，沿第一生成矩阵的对角线方向，第一矩阵块中的第一元素与第二矩阵块中的第二元素之间的距离为u，u为大于或等于1的整数；其中，第二生成矩阵中包括T个第一生成矩阵，T个第一生成矩阵沿第二生成矩阵的对角线分布，T个第一生成矩阵中的第a+1个第一生成矩阵的第一矩阵块与第a个第一生成矩阵的第二矩阵块重合，a为大于或等于1的整数，T为大于或等于2的整数。
在上述过程中，由于第一生成矩阵具有自相似性，第二生成矩阵中包括多个第一矩阵块，因此。因此，根据第二生成矩阵对比特信息进行极化译码，相当于先对多个短码解耦合，在对解耦合后的短码进行译码，对短码进行译码的复杂度较低，因此，使得上述译码的复杂度较低。
在一种可能的实施方式中，第一矩阵块和第二矩阵块中不存在重叠的元素。
在一种可能的实施方式中，第一生成矩阵的尺寸为v*v，第一生成矩阵中的元素满足：a i,j＝a i+u,j+u，其中，i为整数，j为整数，v为正整数，u为整数，1≤i＜v，1≤j＜v，1＜i+u≤v，1＜j+u≤v。
在上述过程中，在第一生成矩阵满足a i,j＝a i+u,j+u时，使得第一生成矩阵满足自相似性，根据第二生成矩阵对K个待译码比特进行极化译码时，相当于先对多个短码进行极化译码，再对多个短码进行耦合，得到译码结果，进而降低译码复杂度。
在一种可能的实施方式中，第一生成矩阵中的元素沿第一生成矩阵的副对角线对称。
在上述过程中，由于第一生成矩阵中的元素沿第一生成矩阵的副对角线对称，使得译码的复杂度较低。
在一种可能的实施方式中，T为使得第一条件被满足的最小整数，第一条件为：第二生成矩阵的尺寸大于或等于译码长度。
在一种可能的实施方式中，T满足如下关系：v+(T-1)*u＜N′≤v+T*u；其中，v为第一生成矩阵的尺寸，N′为译码长度，N′为大于1的整数。
在上述过程中，可以避免第二生成矩阵的尺寸过大或者过小，使得译码的复杂度较低。
在一种可能的实施方式中，比特信息包括N′个第一对数似然比LLR序列，N′为正整数。
在一种可能的实施方式中，N′个第一LLR中包括T个第一LLR序列，第一LLR序列中包括至少两个第一LLR；极化译码包括：确定T个第一LLR序列对应的T个第二LLR序列，一个第一LLR序列对应一组或多组编码前的比特，一个第二LLR序列对应一组编码前的比特；根据T个第二LLR序列进行极化译码。
在上述过程中，先对T个耦合的第一LLR序列进行解耦合，得到解耦合的T个第二LLR序列，再对解耦合的T个第二LLR序列进行译码，由于第二LLR序列的长度较短，使得对第二LLR序列进行译码的复杂度较低，进而使得译码复杂度较低。
在一种可能的实施方式中，确定T个第一LLR序列对应的T个第二LLR序列，包括：根据第i个第一LLR序列、以及前i-1个第二LLR序列中的至少一个第二LLR序列，确定第i个第二LLR序列，i为2至T之间的整数。
在上述过程中，在确定第i个第二LLR序列时，依据第i个第一LLR序列、以及已经解耦合的前i-1个第二LLR序列中至少一个第二LLR序列，进而实现对第一LLR序列进行解耦合，得到第i个第二LLR序列。
在一种可能的实施方式中，码块的耦合度为2；根据第i个第一LLR序列、以及前i-1个第二LLR序列中的至少一个第二LLR序列，确定第i个第二LLR序列，包括：根据第i个第一LLR序列和第i-1个第二LLR序列，确定第i个第二LLR序列。
在一种可能的实施方式中，第一个第二LLR序列与第一个第一LLR序列相同。
在一种可能的实施方式中，码块的耦合度为4；根据第i个第一LLR序列、以及前i-1个第二LLR序列中的至少一个第二LLR序列，确定第i个第二LLR序列，包括：根据第i个第一LLR序列和第i-2个第二LLR序列，确定第i个第二LLR序列，i为3至T之间的整数。
在一种可能的实施方式中，第一个第二LLR序列与第一个第一LLR序列相同；第二个第二LLR序列与第二个第一LLR序列相同。
在一种可能的实施方式中，可以通过如下方式根据T个第二LLR序列进行极化译码：根据第T个第二LLR序列，确定得到第T个译码结果；根据第i+1个译码结果至第T个译码结果中的至少一个译码结果、以及第i个第二LLR序列，确定第i个译码结果，i为1至T-1之间的整数。
在上述过程中，通过对第二LLR序列(短码)进行译码，可以实现得到译码结果，使得译码复杂度较低。
在一种可能的实施方式中，码块的耦合度为2，根据第i+1个译码结果至第T个译码结果中的至少一个译码结果、以及第i个第二LLR序列，确定第i个译码结果，包括：根据第i+1个译码结果、第i+1个第一LLR序列、第i个第二LLR序列，确定第i个译码结果。
第五方面，本申请实施例提供一种编码装置，包括获取模块、确定模块、生成模块和编码模块，其中，
所述获取模块用于，获取K个待编码比特，所述K为正整数；
所述确定模块用于，确定第一生成矩阵，所述第一生成矩阵中包括按照预设位置关系分布的至少两个子块，所述子块中包括多个第一生成矩阵核；
所述生成模块用于，根据所述第一生成矩阵，生成第二生成矩阵，所述第二生成矩阵包括T个子块，所述T个子块中相邻的两个子块之间的位置关系为根据所述预设位置关系确定的，所述T为正整数；
所述编码模块用于，根据所述第二生成矩阵对所述K个待编码比特进行极化编码，得到编码后的比特。
在一种可能的实施方式中，所述T个子块中相邻的两个子块之间的位置关系与所述预设位置关系相同。
在一种可能的实施方式中，所述至少两个子块中存在重合部分。
在一种可能的实施方式中，所述子块的第一对角线上包括所述第一生成矩阵核。
在一种可能的实施方式中，所述子块中的多个第一生成矩阵核以下三角形分布。
在一种可能的实施方式中，所述子块中的第一生成矩阵核的分布与第二生成矩阵核中第一元素的分布相同，所述第二生成矩阵核中的包括的元素数量与所述子块中包括的矩阵单元数量相同，所述子块中包括的矩阵单元为所述第一生成矩阵核或0矩阵。
在一种可能的实施方式中，所述第一生成矩阵中包括两个子块。
在一种可能的实施方式中，所述子块中包括的矩阵单元数量为2*2，所述子块中包括的矩阵单元为所述第一生成矩阵核或0矩阵。
在一种可能的实施方式中，所述第一生成矩阵中包括第一子块和第二子块，所述第一子块中的第一矩阵单元与所述第二子块中的第二矩阵单元重合；
其中，所述第一矩阵单元在所述第一子块中的坐标为(2,2)，所述第二矩阵单元在所述第二子块中的坐标为(1,1)。
在一种可能的实施方式中，所述子块中包括的矩阵单元数量为4*4，所述子块中包括的矩阵单元为第一生成矩阵核或0矩阵。
在一种可能的实施方式中，所述第一生成矩阵中包括第一子块和第二子块，所述第一子块中的4个第一矩阵单元与所述第二子块中的4个第二矩阵单元重合；其中，
所述4个第一矩阵单元在所述第一子块中的坐标分别为：(3,3)、(3,4)、(4,3)、(4,4)；
所述4个第二矩阵单元在所述第二子块中的坐标分别为：(1,1)、(1,2)、(2,1)、(2,2)。
在一种可能的实施方式中，所述K个待编码比特为信息比特；所述编码模块具体用于：
在所述K个待编码比特对应的多个子信道中确定可靠度最高的K个子信道；
根据所述可靠度最高的K个子信道，确定所述K个待编码比特的位置；
根据所述K个待编码比特的位置确定待编码序列，所述待编码序列中包括所述K个待编码比特和冻结比特；
根据所述第二生成矩阵对所述待编码序列进行极化编码，得到编码后的比特。
在一种可能的实施方式中，所述多个子信道中包括P组子信道，所述P为正整数；所述编码模块具体用于：
根据第i组子信道的可靠度，在第i组子信道中确定X i个第一子信道，所述X i个第一子信道为第i组子信道中可靠度最高的X i个子信道，所述i为整数，1≤i≤P，所述X i为正整数，
Figure PCTCN2021086960-appb-000002
所述可靠度最高的K个子信道包括所述第一子信道。
第六方面，本申请实施例提供一种译码装置，包括接收模块和译码模块，其中，
所述接收模块用于，接收极化编码后的比特信息；
所述译码模块用于，根据第二生成矩阵对所述比特信息进行极化译码，得到极化译码后的比特；
其中，所述第二生成矩阵为根据第一生成矩阵生成的，所述第一生成矩阵中包括按照预设位置关系分布的至少两个子块，所述子块中包括多个第一生成矩阵核，所述第二生成矩阵包括T个子块，所述T个子块中相邻的两个子块之间的位置关系为根据所述预设位置关系确定的，所述T为正整数。
在一种可能的实施方式中，所述T个子块中相邻的两个子块之间的位置关系与所述预设位置关系相同。
在一种可能的实施方式中，所述至少两个子块中存在重合部分。
在一种可能的实施方式中，所述子块的第一对角线上包括所述第一生成矩阵核。
在一种可能的实施方式中，所述子块中的多个第一生成矩阵核以下三角形分布。
在一种可能的实施方式中，所述子块中的第一生成矩阵核的分布与第二生成矩阵核中第一元素的分布相同，所述第二生成矩阵核中的包括的元素数量与所述子块中包括的元素数量相同，所述子块中包括的元素为第一生成矩阵核或0矩阵。
在一种可能的实施方式中，所述第一生成矩阵中包括两个子块。
在一种可能的实施方式中，所述子块中包括的元素数量为2*2，所述子块中包括的元素为第一生成矩阵核或0矩阵。
在一种可能的实施方式中，所述第一生成矩阵中包括第一子块和第二子块，所述第一子块中的第一元素与所述第二子块中的第二元素重合；
其中，所述第一元素在所述第一子块中的坐标为(2,2)，所述第二元素在所述第二子块中的坐标为(1,1)。
在一种可能的实施方式中，所述子块中包括的元素数量为4*4，所述子块中包括的元素为第一生成矩阵核或0矩阵。
在一种可能的实施方式中，所述第一生成矩阵中包括第一子块和第二子块，所述第一子块中的4个第一元素与所述第二子块中的4个第二元素重合；其中，
所述4个第一元素在所述第一子块中的坐标分别为：(3,3)、(3,4)、(4,3)、(4,4)；
所述4个第二元素在所述第二子块中的坐标分别为：(1,1)、(1,2)、(2,1)、(2,2)。
在一种可能的实施方式中，所述比特信息包括N′个第一对数似然比LLR序列，所述N′为正整数。
在一种可能的实施方式中，所述N′个第一LLR中包括T个第一LLR序列，所述第一LLR序列中包括至少两个第一LLR；所述译码模块具体用于：
确定所述T个第一LLR序列对应的T个第二LLR序列，一个所述第一LLR序列对应一组或多组编码前的比特，一个所述第二LLR序列对应一组编码前的比特；
根据所述T个第二LLR序列进行极化译码。
在一种可能的实施方式中，所述译码模块具体用于：
根据第i个第一LLR序列、以及前i-1个第二LLR序列中的至少一个第二LLR序列，确定第i个第二LLR序列，所述i为2至T之间的整数。
在一种可能的实施方式中，码块的耦合度为2；所述译码模块具体用于：
根据第i个第一LLR序列和第i-1个第二LLR序列，确定所述第i个第二LLR序列。
在一种可能的实施方式中，第一个第二LLR序列与第一个第一LLR序列相同。
在一种可能的实施方式中，码块的耦合度为4；所述译码模块具体用于：
根据第i个第一LLR序列和第i-2个第二LLR序列，确定所述第i个第二LLR序列，所述i为3至T之间的整数。
在一种可能的实施方式中，第一个第二LLR序列与第一个第一LLR序列相同；
第二个第二LLR序列与第二个第一LLR序列相同。
在一种可能的实施方式中，所述译码模块具体用于：
根据第T个第二LLR序列，确定得到第T个译码结果；
根据第i+1个译码结果至第T个译码结果中的至少一个译码结果、以及第i个第二LLR序列，确定第i个译码结果，所述i为1至T-1之间的整数。
在一种可能的实施方式中，码块的耦合度为2；所述译码模块具体用于：
根据第i+1个译码结果、第i+1个第一LLR序列、第i个第二LLR序列，确定所述第i个译码结果。
第七方面，本申请实施例提供提供一种编码装置，包括获取模块、确定模块、生成模块和编码模块，其中，
所述获取模块用于，获取K个待编码比特，所述K为正整数；
所述确定模块用于，确定第一生成矩阵，所述第一生成矩阵包括第一矩阵块和第二矩阵块，所述第一矩阵块位于所述第一生成矩阵的左上角，所述第二矩阵块位于所述第一生成矩阵的右下角，所述第一矩阵块和所述第二矩阵块相同，沿所述第一生成矩阵的对角线 方向，所述第一矩阵块中的第一元素与所述第二矩阵块中的第二元素之间的距离为u，所述u为大于或等于1的整数；
所述生成模块用于，根据编码长度和所述第一生成矩阵，生成第二生成矩阵，所述第二生成矩阵中包括T个所述第一生成矩阵，所述T个第一生成矩阵沿所述第二生成矩阵的对角线分布，所述T个第一生成矩阵中的第a+1个第一生成矩阵的第一矩阵块与第a个第一生成矩阵的第二矩阵块重合，所述a为大于或等于1的整数，所述T为大于或等于2的整数；
所述编码模块用于，根据所述第二生成矩阵，对所述K个待编码比特进行极化编码，得到编码后的比特。
在一种可能的实施方式中，所述第一矩阵块和所述第二矩阵块中不存在重叠的元素。
在一种可能的实施方式中，所述第一生成矩阵的尺寸为v*v，第一生成矩阵中的元素满足：a i,j＝a i+u,j+u，其中，
所述i为整数，所述j为整数，所述v为正整数，所述u为整数，1≤i＜v，1≤j＜v，1＜i+u≤v，1＜j+u≤v。
在一种可能的实施方式中，所述第一生成矩阵中的元素沿所述第一生成矩阵的副对角线对称。
在一种可能的实施方式中，T为使得第一条件被满足的最小整数，所述第一条件为：所述第二生成矩阵的尺寸大于或等于所述编码长度。
在一种可能的实施方式中，所述T满足如下关系：
v+(T-1)*u＜N′≤v+T*u；
其中，所述v为所述第一生成矩阵的尺寸，所述N′为所述编码长度，所述N′为大于1的整数。
第八方面，本申请实施例提供一种译码装置，包括接收模块和译码模块，其中，
所述接收模块用于，接收极化编码后的比特信息；
所述译码模块用于，根据第二生成矩阵对所述比特信息进行极化译码，得到极化译码后的比特，所述第二生成矩阵为根据第一生成矩阵生成的；
其中，所述第一生成矩阵包括第一矩阵块和第二矩阵块，所述第一矩阵块位于所述第一生成矩阵的左上角，所述第二矩阵块位于所述第一生成矩阵的右下角，所述第一矩阵块和所述第二矩阵块相同，沿所述第一生成矩阵的对角线方向，所述第一矩阵块中的第一元素与所述第二矩阵块中的第二元素之间的距离为u，所述u为大于或等于1的整数；
其中，所述第二生成矩阵中包括T个所述第一生成矩阵，所述T个第一生成矩阵沿所述第二生成矩阵的对角线分布，所述T个第一生成矩阵中的第a+1个第一生成矩阵的第一矩阵块与第a个第一生成矩阵的第二矩阵块重合，所述a为大于或等于1的整数，所述T为大于或等于2的整数。
在一种可能的实施方式中，所述第一矩阵块和所述第二矩阵块中不存在重叠的元素。
在一种可能的实施方式中，所述第一生成矩阵的尺寸为v*v，第一生成矩阵中的元素满足：a i,j＝a i+u,j+u，其中，
所述i为整数，所述j为整数，所述v为正整数，所述u为整数，1≤i＜v，1≤j＜v，1＜i+u≤v，1＜j+u≤v。
在一种可能的实施方式中，所述第一生成矩阵中的元素沿所述第一生成矩阵的副对角线对称。
在一种可能的实施方式中，T为使得第一条件被满足的最小整数，所述第一条件为：所述第二生成矩阵的尺寸大于或等于所述编码长度。
在一种可能的实施方式中，所述T满足如下关系：
v+(T-1)*u＜N′≤v+T*u；
其中，所述v为所述第一生成矩阵的尺寸，所述N′为所述编码长度，所述N′为大于1的整数。
在一种可能的实施方式中，所述比特信息包括N′个第一对数似然比LLR序列，所述N′为正整数。
在一种可能的实施方式中，所述N′个第一LLR中包括T个第一LLR序列，所述第一LLR序列中包括至少两个第一LLR；所述译码模块具体用于：
确定所述T个第一LLR序列对应的T个第二LLR序列，一个所述第一LLR序列对应一组或多组编码前的比特，一个所述第二LLR序列对应一组编码前的比特；
根据所述T个第二LLR序列进行极化译码。
在一种可能的实施方式中，所述译码模块具体用于：
根据第i个第一LLR序列、以及前i-1个第二LLR序列中的至少一个第二LLR序列，确定第i个第二LLR序列，所述i为2至T之间的整数。
在一种可能的实施方式中，码块的耦合度为2；所述译码模块具体用于：
根据第i个第一LLR序列和第i-1个第二LLR序列，确定所述第i个第二LLR序列。
在一种可能的实施方式中，第一个第二LLR序列与第一个第一LLR序列相同。
在一种可能的实施方式中，码块的耦合度为4；所述译码模块具体用于：
根据第i个第一LLR序列和第i-2个第二LLR序列，确定所述第i个第二LLR序列，所述i为3至T之间的整数。
在一种可能的实施方式中，第一个第二LLR序列与第一个第一LLR序列相同；
第二个第二LLR序列与第二个第一LLR序列相同。
在一种可能的实施方式中，所述译码模块具体用于：
根据第T个第二LLR序列，确定得到第T个译码结果；
根据第i+1个译码结果至第T个译码结果中的至少一个译码结果、以及第i个第二LLR序列，确定第i个译码结果，所述i为1至T-1之间的整数。
在一种可能的实施方式中，码块的耦合度为2；所述译码模块具体用于：
根据第i+1个译码结果、第i+1个第一LLR序列、第i个第二LLR序列，确定所述第i个译码结果。
第九方面，本申请实施例提供一种编码装置，包括：存储器、处理器以及计算机程序，所述计算机程序存储在所述存储器中，所述处理器运行所述计算机程序执行如第一方面任一项所述的编码方法。
第十方面，本申请实施例提供一种编码装置，包括：存储器、处理器以及计算机程序，所述计算机程序存储在所述存储器中，所述处理器运行所述计算机程序执行如第二方面任一项所述的译码方法。
第十一方面，本申请实施例提供一种编码装置，包括：存储器、处理器以及计算机程序，所述计算机程序存储在所述存储器中，所述处理器运行所述计算机程序执行如第三方面任一项所述的编码方法。
第十二方面，本申请实施例提供一种编码装置，包括：存储器、处理器以及计算机程序，所述计算机程序存储在所述存储器中，所述处理器运行所述计算机程序执行如第四方面任一项所述的译码方法。
第十三方面，本申请实施例提供一种存储介质，所述存储介质包括计算机程序，所述计算机程序用于实现如第一方面任一项所述的编码方法。
第十四方面，本申请实施例提供一种存储介质，所述存储介质包括计算机程序，所述计算机程序用于实现如第二方面任一项所述的译码方法。
第十五方面，本申请实施例提供一种存储介质，所述存储介质包括计算机程序，所述计算机程序用于实现如第三方面任一项所述的编码方法。
第十六方面，本申请实施例提供一种存储介质，所述存储介质包括计算机程序，所述计算机程序用于实现如第四方面任一项所述的译码方法。
第十七方面，本申请实施例提供一种编码装置，该编码装置可以包括输入接口和逻辑电路，其中，
所述输入接口用于，获取K个待编码比特，所述K为正整数；
所述逻辑电路用于，确定第一生成矩阵，所述第一生成矩阵中包括按照预设位置关系分布的至少两个子块，所述子块中包括多个第一生成矩阵核；根据所述第一生成矩阵，生成第二生成矩阵，所述第二生成矩阵包括T个子块，所述T个子块中相邻的两个子块之间的位置关系为根据所述预设位置关系确定的，所述T为正整数；根据所述第二生成矩阵对所述K个待编码比特进行极化编码，得到编码后的比特。
在一种可能的实施方式中，所述逻辑电路还可以执行第一方面任一项所述的编码方法。
第十八方面，本申请实施例提供一种译码装置，该译码装置可以包括输入接口和逻辑电路，其中，
所述输入接口用于，接收极化编码后的比特信息；
所述逻辑电路用于，根据第二生成矩阵对所述比特信息进行极化译码，得到极化译码后的比特；其中，所述第二生成矩阵为根据第一生成矩阵生成的，所述第一生成矩阵中包括按照预设位置关系分布的至少两个子块，所述子块中包括多个第一生成矩阵核，所述第二生成矩阵包括T个子块，所述T个子块中相邻的两个子块之间的位置关系为根据所述预设位置关系确定的，所述T为正整数。
在一种可能的实施方式中，所述逻辑电路还可以执行第二方面任一项所述的译码方法。
第十九方面，本申请实施例提供一种编码装置的结构示意图，该编码装置可以包括输入接口和逻辑电路，其中，
所述输入接口用于，获取K个待编码比特，所述K为正整数；
所述逻辑电路用于，确定第一生成矩阵，所述第一生成矩阵包括第一矩阵块和第二矩阵块，所述第一矩阵块位于所述第一生成矩阵的左上角，所述第二矩阵块位于所述第一生成矩阵的右下角，所述第一矩阵块和所述第二矩阵块相同，沿所述第一生成矩阵的对角线方向，所述第一矩阵块中的第一元素与所述第二矩阵块中的第二元素之间的距离为u，所 述u为大于或等于1的整数；根据编码长度和所述第一生成矩阵，确定第二生成矩阵，所述第二生成矩阵中包括T个所述第一生成矩阵，所述T个第一生成矩阵沿所述第二生成矩阵的对角线分布，所述T个第一生成矩阵中的第a+1个第一生成矩阵的第一矩阵块与第a个第一生成矩阵的第二矩阵块重合，所述a为大于或等于1的整数，所述T为大于或等于2的整数；根据所述第二生成矩阵，对所述K个待编码比特进行极化编码，得到编码后的比特。
在一种可能的实施方式中，所述逻辑电路还可以执行第三方面任一项所述的编码方法。
第二十方面，本申请实施例提供一种译码装置，该译码装置可以包括输入接口和逻辑电路，其中，
所述输入接口用于，接收极化编码后的比特信息；
所述逻辑电路用于，根据第二生成矩阵对所述比特信息进行极化译码，得到极化译码后的比特，所述第二生成矩阵为根据第一生成矩阵生成的；其中，所述第一生成矩阵包括第一矩阵块和第二矩阵块，所述第一矩阵块位于所述第一生成矩阵的左上角，所述第二矩阵块位于所述第一生成矩阵的右下角，所述第一矩阵块和所述第二矩阵块相同，沿所述第一生成矩阵的对角线方向，所述第一矩阵块中的第一元素与所述第二矩阵块中的第二元素之间的距离为u，所述u为大于或等于1的整数；其中，所述第二生成矩阵中包括T个所述第一生成矩阵，所述T个第一生成矩阵沿所述第二生成矩阵的对角线分布，所述T个第一生成矩阵中的第a+1个第一生成矩阵的第一矩阵块与第a个第一生成矩阵的第二矩阵块重合，所述a为大于或等于1的整数，所述T为大于或等于2的整数。
在一种可能的实施方式中，所述逻辑电路还可以执行第四方面任一项所述的译码方法。
本申请实施例提供一种编码、译码方法、装置及设备方法，当需要对K个待编码比特进行编码时，先确定第一生成矩阵，再根据第一生成矩阵生成第二生成矩阵，并根据第二生成矩阵对K个待编码比特进行极化编码。由于第一生成矩阵中包括至少两个按照预设位置关系分布的子块，每个子块中包括多个第一生成矩阵核，第二生成矩阵中包括T个子块，T个子块中相邻的两个子块之间的位置关系为根据所述预设位置关系确定的，因此，可以得出第二生成矩阵中包括多个按照上述预设位置关系进行排布的子块，每个子块中包括多个第一生成矩阵核。因此，根据第二生成矩阵对K个待编码比特进行极化编码时，相当于先对多个短码进行极化编码，再对多个短码进行耦合，得到编码结果，进而降低编码复杂度。在对根据上述编码方法编码的到的码字进行解码时，可以降低解码的复杂度。
附图说明
图1为本申请提供的通信系统的架构图；
图2为本申请实施例提供的一种编码图；
图3为本申请实施例提供的一种编码方法的流程示意图；
图4为本申请实施例提供的子块的示意图；
图5A为本申请实施例提供的一种第一生成矩阵的示意图；
图5B为本申请实施例提供的另一种第一生成矩阵的示意图；
图5C为本申请实施例提供的又一种第一生成矩阵的示意图；
图6A为本申请实施例提供的一种第二生成矩阵的示意图；
图6B为本申请实施例提供的另一种第二生成矩阵的示意图；
图6C为本申请实施例提供的再一种第二生成矩阵的示意图；
图7A为本申请实施例提供的一种第三生成矩阵的示意图；
图7B为本申请实施例提供的一种第三生成矩阵的示意图；
图8A为本申请实施例提供的一种译码过程示意图；
图8B为本申请实施例提供的另一种译码过程示意图；
图9A为本申请实施例提供的另一种编码图；
图9B为本申请实施例提供的又一种编码图；
图9C为本申请实施例提供的又一种编码图；
图10为本申请实施例提供的另一种编码方法的流程示意图；
图11A为本申请实施例提供的一种第一生成矩阵的示意图；
图11B为本申请实施例提供的又一种第一生成矩阵的示意图；
图11C为本申请实施例提供的另一种第一生成矩阵的示意图；
图12A为本申请实施例提供的再一种第一生成矩阵的示意图；
图12B为本申请实施例提供的再一种第一生成矩阵的示意图；
图13为本申请实施例提供的另一种第二生成矩阵的示意图；
图14为本申请实施例提供的一种生成第二生成矩阵的过程示意图；
图15A为本申请实施例提供的一种第二生成矩阵的示意图；
图15B为本申请实施例提供的另一种第二生成矩阵的示意图；
图15C为本申请实施例提供的一种第二生成矩阵的示意图；
图16为本申请实施例提供的一种译码示意图；
图17为本申请实施例提供的一种译码过程示意图；
图18为本申请实施例提供的一种译码过程示意图；
图19为本申请实施例提供的一种译码性能示意图；
图20A为本申请实施例提供的另一种译码性能示意图；
图20B为本申请实施例提供的另一种译码性能示意图；
图21为本申请实施例提供的一种编码装置的结构示意图；
图22为本申请实施例提供的一种译码装置的结构示意图；
图23为本申请实施例提供的另一种编码装置的结构示意图；
图24为本申请实施例提供的另一种译码装置的结构示意图；
图25为本申请实施例提供的一种编码装置的硬件结构示意图；
图26为本申请实施例提供的译码装置的硬件结构示意图；
图27为本申请实施例提供的另一种编码装置的结构示意图；
图28为本申请实施例提供的另一种译码装置的结构示意图；
图29为本申请实施例提供的另一种编码装置的结构示意图；
图30为本申请实施例提供的另一种译码装置的结构示意图。
具体实施方式
本申请实施例可以应用于各种采用Polar编码的领域，例如：数据存储领域、光网络 通信领域，无线通信领域等等。其中，本申请实施例提及的无线通信系统包括但不限于：窄带物联网系统(narrow band-internet of things，NB-IoT)、Wimax、长期演进系统(long term evolution，LTE)以及下一代5G移动通信系统新空口(new radio，NR)的三大应用场景增强型移动宽带(enhanced mobile broad band，eMBB)、超高可靠与低延迟的通信(ultra reliable low latency communication，URLLC)以及大规模机器通信(massive machine-type communications，mMTC)。当然，采用Polar编码的领域还可以为其它，本申请对此不作具体限定。本申请实施例适用于码长较长的通信场景，例如，包括但不限于大吞吐量的业务场景、高清视频业务场景、大文件传输业务场景、虚拟现实(virtual reality，VR)/增强现实(augmented reality，简称AR)等多媒体业务、无线通信的自动混合重传请求(hybrid automatic repeat request，HARQ)等。
为了便于理解，下面结合图1，介绍本申请实施例所适用的通信系统的架构图。
图1为本申请提供的通信系统的架构图。请参见图1，包括发送设备101和接收设备102。
可选的，当发送设备101为终端设备时，则接收设备102为网络设备。当发送设备101为网络设备时，则接收设备102为终端设备。
请参见图1，发送设备101包括编码器，从而发送设备101可以进行polar编码并输出编码后序列。编码后序列经过速率匹配、交织以及调制后在信道上传输至接收设备102。接收设备102包括译码器，接收设备102可以接收发送设备101发送的信号，对接收到的信号进行译码。
需要说明的是，图1只是以示例的形式示意一种通信系统的架构图，并非对通信系统的架构图的限定。
为了便于理解，下面对本申请实施例所涉及的概念进行介绍。
终端设备：包括但不限于移动台(mobile station，MS)、移动终端(mobile terminal，MT)、移动电话(mobile telephone，MT)、手机(handset)及便携设备(portable equipment)等，该终端设备可以经无线接入网(radio access network，RAN)与一个或多个核心网进行通信。例如，终端设备可以是移动电话(或称为“蜂窝”电话)、具有无线通信功能的计算机等，终端设备还可以是便携式、袖珍式、手持式、计算机内置的或者车载的移动装置或设备。
网络设备：可以是LTE系统中的演进型基站(evolutional node B，eNB或eNodeB)，或者，网络设备可以是5G通信系统中的gNB或者传输和接收点(transmission reception point，TRP)、微基站等，或者网络设备可以为中继站、接入点、车载设备、可穿戴设备以及未来演进的公共陆地移动网络(public land mobile network，PLMN)中的网络设备，或者在其他多种技术融合的网络中，或者在其他各种演进网络中的基站等。
极化编码：极化编码还可以成为polar编码，可以通过如下两种方式描述极化编码：
一种方式：可以通过生成矩阵表示编码过程，即，
Figure PCTCN2021086960-appb-000003
Figure PCTCN2021086960-appb-000004
为一个行向量，
Figure PCTCN2021086960-appb-000005
N为码长，N为大于或等于1的整数。u i为编码前的比特，i为1至N之间的整数。
Figure PCTCN2021086960-appb-000006
中包括信息比特和/或冻结比特，即，u i可以为信息比特或者冻结比特。信息比特为用于携带信息的比特，信息比特可以包括循环冗余校验(Cyclic Redundancy Check，CRC)比特和/或奇偶校验(Parity Check，PC)比特。冻结比 特为填充比特，冻结比特通常可以为0。
G N为生成矩阵，G N为N*N的矩阵，
Figure PCTCN2021086960-appb-000007
其中，B N为一个N*N的转置矩阵，例如，B N可以为比特转置(bit reversal)矩阵。
Figure PCTCN2021086960-appb-000008
为log 2(N)个矩阵F 2的克罗内克(kronecker)乘积。上述所涉及的加法和乘法均为二进制伽罗华域(galois field)上的操作。还可以将G N称为生成矩阵核。
另一种方式：可以通过编码图表示编码过程。
下面，结合图2，对编码图进行说明。
图2为本申请实施例提供的一种编码图。请参见图2，该编码图对应的编码码长为8，第一列中的每个圆圈表示一个信息比特或者冻结比特，第一列所示u 1,u 2,…,u 8为编码前的比特(信息比特或者冻结比特)，其中，u 4,u 6,u 7,u 8为信息比特，u 1,u 2,u 3,u 5为冻结比特。除第一列之外的其它列中每个圆圈表示一个部分和(partial sum)比特。最后一列中的x 1,x 2,…,x 8为编码后的比特。每个蝶形图(图中右侧所示)表示2个比特的一次极化，即，
Figure PCTCN2021086960-appb-000009
在极化编码过程中，码长越大，编码的复杂度越大。例如，当前技术中的极化编码的复杂度为O(N*log 2(N))。为了解决该技术问题，本申请实施例提供一种编码方法，在编码过程中，可以对短码对应的生成矩阵进行处理，得到最终的生成矩阵，并根据最终的生成矩阵进行极化编码，相当于先对多个短码进行极化编码，再对多个短码进行耦合，得到编码结果，进而降低编码复杂度。
通过该最终的生成矩阵进行编码时，可以降低编码的复杂度。
需要说明的是，在本申请实施例中，以矩阵中的起始坐标(最左上角的坐标)为(1,1)为例进行说明，当然，矩阵中的起始坐标还可以(0,0)，本申请实施例对此不作具体限定。
图3为本申请实施例提供的一种编码方法的流程示意图。请参见图3，该方法可以包括：
S301、获取K个待编码比特。
其中，K为正整数。
可选的，K个待编码比特中包括信息比特和冻结比特。或者，K个待编码比特中待编码比特均为信息比特。
S302、确定第一生成矩阵。
其中，第一生成矩阵中包括按照预设位置关系分布的至少两个子块，子块中包括多个第一生成矩阵核。
第一生成矩阵核可以为G N。N＝2 n，n为正整数。在实际应用过程，可以根据实际需要设置N的大小，例如，N可以为预设值。
子块中可以包括第一生成矩阵核和0矩阵(可以表示为0 N)。第一生成矩阵核的尺寸与0矩阵的尺寸相同，例如，假设第一生成矩阵核的尺寸为N*N，则0矩阵的尺寸也为N*N。为了便于描述，在下文中，将第一生成矩阵核或者0矩阵称为矩阵单元。
需要说明的是，在本申请实施例中，矩阵的尺寸是指矩阵中包括行数和列数，可以通过M*N(M为矩阵的行数，N为矩阵的列数)表示矩阵的尺寸。当矩阵为方矩阵(方阵)时，可以通过行数或者列数表示矩阵的尺寸，例如，当矩阵中包括N行N列时，可以通过N*N 表示该矩阵的尺寸，也可以通过N表示该矩阵的尺寸。
下面，结合图4，对子块进行说明。
图4为本申请实施例提供的子块的示意图。请参见图4，子块中包括多个矩阵单元，图4以矩阵单元的数量为16为例进行说明。每个矩阵单元中包括N*N个元素，例如，元素可以为0或1。矩阵单元可以为G N或者0 N。假设N等于2，则
Figure PCTCN2021086960-appb-000010
可选的，子块的第一对角线上包括第一生成矩阵核(G N)。第一对角线可以为子块的主对角线。例如，请参见图4，位于子块的主对角线上的矩阵单元为G N，如第(1,1)、(2,2)、(3,3)、(4,4)个矩阵单元为G N。
可选的，子块中的多个第一生成矩阵核以下三角形分布。例如，请参见图4，子块中的多个G N以下三角形分布。
可选的，子块中的第一生成矩阵核的分布与第二生成矩阵核中第一元素的分布相同，第一元素可以为1。第二生成矩阵核中的元素分布满足
Figure PCTCN2021086960-appb-000011
第二生成矩阵核中的元素数量与第一生成矩阵核中的元素数量可以相同，也可以不同。例如，假设第二生成矩阵核为
Figure PCTCN2021086960-appb-000012
子块如图4所示，则子块中G N的分布与第二生成矩阵核中1的分布相同，相应的，子块中0 N的分布与第二生成矩阵核中0的分布相同。
下面，通过具体示例对子块进行说明。
示例1，假设第二生成矩阵核为
Figure PCTCN2021086960-appb-000013
则子块可以为
Figure PCTCN2021086960-appb-000014
子块中包括的矩阵单元的数量为2*2。其中，子块中G N的分布与第二生成矩阵核中元素1的分布相同。
假设N＝2，则
Figure PCTCN2021086960-appb-000015
将
Figure PCTCN2021086960-appb-000016
代入上述子块中的G N，可以得到子块为：
Figure PCTCN2021086960-appb-000017
假设N＝4，则
Figure PCTCN2021086960-appb-000018
将
Figure PCTCN2021086960-appb-000019
代入上述子块中的G N，可以得到子块为：
Figure PCTCN2021086960-appb-000020
示例2，假设第二生成矩阵核为
Figure PCTCN2021086960-appb-000021
则子块可以为
Figure PCTCN2021086960-appb-000022
子块中G N的分布与第二生成矩阵核中元素1的分布相同。
假设N＝2，则
Figure PCTCN2021086960-appb-000023
将
Figure PCTCN2021086960-appb-000024
代入上述子块中的G N，可以得到子块为：
Figure PCTCN2021086960-appb-000025
第一生成矩阵中包括按照预设位置关系分布的至少两个子块。可选的，第一生成矩阵中包括的子块数量可以为2。
可选的，第一生成矩阵中的至少两个子块中存在重合部分。例如，第一生成矩阵中每两个相邻的子块存在重合部分，假设两个相邻的子块分别为子块1和子块2，子块1的右下角区域中的元素与子块2的左上角区域中的元素重合。
例如，当第一生成矩阵中包括两个子块(分别记为子块1和子块2)时，预设位置关系可以为：子块1位于第一生成矩阵的左上部分，子块2位于第一生成矩阵的右下部分，子块1的右下角区域与子块2的左上角区域重合。
下面，结合图5A-图5C，对第一生成矩阵进行说明。
图5A为本申请实施例提供的一种第一生成矩阵的示意图。图5B为本申请实施例提供的另一种第一生成矩阵的示意图。图5C为本申请实施例提供的又一种第一生成矩阵的示意图。
请参见图5A，第一生成矩阵中包括两个子块，分别记为第一子块和第二子块，第一子块和第二子块相同。第一子块位于第一生成矩阵的左上部分，第二子块位于第一生成矩阵的右下部分。第一子块的右下角区域和第二子块的左上角区域重合，第一子块的右下角区域中的元素与第二子块的左上角区域中的元素分布相同。
请参见图5B，第一生成矩阵中包括第一子块和第二子块，第一子块和第二子块分别为
Figure PCTCN2021086960-appb-000026
则第一生成矩阵可以为
Figure PCTCN2021086960-appb-000027
第一子块位于第一生成矩阵的左上部分，第二子块位于第一生成矩阵的右下部分。第一子块中的第一矩阵单元与第二子块中的第二矩阵单元重合。第一矩阵单元在第一子块中的坐标为(2,2)，第二矩阵单元在第二子块中的坐标为(1,1)。
请参见图5C，第一生成矩阵中包括第一子块和第二子块，第一子块和第二子块分别为
Figure PCTCN2021086960-appb-000028
则第一生成矩阵可以为
Figure PCTCN2021086960-appb-000029
第一子块位于第一生成矩阵的左上部分，第二子块位于第一生成矩阵的右下部分。所述第一子块中的4个第一矩阵单元与所述第二子块中的4个第二矩阵单元重合。4个第一矩阵单元在第一子块中的坐标分别为：(3,3)、(3,4)、(4,3)、(4,4)；4个第二矩阵单元在第二子块中的坐标分别为：(1,1)、(1,2)、(2,1)、(2,2)。
需要说明的是，为了便于描述和查看，在图5B-图5C中，图中省略0 N的标注，即，图 5B-图5C中空白的矩阵单元均为0 N。
S303、根据第一生成矩阵，生成第二生成矩阵。
其中，第二生成矩阵包括T个子块，T个子块中相邻的两个子块之间的位置关系为根据预设位置关系确定的，T为正整数。可选的，T个子块中相邻的两个子块之间的位置关系与预设位置关系相同。
可以根据第一生成矩阵、子块的尺寸和编码长度N′，确定第二生成矩阵中包括的子块的数量T，并根据第一生成矩阵和该数量T生成第二生成矩阵。
可选的，T为使得第一条件满足的最小整数，第一条件为第二生成矩阵的尺寸大于或等于编码长度。第二生成矩阵为方阵，可以通过第二生成矩阵中包括的行数或者列数表示第二生成的尺寸，即，第二生成矩阵的尺寸为第二生成矩阵中包括的行数或者列数。
例如，T满足如下关系：
v+(T-2)*u＜N′≤v+(T-1)*u；
其中，v为子块的尺寸(子块为方阵，v表示子块中包括的元素的行数或者列数)。N′为编码长度，N′为大于1的整数。u为两个相邻子块之间的距离，可以通过两个相邻子块中第一元素(例如，第一元素可以为子块中坐标为(1,1)的元素)之间的距离(行号之差或者列号之差)表示两个相邻子块之间的距离。
例如，假设子块的尺寸v为512，编码长度N′为2048，相邻两个子块之间的距离u为256，则T为7。
例如，假设子块的尺寸v为512，编码长度N′为1500，相邻两个子块之间的距离u为256，则T为5。
下面，结合图6A-图6C，通过具体示例对第二生成矩阵进行说明。
图6A为本申请实施例提供的一种第二生成矩阵的示意图。请参见图6A，第一生成矩阵中包括两个子块，每个子块中包括16个矩阵单元，部分矩阵单元为G N，部分矩阵单元为0 N。两个子块的位置关系如图6A所示。
假设每个矩阵单元的尺寸为128(包括128行128列)，则子块的尺寸为512，第一生成矩阵中的两个子块之间的距离为256，假设编码长度N′为2048，则第二生成矩阵中包括7个子块，分别记为子块1、子块2、……、子块6和子块7。该7个子块中每两个相邻的子块之间的位置关系与第一生成矩阵中的两个子块之间的位置关系相同。第二生成矩阵的尺寸(第二生成矩阵中包括的行数或者列数)为2048。
图6B为本申请实施例提供的另一种第二生成矩阵的示意图。请参见图6B，假设第一生成矩阵中包括两个子块，每个子块中包括16个矩阵单元，部分矩阵单元为G N，部分矩阵单元为0 N。两个子块的位置关系如图6B所示。
假设每个矩阵单元的尺寸为128(包括128行128列)，则子块的尺寸为512，第一生成矩阵中的两个子块之间的距离为256，假设编码长度N′为1500，则第二生成矩阵中包括5个子块，分别记为子块1、子块2、子块3、子块4和子块5，该5个子块中每两个相邻的子块之间的位置关系与第一生成矩阵中的两个子块之间的位置关系相同。第二生成矩阵的尺寸(第二生成矩阵中包括的行数或者列数)为1536。
图6C为本申请实施例提供的再一种第二生成矩阵的示意图。请参见图6C，假设第一生成矩阵中包括两个子块，每个子块中包括4个矩阵单元，部分矩阵单元为G N，部分矩阵 单元为0 N。两个子块的位置关系如图6C所示。
假设每个矩阵单元的尺寸为128(包括128行128列)，则子块的尺寸为256，第一生成矩阵中的两个子块之间的距离为128，假设编码长度N′为1024，则第二生成矩阵中包括7个子块，分别记为子块1、子块2、……、子块6和子块7。该7个子块中每两个相邻的子块之间的位置关系与第一生成矩阵中的两个子块之间的位置关系相同。第二生成矩阵的尺寸(第二生成矩阵中包括的行数或者列数)为1024。
需要说明的是，在图6A-图6C中，除G N之外的矩阵单元均为0 N，为了便于描述和查看，图中省略0 N的标注，即，图6A-图6C中空白的矩阵单元均为0 N。
需要说明的是，图6A-图6C只是以示例的形式示意第二生成矩阵，并非对第二生成矩阵进行的限定，当然，第二生成矩阵还可以为其它，本申请实施例对此不作具体限定。
S304、根据第二生成矩阵对K个待编码比特进行极化编码，得到编码后的比特。
若第二生成矩阵的尺寸等于编码长度，则根据第二生成矩阵对K个待编码比特进行极化编码，得到编码后的比特。
若第二生成矩阵的尺寸大于编码长度，则先在第二生成矩阵中确定第三生成矩阵，并根据第三生成矩阵对K个待编码比特进行极化编码，得到编码后的比特。第三生成矩阵为在第二生成矩阵的左上角区域截取得到的矩阵，或者，第三生成矩阵为在第二生成矩阵的右下角区域截取得到的矩阵。第三生成矩阵为方阵。
下面，结合图7A-图7B，对第三生成矩阵进行说明。
图7A为本申请实施例提供的一种第三生成矩阵的示意图。请参见图7A，假设编码程度为1500，第二生成矩阵的尺寸为1536，则可以在第二生成矩阵的左上角区域截取尺寸为1500的矩阵作为第三生成矩阵。
图7B为本申请实施例提供的一种第三生成矩阵的示意图。请参见图7B，假设编码程度为1500，第二生成矩阵的尺寸为1536，则可以在第二生成矩阵的右下角区域截取尺寸为1500的矩阵作为第三生成矩阵。
在对K个待编码比特进行极化编码时，可以在K个待编码比特对应的多个子信道中确定可靠度最高的K个子信道，根据可靠度最高的K个子信道，确定K个待编码比特的位置，根据K个待编码比特的位置确定待编码序列，待编码序列中包括K个待编码比特和冻结比特，根据第二生成矩阵对待编码序列进行极化编码，得到编码后的比特。
可选的，K个待编码比特的位置为可靠度最高的K个子信道对应的位置。在确定得到K个待编码比特的位置之后，在K个待编码比特的位置填充信息比特(待编码比特)，在其它位置填充冻结比特，得到编码序列，编码序列中包括N′个比特，N′个比特中包括K个信息比特和N′-K个冻结比特。
例如，假设编码长度为8，待编码比特的数量为4，再假设8个子信道中可靠度最高的子信道分别为：子信道4、子信道6、子信道7和子信道8，则子信道4、子信道6、子信道7和子信道8对应的位置用于承载信息比特，其它子信道用于承载冻结比特。则待编码序列可以为00010111，其中，1表示信息比特，0表示冻结比特。
可以通过如下方式确定可靠度最高的K个子信道：
第一种方式：
在多个子信道中确定P组子信道，P为正整数。根据第i组子信道的可靠度，在第i 组子信道中确定X i个第一子信道，可靠度最高的K个子信道包括在每组子信道中确定的第一子信道。其中，X i个第一子信道为第i组子信道中可靠度最高的X i个子信道，i为整数，1≤i≤P，X i为正整数，
Figure PCTCN2021086960-appb-000030
可选的，一组子信道中包括的子信道数量可以与一个矩阵单元的尺寸相同。例如，假设矩阵单元的尺寸为16，则一组子信道中包括16个子信道。
可选的，一组子信道中包括的子信道数量可以与一个子块的尺寸相同。例如，假设一个子块的尺寸为64，则一组子信道中包括64个子信道。
可以预先计算各组子信道的可靠度，并存储各组子信道的可靠度，可以采用如下两种方式存储各组子信道的可靠度：
方式1、存储的可靠度排序序列可以为：r＝{r 1,r 2,…,r N}，其中,r i表示一组子信道的子信道序号，r i在r序列中的位置代表了该子信道r i在所有子信道中的可靠度排名，越靠前表示可靠度越高。
例如，假设一组子信道中包括8个子信道，该8个子信道的序号依次为：1、2、……、7、8。假设可靠度排序序列r＝{4,5,3,6,7,2,1,8}，则说明该8个子信道的可靠度满足：子信道4>子信道5>子信道3>子信道6>子信道7>子信道2>子信道1>子信道8。
方式2、存储的可靠度排序序列为：w＝{w 1,w 2,…,w N}，其中,w i表示一组子信道中第i个子信道的可靠度的大小。w i越大，第i个子信道的可靠度越大。若w i＞w j，则说明第i个子信道的可靠度大于第j个子信道的可靠度。
例如，假设一组子信道中包括8个子信道，可靠度排序序列w＝{2.1,3,4.5,5,3.2，2,2.6，7}，则说明该8个子信道的可靠度分别如表1所示：
表1
子信道 可靠度
子信道1 2.1
子信道2 3
子信道3 4.5
子信道4 5
子信道5 3.2
子信道6 2
子信道7 2.6
子信道8 7
可选的，不同组中子信道的可靠度排序可以相同，也可以不同。当不同组中子信道的可靠度排序相同时，可以仅存储一组子信道的可靠度。
第二种方式：
计算编码码长对应的所有子信道的可靠度，并根据所有子信道的可靠度按照从大到小的顺序排序，将排序后的前K个子信道确定为可靠度最高的K个子信道。
可选的，可以预先计算编码码长对应的所有子信道的可靠度，并存储该可靠度序列。假设协议支持的最大编码码长为N*T，其中，N为一个矩阵单元的尺寸，可以预先计算并存储T个可靠度序列，该T个可靠度序列的长度分别为：T，2T，3T，……，N*T。
在实际应用过程中，若编码码长N′满足如下条件：t′-1＜N′＜t′，则可以选择预先 存储的长度为t′*N的可靠度序列，并在长度为t′*N的可靠度序列中确定可靠度最高的K个子信道。
本申请实施例所示的子信道的可靠度的计算包括：短码之内的可靠度计算和短码之间的可靠度计算。其中，短码内的可靠度计算与现有的计算方式相同。
可选的，当第二生成矩阵不同时，计算子信道的可靠度的方式也不同。下面，结合图8A-图B，通过具体示例介绍计算子信道的可靠度的方式。
示例1，假设第二生成矩阵为图6C所示的第二生成矩阵，该第二生成矩阵对应的编码还可以称为2耦合编码。
下面，结合图8A，对确定子信道的可靠度的过程进行说明。
图8A为本申请实施例提供的一种译码过程示意图。请参见图8A，
Figure PCTCN2021086960-appb-000031
为输入的第i组子信道的第一可靠度，
Figure PCTCN2021086960-appb-000032
为计算得到的第i组子信道的第三可靠度，i为1至8之间的整数。f运算为：f(m 1，m 2)＝φ -1(1-(1-φ(m 1))(1-φ(m 2)))，其中，
Figure PCTCN2021086960-appb-000033
φ -1(x)为φ(x)的反函数。
请参见图8A，先确定第1组子信道的第二可靠度m 1为第1组子信道的第一可靠度
Figure PCTCN2021086960-appb-000034
再对m 1和
Figure PCTCN2021086960-appb-000035
进行f运算，得到第2组子信道的第二可靠度m 2。再对m 2和
Figure PCTCN2021086960-appb-000036
进行f运算，得到第3组子信道的第二可靠度m 3，以此类推，直至得到8组子信道的第二可靠度。用公式表示为：
Figure PCTCN2021086960-appb-000037
Figure PCTCN2021086960-appb-000038
请参见图8A，先确定第8组子信道的第三可靠度
Figure PCTCN2021086960-appb-000039
为第8组子信道的第二可靠度m 8。再确定第7组子信道的第三可靠度
Figure PCTCN2021086960-appb-000040
为
Figure PCTCN2021086960-appb-000041
与m 7之和。再确定第6组子信道的第三可靠度
Figure PCTCN2021086960-appb-000042
为
Figure PCTCN2021086960-appb-000043
与m 6之和，以此类推，直至得到第1组子信道的第三可靠度。用公式表示为：
Figure PCTCN2021086960-appb-000044
图8B为本申请实施例提供的另一种译码过程示意图。请参见图8B，
Figure PCTCN2021086960-appb-000045
为输入的第i组子信道的第一可靠度，f运算与图8A所示的f运算相同。
先根据
Figure PCTCN2021086960-appb-000046
计算m″ i,其中，
Figure PCTCN2021086960-appb-000047
Figure PCTCN2021086960-appb-000048
再根据m″ i计算m i，其中，m 1＝m″ 1，m 3＝m″ 3，m 5＝m″ 5，m 7＝m″ 7，m 8＝f(m″ 8，m″ 7)。
再根据上述计算得到的参数计算
Figure PCTCN2021086960-appb-000049
其中，
Figure PCTCN2021086960-appb-000050
Figure PCTCN2021086960-appb-000051
再根据上述计算得到的参数计算最终的子信道的可靠度
Figure PCTCN2021086960-appb-000052
其中，
Figure PCTCN2021086960-appb-000053
Figure PCTCN2021086960-appb-000054
下面，结合编码图对本申请所示的编码方法进行说明。
图9A为本申请实施例提供的另一种编码图。该编码图对应的第二生成矩阵为图6C中的第二生成矩阵。
请参见图9A，与图2所示的编码图进行对比，图9A中最左侧的方框不再代表一个信息比特或者一个冻结比特，一个方框表示一个短码的编码图，例如，短码的码长可以为一个矩阵单元的尺寸N。除第一列之外的每列中圆圈不再代表一个部分和比特，而是代表一个部分和比特向量。
在上述编译码图中，每个N长的短码的极化次数(编译码图中的边的列数)为log 2(N)次。在此基础上，将短码再进行2次极化，可得到码长为N′的长码。因此，码长为N′的长码的极化次数为log 2(N)+2次，进而总的编译码复杂度为N′*(log 2(N)+2)。由于N可以设为一个不随N′变化的常数，在N′非常大的时候，我们可以忽略常数项，得到编译复杂度为O(N′)。
可以将本申请所示的polar码称为耦合polar码，从编码图的角度看，耦合polar码的编码图可以看作原polar长码编码图的重新组合或者剪裁，下面，结合图9B-图9C，对编码图进行进一步详细说明。
图9B为本申请实施例提供的又一种编码图。请参见图9B，可以在从原Polar长码编码图中抽取若干列，然后组合得到耦合Polar码的编码图。
图9C为本申请实施例提供的又一种编码图。请参见图9C，可以在从原Polar长码编码图中抽取若干行和若干列，然后组合得到耦合Polar码的编码图。
在发送端得到编码后的比特之后，发送编码后的比特，编码后的比特经过速率匹配、交织以及调制后经过信道传输至接收端。
本申请实施例提供的编码方法，当需要对K个待编码比特进行编码时，先确定第一生成矩阵，再根据第一生成矩阵生成第二生成矩阵，并根据第二生成矩阵对K个待编码比特进行极化编码。由于第一生成矩阵中包括至少两个按照预设位置关系分布的子块，每个子块中包括多个第一生成矩阵核，第二生成矩阵中包括T个子块，T个子块中相邻的两个子块之间的位置关系为根据所述预设位置关系确定的，因此，可以得出第二生成矩阵中包括多个按照上述预设位置关系进行排布的子块，每个子块中包括多个第一生成矩阵核。因此，根据第二生成矩阵对K个待编码比特进行极化编码时，相当于先对多个短码进行极化编码，再对多个短码进行耦合，得到编码结果，进而降低编码复杂度。
下面，结合图10介绍另一种编码方法。
图10为本申请实施例提供的另一种编码方法的流程示意图。请参见图10，该方法可以包括：
S1001、获取K个待编码比特。
其中，K为正整数。
需要说明的是，S1001的执行过程可以参见S301，此处不再进行赘述。
S1002、确定第一生成矩阵。
需要说明的是，图10实施例中的第一生成矩阵相当于图3实施例中的子块，图3实施例中对子块的描述可以适用于图10实施例中的第一生成矩阵，此处不再进行赘述。
其中，第一生成矩阵包括第一矩阵块和第二矩阵块，第一矩阵块位于第一生成矩阵的左上角，第二矩阵块位于第一生成矩阵的右下角，第一矩阵块和第二矩阵块相同，沿第一 生成矩阵的对角线方向，第一矩阵块中的第一元素与第二矩阵块中的第二元素之间的距离(下文还可以简称为第一矩阵块和第二矩阵块之间的距离)为u，u为大于或等于1的整数。
可选的，第一元素可以为第一矩阵块中左上角的一个元素，第二元素可以为第二生成矩阵中左上角的一个元素。第一元素和第二元素之间的距离是指第一元素和第二元素的行号之差或者列号之差。例如，第一元素为0或1。
在第一生成矩阵中，除第一矩阵块和第二矩阵块之外的其它元素可以均为0元素。
可选的，第一矩阵块和第二矩阵块中可以包括一个或多个矩阵单元，矩阵单元可以为G N或者0 N。第一矩阵块和第二矩阵块均为方阵。G N和0 N的描述可以参见图3所示的实施例。
第一生成矩阵满足自相似性(或者称为移位自相似性)，自相似性是指：在第一生成矩阵中的第一矩阵块移动(例如，沿第一生成矩阵的主对角线移动)预设距离之后，第一矩阵块可以移动至第二矩阵块所在位置，且第一矩阵块和第二矩阵块中的内容相同。当第一生成矩阵具有自相似性时，第一生成矩阵中的元素满足：a i,j≤a i+u,j+u，其中，i为整数，j为整数，v为第一生成矩阵的尺寸，u为整数，1≤i＜v，1≤j＜v，1＜i+u≤v，1＜j+u≤v。
下面，结合图11A-图11C，对第一生成矩阵中包括第一矩阵块和第二矩阵块进行说明。
图11A为本申请实施例提供的一种第一生成矩阵的示意图。请参见图11A，第一生成矩阵中包括第一矩阵块和第二矩阵块，第一矩阵块位于第一生成矩阵的左上角(或者称为左上角区域)，第二矩阵块位于第一生成矩阵的右下角(或者称为右下角区域)。第一矩阵块和第二矩阵块相同。第一生成矩阵和第二生成矩阵部分重叠。
图11B为本申请实施例提供的又一种第一生成矩阵的示意图。请参见图11B，第一生成矩阵中包括第一矩阵块和第二矩阵块，第一矩阵块位于第一生成矩阵的左上角(或者称为左上角区域)，第二矩阵块位于第一生成矩阵的右下角(或者称为右下角区域)。第一矩阵块和第二矩阵块相同。第一生成矩阵和第二生成矩阵之间具有一定距离，即，第一生成矩阵的右下角的一个元素(简称为元素1)与第二生成矩阵的左上角的一个元素(简称为元素2)之间具有一定距离，例如，元素2与元素1的行号之差大于1。
图11C为本申请实施例提供的另一种第一生成矩阵的示意图。请参见图11C，第一生成矩阵中包括第一矩阵块和第二矩阵块，第一矩阵块位于第一生成矩阵的左上角(或者称为左上角区域)，第二矩阵块位于第一生成矩阵的右下角(或者称为右下角区域)。第一矩阵块和第二矩阵块相同。第一生成矩阵和第二生成矩阵相邻，即，第一生成矩阵的右下角的一个元素(简称为元素1)与第二生成矩阵的左上角的一个元素(简称为元素2)相邻，例如，元素2的行号比元素1的行号大1，元素2的列号比元素1的列号大1。
可选的，第一生成矩阵中的元素沿第一生成矩阵的副对角线对称。
下面，通过具体示例示意第一生成矩阵。
图12A为本申请实施例提供的再一种第一生成矩阵的示意图。请参见图12A，第一生成矩阵中包括第一矩阵块和第二矩阵块，第一矩阵块和第二矩阵块中分别包括一个G N。假设N为128，则第一矩阵块和第二矩阵块之间的距离为128。
图12B为本申请实施例提供的再一种第一生成矩阵的示意图。请参见图12B，第一生 成矩阵中包括第一矩阵块和第二矩阵块，第一矩阵块和第二矩阵块中分别包括四个矩阵单元。假设N为128，则第一矩阵块和第二矩阵块之间的距离为256。
需要说明的是，为了便于描述和查看，在图12A-图12B中，图中省略0 N的标注，即，图12A-图12B中空白的矩阵单元均为0 N。图12A-图12B只是以示例的形式示意第一生成矩阵，并非对第一生成矩阵进行的限定。
S1003、根据编码长度和第一生成矩阵，确定第二生成矩阵。
其中，第二生成矩阵中包括T个第一生成矩阵，T个第一生成矩阵沿第二生成矩阵的对角线(例如，该对角线可以为主对角线)分布，T个第一生成矩阵中的第a+1个第一生成矩阵的第一矩阵块与第a个第一生成矩阵的第二矩阵块重合，a为大于或等于1的整数，T为大于或等于2的整数。
下面，结合图13，对第二生成矩阵进行说明。
图13为本申请实施例提供的另一种第二生成矩阵的示意图。请参见图13，第二生成矩阵中包括5个第一生成矩阵。该5个第一生成矩阵沿第二生成矩阵的主对角线分布，沿着第二生成矩阵的主对角线向下和向右的延伸方向，第一生成矩阵的标号依次增大，位于第二生成矩阵的左上角的矩阵为第1个第一生成矩阵。例如，请参见图13，标号1所指的第一生成矩阵为第1个第一生成矩阵，标号2所指的第一生成矩阵为第2个第一生成矩阵，以此类推，标号5所指的第一生成矩阵为第5个第一生成矩阵。
请参见图13，第1个第一生成矩阵的第二矩阵块与第2个第一生成矩阵的第一矩阵块重合。第2个第一生成矩阵的第二矩阵块与第3个第一生成矩阵的第一矩阵块重合。第3个第一生成矩阵的第二矩阵块与第4个第一生成矩阵的第一矩阵块重合。第4个第一生成矩阵的第二矩阵块与第5个第一生成矩阵的第一矩阵块重合。
T为使得第一条件被满足的最小整数，第一条件为：第二生成矩阵的尺寸大于或等于编码长度。
例如，T满足如下关系：
v+(T-2)*u＜N′≤v+(T-1)*u；
其中，v为第一生成矩阵的尺寸，N′为编码长度，N′为大于1的整数。
例如，假设第一生成矩阵的尺寸v为512，编码长度N′为2048，相邻两个子块之间的距离u为256，则T为7。
例如，假设第一生成矩阵的尺寸v为512，编码长度N′为1500，相邻两个子块之间的距离u为256，则T为5。
可选的，可以根据编码长度和第一生成矩阵，确定第二生成矩阵中包括的第一生成矩阵的数量T，再根据第一生成矩阵和该数量T生成第二生成矩阵。例如，可以沿第一生成矩阵的主对角线方向，复制并移动T-1次第一生成矩阵，得到第二生成矩阵，每次移动距离为u，移动距离是指移动的行数或者列数，例如，移动了3行，则移动距离为3。
下面，结合图14，对根据第一生成矩阵生成第二生成矩阵的过程进行说明。
图14为本申请实施例提供的一种生成第二生成矩阵的过程示意图，请参见图14，第一生成矩阵中包括16个矩阵单元，部分矩阵单元为G N，部分矩阵单元为0 N。第一生成矩阵满足自相似性，第一生成矩阵中第一矩阵块和第二矩阵块的距离(行距或者列距)为u。假设确定得到第二生成矩阵中包括3个第一生成矩阵，则需要对第一生成矩阵进行复制并 移动2次。
请参见图14，在第一次复制并移动的过程中，复制第一生成矩阵1，并将复制的第一生成矩阵1沿主对角线方向移动u行(该u行对应的对角线距离为
Figure PCTCN2021086960-appb-000055
)，得到第一生成矩阵2。第一生成矩阵2的第一矩阵块与第一生成矩阵1的第二矩阵块重合。
请参见图14，在第二次复制并移动的过程中，复制第一生成矩阵2，并将复制的第一生成矩阵2沿主对角线方向移动u行(该u行对应的对角线距离为
Figure PCTCN2021086960-appb-000056
)，得到第一生成矩阵3。第一生成矩阵3的第一矩阵块与第一生成矩阵2的第二矩阵块重合。
确定第二生成矩阵包括第一生成矩阵1、第一生成矩阵2和第一生成矩阵3。
需要说明的是，图14只是以示例的形式示意一种根据第一生成矩阵生成第二生成矩阵的方式，并非对该方式进行的限定。在图14中，除G N之外的矩阵单元均为0 N，为了便于描述和查看，图中省略0 N的标注，即，图14中空白的矩阵单元均为0 N。
下面，结合图15A-图15C，通过具体示例对第二生成矩阵进行说明。
图15A为本申请实施例提供的一种第二生成矩阵的示意图。请参见图15A，第一生成矩阵中包括16个矩阵单元，部分矩阵单元为G N，部分矩阵单元为0 N。第一生成矩阵满足自相似性。
假设每个矩阵单元的尺寸为128(包括128行128列)，则子块的尺寸为512，第一生成矩阵中的两个子块之间的距离为256，假设编码长度N′为2048，则第二生成矩阵中包括7个第一生成矩阵，在该7个第一生成矩阵的每两个相邻的生成矩阵中，后一个生成矩阵的第一矩阵块与前一个第一生成矩阵的第二矩阵块重合。第二生成矩阵的尺寸(第二生成矩阵中包括的行数或者列数)为2048。
图15B为本申请实施例提供的另一种第二生成矩阵的示意图。请参见图15B，第一生成矩阵中包括16个矩阵单元，部分矩阵单元为G N，部分矩阵单元为0 N。第一生成矩阵满足自相似性。
假设每个矩阵单元的尺寸为128(包括128行128列)，则子块的尺寸为512，第一生成矩阵中的两个子块之间的距离为256，假设编码长度N′为1500，则第二生成矩阵中包括5个第一生成矩阵，在该5个第一生成矩阵的每两个相邻的生成矩阵中，后一个生成矩阵的第一矩阵块与前一个第一生成矩阵的第二矩阵块重合。第二生成矩阵的尺寸(第二生成矩阵中包括的行数或者列数)为1536。
图15C为本申请实施例提供的一种第二生成矩阵的示意图。请参见图15C，第一生成矩阵中包括16个矩阵单元，部分矩阵单元为G N，部分矩阵单元为0 N。第一生成矩阵满足自相似性。
假设每个矩阵单元的尺寸为128(包括128行128列)，则子块的尺寸为256，第一生成矩阵中的两个子块之间的距离为128，假设编码长度N′为1024，则第二生成矩阵中包括7个第一生成矩阵，在该7个第一生成矩阵的每两个相邻的生成矩阵中，后一个生成矩阵的第一矩阵块与前一个第一生成矩阵的第二矩阵块重合。第二生成矩阵的尺寸(第二生成矩阵中包括的行数或者列数)为1024。
需要说明的是，在图15A-图15C中，除G N之外的矩阵单元均为0 N，为了便于描述和查看，图中省略0 N的标注，即，图15A-图15C中空白的矩阵单元均为0 N。
S1004、根据第二生成矩阵，对K个待编码比特进行极化编码，得到编码后的比特。
需要说明的是，S1004的执行过程可以参见S304，此处不再进行赘述。
本申请实施例提供的编码方法，当需要对K个待编码比特进行编码时，先确定第一生成矩阵，再根据第一生成矩阵生成第二生成矩阵，并根据第二生成矩阵对K个待编码比特进行极化编码。由于第一生成矩阵具有自相似性，第二生成矩阵中包括多个第一矩阵块，因此，根据第二生成矩阵对K个待编码比特进行极化编码时，相当于先对多个短码进行极化编码，再对多个短码进行耦合，得到编码结果，进而降低编码复杂度。
在上述任意一种编码方法的基础上，下面，介绍基于上述编码方法的译码方法。
图16为本申请实施例提供的一种译码示意图。请参见图16，该方法可以包括：
S1601、接收极化编码后的比特信息。
比特信息包括N′个第一对数似然比(likelihood rate，LLR)序列，N′为正整数。例如，在接收端接收到信号之后，对信号进行解调等处理，得到N′个第一LLR，并根据接收到的N′个第一LLR进行Polar码译码。其中，不管发送端发比特1还是比特0，接收端都可能误判。对于信号r，在接收端正确判为0的概率p(r|b＝0)与正确判为1的概率p(r|b＝1)]的比值就是似然比。为了方便计算处理，对似然比取自然对数，则可以得到对数似然比，也即LLR＝ln[p(r|b＝0)/p(r|b＝1)]。LLR可以是浮点数。
S1602、根据第二生成矩阵对比特信息进行极化译码，得到极化译码后的比特。
可选的，第二生成矩阵为图3实施例中进行极化编码的矩阵。第二生成矩阵的相关描述可以参见图3所示的实施例，此处不再进行赘述。
可选的，第二生成矩阵为图10实施例中进行极化编码的矩阵。第二生成矩阵的相关描述可以参见图10所示的实施例，此处不再进行赘述。
在图3或图10所示的实施例中，编码序列中包括N′个编码前的比特，N′个编码前的比特中包括K个信息比特和N′-K个冻结比特。N′个比特中可以包括T组编码前的比特，每组编码前的比特中包括N个编码前的比特，即，N′＝N*T。
N′个第一LLR中包括T个第一LLR序列，换句话说，N′个第一LLR可以换分为T个第一LLR序列，一个第一LLR序列中包括N个LLR。
一个第一LLR序列可以与两组或者多组编码前的比特。例如，假设编码序列中包括8组编码前的比特，且第二生成矩阵如图6C所示，则N′个第一LLR中包括8个第一LLR序列，该8个第一LLR序列与编码前的比特组的关系如表2所示：
表2
第一LLR序列的标识 编码前的比特组
第一LLR序列1 第1组编码前的比特、第2组编码前的比特
第一LLR序列2 第2组编码前的比特、第3组编码前的比特
第一LLR序列3 第3组编码前的比特、第4组编码前的比特
第一LLR序列4 第4组编码前的比特、第5组编码前的比特
第一LLR序列5 第5组编码前的比特、第6组编码前的比特
第一LLR序列6 第6组编码前的比特、第7组编码前的比特
第一LLR序列7 第7组编码前的比特、第8组编码前的比特
第一LLR序列8 第8组编码前的比特
请参见表2，第一LLR序列1与第1组编码前的比特和第2组编码前的比特相关，第 一LLR序列2与第2组编码前的比特和第3组编码前的比特相关，依次类推。
为了进行准确译码，可以对第一LLR序列进行解耦，得到每个第一LLR序列对应的第二LLR序列，使得一个第二LLR序列与一组编码前的比特对应。例如，对表2所示的第一LLR序列进行解耦，得到8个第二LLR序列，该8个第二LLR序列与编码前的比特组的关系如表3所示：
表3
第一LLR序列的标识 编码前的比特组
第一LLR序列1 第1组编码前的比特
第一LLR序列2 第2组编码前的比特
第一LLR序列3 第3组编码前的比特
第一LLR序列4 第4组编码前的比特
第一LLR序列5 第5组编码前的比特
第一LLR序列6 第6组编码前的比特
第一LLR序列7 第7组编码前的比特
第一LLR序列8 第8组编码前的比特
请参见表2，第一LLR序列1与第1组编码前的比特相关，第一LLR序列2与第2组编码前的比特，依次类推。
可选的，可以通过如下方式根据第一LLR序列确定第二LLR序列：根据第i个第一LLR序列、以及前i-1个第二LLR序列中的至少一个第二LLR序列，确定第i个第二LLR序列，所述i为2至T之间的整数。
可选的，可以通过如下方式根据T个第二LLR序列进行极化译码：根据第T个第二LLR序列，确定得到第T个译码结果；根据第i+1个译码结果至第T个译码结果中的至少一个译码结果、以及第i个第二LLR序列，确定第i个译码结果，i为1至T-1之间的整数。
下面，通过具体示例对确定第二LLR序列，以及根据T个第二LLR序列进行极化译码的过程进行说明。
示例1，假设第二生成矩阵为图6C所示的第二生成矩阵，该第二生成矩阵对应的编码还可以称为2耦合编码。
可以通过如下方式确定第i个第二LLR序列：根据第i个第一LLR序列和第i-1个第二LLR序列，确定第i个第二LLR序列。其中，第1个第二LLR序列与第1个第一LLR序列相同。
可以通过如下方式确定第i个译码结果：根据第i+1个译码结果、第i+1个第一LLR序列、第i个第二LLR序列，确定所述第i个译码结果。
下面，结合图17，对上述第二生成矩阵对应的译码过程进行说明。
图17为本申请实施例提供的一种译码过程示意图。请参见图17，l′ i为第i个第一LLR序列，l i为第i个第二LLR序列，u i为编码前的第i个比特序列，c i为编码后的第i个比特序列，i为1至8之间的整数。f运算为：f(L 1，L 2)＝sgn(L 1)sgn(L 2)min(|L 1|,|L 2|)。g运算为：
Figure PCTCN2021086960-appb-000057
对c进行编码得到u。
在接收端接收到N′个LLR之后，将接收到的N′个LLR被分为8个第一LLR序列，该8个第一LLR序列分别记为：l′ 1、l′ 2、l′ 3、l′ 4、l′ 5、l′ 6、l′ 7、l′ 8。上述8个第一LLR序列对应第 二LLR序列分别记为：l 1、l 2、l 3、l 4、l 5、l 6、l 7、l 8。
请参见图17，先确定得到第1个第二LLR序列l 1。再对第1个第二LLR序列l 1和第2个第一LLR序列l′ 2进行f运算，得到第2个第二LLR序列l 2。再对第2个第二LLR序列l 2和第3个第一LLR序列l′ 3进行f运算，得到第3个第二LLR序列l 3，以此类推，直至得到上述8个第二LLR序列。用公式表示为：l 1＝l′ 1，l 2＝f(l′ 2，l 1)，l 3＝f(l′ 3，l 2)，l 4＝f(l′ 4，l 3)，l 5＝f(l′ 5，l 4)，l 5＝f(l′ 6，l 5)，l 7＝f(l′ 7，l 6)，l 8＝f(l′ 8，l 7)。
请参见图17，先将第8个第二LLR序列l 8输入至译码器进行译码，得到第8个译码结果u 8，其中，u 8中包括N个译码比特。对u 8进行编码，得到第8个编码后的比特序列c 8。对c 8、l′ 8和l 7进行g运算得到g运算结果
Figure PCTCN2021086960-appb-000058
并将g运算结果
Figure PCTCN2021086960-appb-000059
输入至译码器进行译码，得到第7个译码结果u 7。对u 7进行编码，得到第7个编码后的比特序列c 7。对c 7、l′ 7和l 6进行g运算得到g运算结果
Figure PCTCN2021086960-appb-000060
并将g运算结果
Figure PCTCN2021086960-appb-000061
输入至译码器进行译码，得到第6个译码结果u 6。以此类推，直至确定得到第1个译码结果u 1。
示例2，假设第二生成矩阵为图14所示的第二生成矩阵，该第二生成矩阵对应的编码还可以称为4耦合编码。
可以通过如下方式确定第i个第二LLR序列：根据第i个第一LLR序列和第i-2个第二LLR序列，确定所述第i个第二LLR序列，所述i为3至T之间的整数。其中，第一个第二LLR序列与第一个第一LLR序列相同；第二个第二LLR序列与第二个第一LLR序列相同。
下面，结合图18，对上述第二生成矩阵对应的译码过程进行说明。
图18为本申请实施例提供的一种译码过程示意图。在图18中，f运算可以g运算与图17相同。
请参见图17，l′ i为第i个第一LLR序列。在接收端接收到N′个LLR之后，将接收到的N′个LLR被分为8个第一LLR序列，该8个第一LLR序列分别记为：l′ 1、l′ 2、l′ 3、l′ 4、l′ 5、l′ 6、l′ 7、l′ 8。
先根据l′ i计算l″ i，其中，l″ 1＝l′ 1，l″ 2＝l′ 2，l″ 3＝f(l′ 3,l″ 1),l″ 4＝f(l′ 4,l″ 2),l″ 5＝f(l′ 5,l″ 3),l″ 6＝f(l′ 6,l″ 4),l″ 7＝f(l′ 7,l″ 5),l″ 8＝f(l′ 8,l″ 6)。l″ i为第i个第二LLR序列。
再根据l″ i计算l i，其中，l 8＝f(l″ 8,l″ 7)，l 7＝l″ 7，l 5＝l″ 5，l 3＝l″ 3，l 1＝l″ 1。
再根据上述计算得到的参数进行译码：将l 8输入译码器进行译码得到第8个译码结果u 8，其中，u 8中包括N个译码比特。对u 8进行编码，得到第8个编码后的比特序列c 8。对c 8、l″ 8、l″ 7进行g运算，并将g运算结果
Figure PCTCN2021086960-appb-000062
输入至译码器进行译码，得到第7个译码结果u 7，对u 7进行编码，得到第7个编码后的比特序列c 7。对c 8+c 7、l′ 8、l″ 6进行g运算，得到g运算结果
Figure PCTCN2021086960-appb-000063
对
Figure PCTCN2021086960-appb-000064
和
Figure PCTCN2021086960-appb-000065
进行g运算，得到g运算结果
Figure PCTCN2021086960-appb-000066
其中，
Figure PCTCN2021086960-appb-000067
为对c 7、l′ 7、l″ 5进行g运算的结果。将
Figure PCTCN2021086960-appb-000068
输入至译码器进行译码，得到第6个译码结果u 6。以此类推，直至确定得到第1个译码结果u 1。
下面，结合图19，对本申请的译码方法的译码性能进行说明。
图19为本申请实施例提供的一种译码性能示意图。请参见图19，横轴表示信噪比(signal to noise ratio，SNR)，纵轴表示误块率(Block Error Rate，BLER)。
请参见图19，当码长为2048、信息比特的数量为1024、且无耦合(现有的方式)时，性能曲线如虚线所示。当码长为16384、信息比特的数量K为8129、且进行2耦合(例如，第二生成矩阵如图6C所示)时，性能曲线如实线所示。由图19可知，采用本申请所示的 方式，可以使得性能增益约1dB。
在实际应用过程中，耦合Polar码相对于长Polar码来说，在性能不损失的情况下，具有更小的复杂度。当码长增加到一定长度以后，更大范围内的耦合并不能带来显著的性能增益。下面，结合图20A进行说明。
图20A为本申请实施例提供的另一种译码性能示意图。请参见图20A，当码长为65536、信息比特的数量K为32768、且无耦合(现有的方式)时，性能曲线如实线所示。当码长为65536、信息比特的数量K为32768、且进行2耦合(例如，第二生成矩阵如图6C所示)时，性能曲线如其中一条虚线所示。当码长为65536、信息比特的数量K为32768、且进行4耦合(例如，第二生成矩阵如图14所示)时，性能曲线如其中另一条虚线所示。
图20B为本申请实施例提供的另一种译码性能示意图。请参见图20B，当码长为131072、信息比特的数量K为65536、且无耦合(现有的方式)时，性能曲线如实线所示。当码长为131072、信息比特的数量K为65536、且进行2耦合(例如，第二生成矩阵如图6C所示)时，性能曲线如其中一条虚线所示。当码长为131072、信息比特的数量K为65536、且进行4耦合(例如，第二生成矩阵如图14所示)时，性能曲线如其中另一条虚线所示。
当耦合范围越大时，编译码复杂度越高，并且由图20A-图20B可知，可以一定程度地限制耦合范围或宽度，或选择恰当的耦合程度，可以做到不损失性能的情况下，尽可能地降低软硬件实现复杂度。
图21为本申请实施例提供的一种编码装置的结构示意图。请参见图21，该编码装置10可以包括获取模块11、确定模块12、生成模块13和编码模块14，其中，
所述获取模块11用于，获取K个待编码比特，所述K为正整数；
所述确定模块12用于，确定第一生成矩阵，所述第一生成矩阵中包括按照预设位置关系分布的至少两个子块，所述子块中包括多个第一生成矩阵核；
所述生成模块13用于，根据所述第一生成矩阵，生成第二生成矩阵，所述第二生成矩阵包括T个子块，所述T个子块中相邻的两个子块之间的位置关系为根据所述预设位置关系确定的，所述T为正整数；
所述编码模块14用于，根据所述第二生成矩阵对所述K个待编码比特进行极化编码，得到编码后的比特。
可选的，获取模块11可以执行图3实施例中的S301。
可选的，确定模块12可以执行图3实施例中的S302。
可选的，生成模块13可以执行图3实施例中的S303。
可选的，编码模块13可以执行图3实施例中的S304。
需要说明的是，本申请实施例所示的编码装置可以执行上述方法实施例所示的技术方案，其实现原理以及有益效果类似，此次不再进行赘述。
在一种可能的实施方式中，所述T个子块中相邻的两个子块之间的位置关系与所述预设位置关系相同。
在一种可能的实施方式中，所述至少两个子块中存在重合部分。
在一种可能的实施方式中，所述子块的第一对角线上包括所述第一生成矩阵核。
在一种可能的实施方式中，所述子块中的多个第一生成矩阵核以下三角形分布。
在一种可能的实施方式中，所述子块中的第一生成矩阵核的分布与第二生成矩阵核中 第一元素的分布相同，所述第二生成矩阵核中的包括的元素数量与所述子块中包括的矩阵单元数量相同，所述子块中包括的矩阵单元为所述第一生成矩阵核或0矩阵。
在一种可能的实施方式中，所述第一生成矩阵中包括两个子块。
在一种可能的实施方式中，所述子块中包括的矩阵单元数量为2*2，所述子块中包括的矩阵单元为所述第一生成矩阵核或0矩阵。
在一种可能的实施方式中，所述第一生成矩阵中包括第一子块和第二子块，所述第一子块中的第一矩阵单元与所述第二子块中的第二矩阵单元重合；
其中，所述第一矩阵单元在所述第一子块中的坐标为(2,2)，所述第二矩阵单元在所述第二子块中的坐标为(1,1)。
在一种可能的实施方式中，所述子块中包括的矩阵单元数量为4*4，所述子块中包括的矩阵单元为第一生成矩阵核或0矩阵。
在一种可能的实施方式中，所述第一生成矩阵中包括第一子块和第二子块，所述第一子块中的4个第一矩阵单元与所述第二子块中的4个第二矩阵单元重合；其中，
所述4个第一矩阵单元在所述第一子块中的坐标分别为：(3,3)、(3,4)、(4,3)、(4,4)；
所述4个第二矩阵单元在所述第二子块中的坐标分别为：(1,1)、(1,2)、(2,1)、(2,2)。
在一种可能的实施方式中，所述K个待编码比特为信息比特；所述编码模块14具体用于：
在所述K个待编码比特对应的多个子信道中确定可靠度最高的K个子信道；
根据所述可靠度最高的K个子信道，确定所述K个待编码比特的位置；
根据所述K个待编码比特的位置确定待编码序列，所述待编码序列中包括所述K个待编码比特和冻结比特；
根据所述第二生成矩阵对所述待编码序列进行极化编码，得到编码后的比特。
在一种可能的实施方式中，所述多个子信道中包括P组子信道，所述P为正整数；所述编码模块14具体用于：
根据第i组子信道的可靠度，在第i组子信道中确定X i个第一子信道，所述X i个第一子信道为第i组子信道中可靠度最高的X i个子信道，所述i为整数，1≤i≤P，所述X i为正整数，
Figure PCTCN2021086960-appb-000069
所述可靠度最高的K个子信道包括所述第一子信道。
需要说明的是，本申请实施例所示的编码装置可以执行上述方法实施例所示的技术方案，其实现原理以及有益效果类似，此次不再进行赘述。
图22为本申请实施例提供的一种译码装置的结构示意图。请参见图22，该译码装置20可以包括接收模块21和译码模块22，其中，
所述接收模块21用于，接收极化编码后的比特信息；
所述译码模块22用于，根据第二生成矩阵对所述比特信息进行极化译码，得到极化译码后的比特；
其中，所述第二生成矩阵为根据第一生成矩阵生成的，所述第一生成矩阵中包括按照预设位置关系分布的至少两个子块，所述子块中包括多个第一生成矩阵核，所述第二生成 矩阵包括T个子块，所述T个子块中相邻的两个子块之间的位置关系为根据所述预设位置关系确定的，所述T为正整数。
可选的，接收模块21可以执行图16实施例中的S1601。
可选的，译码模块22可以执行图16实施例中的S1602。
需要说明的是，本申请实施例所示的编码装置可以执行上述方法实施例所示的技术方案，其实现原理以及有益效果类似，此次不再进行赘述。
在一种可能的实施方式中，所述T个子块中相邻的两个子块之间的位置关系与所述预设位置关系相同。
在一种可能的实施方式中，所述至少两个子块中存在重合部分。
在一种可能的实施方式中，所述子块的第一对角线上包括所述第一生成矩阵核。
在一种可能的实施方式中，所述子块中的多个第一生成矩阵核以下三角形分布。
在一种可能的实施方式中，所述子块中的第一生成矩阵核的分布与第二生成矩阵核中第一元素的分布相同，所述第二生成矩阵核中的包括的元素数量与所述子块中包括的元素数量相同，所述子块中包括的元素为第一生成矩阵核或0矩阵。
在一种可能的实施方式中，所述第一生成矩阵中包括两个子块。
在一种可能的实施方式中，所述子块中包括的元素数量为2*2，所述子块中包括的元素为第一生成矩阵核或0矩阵。
在一种可能的实施方式中，所述第一生成矩阵中包括第一子块和第二子块，所述第一子块中的第一元素与所述第二子块中的第二元素重合；
其中，所述第一元素在所述第一子块中的坐标为(2,2)，所述第二元素在所述第二子块中的坐标为(1,1)。
在一种可能的实施方式中，所述子块中包括的元素数量为4*4，所述子块中包括的元素为第一生成矩阵核或0矩阵。
在一种可能的实施方式中，所述第一生成矩阵中包括第一子块和第二子块，所述第一子块中的4个第一元素与所述第二子块中的4个第二元素重合；其中，
所述4个第一元素在所述第一子块中的坐标分别为：(3,3)、(3,4)、(4,3)、(4,4)；
所述4个第二元素在所述第二子块中的坐标分别为：(1,1)、(1,2)、(2,1)、(2,2)。
在一种可能的实施方式中，所述比特信息包括N′个第一对数似然比LLR序列，所述N′为正整数。
在一种可能的实施方式中，所述N′个第一LLR中包括T个第一LLR序列，所述第一LLR序列中包括至少两个第一LLR；所述译码模块22具体用于：
确定所述T个第一LLR序列对应的T个第二LLR序列，一个所述第一LLR序列对应一组或多组编码前的比特，一个所述第二LLR序列对应一组编码前的比特；
根据所述T个第二LLR序列进行极化译码。
在一种可能的实施方式中，所述译码模块22具体用于：
根据第i个第一LLR序列、以及前i-1个第二LLR序列中的至少一个第二LLR序列，确定第i个第二LLR序列，所述i为2至T之间的整数。
在一种可能的实施方式中，码块的耦合度为2；所述译码模块22具体用于：
根据第i个第一LLR序列和第i-1个第二LLR序列，确定所述第i个第二LLR序列。
在一种可能的实施方式中，第一个第二LLR序列与第一个第一LLR序列相同。
在一种可能的实施方式中，码块的耦合度为4；所述译码模块22具体用于：
根据第i个第一LLR序列和第i-2个第二LLR序列，确定所述第i个第二LLR序列，所述i为3至T之间的整数。
在一种可能的实施方式中，第一个第二LLR序列与第一个第一LLR序列相同；
第二个第二LLR序列与第二个第一LLR序列相同。
在一种可能的实施方式中，所述译码模块22具体用于：
根据第T个第二LLR序列，确定得到第T个译码结果；
根据第i+1个译码结果至第T个译码结果中的至少一个译码结果、以及第i个第二LLR序列，确定第i个译码结果，所述i为1至T-1之间的整数。
在一种可能的实施方式中，码块的耦合度为2；所述译码模块22具体用于：
根据第i+1个译码结果、第i+1个第一LLR序列、第i个第二LLR序列，确定所述第i个译码结果。
需要说明的是，本申请实施例所示的编码装置可以执行上述方法实施例所示的技术方案，其实现原理以及有益效果类似，此次不再进行赘述。
图23为本申请实施例提供的另一种编码装置的结构示意图。请参见图23，该编码装置30可以包括获取模块31、确定模块32、生成模块33和编码模块34，其中，
所述获取模块31用于，获取K个待编码比特，所述K为正整数；
所述确定模块32用于，确定第一生成矩阵，所述第一生成矩阵包括第一矩阵块和第二矩阵块，所述第一矩阵块位于所述第一生成矩阵的左上角，所述第二矩阵块位于所述第一生成矩阵的右下角，所述第一矩阵块和所述第二矩阵块相同，沿所述第一生成矩阵的对角线方向，所述第一矩阵块中的第一元素与所述第二矩阵块中的第二元素之间的距离为u，所述u为大于或等于1的整数；
所述生成模块33用于，根据编码长度和所述第一生成矩阵，生成第二生成矩阵，所述第二生成矩阵中包括T个所述第一生成矩阵，所述T个第一生成矩阵沿所述第二生成矩阵的对角线分布，所述T个第一生成矩阵中的第a+1个第一生成矩阵的第一矩阵块与第a个第一生成矩阵的第二矩阵块重合，所述a为大于或等于1的整数，所述T为大于或等于2的整数；
所述编码模块34用于，根据所述第二生成矩阵，对所述K个待编码比特进行极化编码，得到编码后的比特。
可选的，获取模块31可以执行图10实施例中的S1001。
可选的，确定模块32可以执行图10实施例中的S1002。
可选的，生成模块33可以执行图10实施例中的S1003。
可选的，编码模块34可以执行图10实施例中的S1004。
需要说明的是，本申请实施例所示的编码装置可以执行上述方法实施例所示的技术方案，其实现原理以及有益效果类似，此次不再进行赘述。
在一种可能的实施方式中，所述第一矩阵块和所述第二矩阵块中不存在重叠的元素。
在一种可能的实施方式中，所述第一生成矩阵的尺寸为v*v，第一生成矩阵中的元素满足：a i,j＝a i+u,j+u，其中，
所述i为整数，所述j为整数，所述v为正整数，所述u为整数，1≤i＜v，1≤j＜v，1＜i+u≤v，1＜j+u≤v。
在一种可能的实施方式中，所述第一生成矩阵中的元素沿所述第一生成矩阵的副对角线对称。
在一种可能的实施方式中，T为使得第一条件被满足的最小整数，所述第一条件为：所述第二生成矩阵的尺寸大于或等于所述编码长度。
在一种可能的实施方式中，所述T满足如下关系：
v+(T-1)*u＜N′≤v+T*u；
其中，所述v为所述第一生成矩阵的尺寸，所述N′为所述编码长度，所述N′为大于1的整数。
需要说明的是，本申请实施例所示的编码装置可以执行上述方法实施例所示的技术方案，其实现原理以及有益效果类似，此次不再进行赘述。
图24为本申请实施例提供的另一种译码装置的结构示意图。请参见图24，该译码装置40可以包括接收模块41和译码模块42，其中，
所述接收模块41用于，接收极化编码后的比特信息；
所述译码模块42用于，根据第二生成矩阵对所述比特信息进行极化译码，得到极化译码后的比特，所述第二生成矩阵为根据第一生成矩阵生成的；
其中，所述第一生成矩阵包括第一矩阵块和第二矩阵块，所述第一矩阵块位于所述第一生成矩阵的左上角，所述第二矩阵块位于所述第一生成矩阵的右下角，所述第一矩阵块和所述第二矩阵块相同，沿所述第一生成矩阵的对角线方向，所述第一矩阵块中的第一元素与所述第二矩阵块中的第二元素之间的距离为u，所述u为大于或等于1的整数；
其中，所述第二生成矩阵中包括T个所述第一生成矩阵，所述T个第一生成矩阵沿所述第二生成矩阵的对角线分布，所述T个第一生成矩阵中的第a+1个第一生成矩阵的第一矩阵块与第a个第一生成矩阵的第二矩阵块重合，所述a为大于或等于1的整数，所述T为大于或等于2的整数。
可选的，接收模块41可以执行图16实施例中的S1601。
可选的，译码模块42可以执行图16实施例中的S1602。
需要说明的是，本申请实施例所示的编码装置可以执行上述方法实施例所示的技术方案，其实现原理以及有益效果类似，此次不再进行赘述。
在一种可能的实施方式中，所述第一矩阵块和所述第二矩阵块中不存在重叠的元素。
在一种可能的实施方式中，所述第一生成矩阵的尺寸为v*v，第一生成矩阵中的元素满足：a i,j＝a i+u,j+u，其中，
所述i为整数，所述j为整数，所述v为正整数，所述u为整数，1≤i＜v，1≤j＜v，1＜i+u≤v，1＜j+u≤v。
在一种可能的实施方式中，所述第一生成矩阵中的元素沿所述第一生成矩阵的副对角线对称。
在一种可能的实施方式中，T为使得第一条件被满足的最小整数，所述第一条件为： 所述第二生成矩阵的尺寸大于或等于所述编码长度。
在一种可能的实施方式中，所述T满足如下关系：
v+(T-1)*u＜N′≤v+T*u；
其中，所述v为所述第一生成矩阵的尺寸，所述N′为所述编码长度，所述N′为大于1的整数。
在一种可能的实施方式中，所述比特信息包括N′个第一对数似然比LLR序列，所述N′为正整数。
在一种可能的实施方式中，所述N′个第一LLR中包括T个第一LLR序列，所述第一LLR序列中包括至少两个第一LLR；所述译码模块42具体用于：
确定所述T个第一LLR序列对应的T个第二LLR序列，一个所述第一LLR序列对应一组或多组编码前的比特，一个所述第二LLR序列对应一组编码前的比特；
根据所述T个第二LLR序列进行极化译码。
在一种可能的实施方式中，所述译码模块42具体用于：
根据第i个第一LLR序列、以及前i-1个第二LLR序列中的至少一个第二LLR序列，确定第i个第二LLR序列，所述i为2至T之间的整数。
在一种可能的实施方式中，码块的耦合度为2；所述译码模块42具体用于：
根据第i个第一LLR序列和第i-1个第二LLR序列，确定所述第i个第二LLR序列。
在一种可能的实施方式中，第一个第二LLR序列与第一个第一LLR序列相同。
在一种可能的实施方式中，码块的耦合度为4；所述译码模块42具体用于：
根据第i个第一LLR序列和第i-2个第二LLR序列，确定所述第i个第二LLR序列，所述i为3至T之间的整数。
在一种可能的实施方式中，第一个第二LLR序列与第一个第一LLR序列相同；
第二个第二LLR序列与第二个第一LLR序列相同。
在一种可能的实施方式中，所述译码模块42具体用于：
根据第T个第二LLR序列，确定得到第T个译码结果；
根据第i+1个译码结果至第T个译码结果中的至少一个译码结果、以及第i个第二LLR序列，确定第i个译码结果，所述i为1至T-1之间的整数。
在一种可能的实施方式中，码块的耦合度为2；所述译码模块42具体用于：
根据第i+1个译码结果、第i+1个第一LLR序列、第i个第二LLR序列，确定所述第i个译码结果。
需要说明的是，本申请实施例所示的编码装置可以执行上述方法实施例所示的技术方案，其实现原理以及有益效果类似，此次不再进行赘述。
图25为本申请实施例提供的一种编码装置的硬件结构示意图。请参见图25，该编码装置50可以包括：处理器51以及存储器52，其中，
存储器52，用于存储计算机程序，还可以用于存储中间数据；
处理器51，用于执行存储器存储的计算机程序，以实现上述编码方法中的各个步骤。具体可以参见前面方法实施例中的相关描述。
可选地，存储器52既可以是独立的，也可以跟处理器51集成在一起。在有些实施方式中，存储器52甚至还可以位于编码装置50之外。
当所述存储器52是独立于处理器51之外的器件时，所述编码装置50还可以包括总线53，用于连接所述存储器52和处理器51。
可选的，编码装置50还可以进一步包括发送器。例如，发送器用于发送编码后的比特。
本实施例提供的编码装置50可以为终端设备，或者也以为网络设备，可用于执行上述的编码方法，其实现方式和技术效果类似，本实施例此处不再赘述。
图26为本申请实施例提供的译码装置的硬件结构示意图。请参见图26，该译码装置60可以包括：处理器61以及存储器62，其中，
存储器62，用于存储计算机程序，还可以用于存储中间数据；
处理器61，用于执行存储器存储的计算机程序，以实现上述译码方法中的各个步骤。具体可以参见前面方法实施例中的相关描述。
可选地，存储器62既可以是独立的，也可以跟处理器61集成在一起。在有些实施方式中，存储器62甚至还可以位于译码装置60之外。
当所述存储器62是独立于处理器61之外的器件时，所述译码装置60还可以包括总线63，用于连接所述存储器62和处理器61。
可选的，译码装置60还可以进一步包括接收器。例如，接收器用于接收极化编码后的比特信息。
本实施例提供的译码装置60可以为终端设备，或者也以为网络设备，可用于执行上述的译码方法，其实现方式和技术效果类似，本实施例此处不再赘述。
图27为本申请实施例提供的另一种编码装置的结构示意图。请参见图27，该编码装置70可以包括输入接口71和逻辑电路72，其中，
所述输入接口71用于，获取K个待编码比特，所述K为正整数；
所述逻辑电路72用于，确定第一生成矩阵，所述第一生成矩阵中包括按照预设位置关系分布的至少两个子块，所述子块中包括多个第一生成矩阵核；根据所述第一生成矩阵，生成第二生成矩阵，所述第二生成矩阵包括T个子块，所述T个子块中相邻的两个子块之间的位置关系为根据所述预设位置关系确定的，所述T为正整数；根据所述第二生成矩阵对所述K个待编码比特进行极化编码，得到编码后的比特。
可选的，输入接口71可以具有图21实施例中的获取模块11的功能。逻辑电路72可以具有图21实施例中的确定模块11、生成模块13和编码模块14的功能。
可选的，逻辑电路72可以具有图25实施例中的处理器61的功能。逻辑电路72还可以执行编码方法中其它的步骤。
可选的，编码装置70还可以包括输出接口。例如，输出接口可以输出编码后的比特。
本申请实施例提供的编码装置70可以执行上述方法实施例所示的技术方案，其实现原理以及有益效果类似此处不再进行赘述。
图28为本申请实施例提供的另一种译码装置的结构示意图。请参见图28，该译码装置80可以包括输入接口81和逻辑电路82，其中，
所述输入接口81用于，接收极化编码后的比特信息；
所述逻辑电路82用于，根据第二生成矩阵对所述比特信息进行极化译码，得到极化译码后的比特；其中，所述第二生成矩阵为根据第一生成矩阵生成的，所述第一生成矩阵 中包括按照预设位置关系分布的至少两个子块，所述子块中包括多个第一生成矩阵核，所述第二生成矩阵包括T个子块，所述T个子块中相邻的两个子块之间的位置关系为根据所述预设位置关系确定的，所述T为正整数。
可选的，输入接口81可以具有图22实施例中的接收模块21的功能。逻辑电路82可以具有图22实施例中的译码模块22的功能。
可选的，输入接口81可以具有图26实施例中的接收器的功能。逻辑电路82可以具有图26实施例中的处理器61的功能。逻辑电路82还可以执行译码方法中其它的步骤。
可选的，译码装置80还可以包括输出接口。例如，输出接口可以输出译码结果。
本申请实施例提供的译码装置80可以执行上述方法实施例所示的技术方案，其实现原理以及有益效果类似此处不再进行赘述。
图29为本申请实施例提供的另一种编码装置的结构示意图。请参见图29，该编码装置90可以包括输入接口91和逻辑电路92，其中，
所述输入接口91用于，获取K个待编码比特，所述K为正整数；
所述逻辑电路92用于，确定第一生成矩阵，所述第一生成矩阵包括第一矩阵块和第二矩阵块，所述第一矩阵块位于所述第一生成矩阵的左上角，所述第二矩阵块位于所述第一生成矩阵的右下角，所述第一矩阵块和所述第二矩阵块相同，沿所述第一生成矩阵的对角线方向，所述第一矩阵块中的第一元素与所述第二矩阵块中的第二元素之间的距离为u，所述u为大于或等于1的整数；根据编码长度和所述第一生成矩阵，确定第二生成矩阵，所述第二生成矩阵中包括T个所述第一生成矩阵，所述T个第一生成矩阵沿所述第二生成矩阵的对角线分布，所述T个第一生成矩阵中的第a+1个第一生成矩阵的第一矩阵块与第a个第一生成矩阵的第二矩阵块重合，所述a为大于或等于1的整数，所述T为大于或等于2的整数；根据所述第二生成矩阵，对所述K个待编码比特进行极化编码，得到编码后的比特。
可选的，输入接口91可以具有图23实施例中的获取模块31的功能。逻辑电路92可以具有图23实施例中的确定模块32、生成模块33和编码模块34的功能。
可选的，逻辑电路92可以具有图25实施例中的处理器61的功能。逻辑电路92还可以执行编码方法中其它的步骤。
可选的，编码装置90还可以包括输出接口。例如，输出接口可以输出编码后的比特。
本申请实施例提供的编码装置90可以执行上述方法实施例所示的技术方案，其实现原理以及有益效果类似此处不再进行赘述。
图30为本申请实施例提供的另一种译码装置的结构示意图。请参见图30，该译码装置100可以包括输入接口101和逻辑电路102，其中，
所述输入接口101用于，接收极化编码后的比特信息；
所述逻辑电路102用于，根据第二生成矩阵对所述比特信息进行极化译码，得到极化译码后的比特，所述第二生成矩阵为根据第一生成矩阵生成的；其中，所述第一生成矩阵包括第一矩阵块和第二矩阵块，所述第一矩阵块位于所述第一生成矩阵的左上角，所述第二矩阵块位于所述第一生成矩阵的右下角，所述第一矩阵块和所述第二矩阵块相同，沿所述第一生成矩阵的对角线方向，所述第一矩阵块中的第一元素与所述第二矩阵块中的第二元素之间的距离为u，所述u为大于或等于1的整数；其中，所述第二生成矩阵中包括T 个所述第一生成矩阵，所述T个第一生成矩阵沿所述第二生成矩阵的对角线分布，所述T个第一生成矩阵中的第a+1个第一生成矩阵的第一矩阵块与第a个第一生成矩阵的第二矩阵块重合，所述a为大于或等于1的整数，所述T为大于或等于2的整数。
可选的，输入接口101可以具有图24实施例中的接收模块41的功能。逻辑电路102可以具有图24实施例中的译码模块42的功能。
可选的，输入接口101可以具有图26实施例中的接收器的功能。逻辑电路102可以具有图26实施例中的处理器61的功能。逻辑电路102还可以执行译码方法中其它的步骤。
可选的，译码装置100还可以包括输出接口。例如，输出接口可以输出译码结果。
本申请实施例提供的译码装置100可以执行上述方法实施例所示的技术方案，其实现原理以及有益效果类似此处不再进行赘述。
本申请实施例还提供一种存储介质，所述存储介质包括计算机程序，所述计算机程序用于实现如上所述的编码方法。
本申请实施例还提供一种存储介质，所述存储介质包括计算机程序，所述计算机程序用于实现如上所述的译码方法。
本申请实施例还提供一种芯片或者集成电路，包括：存储器和处理器；
所述存储器，用于存储程序指令，还可以用于存储中间数据；
所述处理器，用于调用所述存储器中存储的所述程序指令以实现如上所述的编码方法。
可选的，存储器可以是独立的，也可以跟处理器集成在一起。在有些实施方式中，存储器还可以位于所述芯片或者集成电路之外。
本申请实施例还提供一种芯片或者集成电路，包括：存储器和处理器；
所述存储器，用于存储程序指令，还可以用于存储中间数据；
所述处理器，用于调用所述存储器中存储的所述程序指令以实现如上所述的译码方法。
可选的，存储器可以是独立的，也可以跟处理器集成在一起。在有些实施方式中，存储器还可以位于所述芯片或者集成电路之外。
本申请实施例还提供一种程序产品，所述程序产品包括计算机程序，所述计算机程序存储在存储介质中，所述计算机程序用于实现上述的编码方法。
本申请实施例还提供一种程序产品，所述程序产品包括计算机程序，所述计算机程序存储在存储介质中，所述计算机程序用于实现上述的译码方法。
结合本发明实施例公开内容所描述的方法或者算法的步骤可以硬件的方式来实现，也可以是由处理器执行软件指令的方式来实现。软件指令可以由相应的软件模块组成，软件模块可以被存放于随机存取存储器(Random Access Memory，RAM)、闪存、只读存储器(Read Only Memory，ROM)、可擦除可编程只读存储器(Erasable Programmable ROM，EPROM)、电可擦可编程只读存储器(Electrically EPROM，EEPROM)、寄存器、硬盘、移动硬盘、只读光盘(CD-ROM)或者本领域熟知的任何其它形式的存储介质中。一种示例性的存储介质耦合至处理器，从而使处理器能够从该存储介质读取信息，且可向该存储介质写入信息。当然，存储介质也可以是处理器的组成部分。处理器和存储介质可以位于ASIC中。另外，该ASIC可以位于基站或终端中。当然，处理器和存储介质也可以作为分立组件存在于接收设备中。
应理解，上述处理器可以是中央处理单元(英文：Central Processing Unit，简称： CPU)，还可以是其他通用处理器、数字信号处理器(英文：Digital Signal Processor，简称：DSP)、专用集成电路(英文：Application Specific Integrated Circuit，简称：ASIC)等。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。结合发明所公开的方法的步骤可以直接体现为硬件处理器执行完成，或者用处理器中的硬件及软件模块组合执行完成。
存储器可能包含高速RAM存储器，也可能还包括非易失性存储NVM，例如至少一个磁盘存储器，还可以为U盘、移动硬盘、只读存储器、磁盘或光盘等。
总线可以是工业标准体系结构(Industry Standard Architecture，ISA)总线、外部设备互连(Peripheral Component，PCI)总线或扩展工业标准体系结构(Extended Industry Standard Architecture，EISA)总线等。总线可以分为地址总线、数据总线、控制总线等。为便于表示，本申请附图中的总线并不限定仅有一根总线或一种类型的总线。
上述存储介质可以是由任何类型的易失性或非易失性存储设备或者它们的组合实现，如静态随机存取存储器(SRAM)，电可擦除可编程只读存储器(EEPROM)，可擦除可编程只读存储器(EPROM)，可编程只读存储器(PROM)，只读存储器(ROM)，磁存储器，快闪存储器，磁盘或光盘。存储介质可以是通用或专用计算机能够存取的任何可用介质。
本申请中，“至少一个”是指一个或者多个，“多个”是指两个或两个以上。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A,B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。“以下至少一项(个)”或其类似表达，是指的这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a,b,或c中的至少一项(个)，可以表示：a,b,c,a-b,a-c,b-c,或a-b-c，其中a,b,c可以是单个，也可以是多个。
本领域技术人员应该可以意识到，在上述一个或多个示例中，本发明实施例所描述的功能可以用硬件、软件、固件或它们的任意组合来实现。当使用软件实现时，可以将这些功能存储在计算机可读介质中或者作为计算机可读介质上的一个或多个指令或代码进行传输。计算机可读介质包括计算机存储介质和通信介质，其中通信介质包括便于从一个地方向另一个地方传送计算机程序的任何介质。存储介质可以是通用或专用计算机能够存取的任何可用介质。
在本发明所提供的几个实施例中，应该理解到，所揭露的设备和方法，可以通过其它的方式实现。例如，以上所描述的设备实施例仅仅是示意性的，例如，所述模块的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个模块可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或模块的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的模块可以是或者也可以不是物理上分开的，作为模块显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部模块来实现本实施例方案的目的。
另外，在本发明各个实施例中的各功能模块可以集成在一个处理单元中，也可以是各个模块单独物理存在，也可以两个或两个以上模块集成在一个单元中。上述模块成的单元 既可以采用硬件的形式实现，也可以采用硬件加软件功能单元的形式实现。

Claims (56)

  1. 一种编码方法，其特征在于，包括：
    获取K个待编码比特，所述K为正整数；
    确定第一生成矩阵，所述第一生成矩阵中包括按照预设位置关系分布的至少两个子块，所述子块中包括多个第一生成矩阵核；
    根据所述第一生成矩阵，生成第二生成矩阵，所述第二生成矩阵包括T个子块，所述T个子块中相邻的两个子块之间的位置关系为根据所述预设位置关系确定的，所述T为正整数；
    根据所述第二生成矩阵对所述K个待编码比特进行极化编码，得到编码后的比特。
  2. 根据权利要求1所述的方法，其特征在于，所述T个子块中相邻的两个子块之间的位置关系与所述预设位置关系相同。
  3. 根据权利要求1或2所述的方法，其特征在于，所述至少两个子块中存在重合部分。
  4. 根据权利要求1-3任一项所述的方法，其特征在于，所述子块的第一对角线上包括所述第一生成矩阵核。
  5. 根据权利要求1-4任一项所述的方法，其特征在于，所述子块中的多个第一生成矩阵核以下三角形分布。
  6. 根据权利要求1-5任一项所述的方法，其特征在于，所述子块中的第一生成矩阵核的分布与第二生成矩阵核中第一元素的分布相同，所述第二生成矩阵核中的包括的元素数量与所述子块中包括的矩阵单元数量相同，所述子块中包括的矩阵单元为所述第一生成矩阵核或0矩阵。
  7. 根据权利要求6所述的方法，其特征在于，所述子块中包括的矩阵单元数量为2*2，所述子块中包括的矩阵单元为所述第一生成矩阵核或0矩阵。
  8. 根据权利要求7所述的方法，其特征在于，所述第一生成矩阵中包括第一子块和第二子块，所述第一子块中的第一矩阵单元与所述第二子块中的第二矩阵单元重合；
    其中，所述第一矩阵单元在所述第一子块中的坐标为(2,2)，所述第二矩阵单元在所述第二子块中的坐标为(1,1)。
  9. 根据权利要求6所述的方法，其特征在于，所述子块中包括的矩阵单元数量为4*4，所述子块中包括的矩阵单元为第一生成矩阵核或0矩阵。
  10. 根据权利要求9所述的方法，其特征在于，所述第一生成矩阵中包括第一子块和第二子块，所述第一子块中的4个第一矩阵单元与所述第二子块中的4个第二矩阵单元重合；其中，
    所述4个第一矩阵单元在所述第一子块中的坐标分别为：(3,3)、(3,4)、(4,3)、(4,4)；
    所述4个第二矩阵单元在所述第二子块中的坐标分别为：(1,1)、(1,2)、(2,1)、(2,2)。
  11. 一种译码方法，其特征在于，包括：
    接收极化编码后的比特信息；
    根据第二生成矩阵对所述比特信息进行极化译码，得到极化译码后的比特；
    其中，所述第二生成矩阵为根据第一生成矩阵生成的，所述第一生成矩阵中包括按照预设位置关系分布的至少两个子块，所述子块中包括多个第一生成矩阵核，所述第二生成矩阵包括T个子块，所述T个子块中相邻的两个子块之间的位置关系为根据所述预设位置关系确定的，所述T为正整数。
  12. 根据权利要求11所述的方法，其特征在于，所述T个子块中相邻的两个子块之间的位置关系与所述预设位置关系相同。
  13. 根据权利要求11或12所述的方法，其特征在于，所述比特信息包括N′个第一对数似然比LLR序列，所述N′为正整数。
  14. 根据权利要求13所述的方法，其特征在于，所述N′个第一LLR中包括T个第一LLR序列，所述第一LLR序列中包括至少两个第一LLR；所述极化译码包括：
    确定所述T个第一LLR序列对应的T个第二LLR序列，一个所述第一LLR序列对应一组或多组编码前的比特，一个所述第二LLR序列对应一组编码前的比特；
    根据所述T个第二LLR序列进行极化译码。
  15. 根据权利要求14所述的方法，其特征在于，确定所述T个第一LLR序列对应的T个第二LLR序列，包括：
    根据第i个第一LLR序列、以及前i-1个第二LLR序列中的至少一个第二LLR序列，确定第i个第二LLR序列，所述i为2至T之间的整数。
  16. 根据权利要求14或15所述的方法，其特征在于，根据所述T个第二LLR序列进行极化译码，包括：
    根据第T个第二LLR序列，确定得到第T个译码结果；
    根据第i+1个译码结果至第T个译码结果中的至少一个译码结果、以及第i个第二LLR序列，确定第i个译码结果，所述i为1至T-1之间的整数。
  17. 一种编码方法，其特征在于，包括：
    获取K个待编码比特，所述K为正整数；
    确定第一生成矩阵，所述第一生成矩阵包括第一矩阵块和第二矩阵块，所述第一矩阵块位于所述第一生成矩阵的左上角，所述第二矩阵块位于所述第一生成矩阵的右下角，所述第一矩阵块和所述第二矩阵块相同，沿所述第一生成矩阵的对角线方向，所述第一矩阵块中的第一元素与所述第二矩阵块中的第二元素之间的距离为u，所述u为大于或等于1的整数；
    根据编码长度和所述第一生成矩阵，确定第二生成矩阵，所述第二生成矩阵中包括T个所述第一生成矩阵，所述T个第一生成矩阵沿所述第二生成矩阵的对角线分布，所述T个第一生成矩阵中的第a+1个第一生成矩阵的第一矩阵块与第a个第一生成矩阵的第二矩阵块重合，所述a为大于或等于1的整数，所述T为大于或等于2的整数；
    根据所述第二生成矩阵，对所述K个待编码比特进行极化编码，得到编码后的比特。
  18. 根据权利要求17所述的方法，其特征在于，所述第一矩阵块和所述第二矩阵块中不存在重叠的元素。
  19. 根据权利要求17或18所述的方法，其特征在于，所述第一生成矩阵的尺寸为v*v，第一生成矩阵中的元素满足：a i,j＝a i+u,j+u，其中，
    所述i为整数，所述j为整数，所述v为正整数，所述u为整数，1≤i＜v，1≤j＜v， 1＜i+u≤v，1＜j+u≤v。
  20. 根据权利要求17-19任一项所述的方法，其特征在于，T为使得第一条件被满足的最小整数，所述第一条件为：所述第二生成矩阵的尺寸大于或等于所述编码长度。
  21. 一种译码方法，其特征在于，包括：
    接收极化编码后的比特信息；
    根据第二生成矩阵对所述比特信息进行极化译码，得到极化译码后的比特，所述第二生成矩阵为根据第一生成矩阵生成的；
    其中，所述第一生成矩阵包括第一矩阵块和第二矩阵块，所述第一矩阵块位于所述第一生成矩阵的左上角，所述第二矩阵块位于所述第一生成矩阵的右下角，所述第一矩阵块和所述第二矩阵块相同，沿所述第一生成矩阵的对角线方向，所述第一矩阵块中的第一元素与所述第二矩阵块中的第二元素之间的距离为u，所述u为大于或等于1的整数；
    其中，所述第二生成矩阵中包括T个所述第一生成矩阵，所述T个第一生成矩阵沿所述第二生成矩阵的对角线分布，所述T个第一生成矩阵中的第a+1个第一生成矩阵的第一矩阵块与第a个第一生成矩阵的第二矩阵块重合，所述a为大于或等于1的整数，所述T为大于或等于2的整数。
  22. 根据权利要求21所述的方法，其特征在于，所述第一生成矩阵的尺寸为v*v，第一生成矩阵中的元素满足：a i,j＝a i+u,j+u，其中，
    所述i为整数，所述j为整数，所述v为正整数，所述u为整数，1≤i＜v，1≤j＜v，1＜i+u≤v，1＜j+u≤v。
  23. 根据权利要求21或22所述的方法，其特征在于，T为使得第一条件被满足的最小整数，所述第一条件为：所述第二生成矩阵的尺寸大于或等于所述编码长度。
  24. 根据权利要求21-23任一项所述的方法，其特征在于，所述比特信息包括N′个第一对数似然比LLR序列，所述N′为正整数。
  25. 一种编码装置，其特征在于，包括输入接口和逻辑电路，其中，
    所述输入接口用于，获取K个待编码比特，所述K为正整数；
    所述逻辑电路用于，确定第一生成矩阵，所述第一生成矩阵中包括按照预设位置关系分布的至少两个子块，所述子块中包括多个第一生成矩阵核；根据所述第一生成矩阵，生成第二生成矩阵，所述第二生成矩阵包括T个子块，所述T个子块中相邻的两个子块之间的位置关系为根据所述预设位置关系确定的，所述T为正整数；根据所述第二生成矩阵对所述K个待编码比特进行极化编码，得到编码后的比特。
  26. 根据权利要求25所述的装置，其特征在于，所述逻辑电路还用于执行权利要求2-10任一项所述的编码方法。
  27. 一种编码装置，其特征在于，包括输入接口和逻辑电路，其中，
    所述输入接口用于，获取K个待编码比特，所述K为正整数；
    所述逻辑电路用于，确定第一生成矩阵，所述第一生成矩阵包括第一矩阵块和第二矩阵块，所述第一矩阵块位于所述第一生成矩阵的左上角，所述第二矩阵块位于所述第一生成矩阵的右下角，所述第一矩阵块和所述第二矩阵块相同，沿所述第一生成矩阵的对角线方向，所述第一矩阵块中的第一元素与所述第二矩阵块中的第二元素之间的距离为u，所述u为大于或等于1的整数；根据编码长度和所述第一生成矩阵，确定第二生成矩阵，所 述第二生成矩阵中包括T个所述第一生成矩阵，所述T个第一生成矩阵沿所述第二生成矩阵的对角线分布，所述T个第一生成矩阵中的第a+1个第一生成矩阵的第一矩阵块与第a个第一生成矩阵的第二矩阵块重合，所述a为大于或等于1的整数，所述T为大于或等于2的整数；根据所述第二生成矩阵，对所述K个待编码比特进行极化编码，得到编码后的比特。
  28. 根据权利要求27所述的装置，其特征在于，所述逻辑电路还用于执行权利要求18-20任一项所述的编码方法。
  29. 一种编码装置，其特征在于，包括：存储器、处理器以及计算机程序，所述计算机程序存储在所述存储器中，所述处理器运行所述计算机程序执行如权利要求1-10任一项所述的编码方法或者权利要求17-20任一项所述的编码方法。
  30. 一种计算机可读存储介质，其特征在于，所述存储介质包括计算机程序，所述计算机程序用于实现如权利要求1-10任一项所述的编码方法或者权利要求17-20任一项所述的编码方法。
  31. 一种计算机程序产品，当其在计算机上运行时，使得
    权利要求1-10任一项所述的编码方法被执行；或者
    权利要求17-20任一项所述的编码方法被执行。
  32. 一种计算机程序，当其在计算机上运行时，使得
    权利要求1-10任一项所述的编码方法被执行；或者
    权利要求17-20任一项所述的编码方法被执行。
  33. 一种编码装置，其特征在于，包括获取模块、确定模块、生成模块和编码模块，其中，
    所述获取模块用于，获取K个待编码比特，所述K为正整数；
    所述确定模块用于，确定第一生成矩阵，所述第一生成矩阵中包括按照预设位置关系分布的至少两个子块，所述子块中包括多个第一生成矩阵核；
    所述生成模块用于，根据所述第一生成矩阵，生成第二生成矩阵，所述第二生成矩阵包括T个子块，所述T个子块中相邻的两个子块之间的位置关系为根据所述预设位置关系确定的，所述T为正整数；
    所述编码模块用于，根据所述第二生成矩阵对所述K个待编码比特进行极化编码，得到编码后的比特。
  34. 根据权利要求33所述的装置，其特征在于，所述T个子块中相邻的两个子块之间的位置关系与所述预设位置关系相同。
  35. 根据权利要求33或34所述的装置，其特征在于，所述至少两个子块中存在重合部分。
  36. 根据权利要求33-35任一项所述的装置，其特征在于，所述子块的第一对角线上包括所述第一生成矩阵核。
  37. 根据权利要求33-36任一项所述的装置，其特征在于，所述子块中的多个第一生成矩阵核以下三角形分布。
  38. 根据权利要求33-37任一项所述的装置，其特征在于，所述子块中的第一生成矩阵核的分布与第二生成矩阵核中第一元素的分布相同，所述第二生成矩阵核中的包括的元 素数量与所述子块中包括的矩阵单元数量相同，所述子块中包括的矩阵单元为所述第一生成矩阵核或0矩阵。
  39. 根据权利要求38所述的装置，其特征在于，所述子块中包括的矩阵单元数量为2*2，所述子块中包括的矩阵单元为所述第一生成矩阵核或0矩阵。
  40. 根据权利要求39所述的装置，其特征在于，所述第一生成矩阵中包括第一子块和第二子块，所述第一子块中的第一矩阵单元与所述第二子块中的第二矩阵单元重合；
    其中，所述第一矩阵单元在所述第一子块中的坐标为(2,2)，所述第二矩阵单元在所述第二子块中的坐标为(1,1)。
  41. 根据权利要求38所述的装置，其特征在于，所述子块中包括的矩阵单元数量为4*4，所述子块中包括的矩阵单元为第一生成矩阵核或0矩阵。
  42. 根据权利要求41所述的装置，其特征在于，所述第一生成矩阵中包括第一子块和第二子块，所述第一子块中的4个第一矩阵单元与所述第二子块中的4个第二矩阵单元重合；其中，
    所述4个第一矩阵单元在所述第一子块中的坐标分别为：(3,3)、(3,4)、(4,3)、(4,4)；
    所述4个第二矩阵单元在所述第二子块中的坐标分别为：(1,1)、(1,2)、(2,1)、(2,2)。
  43. 一种译码装置，其特征在于，包括接收模块和译码模块，其中，
    所述接收模块用于，接收极化编码后的比特信息；
    所述译码模块用于，根据第二生成矩阵对所述比特信息进行极化译码，得到极化译码后的比特；
    其中，所述第二生成矩阵为根据第一生成矩阵生成的，所述第一生成矩阵中包括按照预设位置关系分布的至少两个子块，所述子块中包括多个第一生成矩阵核，所述第二生成矩阵包括T个子块，所述T个子块中相邻的两个子块之间的位置关系为根据所述预设位置关系确定的，所述T为正整数。
  44. 根据权利要求43所述的装置，其特征在于，所述T个子块中相邻的两个子块之间的位置关系与所述预设位置关系相同。
  45. 根据权利要求43或44所述的装置，其特征在于，所述比特信息包括N′个第一对数似然比LLR序列，所述N′为正整数。
  46. 根据权利要求45所述的装置，其特征在于，所述N′个第一LLR中包括T个第一LLR序列，所述第一LLR序列中包括至少两个第一LLR；所述译码模块具体用于：
    确定所述T个第一LLR序列对应的T个第二LLR序列，一个所述第一LLR序列对应一组或多组编码前的比特，一个所述第二LLR序列对应一组编码前的比特；
    根据所述T个第二LLR序列进行极化译码。
  47. 根据权利要求46所述的装置，其特征在于，所述译码模块具体用于：
    根据第i个第一LLR序列、以及前i-1个第二LLR序列中的至少一个第二LLR序列，确定第i个第二LLR序列，所述i为2至T之间的整数。
  48. 根据权利要求46或47所述的装置，其特征在于，所述译码模块具体用于：
    根据第T个第二LLR序列，确定得到第T个译码结果；
    根据第i+1个译码结果至第T个译码结果中的至少一个译码结果、以及第i个第二LLR序列，确定第i个译码结果，所述i为1至T-1之间的整数。
  49. 一种编码装置，其特征在于，包括获取模块、确定模块、生成模块和编码模块，其中，
    所述获取模块用于，获取K个待编码比特，所述K为正整数；
    所述确定模块用于，确定第一生成矩阵，所述第一生成矩阵包括第一矩阵块和第二矩阵块，所述第一矩阵块位于所述第一生成矩阵的左上角，所述第二矩阵块位于所述第一生成矩阵的右下角，所述第一矩阵块和所述第二矩阵块相同，沿所述第一生成矩阵的对角线方向，所述第一矩阵块中的第一元素与所述第二矩阵块中的第二元素之间的距离为u，所述u为大于或等于1的整数；
    所述生成模块用于，根据编码长度和所述第一生成矩阵，确定第二生成矩阵，所述第二生成矩阵中包括T个所述第一生成矩阵，所述T个第一生成矩阵沿所述第二生成矩阵的对角线分布，所述T个第一生成矩阵中的第a+1个第一生成矩阵的第一矩阵块与第a个第一生成矩阵的第二矩阵块重合，所述a为大于或等于1的整数，所述T为大于或等于2的整数；
    所述编码模块用于，根据所述第二生成矩阵，对所述K个待编码比特进行极化编码，得到编码后的比特。
  50. 根据权利要求49所述的装置，其特征在于，所述第一矩阵块和所述第二矩阵块中不存在重叠的元素。
  51. 根据权利要求49或50所述的装置，其特征在于，所述第一生成矩阵的尺寸为v*v，第一生成矩阵中的元素满足：a i,j＝a i+u,j+u，其中，
    所述i为整数，所述j为整数，所述v为正整数，所述u为整数，1≤i＜v，1≤j＜v，1＜i+u≤v，1＜j+u≤v。
  52. 根据权利要求49-51任一项所述的装置，其特征在于，T为使得第一条件被满足的最小整数，所述第一条件为：所述第二生成矩阵的尺寸大于或等于所述编码长度。
  53. 一种译码装置，其特征在于，包括接收模块和译码模块，其中，
    所述接收模块用于，接收极化编码后的比特信息；
    所述译码模块用于，根据第二生成矩阵对所述比特信息进行极化译码，得到极化译码后的比特，所述第二生成矩阵为根据第一生成矩阵生成的；
    其中，所述第一生成矩阵包括第一矩阵块和第二矩阵块，所述第一矩阵块位于所述第一生成矩阵的左上角，所述第二矩阵块位于所述第一生成矩阵的右下角，所述第一矩阵块和所述第二矩阵块相同，沿所述第一生成矩阵的对角线方向，所述第一矩阵块中的第一元素与所述第二矩阵块中的第二元素之间的距离为u，所述u为大于或等于1的整数；
    其中，所述第二生成矩阵中包括T个所述第一生成矩阵，所述T个第一生成矩阵沿所述第二生成矩阵的对角线分布，所述T个第一生成矩阵中的第a+1个第一生成矩阵的第一矩阵块与第a个第一生成矩阵的第二矩阵块重合，所述a为大于或等于1的整数，所述T为大于或等于2的整数。
  54. 根据权利要求53所述的装置，其特征在于，所述第一生成矩阵的尺寸为v*v，第一生成矩阵中的元素满足：a i,j＝a i+u,j+u，其中，
    所述i为整数，所述j为整数，所述v为正整数，所述u为整数，1≤i＜v，1≤j＜v，1＜i+u≤v，1＜j+u≤v。
  55. 根据权利要求53或54所述的装置，其特征在于，T为使得第一条件被满足的最小整数，所述第一条件为：所述第二生成矩阵的尺寸大于或等于所述编码长度。
  56. 根据权利要求53-55任一项所述的装置，其特征在于，所述比特信息包括N′个第一对数似然比LLR序列，所述N′为正整数。
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