WO2021213219A1 - Procédés et appareils de codage et de décodage et dispositif - Google Patents

Procédés et appareils de codage et de décodage et dispositif Download PDF

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WO2021213219A1
WO2021213219A1 PCT/CN2021/086960 CN2021086960W WO2021213219A1 WO 2021213219 A1 WO2021213219 A1 WO 2021213219A1 CN 2021086960 W CN2021086960 W CN 2021086960W WO 2021213219 A1 WO2021213219 A1 WO 2021213219A1
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matrix
block
sub
generator
generator matrix
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PCT/CN2021/086960
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Chinese (zh)
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张华滋
童佳杰
王献斌
戴胜辰
李榕
王俊
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华为技术有限公司
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Priority to EP21791667.5A priority Critical patent/EP4131785A4/fr
Priority to JP2022564458A priority patent/JP2023523254A/ja
Publication of WO2021213219A1 publication Critical patent/WO2021213219A1/fr
Priority to US17/969,736 priority patent/US20230058149A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/118—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/033—Theoretical methods to calculate these checking codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H03M13/1111—Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms
    • H03M13/1125—Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms using different domains for check node and bit node processing, wherein the different domains include probabilities, likelihood ratios, likelihood differences, log-likelihood ratios or log-likelihood difference pairs
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H03M13/1131—Scheduling of bit node or check node processing
    • H03M13/1137—Partly parallel processing, i.e. sub-blocks or sub-groups of nodes being processed in parallel
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit

Definitions

  • This application relates to the field of communication technology, and in particular to an encoding and decoding method, device and equipment.
  • communication equipment such as terminal equipment, base stations, etc.
  • the complexity of the codec is usually related to the code length.
  • the code length is very long (for example, the code length is greater than 16384), the complexity of encoding and decoding through polarized codes is high, resulting in poor encoding and decoding performance.
  • the embodiments of the present application provide an encoding and decoding method, device, and equipment, which reduce the complexity of encoding and decoding.
  • an embodiment of the present application provides an encoding method.
  • the method includes: obtaining K bits to be encoded, where K is a positive integer; and determining a first generator matrix, the first generator matrix including at least Two sub-blocks, the sub-blocks include multiple first generator matrix cores; according to the first generator matrix, the second generator matrix is generated, and the second generator matrix includes T sub-blocks.
  • the positional relationship is determined according to the preset positional relationship, and T is a positive integer; the K bits to be encoded are polarized encoding according to the second generating matrix to obtain the encoded bits.
  • the first generator matrix is determined first, and then the second generator matrix is generated according to the first generator matrix, and the K bits to be coded are maximized according to the second generator matrix. ⁇ coding. Since the first generator matrix includes at least two sub-blocks distributed according to a preset positional relationship, each sub-block includes a plurality of first generator matrix cores, the second generator matrix includes T sub-blocks, and adjacent ones of the T sub-blocks The positional relationship between the two sub-blocks is determined according to the preset positional relationship.
  • the second generating matrix includes a plurality of sub-blocks arranged according to the above-mentioned preset positional relationship, and each sub-block includes Multiple first generator matrix cores. Therefore, when the K bits to be encoded are polarized encoding according to the second generator matrix, it is equivalent to polar encoding multiple short codes first, and then coupling multiple short codes to obtain the encoding result, thereby reducing the encoding complexity .
  • the positional relationship between two adjacent sub-blocks among the T sub-blocks is the same as the preset positional relationship.
  • the positional relationship between the two adjacent sub-blocks in the T sub-blocks is the same as the preset positional relationship, so that the coupling mode between the short codes is the same, making the coding complexity relatively high. Low.
  • the first diagonal of the sub-block includes the first generator matrix core.
  • the multiple first generator matrix cores in the sub-block are distributed in a triangle below.
  • the distribution of the first generator matrix core in the sub-block is the same as the distribution of the first element in the second generator matrix core, and the number of elements included in the second generator matrix core is the same as that in the sub-block.
  • the number of matrix units is the same, and the matrix units included in the sub-block are the first generator matrix core or the 0 matrix.
  • the coupling method of the short code is similar to the existing coding method, which makes the coding complexity Lower.
  • the first generator matrix includes two sub-blocks.
  • the second generator matrix includes fewer sub-blocks, which makes the process of constructing the second generator matrix easier.
  • the number of matrix units included in the sub-block is 2*2, and the matrix units included in the sub-block are the first generator matrix core or the 0 matrix.
  • the first generator matrix includes a first sub-block and a second sub-block, and the first matrix unit in the first sub-block coincides with the second matrix unit in the second sub-block; wherein, The coordinates of the first matrix unit in the first sub-block are (2, 2), and the coordinates of the second matrix unit in the second sub-block are (1, 1).
  • the second generator matrix is symmetric, so that the coding complexity is low, and the decoding complexity is also low.
  • the number of matrix units included in the sub-block is 4*4, and the matrix units included in the sub-block are the first generator matrix core or the 0 matrix.
  • the first generator matrix includes a first sub-block and a second sub-block, four first matrix units in the first sub-block and four second matrix units in the second sub-block Coincidence; among them, the coordinates of the 4 first matrix units in the first sub-block are: (3,3), (3,4), (4,3), (4,4); 4 second matrices The coordinates of the unit in the second sub-block are: (1,1), (1,2), (2,1), (2,2).
  • the second generator matrix is symmetric, so that the coding complexity is low, and the decoding complexity is also low.
  • the K bits to be encoded are information bits; the K bits to be encoded are polarized encoding according to the second generating matrix to obtain the encoded bits, including: Determine the K subchannels with the highest reliability among multiple subchannels; determine the positions of K bits to be coded according to the K subchannels with the highest reliability; determine the sequence to be coded according to the positions of the K bits to be coded, and the sequence to be coded includes K Bits to be coded and frozen bits; according to the second generating matrix, polarization coding is performed on the sequence to be coded to obtain the coded bits.
  • the sub-channel with the highest reliability is selected to transmit the information bits, so that the coding performance is higher.
  • the multiple sub-channels include P groups of sub-channels, and P is a positive integer; determining the K sub-channels with the highest reliability among the multiple sub-channels corresponding to the K bits to be coded includes: set of subchannels reliability determined in the i-th set of subchannels in the first subchannel X i, X i is the i th first group of subchannels in the subchannel highest reliability subchannel X i, i is an integer, 1 ⁇ i ⁇ P, X i is a positive integer, The K sub-channels with the highest reliability include the first sub-channel.
  • an embodiment of the present application provides a decoding method, including: receiving polarization-encoded bit information; performing polarization decoding on the bit information according to a second generating matrix to obtain polarization-decoded bits; wherein , The second generator matrix is generated according to the first generator matrix, the first generator matrix includes at least two sub-blocks distributed according to a preset position relationship, the sub-block includes a plurality of first generator matrix cores, and the second generator matrix includes T Sub-blocks, the positional relationship between two adjacent sub-blocks in the T sub-blocks is determined according to the preset positional relationship, and T is a positive integer.
  • each sub-block includes multiple first generator matrix cores
  • the second generator matrix includes T sub-blocks
  • the positional relationship between two adjacent sub-blocks in the T sub-blocks is determined according to the preset positional relationship. Therefore, it can be concluded that the second generating matrix includes a plurality of sub-blocks arranged according to the above-mentioned preset positional relationship.
  • each sub-block includes multiple first generator matrix cores. Therefore, the polarization decoding of the bit information according to the second generator matrix is equivalent to decoupling multiple short codes first, and decoding the short codes after the decoupling.
  • the complexity of decoding the short codes is relatively low. Therefore, the complexity of the above-mentioned decoding is lower.
  • the positional relationship between two adjacent sub-blocks among the T sub-blocks is the same as the preset positional relationship.
  • the positional relationship between two adjacent sub-blocks in the T sub-blocks is the same as the preset positional relationship, so that the coupling mode between the short codes is the same, which makes the decoding complexity Lower.
  • the first diagonal of the sub-block includes the first generator matrix core.
  • the multiple first generator matrix cores in the sub-block are distributed in a triangle below.
  • the distribution of the first generator matrix core in the sub-block is the same as the distribution of the first element in the second generator matrix core, and the number of elements included in the second generator matrix core is the same as that in the sub-block.
  • the number of matrix units is the same, and the matrix units included in the sub-block are the first generator matrix core or the 0 matrix.
  • the coupling method of the short code is similar to the existing decoding method, making the decoding The complexity is low.
  • the first generator matrix includes two sub-blocks.
  • the second generator matrix includes fewer sub-blocks, which makes the process of constructing the second generator matrix easier.
  • the number of matrix units included in the sub-block is 2*2, and the matrix units included in the sub-block are the first generator matrix core or the 0 matrix.
  • the first generator matrix includes a first sub-block and a second sub-block, and the first matrix unit in the first sub-block coincides with the second matrix unit in the second sub-block; wherein, The coordinates of the first matrix unit in the first sub-block are (2, 2), and the coordinates of the second matrix unit in the second sub-block are (1, 1).
  • the second generator matrix is symmetric, so that the complexity of decoding is lower.
  • the number of matrix units included in the sub-block is 4*4, and the matrix units included in the sub-block are the first generator matrix core or the 0 matrix.
  • the first generator matrix includes a first sub-block and a second sub-block, four first matrix units in the first sub-block and four second matrix units in the second sub-block Coincidence; among them, the coordinates of the 4 first matrix units in the first sub-block are: (3,3), (3,4), (4,3), (4,4); 4 second matrices The coordinates of the unit in the second sub-block are: (1,1), (1,2), (2,1), (2,2).
  • the second generator matrix is symmetric, so that the complexity of decoding is lower.
  • the bit information includes N′ first log-likelihood ratio LLR sequences, and N′ is a positive integer.
  • the N′ first LLRs include T first LLR sequences, and the first LLR sequences include at least two first LLRs; polarization decoding includes: determining T first LLR sequences Corresponding to T second LLR sequences, a first LLR sequence corresponds to one or more groups of bits before encoding, and a second LLR sequence corresponds to a group of bits before encoding; polarization decoding is performed according to T second LLR sequences .
  • determining the T second LLR sequences corresponding to the T first LLR sequences includes: according to at least one of the i-th first LLR sequence and the first i-1 second LLR sequence The second LLR sequence determines the i-th second LLR sequence, where i is an integer between 2 and T.
  • the pairing is then realized.
  • the first LLR sequence is decoupled to obtain the i-th second LLR sequence.
  • the coupling degree of the code block is 2; according to the i-th first LLR sequence and at least one second LLR sequence among the first i-1 second LLR sequences, the i-th LLR sequence is determined
  • the second LLR sequence includes: determining the i-th second LLR sequence according to the i-th first LLR sequence and the i-1th second LLR sequence.
  • the first second LLR sequence is the same as the first first LLR sequence.
  • the coupling degree of the code block is 4; according to the i-th first LLR sequence and at least one second LLR sequence of the first i-1 second LLR sequences, the i-th LLR sequence is determined
  • the second LLR sequence includes: determining the i-th second LLR sequence according to the i-th first LLR sequence and the i-2th second LLR sequence, where i is an integer between 3 and T.
  • the first second LLR sequence is the same as the first first LLR sequence; the second second LLR sequence is the same as the second first LLR sequence.
  • polarization decoding can be performed according to the T second LLR sequence in the following manner: according to the T second LLR sequence, it is determined to obtain the Tth decoding result; according to the i+1th LLR sequence; At least one decoding result from the decoding result to the T-th decoding result and the i-th second LLR sequence determine the i-th decoding result, where i is an integer between 1 and T-1.
  • the decoding result can be obtained, so that the decoding complexity is low.
  • the coupling degree of the code block is 2, according to at least one decoding result from the (i+1)th decoding result to the T-th decoding result, and the i-th second LLR sequence
  • Determining the i-th decoding result includes: determining the i-th decoding result according to the i+1-th decoding result, the i+1-th first LLR sequence, and the i-th second LLR sequence.
  • an embodiment of the present application provides an encoding method.
  • the method includes: obtaining K bits to be encoded, where K is a positive integer; determining a first generator matrix, the first generator matrix including a first matrix block and a second matrix block , The first matrix block is located at the upper left corner of the first generator matrix, the second matrix block is located at the lower right corner of the first generator matrix, the first matrix block and the second matrix block are the same, along the diagonal direction of the first generator matrix, the first The distance between the first element in one matrix block and the second element in the second matrix block is u, where u is an integer greater than or equal to 1, and the second generator matrix is determined according to the coding length and the first generator matrix.
  • the second generator matrix includes T first generator matrices, the T first generator matrices are distributed along the diagonal of the second generator matrix, and the first matrix of the a+1 first generator matrix among the T first generator matrices
  • the block coincides with the second matrix block of the a-th first generator matrix, a is an integer greater than or equal to 1, and T is an integer greater than or equal to 2; according to the second generator matrix, K bits to be encoded are polarized encoding , Get the encoded bits.
  • the first generator matrix is determined first, and then the second generator matrix is generated according to the first generator matrix, and the K bits to be coded are maximized according to the second generator matrix. ⁇ coding. Since the first generator matrix has self-similarity, the second generator matrix includes multiple first matrix blocks. Therefore, when the K bits to be encoded are polarized encoding according to the second generator matrix, it is equivalent to performing multiple short codes first. Perform polarization coding, and then couple multiple short codes to obtain coding results, thereby reducing coding complexity.
  • the size of the first generator matrix is v*v
  • encoding it is equivalent to first performing polarization encoding on multiple short codes, and then coupling multiple short codes to obtain an encoding result, thereby reducing encoding complexity.
  • the elements in the first generator matrix are symmetrical along the subdiagonal line of the first generator matrix.
  • T is the smallest integer that enables the first condition to be satisfied, and the first condition is: the size of the second generator matrix is greater than or equal to the code length.
  • T satisfies the following relationship: v+(T-1)*u ⁇ N′ ⁇ v+T*u; where v is the size of the first generator matrix, N′ is the coding length, and N 'Is an integer greater than 1.
  • the size of the second generator matrix can be avoided to be too large or too small, so that the coding complexity is low.
  • an embodiment of the present application provides a decoding method, which may include: receiving polarization-encoded bit information; performing polarization decoding on the bit information according to a second generating matrix to obtain polarization-decoded bit information Bit, the second generator matrix is generated according to the first generator matrix; wherein, the first generator matrix includes a first matrix block and a second matrix block, the first matrix block is located at the upper left corner of the first generator matrix, and the second matrix block is located In the lower right corner of the first generator matrix, the first matrix block and the second matrix block are the same.
  • the second generator matrix includes T first generator matrices, and the T first generator matrices are distributed along the diagonal of the second generator matrix.
  • the first matrix block of the a+1 first generator matrix in a generator matrix coincides with the second matrix block of the a-th first generator matrix, a is an integer greater than or equal to 1, and T is greater than or equal to 2. Integer.
  • the second generator matrix since the first generator matrix has self-similarity, the second generator matrix includes a plurality of first matrix blocks, therefore. Therefore, the polarization decoding of the bit information according to the second generator matrix is equivalent to decoupling multiple short codes first, and decoding the short codes after the decoupling.
  • the complexity of decoding the short codes is relatively low. Therefore, the complexity of the above-mentioned decoding is lower.
  • the size of the first generator matrix is v*v
  • decoding decoding it is equivalent to performing polarization decoding on multiple short codes first, and then coupling multiple short codes to obtain the decoding result, thereby reducing the decoding complexity.
  • the elements in the first generator matrix are symmetrical along the subdiagonal line of the first generator matrix.
  • the decoding complexity is relatively low.
  • T is the smallest integer that enables the first condition to be satisfied, and the first condition is: the size of the second generator matrix is greater than or equal to the decoding length.
  • T satisfies the following relationship: v+(T-1)*u ⁇ N′ ⁇ v+T*u; where v is the size of the first generator matrix, and N′ is the decoding length, N'is an integer greater than 1.
  • the size of the second generator matrix can be prevented from being too large or too small, so that the decoding complexity is low.
  • the bit information includes N′ first log-likelihood ratio LLR sequences, and N′ is a positive integer.
  • the N′ first LLRs include T first LLR sequences, and the first LLR sequences include at least two first LLRs; polarization decoding includes: determining T first LLR sequences Corresponding to T second LLR sequences, a first LLR sequence corresponds to one or more groups of bits before encoding, and a second LLR sequence corresponds to a group of bits before encoding; polarization decoding is performed according to T second LLR sequences .
  • determining the T second LLR sequences corresponding to the T first LLR sequences includes: according to at least one of the i-th first LLR sequence and the first i-1 second LLR sequence The second LLR sequence determines the i-th second LLR sequence, where i is an integer between 2 and T.
  • the pairing is then realized.
  • the first LLR sequence is decoupled to obtain the i-th second LLR sequence.
  • the coupling degree of the code block is 2; according to the i-th first LLR sequence and at least one second LLR sequence among the first i-1 second LLR sequences, the i-th LLR sequence is determined
  • the second LLR sequence includes: determining the i-th second LLR sequence according to the i-th first LLR sequence and the i-1th second LLR sequence.
  • the first second LLR sequence is the same as the first first LLR sequence.
  • the coupling degree of the code block is 4; according to the i-th first LLR sequence and at least one second LLR sequence of the first i-1 second LLR sequences, the i-th LLR sequence is determined
  • the second LLR sequence includes: determining the i-th second LLR sequence according to the i-th first LLR sequence and the i-2th second LLR sequence, where i is an integer between 3 and T.
  • the first second LLR sequence is the same as the first first LLR sequence; the second second LLR sequence is the same as the second first LLR sequence.
  • polarization decoding can be performed according to the T second LLR sequence in the following manner: according to the T second LLR sequence, it is determined to obtain the Tth decoding result; according to the i+1th LLR sequence; At least one decoding result from the decoding result to the T-th decoding result and the i-th second LLR sequence determine the i-th decoding result, where i is an integer between 1 and T-1.
  • the decoding result can be obtained, so that the decoding complexity is low.
  • the coupling degree of the code block is 2, according to at least one decoding result from the (i+1)th decoding result to the T-th decoding result, and the i-th second LLR sequence
  • Determining the i-th decoding result includes: determining the i-th decoding result according to the i+1-th decoding result, the i+1-th first LLR sequence, and the i-th second LLR sequence.
  • an embodiment of the present application provides an encoding device, including an acquisition module, a determination module, a generation module, and an encoding module, where:
  • the obtaining module is configured to obtain K bits to be coded, where K is a positive integer
  • the determining module is configured to determine a first generator matrix, where the first generator matrix includes at least two sub-blocks distributed according to a preset position relationship, and the sub-block includes a plurality of first generator matrix cores;
  • the generating module is configured to generate a second generating matrix according to the first generating matrix, the second generating matrix including T sub-blocks, and the positional relationship between two adjacent sub-blocks in the T sub-blocks is Determined according to the preset positional relationship, the T is a positive integer;
  • the encoding module is configured to perform polarization encoding on the K to-be-encoded bits according to the second generating matrix to obtain encoded bits.
  • the positional relationship between two adjacent sub-blocks in the T sub-blocks is the same as the preset positional relationship.
  • the first diagonal of the sub-block includes the first generator matrix core.
  • the multiple first generator matrix cores in the sub-block are distributed in a triangle below.
  • the distribution of the first generator matrix core in the sub-block is the same as the distribution of the first element in the second generator matrix core, and the number of elements included in the second generator matrix core is equal to The number of matrix units included in the sub-blocks is the same, and the matrix units included in the sub-blocks are the first generator matrix core or the 0 matrix.
  • the first generator matrix includes two sub-blocks.
  • the number of matrix units included in the sub-block is 2*2, and the matrix units included in the sub-block are the first generator matrix core or the 0 matrix.
  • the first generator matrix includes a first sub-block and a second sub-block, and the first matrix unit in the first sub-block and the second sub-block in the second sub-block are The matrix units coincide;
  • the coordinates of the first matrix unit in the first sub-block are (2, 2), and the coordinates of the second matrix unit in the second sub-block are (1, 1).
  • the number of matrix units included in the sub-block is 4*4, and the matrix units included in the sub-block are the first generator matrix core or the 0 matrix.
  • the first generator matrix includes a first sub-block and a second sub-block, and the four first matrix units in the first sub-block and the second sub-block in the The 4 second matrix units overlap; among them,
  • the coordinates of the four first matrix units in the first sub-block are: (3,3), (3,4), (4,3), (4,4);
  • the coordinates of the four second matrix units in the second sub-block are respectively: (1,1), (1,2), (2,1), (2,2).
  • the K bits to be encoded are information bits; the encoding module is specifically configured to:
  • the multiple sub-channels include P groups of sub-channels, and the P is a positive integer;
  • the encoding module is specifically configured to:
  • the reliability of the sub-group i, determining X i in the i-th first sub-set of subchannels in the first subchannel X i is the i-th set of subchannels highest reliability X i subchannels ,
  • the i is an integer, 1 ⁇ i ⁇ P, the X i is a positive integer,
  • the K subchannels with the highest reliability include the first subchannel.
  • an embodiment of the present application provides a decoding device, including a receiving module and a decoding module, where:
  • the receiving module is configured to receive polarization-encoded bit information
  • the decoding module is configured to perform polarization decoding on the bit information according to a second generating matrix to obtain polarization decoded bits
  • the second generator matrix is generated according to the first generator matrix
  • the first generator matrix includes at least two sub-blocks distributed according to a preset position relationship
  • the sub-block includes a plurality of first generator matrix cores
  • the second generating matrix includes T sub-blocks, the positional relationship between two adjacent sub-blocks in the T sub-blocks is determined according to the preset positional relationship, and the T is a positive integer.
  • the positional relationship between two adjacent sub-blocks in the T sub-blocks is the same as the preset positional relationship.
  • the first diagonal of the sub-block includes the first generator matrix core.
  • the multiple first generator matrix cores in the sub-block are distributed in a triangle below.
  • the distribution of the first generator matrix core in the sub-block is the same as the distribution of the first element in the second generator matrix core, and the number of elements included in the second generator matrix core is equal to The number of elements included in the sub-blocks is the same, and the elements included in the sub-blocks are the first generator matrix core or the 0 matrix.
  • the first generator matrix includes two sub-blocks.
  • the number of elements included in the sub-block is 2*2, and the elements included in the sub-block are the first generator matrix core or the 0 matrix.
  • the first generator matrix includes a first sub-block and a second sub-block, and the first element in the first sub-block and the second element in the second sub-block are coincide;
  • the coordinates of the first element in the first sub-block are (2, 2), and the coordinates of the second element in the second sub-block are (1, 1).
  • the number of elements included in the sub-block is 4*4, and the elements included in the sub-block are the first generator matrix core or the 0 matrix.
  • the first generating matrix includes a first sub-block and a second sub-block, and the four first elements in the first sub-block and the four in the second sub-block are Two second elements coincide; among them,
  • the coordinates of the four first elements in the first sub-block are: (3,3), (3,4), (4,3), (4,4);
  • the coordinates of the four second elements in the second sub-block are respectively: (1,1), (1,2), (2,1), (2,2).
  • the bit information includes N′ first log-likelihood ratio LLR sequences, and the N′ is a positive integer.
  • the N′ first LLRs include T first LLR sequences, and the first LLR sequences include at least two first LLRs; the decoding module is specifically configured to:
  • T second LLR sequences corresponding to the T first LLR sequences one of the first LLR sequences corresponds to one or more sets of bits before encoding, and one of the second LLR sequences corresponds to a set of bits before encoding ;
  • the decoding module is specifically configured to:
  • the coupling degree of the code block is 2; the decoding module is specifically configured to:
  • the i-th second LLR sequence is determined according to the i-th first LLR sequence and the i-1th second LLR sequence.
  • the first second LLR sequence is the same as the first first LLR sequence.
  • the coupling degree of the code block is 4; the decoding module is specifically configured to:
  • the i-th second LLR sequence is determined according to the i-th first LLR sequence and the i-2th second LLR sequence, and the i is an integer between 3 and T.
  • the first second LLR sequence is the same as the first first LLR sequence
  • the second second LLR sequence is the same as the second first LLR sequence.
  • the decoding module is specifically configured to:
  • the coupling degree of the code block is 2; the decoding module is specifically configured to:
  • the i-th decoding result is determined according to the i+1-th decoding result, the i+1-th first LLR sequence, and the i-th second LLR sequence.
  • an embodiment of the present application provides an encoding device, including an acquisition module, a determination module, a generation module, and an encoding module, where:
  • the obtaining module is configured to obtain K bits to be coded, where K is a positive integer
  • the determining module is configured to determine a first generator matrix.
  • the first generator matrix includes a first matrix block and a second matrix block.
  • the first matrix block is located at the upper left corner of the first generator matrix.
  • the two matrix blocks are located at the lower right corner of the first generator matrix.
  • the first matrix block and the second matrix block are the same.
  • the distance between the first element and the second element in the second matrix block is u, and the u is an integer greater than or equal to 1;
  • the generating module is configured to generate a second generator matrix according to the coding length and the first generator matrix.
  • the second generator matrix includes T first generator matrices, and the T first generator matrices are The diagonal distribution of the second generator matrix, the first matrix block of the a+1-th first generator matrix in the T first generator matrices coincides with the second matrix block of the a-th first generator matrix ,
  • the a is an integer greater than or equal to 1
  • the T is an integer greater than or equal to 2;
  • the encoding module is configured to perform polarization encoding on the K to-be-encoded bits according to the second generating matrix to obtain encoded bits.
  • the i is an integer
  • the j is an integer
  • the v is a positive integer
  • the u is an integer, 1 ⁇ i ⁇ v, 1 ⁇ j ⁇ v, 1 ⁇ i+u ⁇ v, 1 ⁇ j+u ⁇ v.
  • the elements in the first generator matrix are symmetrical along a subdiagonal line of the first generator matrix.
  • T is the smallest integer that enables the first condition to be satisfied, and the first condition is: the size of the second generator matrix is greater than or equal to the code length.
  • the T satisfies the following relationship:
  • the v is the size of the first generator matrix
  • the N′ is the coding length
  • the N′ is an integer greater than 1.
  • an embodiment of the present application provides a decoding device, including a receiving module and a decoding module, where:
  • the receiving module is configured to receive polarization-encoded bit information
  • the decoding module is configured to perform polarization decoding on the bit information according to a second generating matrix to obtain polarized decoded bits, and the second generating matrix is generated according to the first generating matrix;
  • the first generator matrix includes a first matrix block and a second matrix block, the first matrix block is located at the upper left corner of the first generator matrix, and the second matrix block is located at the upper left corner of the first generator matrix.
  • the first matrix block and the second matrix block are the same, and along the diagonal direction of the first generator matrix, the first element in the first matrix block is the same as that in the second matrix block.
  • the distance between the second elements of is u, and the u is an integer greater than or equal to 1;
  • the second generator matrix includes T first generator matrices, the T first generator matrices are distributed along the diagonal of the second generator matrix, and the T first generator matrices are The first matrix block of the a+1th first generator matrix coincides with the second matrix block of the ath first generator matrix, where a is an integer greater than or equal to 1, and the T is an integer greater than or equal to 2 .
  • the i is an integer
  • the j is an integer
  • the v is a positive integer
  • the u is an integer, 1 ⁇ i ⁇ v, 1 ⁇ j ⁇ v, 1 ⁇ i+u ⁇ v, 1 ⁇ j+u ⁇ v.
  • the elements in the first generator matrix are symmetrical along a subdiagonal line of the first generator matrix.
  • T is the smallest integer that enables the first condition to be satisfied, and the first condition is: the size of the second generator matrix is greater than or equal to the code length.
  • the T satisfies the following relationship:
  • the v is the size of the first generator matrix
  • the N′ is the coding length
  • the N′ is an integer greater than 1.
  • the bit information includes N′ first log-likelihood ratio LLR sequences, and the N′ is a positive integer.
  • the N′ first LLRs include T first LLR sequences, and the first LLR sequences include at least two first LLRs; the decoding module is specifically configured to:
  • T second LLR sequences corresponding to the T first LLR sequences one of the first LLR sequences corresponds to one or more sets of bits before encoding, and one of the second LLR sequences corresponds to a set of bits before encoding ;
  • the decoding module is specifically configured to:
  • the coupling degree of the code block is 2; the decoding module is specifically configured to:
  • the i-th second LLR sequence is determined according to the i-th first LLR sequence and the i-1th second LLR sequence.
  • the first second LLR sequence is the same as the first first LLR sequence.
  • the coupling degree of the code block is 4; the decoding module is specifically configured to:
  • the i-th second LLR sequence is determined according to the i-th first LLR sequence and the i-2th second LLR sequence, and the i is an integer between 3 and T.
  • the first second LLR sequence is the same as the first first LLR sequence
  • the second second LLR sequence is the same as the second first LLR sequence.
  • the decoding module is specifically configured to:
  • the coupling degree of the code block is 2; the decoding module is specifically configured to:
  • the i-th decoding result is determined according to the i+1-th decoding result, the i+1-th first LLR sequence, and the i-th second LLR sequence.
  • an embodiment of the present application provides an encoding device, including: a memory, a processor, and a computer program.
  • the computer program is stored in the memory, and the processor runs the computer program to execute any of the computer programs as in the first aspect.
  • an embodiment of the present application provides an encoding device, including: a memory, a processor, and a computer program.
  • the computer program is stored in the memory, and the processor runs the computer program to execute any of the operations as in the second aspect.
  • an embodiment of the present application provides an encoding device, including: a memory, a processor, and a computer program.
  • the computer program is stored in the memory, and the processor runs the computer program to execute the computer program as in the third aspect. Any one of the encoding methods.
  • an embodiment of the present application provides an encoding device, including: a memory, a processor, and a computer program, the computer program is stored in the memory, and the processor runs the computer program to execute as in the fourth aspect Any one of the decoding methods.
  • an embodiment of the present application provides a storage medium, where the storage medium includes a computer program, and the computer program is used to implement the encoding method according to any one of the first aspect.
  • an embodiment of the present application provides a storage medium, where the storage medium includes a computer program, and the computer program is used to implement the decoding method according to any one of the second aspects.
  • an embodiment of the present application provides a storage medium, the storage medium includes a computer program, and the computer program is used to implement the encoding method according to any one of the third aspect.
  • an embodiment of the present application provides a storage medium, where the storage medium includes a computer program, and the computer program is used to implement the decoding method according to any one of the fourth aspect.
  • an embodiment of the present application provides an encoding device, which may include an input interface and a logic circuit, where:
  • the input interface is used to obtain K bits to be encoded, where K is a positive integer;
  • the logic circuit is configured to determine a first generator matrix, the first generator matrix includes at least two sub-blocks distributed according to a preset positional relationship, and the sub-block includes a plurality of first generator matrix cores;
  • a first generator matrix generates a second generator matrix, the second generator matrix includes T sub-blocks, and the positional relationship between two adjacent sub-blocks in the T sub-blocks is determined according to the preset positional relationship,
  • the T is a positive integer;
  • the K bits to be encoded are polarized encoding according to the second generating matrix to obtain encoded bits.
  • the logic circuit may also execute the encoding method described in any one of the first aspect.
  • an embodiment of the present application provides a decoding device.
  • the decoding device may include an input interface and a logic circuit, where:
  • the input interface is used to receive polarization-encoded bit information
  • the logic circuit is configured to perform polarization decoding on the bit information according to a second generating matrix to obtain polarization decoded bits; wherein, the second generating matrix is generated according to the first generating matrix, so
  • the first generator matrix includes at least two sub-blocks distributed according to a preset position relationship, the sub-block includes a plurality of first generator matrix cores, the second generator matrix includes T sub-blocks, and in the T sub-blocks The positional relationship between two adjacent sub-blocks is determined according to the preset positional relationship, and the T is a positive integer.
  • the logic circuit may also execute the decoding method described in any one of the second aspect.
  • an embodiment of the present application provides a schematic structural diagram of an encoding device.
  • the encoding device may include an input interface and a logic circuit, where:
  • the input interface is used to obtain K bits to be encoded, where K is a positive integer;
  • the logic circuit is configured to determine a first generator matrix.
  • the first generator matrix includes a first matrix block and a second matrix block.
  • the first matrix block is located at the upper left corner of the first generator matrix.
  • the two matrix blocks are located at the lower right corner of the first generator matrix.
  • the first matrix block and the second matrix block are the same.
  • the distance between the first element and the second element in the second matrix block is u, where u is an integer greater than or equal to 1, and the second generator matrix is determined according to the coding length and the first generator matrix
  • the second generator matrix includes T first generator matrices, the T first generator matrices are distributed along the diagonal of the second generator matrix, and the ath of the T first generator matrices
  • the first matrix block of the +1 first generator matrix coincides with the second matrix block of the a-th first generator matrix, where a is an integer greater than or equal to 1, and the T is an integer greater than or equal to 2; according to The second generating matrix performs polarization encoding on the K to-be-encoded bits to obtain encoded bits.
  • the logic circuit may also execute the encoding method described in any one of the third aspect.
  • an embodiment of the present application provides a decoding device.
  • the decoding device may include an input interface and a logic circuit, where:
  • the input interface is used to receive polarization-encoded bit information
  • the logic circuit is configured to perform polarization decoding on the bit information according to a second generator matrix to obtain polarized decoded bits, and the second generator matrix is generated according to the first generator matrix; wherein,
  • the first generator matrix includes a first matrix block and a second matrix block, the first matrix block is located at the upper left corner of the first generator matrix, and the second matrix block is located at the lower right corner of the first generator matrix,
  • the first matrix block and the second matrix block are the same, and along the diagonal direction of the first generator matrix, the first element in the first matrix block is the same as the second element in the second matrix block.
  • the distance between the elements is u, and the u is an integer greater than or equal to 1; wherein, the second generating matrix includes T first generating matrices, and the T first generating matrices are along the first generating matrix.
  • the diagonal distribution of the second generator matrix, the first matrix block of the a+1-th first generator matrix in the T first generator matrices coincides with the second matrix block of the a-th first generator matrix, the a is an integer greater than or equal to 1, and the T is an integer greater than or equal to 2.
  • the logic circuit may also execute the decoding method described in any one of the fourth aspect.
  • the embodiments of the application provide an encoding and decoding method, device, and equipment method.
  • a first generator matrix is determined first, and then a second generator matrix is generated according to the first generator matrix, and Perform polarization coding on the K bits to be coded according to the second generating matrix.
  • the first generator matrix includes at least two sub-blocks distributed according to a preset positional relationship, each sub-block includes a plurality of first generator matrix cores, the second generator matrix includes T sub-blocks, and adjacent ones of the T sub-blocks The positional relationship between the two sub-blocks is determined according to the preset positional relationship.
  • the second generating matrix includes a plurality of sub-blocks arranged according to the above-mentioned preset positional relationship, and each sub-block includes Multiple first generator matrix cores. Therefore, when the K bits to be encoded are polarized encoding according to the second generator matrix, it is equivalent to polar encoding multiple short codes first, and then coupling multiple short codes to obtain the encoding result, thereby reducing the encoding complexity .
  • the complexity of decoding can be reduced.
  • Figure 1 is an architecture diagram of the communication system provided by this application.
  • Figure 2 is a coding diagram provided by an embodiment of the application.
  • FIG. 3 is a schematic flowchart of an encoding method provided by an embodiment of the application.
  • FIG. 4 is a schematic diagram of sub-blocks provided by an embodiment of the application.
  • FIG. 5A is a schematic diagram of a first generating matrix provided by an embodiment of this application.
  • FIG. 5B is a schematic diagram of another first generating matrix provided by an embodiment of this application.
  • FIG. 5C is a schematic diagram of yet another first generating matrix provided by an embodiment of this application.
  • FIG. 6A is a schematic diagram of a second generating matrix provided by an embodiment of this application.
  • 6B is a schematic diagram of another second generating matrix provided by an embodiment of this application.
  • FIG. 6C is a schematic diagram of still another second generating matrix provided by an embodiment of this application.
  • FIG. 7A is a schematic diagram of a third generating matrix provided by an embodiment of this application.
  • FIG. 7B is a schematic diagram of a third generating matrix provided by an embodiment of this application.
  • FIG. 8A is a schematic diagram of a decoding process provided by an embodiment of this application.
  • FIG. 8B is a schematic diagram of another decoding process provided by an embodiment of this application.
  • FIG. 9A is another encoding diagram provided by an embodiment of this application.
  • FIG. 9B is another encoding diagram provided by an embodiment of this application.
  • FIG. 9C is another encoding diagram provided by an embodiment of this application.
  • FIG. 10 is a schematic flowchart of another encoding method provided by an embodiment of this application.
  • FIG. 11A is a schematic diagram of a first generating matrix provided by an embodiment of this application.
  • FIG. 11B is a schematic diagram of still another first generating matrix provided by an embodiment of this application.
  • FIG. 11C is a schematic diagram of another first generating matrix provided by an embodiment of this application.
  • FIG. 12A is a schematic diagram of still another first generating matrix provided by an embodiment of this application.
  • FIG. 12B is a schematic diagram of still another first generating matrix provided by an embodiment of this application.
  • FIG. 13 is a schematic diagram of another second generating matrix provided by an embodiment of this application.
  • FIG. 14 is a schematic diagram of a process of generating a second generator matrix according to an embodiment of the application.
  • FIG. 15A is a schematic diagram of a second generating matrix provided by an embodiment of this application.
  • 15B is a schematic diagram of another second generating matrix provided by an embodiment of this application.
  • 15C is a schematic diagram of a second generating matrix provided by an embodiment of this application.
  • FIG. 16 is a schematic diagram of decoding provided by an embodiment of this application.
  • FIG. 17 is a schematic diagram of a decoding process provided by an embodiment of this application.
  • FIG. 18 is a schematic diagram of a decoding process provided by an embodiment of this application.
  • FIG. 19 is a schematic diagram of decoding performance provided by an embodiment of this application.
  • 20A is a schematic diagram of another decoding performance provided by an embodiment of this application.
  • 20B is a schematic diagram of another decoding performance provided by an embodiment of this application.
  • FIG. 21 is a schematic structural diagram of an encoding device provided by an embodiment of this application.
  • FIG. 22 is a schematic structural diagram of a decoding device provided by an embodiment of this application.
  • FIG. 23 is a schematic structural diagram of another encoding device provided by an embodiment of this application.
  • FIG. 24 is a schematic structural diagram of another decoding device provided by an embodiment of this application.
  • 25 is a schematic diagram of the hardware structure of an encoding device provided by an embodiment of the application.
  • FIG. 26 is a schematic diagram of the hardware structure of a decoding device provided by an embodiment of the application.
  • FIG. 27 is a schematic structural diagram of another encoding device provided by an embodiment of this application.
  • FIG. 28 is a schematic structural diagram of another decoding device provided by an embodiment of this application.
  • FIG. 29 is a schematic structural diagram of another encoding device provided by an embodiment of this application.
  • FIG. 30 is a schematic structural diagram of another decoding device provided by an embodiment of this application.
  • the embodiments of the present application can be applied to various fields that adopt Polar coding, such as: data storage field, optical network communication field, wireless communication field, and so on.
  • the wireless communication systems mentioned in the embodiments of this application include but are not limited to: narrowband-internet of things (NB-IoT), Wimax, long-term evolution (LTE), and next-generation 5G Three application scenarios of the new radio (NR) of the mobile communication system Enhanced mobile broadband (eMBB), ultra-reliable and low-latency communication (URLLC), and large-scale machines Communications (massive machine-type communications, mMTC).
  • NB-IoT narrowband-internet of things
  • LTE long-term evolution
  • 5G Three application scenarios of the new radio (NR) of the mobile communication system Enhanced mobile broadband (eMBB), ultra-reliable and low-latency communication (URLLC), and large-scale machines Communications (massive machine-type communications, mMTC).
  • eMBB new radio
  • URLLC ultra-reliable and low-late
  • the embodiments of this application are suitable for communication scenarios with a long code length, for example, including but not limited to large-throughput business scenarios, high-definition video business scenarios, large file transmission business scenarios, virtual reality (VR)/augmented reality ( Multimedia services such as augmented reality (AR for short), and automatic hybrid repeat request (HARQ) of wireless communication, etc.
  • large-throughput business scenarios high-definition video business scenarios
  • high-definition video business scenarios large file transmission business scenarios
  • VR virtual reality
  • augmented reality Multimedia services such as augmented reality (AR for short)
  • HARQ automatic hybrid repeat request
  • Figure 1 is an architecture diagram of the communication system provided by this application. Please refer to Fig. 1, which includes a sending device 101 and a receiving device 102.
  • the receiving device 102 is a network device.
  • the sending device 101 is a network device
  • the receiving device 102 is a terminal device.
  • the sending device 101 includes an encoder, so that the sending device 101 can perform polar encoding and output an encoded sequence.
  • the encoded sequence is transmitted to the receiving device 102 on the channel after rate matching, interleaving, and modulation.
  • the receiving device 102 includes a decoder, and the receiving device 102 can receive a signal sent by the sending device 101 and decode the received signal.
  • FIG. 1 merely illustrates an architecture diagram of a communication system in the form of an example, and is not a limitation on the architecture diagram of the communication system.
  • Terminal equipment including but not limited to mobile station (MS), mobile terminal (MT), mobile phone (mobile telephone, MT), mobile phone (handset) and portable equipment (portable equipment), etc., the terminal equipment It can communicate with one or more core networks via a radio access network (RAN).
  • RAN radio access network
  • the terminal device may be a mobile phone (or called a "cellular" phone), a computer with wireless communication function, etc.
  • the terminal device may also be a portable, pocket-sized, handheld, built-in computer or vehicle-mounted mobile device or device.
  • Network equipment It can be an evolutional node B (eNB or eNodeB) in the LTE system, or it can be a gNB or a transmission and reception point (TRP) in a 5G communication system, a micro base station, etc. , Or the network equipment can be relay stations, access points, in-vehicle equipment, wearable devices, and network equipment in the public land mobile network (PLMN) that will evolve in the future, or in a network where multiple technologies are converged, Or base stations in various other evolved networks, etc.
  • eNB evolutional node B
  • TRP transmission and reception point
  • PLMN public land mobile network
  • Polarization coding can also become polar coding. Polar coding can be described in the following two ways:
  • the encoding process can be represented by a generator matrix, that is,
  • N is the code length, and N is an integer greater than or equal to 1.
  • u i is the bit before encoding, i is an integer between 1 and N. It includes information bits and/or frozen bits, that is, u i can be information bits or frozen bits.
  • Information bits are bits used to carry information, and the information bits may include Cyclic Redundancy Check (CRC) bits and/or Parity Check (PC) bits.
  • CRC Cyclic Redundancy Check
  • PC Parity Check
  • G N is the generator matrix
  • G N is the N*N matrix
  • B N is an N*N transposed matrix
  • B N may be a bit reversal matrix
  • the above mentioned addition and multiplication are all operations on the binary Galois field (galois field).
  • G N can also be referred to as a generator matrix core.
  • the coding process can be represented by a coding diagram.
  • Figure 2 is a coding diagram provided by an embodiment of the application.
  • the encoding code length corresponding to the encoding diagram is 8, each circle in the first column represents an information bit or a frozen bit, and u 1 , u 2 ,..., u 8 in the first column are before encoding Of bits (information bits or frozen bits), where u 4 , u 6 , u 7 , and u 8 are information bits, and u 1 , u 2 , u 3 , and u 5 are frozen bits.
  • Each circle in the columns except the first column represents a partial sum bit.
  • the x 1 , x 2 ,..., x 8 in the last column are the encoded bits.
  • Each butterfly diagram (shown on the right in the figure) represents a polarization of 2 bits, that is,
  • an embodiment of the present application provides an encoding method.
  • the generator matrix corresponding to the short code can be processed to obtain the final generator matrix, and polarization encoding is performed according to the final generator matrix. Yu firstly performs polarization coding on multiple short codes, and then couples multiple short codes to obtain coding results, thereby reducing coding complexity.
  • the starting coordinates in the matrix are (1, 1) as an example for description.
  • the starting coordinates in the matrix can also be (0, 0), the embodiment of the present application does not specifically limit this.
  • FIG. 3 is a schematic flowchart of an encoding method provided by an embodiment of the application. See Figure 3. The method can include:
  • K is a positive integer.
  • the K bits to be encoded include information bits and frozen bits. Or, all the K bits to be encoded are information bits.
  • the first generator matrix includes at least two sub-blocks distributed according to a preset position relationship, and the sub-block includes a plurality of first generator matrix cores.
  • the first generator matrix core may be G N.
  • N 2 n , where n is a positive integer.
  • the size of N can be set according to actual needs, for example, N can be a preset value.
  • the sub-block may include the first generator matrix core and the 0 matrix (which can be expressed as 0 N ).
  • the size of the first generator matrix core is the same as the size of the 0 matrix. For example, if the size of the first generator matrix core is N*N, the size of the 0 matrix is also N*N.
  • the first generator matrix core or the 0 matrix is referred to as a matrix unit.
  • the size of the matrix refers to the number of rows and columns in the matrix.
  • the size of the matrix can be expressed by M*N (M is the number of rows in the matrix, and N is the number of columns in the matrix).
  • M is the number of rows in the matrix
  • N is the number of columns in the matrix.
  • the size of the matrix can be expressed by the number of rows or columns.
  • the size of the matrix can be expressed by N*N, or by N Indicates the size of the matrix.
  • Fig. 4 is a schematic diagram of sub-blocks provided by an embodiment of the application. Please refer to FIG. 4, the sub-block includes multiple matrix units, and FIG. 4 takes 16 matrix units as an example for illustration.
  • Each matrix unit includes N*N elements, for example, the elements can be 0 or 1.
  • the matrix unit can be G N or 0 N. Assuming that N is equal to 2, then
  • the first diagonal of the sub-block includes a first generator matrix kernel (G N ).
  • the first diagonal may be the main diagonal of the sub-block.
  • the matrix unit on the main diagonal of the sub-block is G N , such as the (1,1), (2,2), (3,3), (4,4)th matrix
  • the unit is G N.
  • the multiple first generator matrix cores in the sub-block are distributed in a triangle below.
  • multiple G N in the sub-block are distributed below the triangle.
  • the distribution of the first generator matrix core in the sub-block is the same as the distribution of the first element in the second generator matrix core, and the first element may be 1.
  • the element distribution in the core of the second generator matrix satisfies
  • the number of elements in the second generator matrix core and the number of elements in the first generator matrix core may be the same or different.
  • the distribution of G N in the sub-block is the same as the distribution of 1 in the second generator matrix core, and correspondingly, the distribution of 0 N in the sub-block is the same as the distribution of 0 in the second generator matrix core.
  • Example 1 assuming that the second generator matrix core is Then the sub-block can be The number of matrix units included in the sub-block is 2*2. Among them, the distribution of G N in the sub-block is the same as the distribution of element 1 in the second generator matrix core.
  • the sub-block can be obtained as:
  • the sub-block can be obtained as:
  • Example 2 Assuming that the second generator matrix core is Then the sub-block can be The distribution of G N in the sub-block is the same as the distribution of element 1 in the second generator matrix core.
  • the sub-block can be obtained as:
  • the first generating matrix includes at least two sub-blocks distributed according to a preset position relationship.
  • the number of sub-blocks included in the first generating matrix may be two.
  • overlapping parts in at least two sub-blocks in the first generator matrix there are overlapping parts in at least two sub-blocks in the first generator matrix.
  • every two adjacent sub-blocks in the first generator matrix have overlapping parts.
  • the two adjacent sub-blocks are sub-block 1 and sub-block 2, respectively.
  • the element in the lower right corner area of sub-block 1 is the same as sub-block 2.
  • the elements in the upper left corner of the area overlap.
  • the preset positional relationship may be: sub-block 1 is located in the upper left part of the first generator matrix, and sub-block 2 is located in the first In the lower right part of the generator matrix, the lower right corner area of sub-block 1 coincides with the upper left corner area of sub-block 2.
  • FIG. 5A is a schematic diagram of a first generating matrix provided by an embodiment of this application.
  • FIG. 5B is a schematic diagram of another first generating matrix provided by an embodiment of this application.
  • FIG. 5C is a schematic diagram of still another first generating matrix provided by an embodiment of this application.
  • the first generating matrix includes two sub-blocks, which are respectively denoted as the first sub-block and the second sub-block, and the first sub-block and the second sub-block are the same.
  • the first sub-block is located in the upper left part of the first generator matrix
  • the second sub-block is located in the lower right part of the first generator matrix.
  • the lower-right corner area of the first sub-block overlaps with the upper-left corner area of the second sub-block, and the elements in the lower-right corner area of the first sub-block have the same distribution of elements in the upper-left corner area of the second sub-block.
  • the first generator matrix includes the first sub-block and the second sub-block, and the first sub-block and the second sub-block are respectively Then the first generator matrix can be
  • the first sub-block is located in the upper left part of the first generator matrix
  • the second sub-block is located in the lower right part of the first generator matrix.
  • the first matrix unit in the first sub-block coincides with the second matrix unit in the second sub-block.
  • the coordinates of the first matrix unit in the first sub-block are (2, 2), and the coordinates of the second matrix unit in the second sub-block are (1, 1).
  • the first generator matrix includes the first sub-block and the second sub-block, and the first sub-block and the second sub-block are respectively Then the first generator matrix can be The first sub-block is located in the upper left part of the first generator matrix, and the second sub-block is located in the lower right part of the first generator matrix.
  • the four first matrix units in the first sub-block overlap with the four second matrix units in the second sub-block.
  • the coordinates of the 4 first matrix units in the first sub-block are: (3,3), (3,4), (4,3), (4,4); the 4 second matrix units are in the second
  • the coordinates in the sub-block are: (1,1), (1,2), (2,1), (2,2).
  • FIG labeled 0 N omitted i.e., the blank of FIG. 5B- FIG. 5C are 0 N unit matrix.
  • the second generating matrix includes T sub-blocks, the positional relationship between two adjacent sub-blocks in the T sub-blocks is determined according to a preset positional relationship, and T is a positive integer.
  • the positional relationship between two adjacent sub-blocks in the T sub-blocks is the same as the preset positional relationship.
  • the number T of sub-blocks included in the second generator matrix can be determined according to the first generator matrix, the size of the sub-block and the coding length N′, and the second generator matrix can be generated according to the first generator matrix and the number T.
  • T is the smallest integer that satisfies the first condition
  • the first condition is that the size of the second generator matrix is greater than or equal to the code length.
  • the second generator matrix is a square matrix, and the size of the second generator can be represented by the number of rows or columns included in the second generator matrix, that is, the size of the second generator matrix is the number of rows or columns included in the second generator matrix .
  • T satisfies the following relationship:
  • v is the size of the sub-block (the sub-block is a square matrix, and v represents the number of rows or columns of elements included in the sub-block).
  • N' is the code length, and N'is an integer greater than one.
  • u is the distance between two adjacent sub-blocks, which can pass through the distance between the first element in two adjacent sub-blocks (for example, the first element can be an element with coordinates (1,1) in the sub-block) (Difference of row number or difference of column number) represents the distance between two adjacent sub-blocks.
  • T 7.
  • T is 5.
  • FIG. 6A is a schematic diagram of a second generating matrix provided by an embodiment of this application.
  • the first generator matrix includes two sub-blocks, each sub-block includes 16 matrix units, some of the matrix units are G N , and some of the matrix units are 0 N.
  • the positional relationship of the two sub-blocks is shown in Figure 6A.
  • the second generator matrix includes 7 sub-blocks, which are respectively denoted as sub-block 1, sub-block 2, ..., sub-block 6, and sub-block 7.
  • the positional relationship between every two adjacent sub-blocks in the 7 sub-blocks is the same as the positional relationship between the two sub-blocks in the first generating matrix.
  • the size of the second generator matrix (the number of rows or columns included in the second generator matrix) is 2048.
  • FIG. 6B is a schematic diagram of another second generating matrix provided by an embodiment of this application. Referring to FIG. 6B, it is assumed that the first generator matrix includes two sub-blocks, each sub-block includes 16 matrix units, some of the matrix units are G N , and some of the matrix units are 0 N. The positional relationship of the two sub-blocks is shown in Figure 6B.
  • the second generating matrix includes 5 sub-blocks, which are respectively denoted as sub-block 1, sub-block 2, sub-block 3, sub-block 4, and sub-block 5.
  • the positional relationship between every two adjacent sub-blocks in the 5 sub-blocks It is the same as the positional relationship between the two sub-blocks in the first generator matrix.
  • the size of the second generator matrix (the number of rows or columns included in the second generator matrix) is 1536.
  • FIG. 6C is a schematic diagram of still another second generating matrix provided by an embodiment of this application.
  • the first generator matrix includes two sub-blocks, each sub-block includes 4 matrix units, some of the matrix units are G N , and some of the matrix units are 0 N.
  • the positional relationship of the two sub-blocks is shown in Figure 6C.
  • the second generator matrix includes 7 sub-blocks, which are respectively denoted as sub-block 1, sub-block 2, ..., sub-block 6, and sub-block 7.
  • the positional relationship between every two adjacent sub-blocks in the 7 sub-blocks is the same as the positional relationship between the two sub-blocks in the first generating matrix.
  • the size of the second generator matrix (the number of rows or columns included in the second generator matrix) is 1024.
  • the matrix units except G N are all 0 N.
  • the mark of 0 N is omitted in the figure, that is, the blanks in FIGS. 6A-6C
  • the matrix units are all 0 N.
  • FIGS. 6A-6C are only illustrative of the second generator matrix in the form of examples, and are not a limitation on the second generator matrix.
  • the second generator matrix may also be other. limited.
  • the K bits to be coded are subjected to polarization coding according to the second generating matrix to obtain the coded bits.
  • the third generator matrix is a matrix truncated in the upper left corner area of the second generator matrix, or the third generator matrix is a matrix truncated in the lower right corner area of the second generator matrix.
  • the third generator matrix is a square matrix.
  • FIG. 7A is a schematic diagram of a third generating matrix provided by an embodiment of this application. Referring to FIG. 7A, assuming that the coding level is 1500 and the size of the second generator matrix is 1536, a matrix with a size of 1500 can be intercepted in the upper left corner area of the second generator matrix as the third generator matrix.
  • FIG. 7B is a schematic diagram of a third generating matrix provided by an embodiment of this application. Referring to FIG. 7B, assuming that the coding level is 1500 and the size of the second generator matrix is 1536, a matrix with a size of 1500 can be intercepted in the lower right corner area of the second generator matrix as the third generator matrix.
  • the K sub-channels with the highest reliability can be determined among the multiple sub-channels corresponding to the K bits to be coded, and the K bits to be coded can be determined according to the K sub-channels with the highest reliability.
  • the sequence to be coded includes K bits to be coded and frozen bits. According to the second generating matrix, the coded sequence is polarized and coded to obtain the coded bits.
  • the positions of the K bits to be coded are positions corresponding to the K subchannels with the highest reliability.
  • fill information bits bits to be coded
  • the coded sequence includes N'bits, N The'bits include K information bits and N'-K frozen bits.
  • the code length is 8
  • the number of bits to be coded is 4, and the sub-channels with the highest reliability among the eight sub-channels are: sub-channel 4, sub-channel 6, sub-channel 7 and sub-channel 8, then sub-channel 4
  • the corresponding positions of subchannel 6, subchannel 7 and subchannel 8 are used to carry information bits, and the other subchannels are used to carry frozen bits.
  • the sequence to be coded may be 00010111, where 1 represents information bits, and 0 represents frozen bits.
  • the K sub-channels with the highest reliability can be determined in the following way:
  • P group of sub-channels is determined among multiple sub-channels, and P is a positive integer.
  • X i first sub-channels are determined in the i-th group of sub-channels
  • the K sub-channels with the highest reliability include the first sub-channels determined in each group of sub-channels.
  • the X i first sub-channels are the X i sub-channels with the highest reliability in the i-th group of sub-channels, i is an integer, 1 ⁇ i ⁇ P, and X i is a positive integer,
  • the number of sub-channels included in a group of sub-channels may be the same as the size of one matrix unit. For example, assuming that the size of the matrix unit is 16, a group of sub-channels includes 16 sub-channels.
  • the number of sub-channels included in a group of sub-channels may be the same as the size of one sub-block. For example, assuming that the size of a sub-block is 64, a group of sub-channels includes 64 sub-channels.
  • the reliability of each group of sub-channels can be pre-calculated, and the reliability of each group of sub-channels can be stored.
  • the following two methods can be used to store the reliability of each group of sub-channels:
  • the sequence numbers of the 8 sub-channels are: 1, 2, ..., 7, 8.
  • Sub-channel Reliability Subchannel 1 2.1 Subchannel 2 3 Subchannel 3 4.5 Subchannel 4 5 Subchannel 5 3.2 Subchannel 6 2 Subchannel 7 2.6 Subchannel 8 7
  • the reliability rankings of the sub-channels in different groups may be the same or different.
  • the reliability rankings of the sub-channels in different groups are the same, the reliability of only one group of sub-channels can be stored.
  • the reliability of all sub-channels corresponding to the coding code length may be calculated in advance, and the reliability sequence may be stored. Assuming that the maximum encoding code length supported by the protocol is N*T, where N is the size of a matrix unit, T reliability sequences can be pre-calculated and stored, and the lengths of the T reliability sequences are: T, 2T, 3T ,..., N*T.
  • the calculation of the reliability of the sub-channel shown in the embodiment of the present application includes: the reliability calculation within the short code and the reliability calculation between the short codes. Among them, the reliability calculation in the short code is the same as the existing calculation method.
  • the method of calculating the reliability of the sub-channel is also different.
  • the method of calculating the reliability of the sub-channel is introduced through specific examples.
  • Example 1 Assuming that the second generator matrix is the second generator matrix shown in FIG. 6C, the code corresponding to the second generator matrix may also be referred to as 2-coupled coding.
  • ⁇ -1 (x) is the inverse function of ⁇ (x).
  • FIG. 8B is a schematic diagram of another decoding process provided by an embodiment of this application. See Figure 8B, For the input first reliability of the i-th group of sub-channels, the f operation is the same as the f operation shown in FIG. 8A.
  • FIG. 9A is another encoding diagram provided by an embodiment of this application.
  • the second generator matrix corresponding to the coding image is the second generator matrix in FIG. 6C.
  • Figure 9A compared with the encoding diagram shown in Figure 2, the leftmost box in Figure 9A no longer represents an information bit or a frozen bit, and a box represents a short code encoding image, for example, short
  • the code length of the code can be the size N of a matrix unit.
  • the circles in each column except the first column no longer represent a part and bit, but a part and bit vector.
  • the number of polarizations (the number of columns of edges in the coding and decoding diagram) of each N-length short code is log 2 (N) times.
  • the short code is polarized twice to obtain a long code with a code length of N′. Therefore, the number of polarizations of a long code with a code length of N′ is log 2 (N)+2 times, and the total coding and decoding complexity is N′*(log 2 (N)+2). Since N can be set as a constant that does not change with N', when N'is very large, we can ignore the constant term, and the compilation complexity is O(N').
  • the polar code shown in this application can be referred to as a coupled polar code.
  • the coding diagram of the coupled polar code can be regarded as a recombination or cropping of the original long code coding diagram. 9C, a further detailed description of the coded picture.
  • FIG. 9B is another encoding diagram provided by an embodiment of this application. Referring to FIG. 9B, several columns can be extracted from the original Polar long code encoding diagram, and then combined to obtain an encoding diagram of the coupled Polar code.
  • FIG. 9C is another encoding diagram provided by an embodiment of this application. Referring to Fig. 9C, several rows and several columns can be extracted from the original Polar long code coding diagram, and then combined to obtain a coding diagram of the coupled Polar code.
  • the transmitting end obtains the coded bits
  • the coded bits are sent, and the coded bits are transmitted to the receiving end through the channel after rate matching, interleaving, and modulation.
  • the first generator matrix is determined first, and then the second generator matrix is generated according to the first generator matrix, and the K bits to be encoded are determined according to the second generator matrix.
  • the coded bits are polarized coded. Since the first generator matrix includes at least two sub-blocks distributed according to a preset positional relationship, each sub-block includes a plurality of first generator matrix cores, the second generator matrix includes T sub-blocks, and adjacent ones of the T sub-blocks The positional relationship between the two sub-blocks is determined according to the preset positional relationship.
  • the second generating matrix includes a plurality of sub-blocks arranged according to the above-mentioned preset positional relationship, and each sub-block includes Multiple first generator matrix cores. Therefore, when the K bits to be encoded are polarized encoding according to the second generator matrix, it is equivalent to polar encoding multiple short codes first, and then coupling multiple short codes to obtain the encoding result, thereby reducing the encoding complexity .
  • FIG. 10 is a schematic flowchart of another encoding method provided by an embodiment of this application. Referring to Figure 10, the method can include:
  • K is a positive integer.
  • first generator matrix in the embodiment in FIG. 10 is equivalent to the sub-block in the embodiment in FIG. 3, and the description of the sub-block in the embodiment in FIG. 3 can be applied to the first generator matrix in the embodiment in FIG. 10. I will not repeat them here.
  • the first generator matrix includes a first matrix block and a second matrix block
  • the first matrix block is located at the upper left corner of the first generator matrix
  • the second matrix block is located at the lower right corner of the first generator matrix
  • the first matrix block and the second matrix block The matrix blocks are the same, along the diagonal direction of the first generator matrix, the distance between the first element in the first matrix block and the second element in the second matrix block (hereinafter may also be referred to as the first matrix block and the second element for short)
  • the distance between the two matrix blocks) is u, and u is an integer greater than or equal to 1.
  • the first element may be an element in the upper left corner of the first matrix block
  • the second element may be an element in the upper left corner of the second generator matrix.
  • the distance between the first element and the second element refers to the difference between the row number or the column number of the first element and the second element.
  • the first element is 0 or 1.
  • first generator matrix other elements except the first matrix block and the second matrix block may all be 0 elements.
  • a first matrix and a second matrix block may comprise a block or a plurality of matrix cells, matrix cells, or may be a G N 0 N. Both the first matrix block and the second matrix block are square matrices. G N 0 N may be described and illustrated embodiment Referring to FIG. 3.
  • the first generator matrix satisfies self-similarity (or shifted self-similarity).
  • Self-similarity refers to the movement of the first matrix block in the first generator matrix (for example, along the main diagonal of the first generator matrix). After moving) the preset distance, the first matrix block can be moved to the position of the second matrix block, and the content in the first matrix block and the second matrix block are the same.
  • the elements in the first generator matrix satisfy: a i,j ⁇ a i+u,j+u , where i is an integer, j is an integer, and v is the first generator matrix
  • i is an integer
  • j is an integer
  • v is the first generator matrix
  • the size of u is an integer, 1 ⁇ i ⁇ v, 1 ⁇ j ⁇ v, 1 ⁇ i+u ⁇ v, 1 ⁇ j+u ⁇ v.
  • FIG. 11A is a schematic diagram of a first generating matrix provided by an embodiment of this application.
  • the first generator matrix includes a first matrix block and a second matrix block.
  • the first matrix block is located in the upper left corner (or called the upper left corner area) of the first generator matrix
  • the second matrix block is located in the first generator.
  • the bottom right corner of the matrix (or called the bottom right area).
  • the first matrix block is the same as the second matrix block.
  • the first generator matrix and the second generator matrix partially overlap.
  • FIG. 11B is a schematic diagram of still another first generating matrix provided by an embodiment of this application.
  • the first generator matrix includes a first matrix block and a second matrix block.
  • the first matrix block is located in the upper left corner (or called the upper left corner area) of the first generator matrix
  • the second matrix block is located in the first generator.
  • the bottom right corner of the matrix (or called the bottom right area).
  • the first matrix block is the same as the second matrix block.
  • first generator matrix and the second generator matrix there is a certain distance between the first generator matrix and the second generator matrix, that is, an element in the lower right corner of the first generator matrix (referred to as element 1) and an element in the upper left corner of the second generator matrix (referred to as element 2) There is a certain distance between them, for example, the difference between the row numbers of element 2 and element 1 is greater than 1.
  • FIG. 11C is a schematic diagram of another first generating matrix provided by an embodiment of this application.
  • the first generator matrix includes a first matrix block and a second matrix block.
  • the first matrix block is located in the upper left corner (or called the upper left corner area) of the first generator matrix
  • the second matrix block is located in the first generator.
  • the bottom right corner of the matrix (or called the bottom right area).
  • the first matrix block is the same as the second matrix block.
  • the first generator matrix and the second generator matrix are adjacent, that is, an element in the lower right corner of the first generator matrix (referred to as element 1) is adjacent to an element in the upper left corner of the second generator matrix (referred to as element 2),
  • element 1 an element in the lower right corner of the first generator matrix
  • element 2 an element in the upper left corner of the second generator matrix
  • the row number of element 2 is one greater than the row number of element 1
  • the column number of element 2 is one greater than the column number of element 1.
  • the elements in the first generator matrix are symmetrical along the subdiagonal line of the first generator matrix.
  • FIG. 12A is a schematic diagram of still another first generating matrix provided by an embodiment of this application.
  • the first generator matrix includes a first matrix block and a second matrix block, and the first matrix block and the second matrix block each include a G N. Assuming that N is 128, the distance between the first matrix block and the second matrix block is 128.
  • FIG. 12B is a schematic diagram of still another first generating matrix provided by an embodiment of this application.
  • the first generated matrix includes a first matrix block and a second matrix block, and the first matrix block and the second matrix block respectively include four matrix units. Assuming that N is 128, the distance between the first matrix block and the second matrix block is 256.
  • FIG 12A- FIG. 12B FIG labeled 0 N omitted, i.e., in FIG 12A- FIG. 12B are blank 0 N unit matrix.
  • Figures 12A to 12B illustrate the first generator matrix only by way of example, and do not limit the first generator matrix.
  • the second generator matrix includes T first generator matrices, the T first generator matrices are distributed along the diagonal of the second generator matrix (for example, the diagonal may be the main diagonal), and the T first generators
  • the first matrix block of the a+1 first generator matrix in the generator matrix coincides with the second matrix block of the a-th first generator matrix, a is an integer greater than or equal to 1, and T is an integer greater than or equal to 2 .
  • FIG. 13 is a schematic diagram of another second generating matrix provided by an embodiment of this application.
  • the second generator matrix includes five first generator matrices.
  • the five first generator matrices are distributed along the main diagonal of the second generator matrix, along the downward and rightward extension direction of the main diagonal of the second generator matrix.
  • the matrix in the upper left corner of the second generator matrix is the first first generator matrix.
  • the first generator matrix referred to by the number 1 is the first first generator matrix
  • the first generator matrix referred to by the number 2 is the second first generator matrix, and so on, as shown by the number 5.
  • the first generator matrix referred to is the fifth first generator matrix.
  • the second matrix block of the first first generator matrix coincides with the first matrix block of the second first generator matrix.
  • the second matrix block of the second first generator matrix coincides with the first matrix block of the third first generator matrix.
  • the second matrix block of the third first generator matrix coincides with the first matrix block of the fourth first generator matrix.
  • the second matrix block of the fourth first generator matrix coincides with the first matrix block of the fifth first generator matrix.
  • T is the smallest integer that enables the first condition to be satisfied, and the first condition is: the size of the second generator matrix is greater than or equal to the code length.
  • T satisfies the following relationship:
  • v is the size of the first generator matrix
  • N′ is the coding length
  • N′ is an integer greater than 1.
  • T 7.
  • T is 5.
  • the number T of the first generator matrix included in the second generator matrix may be determined according to the coding length and the first generator matrix, and then the second generator matrix is generated according to the first generator matrix and the number T. For example, you can copy and move the first generator matrix T-1 times along the main diagonal of the first generator matrix to obtain the second generator matrix.
  • Each movement distance is u, and the movement distance refers to the number of rows or columns moved. For example, if you move 3 rows, the moving distance is 3.
  • FIG. 14 is a schematic diagram of a process of generating a second generator matrix according to an embodiment of the application.
  • the first generator matrix includes 16 matrix units, some of which are G N and some of them are 0 N.
  • the first generator matrix satisfies self-similarity, and the distance (row or column distance) between the first matrix block and the second matrix block in the first generator matrix is u. Assuming that it is determined that the second generator matrix includes three first generator matrices, the first generator matrix needs to be copied and moved twice.
  • the second generator matrix includes the first generator matrix 1, the first generator matrix 2, and the first generator matrix 3.
  • FIG. 14 merely illustrates a way of generating a second generator matrix according to the first generator matrix by way of example, and is not a limitation on this way.
  • the matrix units except G N are all 0 N.
  • the mark of 0 N is omitted in the figure, that is, the blank matrix units in FIG. 14 are all 0 N.
  • FIG. 15A is a schematic diagram of a second generating matrix provided by an embodiment of this application.
  • the first generator matrix includes 16 matrix units, some of which are G N , and some of them are 0 N.
  • the first generator matrix satisfies self-similarity.
  • the second generator matrix includes 7 first generator matrices. In every two adjacent generator matrices of the 7 first generator matrices, the first matrix block of the latter generator matrix and the first matrix block of the previous first generator matrix The two matrices overlap.
  • the size of the second generator matrix (the number of rows or columns included in the second generator matrix) is 2048.
  • FIG. 15B is a schematic diagram of another second generating matrix provided by an embodiment of this application.
  • the first generator matrix includes 16 matrix units, some of which are G N , and some of them are 0 N.
  • the first generator matrix satisfies self-similarity.
  • the second generator matrix includes 5 first generator matrices. In every two adjacent generator matrices of the 5 first generator matrices, the first matrix block of the latter generator matrix and the first matrix block of the previous first generator matrix The two matrices overlap.
  • the size of the second generator matrix (the number of rows or columns included in the second generator matrix) is 1536.
  • FIG. 15C is a schematic diagram of a second generating matrix provided by an embodiment of this application.
  • the first generator matrix includes 16 matrix units, some of which are G N , and some of them are 0 N.
  • the first generator matrix satisfies self-similarity.
  • the second generator matrix includes 7 first generator matrices. In every two adjacent generator matrices of the 7 first generator matrices, the first matrix block of the latter generator matrix and the first matrix block of the previous first generator matrix The two matrices overlap.
  • the size of the second generator matrix (the number of rows or columns included in the second generator matrix) is 1024.
  • the matrix units except G N are all 0 N.
  • the mark of 0 N is omitted in the figure, that is, the blanks in FIGS. 15A-15C
  • the matrix units are all 0 N.
  • the first generator matrix is determined first, and then the second generator matrix is generated according to the first generator matrix, and the K bits to be encoded are determined according to the second generator matrix.
  • the coded bits are polarized coded. Since the first generator matrix has self-similarity, the second generator matrix includes multiple first matrix blocks. Therefore, when the K bits to be encoded are polarized encoding according to the second generator matrix, it is equivalent to performing multiple short codes first. Perform polarization coding, and then couple multiple short codes to obtain coding results, thereby reducing coding complexity.
  • FIG. 16 is a schematic diagram of decoding provided by an embodiment of this application. Referring to Figure 16, the method can include:
  • the bit information includes N′ first likelihood ratio (LLR) sequences, and N′ is a positive integer.
  • N′ is a positive integer.
  • the signal is demodulated and other processing to obtain N′ first LLRs, and Polar code decoding is performed according to the received N′ first LLRs.
  • the receiving end may misjudge.
  • b 0) that is correctly judged as 0 at the receiving end and the probability p(r
  • LLR log-likelihood ratio
  • S1602 Perform polarization decoding on the bit information according to the second generating matrix to obtain polarization decoded bits.
  • the second generating matrix is a matrix for performing polarization coding in the embodiment of FIG. 3.
  • the second generating matrix refers to the embodiment shown in FIG. 3, which will not be repeated here.
  • the second generator matrix is a matrix for polarization coding in the embodiment of FIG. 10.
  • the second generating matrix refer to the embodiment shown in FIG. 10, which will not be repeated here.
  • the coding sequence includes N′ bits before coding, and the N′ bits before coding include K information bits and N′-K frozen bits.
  • the N′ first LLRs include T first LLR sequences.
  • the N′ first LLRs can be divided into T first LLR sequences, and one first LLR sequence includes N LLRs.
  • a first LLR sequence can be combined with two or more sets of bits before encoding. For example, assuming that the coding sequence includes 8 groups of bits before coding, and the second generator matrix is shown in FIG. The relationship of the previous bit group is shown in Table 2:
  • the first LLR sequence 1 is related to the first group of bits before encoding and the second group of bits before encoding
  • the first LLR sequence 2 is related to the second group of bits before encoding and the third group of bits before encoding. ,And so on.
  • the first LLR sequence can be decoupled to obtain the second LLR sequence corresponding to each first LLR sequence, so that a second LLR sequence corresponds to a set of bits before encoding.
  • the first LLR sequence shown in Table 2 is decoupled to obtain 8 second LLR sequences.
  • the relationship between the 8 second LLR sequences and the bit group before encoding is shown in Table 3:
  • Identification of the first LLR sequence Bit group before encoding First LLR sequence 1 The first group of bits before encoding First LLR sequence 2 Group 2 bits before encoding First LLR sequence 3 3rd group of bits before encoding First LLR sequence 4 4th group of bits before encoding First LLR sequence 5 Group 5 bits before encoding First LLR sequence 6 Group 6 bits before encoding First LLR sequence 7 Group 7 bits before encoding First LLR sequence 8 Group 8 bits before encoding
  • the first LLR sequence 1 is related to the first group of bits before encoding
  • the first LLR sequence 2 is related to the second group of bits before encoding, and so on.
  • the second LLR sequence may be determined according to the first LLR sequence in the following manner: according to the i-th first LLR sequence and at least one second LLR sequence among the first i-1 second LLR sequences, the i-th LLR sequence is determined A second LLR sequence, the i is an integer between 2 and T.
  • the polarization decoding can be performed according to the T second LLR sequence in the following manner: according to the T second LLR sequence, it is determined to obtain the T-th decoding result; according to the i+1-th decoding result to the first At least one of the T decoding results and the i-th second LLR sequence determine the i-th decoding result, where i is an integer between 1 and T-1.
  • Example 1 Assuming that the second generator matrix is the second generator matrix shown in FIG. 6C, the code corresponding to the second generator matrix may also be referred to as 2-coupled coding.
  • the i-th second LLR sequence can be determined in the following manner: the i-th second LLR sequence is determined according to the i-th first LLR sequence and the i-1th second LLR sequence. Among them, the first second LLR sequence is the same as the first first LLR sequence.
  • the i-th decoding result may be determined in the following manner: the i-th decoding result is determined according to the i+1-th decoding result, the i+1-th first LLR sequence, and the i-th second LLR sequence.
  • FIG. 17 is a schematic diagram of a decoding process provided by an embodiment of this application.
  • l' i is the i-th first LLR sequence
  • l i is the i-th second LLR sequence
  • u i is the i-th bit sequence before encoding
  • c i is the i-th bit after encoding Sequence
  • i is an integer between 1 and 8.
  • g operation is: Encode c to get u.
  • the received N′ LLRs are divided into 8 first LLR sequences, which are respectively denoted as: l′ 1 , l′ 2 , l′ 3 , l' 4 , l' 5 , l' 6 , l' 7 , l' 8 .
  • the eight first LLR sequences corresponding to the second LLR sequences are respectively denoted as: l 1 , l 2 , l 3 , l 4 , l 5 , l 6 , l 7 , l 8 .
  • Fig. 17 first determine to obtain the first second LLR sequence l 1 . Then perform f operation on the first second LLR sequence l 1 and the second first LLR sequence l′ 2 to obtain the second second LLR sequence l 2 . Then perform f operation on the second second LLR sequence l 2 and the third first LLR sequence l′ 3 to obtain the third second LLR sequence l 3 , and so on, until the above 8 second LLR sequences are obtained .
  • first series of 8 l 8 second LLR input to the decoder for decoding to obtain a first decoding result of 8 u 8, wherein, u 8 includes the N decoded bits.
  • the result of g operation Input to the decoder for decoding and get the seventh decoding result u 7 .
  • Example 2 Assuming that the second generator matrix is the second generator matrix shown in FIG. 14, the encoding corresponding to the second generator matrix may also be referred to as 4-coupled encoding.
  • the i-th second LLR sequence can be determined in the following manner: the i-th second LLR sequence is determined according to the i-th first LLR sequence and the i-2 second LLR sequence, and the i is 3 to T Integer between.
  • the first second LLR sequence is the same as the first first LLR sequence; the second second LLR sequence is the same as the second first LLR sequence.
  • FIG. 18 is a schematic diagram of a decoding process provided by an embodiment of this application.
  • the f operation can be the same as the g operation in FIG. 17.
  • l' i is the i-th first LLR sequence.
  • the received N′ LLRs are divided into 8 first LLR sequences, which are respectively denoted as: l′ 1 , l′ 2 , l′ 3 , l' 4 , l' 5 , l' 6 , l' 7 , l' 8 .
  • decode according to the above-mentioned calculated parameters input l 8 into the decoder for decoding to obtain the eighth decoding result u 8 , where u 8 includes N decoding bits.
  • FIG. 19 is a schematic diagram of decoding performance provided by an embodiment of this application.
  • the horizontal axis represents the signal to noise ratio (SNR), and the vertical axis represents the block error rate (BLER).
  • SNR signal to noise ratio
  • BLER block error rate
  • the performance curve is shown as a dotted line.
  • the code length is 16384
  • the number K of information bits is 8129
  • two couplings are performed (for example, the second generator matrix is shown in FIG. 6C)
  • the performance curve is shown as a solid line. It can be seen from Fig. 19 that the method shown in this application can achieve a performance gain of about 1 dB.
  • the coupled Polar code has less complexity than the long Polar code without loss of performance.
  • the code length is increased to a certain length, the coupling in a larger range cannot bring significant performance gains.
  • FIG. 20A is a schematic diagram of another decoding performance provided by an embodiment of this application.
  • the performance curve is shown as a solid line.
  • the code length is 65536
  • the number of information bits K is 32768
  • two couplings are performed (for example, the second generator matrix is shown in FIG. 6C)
  • the performance curve is shown by one of the dashed lines.
  • the code length is 65536
  • the number of information bits K is 32768
  • 4-coupling for example, the second generator matrix is shown in FIG. 14
  • the performance curve is shown by the other dashed line.
  • FIG. 20B is a schematic diagram of another decoding performance provided by an embodiment of this application.
  • the performance curve is shown as a solid line.
  • the code length is 131072
  • the number K of information bits is 65536
  • two couplings for example, the second generator matrix is shown in FIG. 6C
  • the performance curve is shown by one of the dashed lines.
  • the code length is 131072
  • the number K of information bits is 65536
  • 4-coupling for example, the second generator matrix is shown in FIG. 14
  • the performance curve is shown by the other dashed line.
  • the coupling range or width can be limited to a certain extent, or an appropriate degree of coupling can be selected, so that performance can be achieved without loss of performance. Reduce the complexity of software and hardware implementation as much as possible.
  • FIG. 21 is a schematic structural diagram of an encoding device provided by an embodiment of this application.
  • the encoding device 10 may include an obtaining module 11, a determining module 12, a generating module 13, and an encoding module 14, where:
  • the obtaining module 11 is configured to obtain K bits to be coded, where K is a positive integer;
  • the determining module 12 is configured to determine a first generator matrix, where the first generator matrix includes at least two sub-blocks distributed according to a preset position relationship, and the sub-block includes a plurality of first generator matrix cores;
  • the generating module 13 is configured to generate a second generating matrix according to the first generating matrix, the second generating matrix including T sub-blocks, and the positional relationship between two adjacent sub-blocks in the T sub-blocks Is determined according to the preset position relationship, the T is a positive integer;
  • the encoding module 14 is configured to perform polarization encoding on the K to-be-encoded bits according to the second generating matrix to obtain encoded bits.
  • the obtaining module 11 may execute S301 in the embodiment of FIG. 3.
  • the determining module 12 may execute S302 in the embodiment of FIG. 3.
  • the generating module 13 may execute S303 in the embodiment of FIG. 3.
  • the encoding module 13 may perform S304 in the embodiment of FIG. 3.
  • the encoding device shown in the embodiment of the present application can execute the technical solution shown in the foregoing method embodiment, and its implementation principles and beneficial effects are similar, and will not be repeated this time.
  • the positional relationship between two adjacent sub-blocks in the T sub-blocks is the same as the preset positional relationship.
  • the first diagonal of the sub-block includes the first generator matrix core.
  • the multiple first generator matrix cores in the sub-block are distributed in a triangle below.
  • the distribution of the first generator matrix core in the sub-block is the same as the distribution of the first element in the second generator matrix core, and the number of elements included in the second generator matrix core is equal to The number of matrix units included in the sub-blocks is the same, and the matrix units included in the sub-blocks are the first generator matrix core or the 0 matrix.
  • the first generator matrix includes two sub-blocks.
  • the number of matrix units included in the sub-block is 2*2, and the matrix units included in the sub-block are the first generator matrix core or the 0 matrix.
  • the first generator matrix includes a first sub-block and a second sub-block, and the first matrix unit in the first sub-block and the second sub-block in the second sub-block are The matrix units coincide;
  • the coordinates of the first matrix unit in the first sub-block are (2, 2), and the coordinates of the second matrix unit in the second sub-block are (1, 1).
  • the number of matrix units included in the sub-block is 4*4, and the matrix units included in the sub-block are the first generator matrix core or the 0 matrix.
  • the first generator matrix includes a first sub-block and a second sub-block, and the four first matrix units in the first sub-block and the second sub-block in the The 4 second matrix units overlap; among them,
  • the coordinates of the four first matrix units in the first sub-block are: (3,3), (3,4), (4,3), (4,4);
  • the coordinates of the four second matrix units in the second sub-block are respectively: (1,1), (1,2), (2,1), (2,2).
  • the K bits to be encoded are information bits; the encoding module 14 is specifically configured to:
  • the multiple sub-channels include P groups of sub-channels, where P is a positive integer; the encoding module 14 is specifically configured to:
  • the reliability of the sub-group i, determining X i in the i-th first sub-set of subchannels in the first subchannel X i is the i-th set of subchannels highest reliability X i subchannels ,
  • the i is an integer, 1 ⁇ i ⁇ P, the X i is a positive integer,
  • the K subchannels with the highest reliability include the first subchannel.
  • the encoding device shown in the embodiment of the present application can execute the technical solution shown in the foregoing method embodiment, and its implementation principles and beneficial effects are similar, and will not be repeated this time.
  • FIG. 22 is a schematic structural diagram of a decoding device provided by an embodiment of this application.
  • the decoding device 20 may include a receiving module 21 and a decoding module 22, where:
  • the receiving module 21 is configured to receive polarization-encoded bit information
  • the decoding module 22 is configured to perform polarization decoding on the bit information according to the second generating matrix to obtain polarization decoded bits;
  • the second generator matrix is generated according to the first generator matrix
  • the first generator matrix includes at least two sub-blocks distributed according to a preset position relationship
  • the sub-block includes a plurality of first generator matrix cores
  • the second generating matrix includes T sub-blocks, the positional relationship between two adjacent sub-blocks in the T sub-blocks is determined according to the preset positional relationship, and the T is a positive integer.
  • the receiving module 21 may execute S1601 in the embodiment of FIG. 16.
  • the decoding module 22 may execute S1602 in the embodiment of FIG. 16.
  • the encoding device shown in the embodiment of the present application can execute the technical solution shown in the foregoing method embodiment, and its implementation principles and beneficial effects are similar, and will not be repeated this time.
  • the positional relationship between two adjacent sub-blocks in the T sub-blocks is the same as the preset positional relationship.
  • the first diagonal of the sub-block includes the first generator matrix core.
  • the multiple first generator matrix cores in the sub-block are distributed in a triangle below.
  • the distribution of the first generator matrix core in the sub-block is the same as the distribution of the first element in the second generator matrix core, and the number of elements included in the second generator matrix core is equal to The number of elements included in the sub-blocks is the same, and the elements included in the sub-blocks are the first generator matrix core or the 0 matrix.
  • the first generator matrix includes two sub-blocks.
  • the number of elements included in the sub-block is 2*2, and the elements included in the sub-block are the first generator matrix core or the 0 matrix.
  • the first generator matrix includes a first sub-block and a second sub-block, and the first element in the first sub-block and the second element in the second sub-block are coincide;
  • the coordinates of the first element in the first sub-block are (2, 2), and the coordinates of the second element in the second sub-block are (1, 1).
  • the number of elements included in the sub-block is 4*4, and the elements included in the sub-block are the first generator matrix core or the 0 matrix.
  • the first generating matrix includes a first sub-block and a second sub-block, and the four first elements in the first sub-block and the four in the second sub-block are Two second elements coincide; among them,
  • the coordinates of the four first elements in the first sub-block are: (3,3), (3,4), (4,3), (4,4);
  • the coordinates of the four second elements in the second sub-block are respectively: (1,1), (1,2), (2,1), (2,2).
  • the bit information includes N′ first log-likelihood ratio LLR sequences, and the N′ is a positive integer.
  • the N′ first LLRs include T first LLR sequences, and the first LLR sequences include at least two first LLRs; the decoding module 22 is specifically configured to :
  • T second LLR sequences corresponding to the T first LLR sequences one of the first LLR sequences corresponds to one or more sets of bits before encoding, and one of the second LLR sequences corresponds to a set of bits before encoding ;
  • the decoding module 22 is specifically configured to:
  • the coupling degree of the code block is 2; the decoding module 22 is specifically configured to:
  • the i-th second LLR sequence is determined according to the i-th first LLR sequence and the i-1th second LLR sequence.
  • the first second LLR sequence is the same as the first first LLR sequence.
  • the coupling degree of the code block is 4; the decoding module 22 is specifically configured to:
  • the i-th second LLR sequence is determined according to the i-th first LLR sequence and the i-2th second LLR sequence, and the i is an integer between 3 and T.
  • the first second LLR sequence is the same as the first first LLR sequence
  • the second second LLR sequence is the same as the second first LLR sequence.
  • the decoding module 22 is specifically configured to:
  • the coupling degree of the code block is 2; the decoding module 22 is specifically configured to:
  • the i-th decoding result is determined according to the i+1-th decoding result, the i+1-th first LLR sequence, and the i-th second LLR sequence.
  • the encoding device shown in the embodiment of the present application can execute the technical solution shown in the foregoing method embodiment, and its implementation principles and beneficial effects are similar, and will not be repeated this time.
  • FIG. 23 is a schematic structural diagram of another encoding device provided by an embodiment of this application.
  • the encoding device 30 may include an acquiring module 31, a determining module 32, a generating module 33, and an encoding module 34, where:
  • the obtaining module 31 is configured to obtain K bits to be coded, where K is a positive integer;
  • the determining module 32 is configured to determine a first generator matrix.
  • the first generator matrix includes a first matrix block and a second matrix block.
  • the first matrix block is located at the upper left corner of the first generator matrix.
  • the second matrix block is located at the lower right corner of the first generator matrix.
  • the first matrix block and the second matrix block are the same, along the diagonal direction of the first generator matrix, in the first matrix block
  • the distance between the first element of and the second element in the second matrix block is u, and the u is an integer greater than or equal to 1;
  • the generating module 33 is configured to generate a second generator matrix according to the coding length and the first generator matrix, the second generator matrix includes T first generator matrices, and the T first generator matrices Distributed along the diagonal of the second generator matrix, the first matrix block of the a+1-th first generator matrix and the second matrix block of the a-th first generator matrix among the T first generator matrices Coincident, said a is an integer greater than or equal to 1, and said T is an integer greater than or equal to 2;
  • the encoding module 34 is configured to perform polarization encoding on the K to-be-encoded bits according to the second generating matrix to obtain encoded bits.
  • the obtaining module 31 may execute S1001 in the embodiment of FIG. 10.
  • the determining module 32 may execute S1002 in the embodiment of FIG. 10.
  • the generating module 33 may execute S1003 in the embodiment of FIG. 10.
  • the encoding module 34 may execute S1004 in the embodiment in FIG. 10.
  • the encoding device shown in the embodiment of the present application can execute the technical solution shown in the foregoing method embodiment, and its implementation principles and beneficial effects are similar, and will not be repeated this time.
  • the i is an integer
  • the j is an integer
  • the v is a positive integer
  • the u is an integer, 1 ⁇ i ⁇ v, 1 ⁇ j ⁇ v, 1 ⁇ i+u ⁇ v, 1 ⁇ j+u ⁇ v.
  • the elements in the first generator matrix are symmetrical along a subdiagonal line of the first generator matrix.
  • T is the smallest integer that enables the first condition to be satisfied, and the first condition is: the size of the second generator matrix is greater than or equal to the code length.
  • the T satisfies the following relationship:
  • the v is the size of the first generator matrix
  • the N′ is the coding length
  • the N′ is an integer greater than 1.
  • the encoding device shown in the embodiment of the present application can execute the technical solution shown in the foregoing method embodiment, and its implementation principles and beneficial effects are similar, and will not be repeated this time.
  • FIG. 24 is a schematic structural diagram of another decoding device provided by an embodiment of this application.
  • the decoding device 40 may include a receiving module 41 and a decoding module 42, wherein,
  • the receiving module 41 is configured to receive polarization-encoded bit information
  • the decoding module 42 is configured to perform polarization decoding on the bit information according to a second generating matrix to obtain polarized decoded bits, and the second generating matrix is generated according to the first generating matrix;
  • the first generator matrix includes a first matrix block and a second matrix block, the first matrix block is located at the upper left corner of the first generator matrix, and the second matrix block is located at the upper left corner of the first generator matrix.
  • the first matrix block and the second matrix block are the same, and along the diagonal direction of the first generator matrix, the first element in the first matrix block is the same as that in the second matrix block.
  • the distance between the second elements of is u, and the u is an integer greater than or equal to 1;
  • the second generator matrix includes T first generator matrices, the T first generator matrices are distributed along the diagonal of the second generator matrix, and the T first generator matrices are The first matrix block of the a+1th first generator matrix coincides with the second matrix block of the ath first generator matrix, where a is an integer greater than or equal to 1, and the T is an integer greater than or equal to 2 .
  • the receiving module 41 may execute S1601 in the embodiment of FIG. 16.
  • the decoding module 42 may execute S1602 in the embodiment of FIG. 16.
  • the encoding device shown in the embodiment of the present application can execute the technical solution shown in the foregoing method embodiment, and its implementation principles and beneficial effects are similar, and will not be repeated this time.
  • the i is an integer
  • the j is an integer
  • the v is a positive integer
  • the u is an integer, 1 ⁇ i ⁇ v, 1 ⁇ j ⁇ v, 1 ⁇ i+u ⁇ v, 1 ⁇ j+u ⁇ v.
  • the elements in the first generator matrix are symmetrical along a subdiagonal line of the first generator matrix.
  • T is the smallest integer that enables the first condition to be satisfied, and the first condition is: the size of the second generator matrix is greater than or equal to the code length.
  • the T satisfies the following relationship:
  • the v is the size of the first generator matrix
  • the N′ is the coding length
  • the N′ is an integer greater than 1.
  • the bit information includes N′ first log-likelihood ratio LLR sequences, and the N′ is a positive integer.
  • the N′ first LLRs include T first LLR sequences, and the first LLR sequences include at least two first LLRs; the decoding module 42 is specifically configured to :
  • T second LLR sequences corresponding to the T first LLR sequences one of the first LLR sequences corresponds to one or more sets of bits before encoding, and one of the second LLR sequences corresponds to a set of bits before encoding ;
  • the decoding module 42 is specifically configured to:
  • the coupling degree of the code block is 2; the decoding module 42 is specifically configured to:
  • the i-th second LLR sequence is determined according to the i-th first LLR sequence and the i-1th second LLR sequence.
  • the first second LLR sequence is the same as the first first LLR sequence.
  • the coupling degree of the code block is 4; the decoding module 42 is specifically configured to:
  • the i-th second LLR sequence is determined according to the i-th first LLR sequence and the i-2th second LLR sequence, and the i is an integer between 3 and T.
  • the first second LLR sequence is the same as the first first LLR sequence
  • the second second LLR sequence is the same as the second first LLR sequence.
  • the decoding module 42 is specifically configured to:
  • the coupling degree of the code block is 2; the decoding module 42 is specifically configured to:
  • the i-th decoding result is determined according to the i+1-th decoding result, the i+1-th first LLR sequence, and the i-th second LLR sequence.
  • the encoding device shown in the embodiment of the present application can execute the technical solution shown in the foregoing method embodiment, and its implementation principles and beneficial effects are similar, and will not be repeated this time.
  • FIG. 25 is a schematic diagram of the hardware structure of an encoding device provided by an embodiment of the application.
  • the encoding device 50 may include: a processor 51 and a memory 52, where:
  • the memory 52 is used to store computer programs and can also be used to store intermediate data
  • the processor 51 is configured to execute a computer program stored in the memory to implement each step in the foregoing encoding method. For details, refer to the related description in the foregoing method embodiment.
  • the memory 52 may be independent or integrated with the processor 51. In some embodiments, the memory 52 may even be located outside the encoding device 50.
  • the encoding device 50 may further include a bus 53 for connecting the memory 52 and the processor 51.
  • the encoding device 50 may further include a transmitter.
  • the transmitter is used to transmit encoded bits.
  • the encoding device 50 provided in this embodiment may be a terminal device, or also a network device, and may be used to execute the above-mentioned encoding method, and its implementation and technical effects are similar, and will not be repeated here in this embodiment.
  • FIG. 26 is a schematic diagram of the hardware structure of a decoding device provided by an embodiment of the application.
  • the decoding device 60 may include: a processor 61 and a memory 62, where:
  • the memory 62 is used to store computer programs and can also be used to store intermediate data
  • the processor 61 is configured to execute a computer program stored in the memory to implement each step in the foregoing decoding method. For details, refer to the related description in the foregoing method embodiment.
  • the memory 62 may be independent or integrated with the processor 61. In some embodiments, the memory 62 may even be located outside the decoding device 60.
  • the decoding device 60 may further include a bus 63 for connecting the memory 62 and the processor 61.
  • the decoding device 60 may further include a receiver.
  • the receiver is used to receive polarization-encoded bit information.
  • the decoding device 60 provided in this embodiment may be a terminal device, or also a network device, and may be used to execute the above-mentioned decoding method.
  • the implementation manner and technical effect are similar, and the details are not described herein again in this embodiment.
  • FIG. 27 is a schematic structural diagram of another encoding device provided by an embodiment of this application. Please refer to FIG. 27.
  • the encoding device 70 may include an input interface 71 and a logic circuit 72, where:
  • the input interface 71 is used to obtain K bits to be coded, where K is a positive integer;
  • the logic circuit 72 is configured to determine a first generator matrix, the first generator matrix includes at least two sub-blocks distributed according to a preset position relationship, and the sub-block includes a plurality of first generator matrix cores;
  • the first generator matrix generates a second generator matrix, the second generator matrix includes T sub-blocks, and the positional relationship between two adjacent sub-blocks in the T sub-blocks is determined according to the preset positional relationship ,
  • the T is a positive integer; performing polarization coding on the K bits to be coded according to the second generating matrix to obtain the coded bits.
  • the input interface 71 may have the function of the acquisition module 11 in the embodiment of FIG. 21.
  • the logic circuit 72 may have the functions of the determining module 11, the generating module 13 and the encoding module 14 in the embodiment of FIG. 21.
  • the logic circuit 72 may have the function of the processor 61 in the embodiment of FIG. 25.
  • the logic circuit 72 can also perform other steps in the encoding method.
  • the encoding device 70 may further include an output interface.
  • the output interface can output encoded bits.
  • the encoding device 70 provided in the embodiment of the present application can execute the technical solutions shown in the foregoing method embodiments, and its implementation principles and beneficial effects are similar to those described herein.
  • FIG. 28 is a schematic structural diagram of another decoding device provided by an embodiment of this application.
  • the decoding device 80 may include an input interface 81 and a logic circuit 82, where:
  • the input interface 81 is used to receive polarization-encoded bit information
  • the logic circuit 82 is configured to perform polarization decoding on the bit information according to a second generating matrix to obtain polarized decoded bits; wherein, the second generating matrix is generated according to the first generating matrix,
  • the first generator matrix includes at least two sub-blocks distributed according to a preset position relationship, the sub-block includes a plurality of first generator matrix cores, the second generator matrix includes T sub-blocks, and the T sub-blocks
  • the positional relationship between two adjacent sub-blocks in is determined according to the preset positional relationship, and the T is a positive integer.
  • the input interface 81 may have the function of the receiving module 21 in the embodiment of FIG. 22.
  • the logic circuit 82 may have the function of the decoding module 22 in the embodiment of FIG. 22.
  • the input interface 81 may have the function of the receiver in the embodiment of FIG. 26.
  • the logic circuit 82 may have the function of the processor 61 in the embodiment of FIG. 26.
  • the logic circuit 82 can also perform other steps in the decoding method.
  • the decoding device 80 may also include an output interface.
  • the output interface can output the decoding result.
  • the decoding device 80 provided in the embodiment of the present application can execute the technical solutions shown in the foregoing method embodiments, and its implementation principles and beneficial effects are similar to those described herein.
  • FIG. 29 is a schematic structural diagram of another encoding device provided by an embodiment of this application.
  • the encoding device 90 may include an input interface 91 and a logic circuit 92, where:
  • the input interface 91 is used to obtain K bits to be encoded, where K is a positive integer;
  • the logic circuit 92 is configured to determine a first generator matrix.
  • the first generator matrix includes a first matrix block and a second matrix block.
  • the first matrix block is located at the upper left corner of the first generator matrix.
  • the second matrix block is located at the lower right corner of the first generator matrix.
  • the first matrix block and the second matrix block are the same, along the diagonal direction of the first generator matrix, in the first matrix block
  • the distance between the first element of and the second element in the second matrix block is u, where u is an integer greater than or equal to 1;
  • the second generator matrix is determined according to the coding length and the first generator matrix ,
  • the second generator matrix includes T first generator matrices, the T first generator matrices are distributed along the diagonal of the second generator matrix, and the first generator matrix in the T first generator matrix a+1 first matrix blocks of the first generator matrix overlap with the second matrix blocks of the a-th first generator matrix, where a is an integer greater than or equal to 1, and the T is an integer greater than or equal to 2;
  • According to the second generating matrix perform polarization encoding on the K to-be-encoded bits to obtain encoded bits.
  • the input interface 91 may have the function of the acquisition module 31 in the embodiment of FIG. 23.
  • the logic circuit 92 may have the functions of the determining module 32, the generating module 33, and the encoding module 34 in the embodiment of FIG. 23.
  • the logic circuit 92 may have the function of the processor 61 in the embodiment of FIG. 25.
  • the logic circuit 92 can also perform other steps in the encoding method.
  • the encoding device 90 may also include an output interface.
  • the output interface can output encoded bits.
  • the encoding device 90 provided in the embodiment of the present application can execute the technical solutions shown in the foregoing method embodiments, and its implementation principles and beneficial effects are similar to those described herein.
  • FIG. 30 is a schematic structural diagram of another decoding device provided by an embodiment of this application.
  • the decoding device 100 may include an input interface 101 and a logic circuit 102, where:
  • the input interface 101 is used to receive polarization-encoded bit information
  • the logic circuit 102 is configured to perform polarization decoding on the bit information according to a second generator matrix to obtain polarized decoded bits, and the second generator matrix is generated according to the first generator matrix; wherein,
  • the first generator matrix includes a first matrix block and a second matrix block, the first matrix block is located at the upper left corner of the first generator matrix, and the second matrix block is located at the lower right corner of the first generator matrix ,
  • the first matrix block and the second matrix block are the same, and along the diagonal direction of the first generator matrix, the first element in the first matrix block is the same as the first element in the second matrix block.
  • the distance between the two elements is u, and the u is an integer greater than or equal to 1; wherein, the second generating matrix includes T first generating matrices, and the T first generating matrices are along the The diagonal distribution of the second generator matrix, the first matrix block of the a+1-th first generator matrix in the T first generator matrices coincides with the second matrix block of the a-th first generator matrix, so The a is an integer greater than or equal to 1, and the T is an integer greater than or equal to 2.
  • the input interface 101 may have the function of the receiving module 41 in the embodiment of FIG. 24.
  • the logic circuit 102 may have the function of the decoding module 42 in the embodiment of FIG. 24.
  • the input interface 101 may have the function of the receiver in the embodiment of FIG. 26.
  • the logic circuit 102 may have the function of the processor 61 in the embodiment of FIG. 26.
  • the logic circuit 102 can also perform other steps in the decoding method.
  • the decoding device 100 may further include an output interface.
  • the output interface can output the decoding result.
  • the decoding device 100 provided in the embodiment of the present application can execute the technical solutions shown in the foregoing method embodiments, and its implementation principles and beneficial effects are similar to those described herein.
  • An embodiment of the present application further provides a storage medium, the storage medium includes a computer program, and the computer program is used to implement the encoding method described above.
  • An embodiment of the present application further provides a storage medium, the storage medium includes a computer program, and the computer program is used to implement the decoding method described above.
  • the embodiment of the present application also provides a chip or integrated circuit, including: a memory and a processor;
  • the memory is used to store program instructions and can also be used to store intermediate data
  • the processor is configured to call the program instructions stored in the memory to implement the encoding method described above.
  • the memory can be independent or integrated with the processor.
  • the memory may also be located outside the chip or integrated circuit.
  • the embodiment of the present application also provides a chip or integrated circuit, including: a memory and a processor;
  • the memory is used to store program instructions and can also be used to store intermediate data
  • the processor is configured to call the program instructions stored in the memory to implement the decoding method as described above.
  • the memory can be independent or integrated with the processor.
  • the memory may also be located outside the chip or integrated circuit.
  • An embodiment of the present application also provides a program product, the program product includes a computer program, the computer program is stored in a storage medium, and the computer program is used to implement the foregoing encoding method.
  • An embodiment of the present application also provides a program product, the program product includes a computer program, the computer program is stored in a storage medium, and the computer program is used to implement the above-mentioned decoding method.
  • the steps of the method or algorithm described in combination with the disclosure of the embodiment of the present invention may be implemented in a hardware manner, or may be implemented in a manner in which a processor executes software instructions.
  • Software instructions can be composed of corresponding software modules, which can be stored in random access memory (Random Access Memory, RAM), flash memory, read-only memory (Read Only Memory, ROM), and erasable programmable read-only memory ( Erasable Programmable ROM (EPROM), Electrically Erasable Programmable Read-Only Memory (Electrically EPROM, EEPROM), register, hard disk, mobile hard disk, CD-ROM or any other form of storage medium known in the art.
  • RAM Random Access Memory
  • ROM read-only memory
  • EPROM Erasable Programmable ROM
  • EPROM Electrically Erasable Programmable Read-Only Memory
  • register hard disk, mobile hard disk, CD-ROM or any other form of storage medium known in the art.
  • An exemplary storage medium is coupled to the processor, so that the processor can read information from the storage medium and write information to the storage medium.
  • the storage medium may also be an integral part of the processor.
  • the processor and the storage medium may be located in the ASIC.
  • the ASIC may be located in a base station or terminal.
  • the processor and the storage medium may also exist as discrete components in the receiving device.
  • processor may be a central processing unit (English: Central Processing Unit, abbreviated as: CPU), or other general-purpose processors, digital signal processors (English: Digital Signal Processor, abbreviated as: DSP), and application-specific integrated circuits. (English: Application Specific Integrated Circuit, referred to as ASIC) etc.
  • the general-purpose processor may be a microprocessor or the processor may also be any conventional processor or the like. The steps of the method disclosed in combination with the invention can be directly embodied as executed and completed by a hardware processor, or executed and completed by a combination of hardware and software modules in the processor.
  • the memory may include a high-speed RAM memory, or may also include a non-volatile storage NVM, such as at least one disk storage, and may also be a U disk, a mobile hard disk, a read-only memory, a magnetic disk, or an optical disk.
  • NVM non-volatile storage
  • the bus can be an Industry Standard Architecture (ISA) bus, Peripheral Component (PCI) bus, or Extended Industry Standard Architecture (EISA) bus, etc.
  • ISA Industry Standard Architecture
  • PCI Peripheral Component
  • EISA Extended Industry Standard Architecture
  • the bus can be divided into address bus, data bus, control bus and so on.
  • the buses in the drawings of this application are not limited to only one bus or one type of bus.
  • the above-mentioned storage medium can be realized by any type of volatile or non-volatile storage device or their combination, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable Except programmable read only memory (EPROM), programmable read only memory (PROM), read only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.
  • SRAM static random access memory
  • EEPROM electrically erasable programmable read-only memory
  • EPROM erasable except programmable read only memory
  • PROM programmable read only memory
  • ROM read only memory
  • magnetic memory flash memory
  • flash memory magnetic disk or optical disk.
  • optical disk any available medium that can be accessed by a general-purpose or special-purpose computer.
  • At least one refers to one or more, and “multiple” refers to two or more.
  • “And/or” describes the association relationship of the associated objects, indicating that there can be three relationships, for example, A and/or B, which can mean: A alone exists, A and B exist at the same time, and B exists alone, where A, B can be singular or plural.
  • the character “/” generally indicates that the associated objects before and after are in an “or” relationship.
  • the following at least one item (a)” or similar expressions refers to any combination of these items, including any combination of a single item (a) or a plurality of items (a).
  • at least one item (a) of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple .
  • the functions described in the embodiments of the present invention may be implemented by hardware, software, firmware, or any combination thereof.
  • these functions can be stored in a computer-readable medium or transmitted as one or more instructions or codes on the computer-readable medium.
  • the computer-readable medium includes a computer storage medium and a communication medium, where the communication medium includes any medium that facilitates the transfer of a computer program from one place to another.
  • the storage medium may be any available medium that can be accessed by a general-purpose or special-purpose computer.
  • the disclosed device and method may be implemented in other ways.
  • the device embodiments described above are merely illustrative.
  • the division of the modules is only a logical function division, and there may be other divisions in actual implementation, for example, multiple modules can be combined or integrated. To another system, or some features can be ignored, or not implemented.
  • the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or modules, and may be in electrical, mechanical or other forms.
  • modules described as separate components may or may not be physically separated, and the components displayed as modules may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules can be selected according to actual needs to achieve the objectives of the solutions of the embodiments.
  • the functional modules in the various embodiments of the present invention may be integrated into one processing unit, or each module may exist alone physically, or two or more modules may be integrated into one unit.
  • the units formed by the above-mentioned modules can be realized in the form of hardware, or in the form of hardware plus software functional units.

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  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Error Detection And Correction (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)

Abstract

L'invention concerne des procédés et des appareils de codage et de décodage, ainsi qu'un dispositif. Le procédé de codage comprend les étapes consistant à : obtenir K bits à coder (S301), K étant un nombre entier positif ; déterminer une première matrice de génération, la première matrice de génération comprenant au moins deux sous-blocs distribués selon une relation de position prédéfinie, les sous-blocs comprenant de multiples noyaux de matrice de génération (S302) ; générer une seconde matrice de génération selon la première matrice de génération, la seconde matrice de génération comprenant des sous-blocs T, une relation de position entre deux sous-blocs adjacents dans les sous-blocs T étant déterminée selon la relation de position prédéfinie (S303), et T étant un nombre entier positif ; et selon la seconde matrice de génération, réaliser un codage de polarisation sur lesdits K bits pour obtenir des bits codés (S304). Le procédé réduit la complexité du codage et du décodage.
PCT/CN2021/086960 2020-04-22 2021-04-13 Procédés et appareils de codage et de décodage et dispositif WO2021213219A1 (fr)

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EP21791667.5A EP4131785A4 (fr) 2020-04-22 2021-04-13 Procédés et appareils de codage et de décodage et dispositif
JP2022564458A JP2023523254A (ja) 2020-04-22 2021-04-13 符号化方法及び装置、復号方法及び装置、並びにデバイス
US17/969,736 US20230058149A1 (en) 2020-04-22 2022-10-20 Encoding method and apparatus, decoding method and apparatus, and device

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CN202010323605.XA CN113541698B (zh) 2020-04-22 2020-04-22 编码、译码方法、装置及设备

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Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024031286A1 (fr) * 2022-08-08 2024-02-15 华为技术有限公司 Procédé, appareil et dispositif de traitement des données

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1960188A (zh) * 2006-04-29 2007-05-09 北京泰美世纪科技有限公司 构造低密度奇偶校验码的方法、译码方法及其传输系统
CN102035556A (zh) * 2009-10-05 2011-04-27 香港理工大学 对数据进行编码及解码的方法和系统
US8352846B2 (en) * 2009-05-07 2013-01-08 Adeptence, Llc Method an apparatus for low density parity check codes encoding and decoding
US20140331083A1 (en) * 2012-12-29 2014-11-06 Emc Corporation Polar codes for efficient encoding and decoding in redundant disk arrays
CN110800216A (zh) * 2017-06-19 2020-02-14 三星电子株式会社 用于通信和广播系统的速率匹配的方法和装置
CN110868226A (zh) * 2019-11-19 2020-03-06 武汉理工大学 基于混合极化核的极化码的编译码方法

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015026148A1 (fr) * 2013-08-20 2015-02-26 엘지전자 주식회사 Procédé de transmission de données à l'aide d'un codage polaire dans un système d'accès sans fil
US10523364B2 (en) * 2015-11-06 2019-12-31 Samsung Electronics Co., Ltd. Channel coding framework for 802.11AY and larger block-length LDPC codes for 11AY with 2-step lifting matrices and in-place property
WO2017193614A1 (fr) * 2016-05-13 2017-11-16 中兴通讯股份有限公司 Procédé et dispositif de codage et procédé et dispositif de décodage pour code ldpc structuré
US10579452B2 (en) * 2016-06-17 2020-03-03 Huawei Technologies Co., Ltd. Systems and methods for rate matching via a heterogeneous kernel when using general polar codes
EP3273602B1 (fr) * 2016-07-19 2022-01-26 MediaTek Inc. Adaptation de taux de codage à faible complexité pour codes polaires
US10700816B2 (en) * 2016-08-09 2020-06-30 Lg Electronics Inc. Method for performing HARQ using polar code
US10644829B2 (en) * 2016-09-15 2020-05-05 Huawei Technologies Co., Ltd. Method and apparatus for encoding data using a polar code
WO2018060961A1 (fr) * 2016-09-30 2018-04-05 Telefonaktiebolaget Lm Ericsson (Publ) Codes polaires couplés spatialement
US10554223B2 (en) * 2016-12-23 2020-02-04 Huawei Technologies Co., Ltd. Apparatus and methods for polar code construction
WO2018126914A1 (fr) * 2017-01-09 2018-07-12 中兴通讯股份有限公司 Procédé et dispositif de codage de code de contrôle de parité à faible densité quasi-cyclique, et support de stockage
FR3064436B1 (fr) * 2017-03-21 2022-11-18 Orange Procede de codage et codeur a code polaire
WO2018187902A1 (fr) * 2017-04-10 2018-10-18 Qualcomm Incorporated Conception d'entrelaceur efficace de codes polaires
CN108809332B (zh) * 2017-05-05 2021-09-03 华为技术有限公司 一种Polar码传输方法及装置
GB2563418B (en) * 2017-06-15 2020-04-22 Accelercomm Ltd Polar encoder, communication unit, integrated circuit and method therefor
WO2019191944A1 (fr) * 2018-04-04 2019-10-10 Qualcomm Incorporated Schéma harq codé polaire sur un canal variant dans le temps
KR20200036338A (ko) * 2018-09-28 2020-04-07 삼성전자주식회사 무선 통신 시스템에서 극 부호를 이용한 부호화 및 복호화를 위한 장치 및 방법
CN113810061A (zh) * 2020-06-17 2021-12-17 华为技术有限公司 Polar码编码方法、Polar码译码方法及其装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1960188A (zh) * 2006-04-29 2007-05-09 北京泰美世纪科技有限公司 构造低密度奇偶校验码的方法、译码方法及其传输系统
US8352846B2 (en) * 2009-05-07 2013-01-08 Adeptence, Llc Method an apparatus for low density parity check codes encoding and decoding
CN102035556A (zh) * 2009-10-05 2011-04-27 香港理工大学 对数据进行编码及解码的方法和系统
US20140331083A1 (en) * 2012-12-29 2014-11-06 Emc Corporation Polar codes for efficient encoding and decoding in redundant disk arrays
CN110800216A (zh) * 2017-06-19 2020-02-14 三星电子株式会社 用于通信和广播系统的速率匹配的方法和装置
CN110868226A (zh) * 2019-11-19 2020-03-06 武汉理工大学 基于混合极化核的极化码的编译码方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4131785A4

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EP4131785A4 (fr) 2023-06-28
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CN113541698A (zh) 2021-10-22
JP2023523254A (ja) 2023-06-02
CN113541698B (zh) 2022-07-12
CN115622572A (zh) 2023-01-17

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